Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.22 99.97 98.73 97.09 100.00 99.99 99.38 99.36


Total test records in report: 825
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T163 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2936978796 Aug 03 04:46:04 PM PDT 24 Aug 03 04:46:50 PM PDT 24 4165810563 ps
T768 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2478091027 Aug 03 04:46:44 PM PDT 24 Aug 03 04:46:46 PM PDT 24 30219839 ps
T769 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.285354426 Aug 03 04:46:39 PM PDT 24 Aug 03 04:46:40 PM PDT 24 12632885 ps
T291 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3840503703 Aug 03 04:46:41 PM PDT 24 Aug 03 04:46:44 PM PDT 24 50525033 ps
T770 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.310230240 Aug 03 04:46:32 PM PDT 24 Aug 03 04:46:42 PM PDT 24 201261591 ps
T771 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.449800731 Aug 03 04:46:40 PM PDT 24 Aug 03 04:46:45 PM PDT 24 121276663 ps
T772 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3058404080 Aug 03 04:46:42 PM PDT 24 Aug 03 04:46:43 PM PDT 24 27215708 ps
T161 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.568278813 Aug 03 04:46:19 PM PDT 24 Aug 03 04:46:57 PM PDT 24 2190879274 ps
T773 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3941323588 Aug 03 04:46:09 PM PDT 24 Aug 03 04:46:17 PM PDT 24 107829366 ps
T774 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3868107655 Aug 03 04:46:30 PM PDT 24 Aug 03 04:46:39 PM PDT 24 96418195 ps
T775 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2277417625 Aug 03 04:46:22 PM PDT 24 Aug 03 04:46:38 PM PDT 24 123887220 ps
T776 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1417448349 Aug 03 04:46:22 PM PDT 24 Aug 03 04:47:06 PM PDT 24 1217486518 ps
T164 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.369483595 Aug 03 04:46:15 PM PDT 24 Aug 03 04:46:19 PM PDT 24 169156567 ps
T777 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1613691391 Aug 03 04:46:39 PM PDT 24 Aug 03 04:46:41 PM PDT 24 10249194 ps
T778 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2024715250 Aug 03 04:46:03 PM PDT 24 Aug 03 04:46:04 PM PDT 24 9816108 ps
T779 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.702813473 Aug 03 04:46:25 PM PDT 24 Aug 03 04:46:27 PM PDT 24 11864233 ps
T138 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3949961201 Aug 03 04:46:28 PM PDT 24 Aug 03 04:49:53 PM PDT 24 3204583018 ps
T169 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.936038409 Aug 03 04:46:02 PM PDT 24 Aug 03 04:46:08 PM PDT 24 95955464 ps
T780 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.427785566 Aug 03 04:46:35 PM PDT 24 Aug 03 04:46:37 PM PDT 24 9420605 ps
T146 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.4270404746 Aug 03 04:46:33 PM PDT 24 Aug 03 04:50:16 PM PDT 24 3426832626 ps
T781 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.4279152672 Aug 03 04:46:43 PM PDT 24 Aug 03 04:46:45 PM PDT 24 6628131 ps
T782 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1548474186 Aug 03 04:46:15 PM PDT 24 Aug 03 04:46:25 PM PDT 24 115548453 ps
T783 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.339130099 Aug 03 04:46:45 PM PDT 24 Aug 03 04:46:46 PM PDT 24 15544944 ps
T784 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3612035103 Aug 03 04:46:43 PM PDT 24 Aug 03 04:46:56 PM PDT 24 167929330 ps
T142 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2140780424 Aug 03 04:46:09 PM PDT 24 Aug 03 04:56:08 PM PDT 24 161790025249 ps
T785 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2977746504 Aug 03 04:46:19 PM PDT 24 Aug 03 04:46:32 PM PDT 24 172335846 ps
T786 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.972676582 Aug 03 04:46:30 PM PDT 24 Aug 03 04:46:38 PM PDT 24 110379768 ps
T787 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1006168259 Aug 03 04:46:00 PM PDT 24 Aug 03 04:47:10 PM PDT 24 563653596 ps
T788 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1502793826 Aug 03 04:46:07 PM PDT 24 Aug 03 04:46:12 PM PDT 24 51968612 ps
T144 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.617011410 Aug 03 04:46:00 PM PDT 24 Aug 03 04:49:43 PM PDT 24 6061621128 ps
T789 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1132823933 Aug 03 04:46:29 PM PDT 24 Aug 03 04:46:37 PM PDT 24 1511034696 ps
T790 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2952123608 Aug 03 04:46:35 PM PDT 24 Aug 03 04:46:37 PM PDT 24 8582029 ps
T173 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.4261500401 Aug 03 04:46:36 PM PDT 24 Aug 03 04:46:39 PM PDT 24 244664694 ps
T791 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3319267474 Aug 03 04:46:17 PM PDT 24 Aug 03 04:50:03 PM PDT 24 6530138576 ps
T792 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.129212290 Aug 03 04:46:37 PM PDT 24 Aug 03 04:46:39 PM PDT 24 10217561 ps
T793 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4191536432 Aug 03 04:46:34 PM PDT 24 Aug 03 04:47:11 PM PDT 24 4007735735 ps
T143 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2429100691 Aug 03 04:46:36 PM PDT 24 Aug 03 04:57:48 PM PDT 24 19546916255 ps
T794 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1077299553 Aug 03 04:46:44 PM PDT 24 Aug 03 04:46:46 PM PDT 24 6776262 ps
T795 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3699535510 Aug 03 04:46:40 PM PDT 24 Aug 03 04:46:41 PM PDT 24 14198074 ps
T796 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.322369924 Aug 03 04:46:12 PM PDT 24 Aug 03 04:47:57 PM PDT 24 1725052625 ps
T797 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.4069358553 Aug 03 04:46:15 PM PDT 24 Aug 03 04:46:21 PM PDT 24 65654838 ps
T798 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.786352477 Aug 03 04:46:40 PM PDT 24 Aug 03 04:47:00 PM PDT 24 285750536 ps
T162 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2056085306 Aug 03 04:46:40 PM PDT 24 Aug 03 04:47:21 PM PDT 24 637772709 ps
T799 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1174621256 Aug 03 04:46:04 PM PDT 24 Aug 03 04:46:11 PM PDT 24 95322355 ps
T800 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2318768299 Aug 03 04:46:45 PM PDT 24 Aug 03 04:46:51 PM PDT 24 58216656 ps
T801 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1953661111 Aug 03 04:46:23 PM PDT 24 Aug 03 04:46:28 PM PDT 24 40512814 ps
T802 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.147273939 Aug 03 04:46:24 PM PDT 24 Aug 03 04:46:28 PM PDT 24 62570620 ps
T803 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3471667096 Aug 03 04:46:36 PM PDT 24 Aug 03 04:46:49 PM PDT 24 90616087 ps
T804 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.343952485 Aug 03 04:46:38 PM PDT 24 Aug 03 04:46:39 PM PDT 24 16777997 ps
T147 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2686223461 Aug 03 04:46:41 PM PDT 24 Aug 03 04:51:30 PM PDT 24 17673416715 ps
T805 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2951126012 Aug 03 04:46:40 PM PDT 24 Aug 03 04:46:42 PM PDT 24 9323490 ps
T806 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.89226578 Aug 03 04:46:39 PM PDT 24 Aug 03 04:46:49 PM PDT 24 380375774 ps
T167 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3077808266 Aug 03 04:46:38 PM PDT 24 Aug 03 04:46:41 PM PDT 24 98095100 ps
T807 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.913160045 Aug 03 04:46:01 PM PDT 24 Aug 03 04:46:10 PM PDT 24 425454581 ps
T808 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1206636576 Aug 03 04:45:57 PM PDT 24 Aug 03 04:51:16 PM PDT 24 2942002057 ps
T809 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1964547025 Aug 03 04:46:38 PM PDT 24 Aug 03 04:46:40 PM PDT 24 11183624 ps
T810 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3924805151 Aug 03 04:46:40 PM PDT 24 Aug 03 04:46:52 PM PDT 24 85794778 ps
T811 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3647632917 Aug 03 04:46:43 PM PDT 24 Aug 03 04:46:45 PM PDT 24 6568820 ps
T812 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2609685536 Aug 03 04:46:41 PM PDT 24 Aug 03 04:46:42 PM PDT 24 14368090 ps
T813 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1677138675 Aug 03 04:46:01 PM PDT 24 Aug 03 04:46:06 PM PDT 24 35234682 ps
T814 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4095519227 Aug 03 04:46:23 PM PDT 24 Aug 03 04:46:41 PM PDT 24 886633664 ps
T815 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.464482494 Aug 03 04:46:02 PM PDT 24 Aug 03 04:46:10 PM PDT 24 44607673 ps
T816 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.74160875 Aug 03 04:46:26 PM PDT 24 Aug 03 04:46:34 PM PDT 24 113501332 ps
T817 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3245852247 Aug 03 04:46:32 PM PDT 24 Aug 03 04:47:11 PM PDT 24 514243001 ps
T818 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1549831655 Aug 03 04:46:18 PM PDT 24 Aug 03 04:46:20 PM PDT 24 6775847 ps
T149 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1787735049 Aug 03 04:46:48 PM PDT 24 Aug 03 04:54:59 PM PDT 24 24449152616 ps
T819 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2299121331 Aug 03 04:46:08 PM PDT 24 Aug 03 04:46:15 PM PDT 24 217404761 ps
T820 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2425593845 Aug 03 04:46:01 PM PDT 24 Aug 03 04:53:33 PM PDT 24 6634910422 ps
T821 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2136292502 Aug 03 04:46:36 PM PDT 24 Aug 03 04:46:54 PM PDT 24 269807895 ps
T822 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1707119237 Aug 03 04:46:18 PM PDT 24 Aug 03 04:46:20 PM PDT 24 11099295 ps
T148 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1291456684 Aug 03 04:46:18 PM PDT 24 Aug 03 04:48:35 PM PDT 24 1271371628 ps
T823 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.185539640 Aug 03 04:46:15 PM PDT 24 Aug 03 04:46:25 PM PDT 24 143895749 ps
T824 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3981705032 Aug 03 04:46:34 PM PDT 24 Aug 03 04:46:35 PM PDT 24 8070628 ps
T825 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.777972332 Aug 03 04:46:46 PM PDT 24 Aug 03 04:47:10 PM PDT 24 1336004087 ps
T170 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3497219669 Aug 03 04:46:18 PM PDT 24 Aug 03 04:46:21 PM PDT 24 103189853 ps

Test location /workspace/coverage/default/45.alert_handler_stress_all.2278052109
Short name T3
Test name
Test status
Simulation time 13790849821 ps
CPU time 1385.08 seconds
Started Aug 03 05:11:16 PM PDT 24
Finished Aug 03 05:34:22 PM PDT 24
Peak memory 288816 kb
Host smart-46382592-2d22-4387-954e-2ba926ad7fcb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278052109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2278052109
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.1737978405
Short name T4
Test name
Test status
Simulation time 384860415940 ps
CPU time 10780.9 seconds
Started Aug 03 05:10:58 PM PDT 24
Finished Aug 03 08:10:40 PM PDT 24
Peak memory 419976 kb
Host smart-081faa28-28e8-463d-b5a5-d86beaa9af49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737978405 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.1737978405
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2603105446
Short name T7
Test name
Test status
Simulation time 1121584881 ps
CPU time 49.81 seconds
Started Aug 03 05:09:48 PM PDT 24
Finished Aug 03 05:10:38 PM PDT 24
Peak memory 270544 kb
Host smart-f8019a8d-8446-43e0-b9c0-40a525974fdd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2603105446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2603105446
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.162151158
Short name T165
Test name
Test status
Simulation time 701357859 ps
CPU time 44.63 seconds
Started Aug 03 04:46:27 PM PDT 24
Finished Aug 03 04:47:12 PM PDT 24
Peak memory 240600 kb
Host smart-0df94793-c2d1-43bc-b13c-fd9192f7787c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=162151158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.162151158
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.227135094
Short name T50
Test name
Test status
Simulation time 200368847309 ps
CPU time 3352.16 seconds
Started Aug 03 05:11:19 PM PDT 24
Finished Aug 03 06:07:12 PM PDT 24
Peak memory 301992 kb
Host smart-369d33a8-51ec-486e-96fa-8bc543ab34dd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227135094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.227135094
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.223555643
Short name T81
Test name
Test status
Simulation time 61172398768 ps
CPU time 5839.55 seconds
Started Aug 03 05:09:53 PM PDT 24
Finished Aug 03 06:47:13 PM PDT 24
Peak memory 354748 kb
Host smart-880965aa-0c6b-4f69-af95-cc05175b5de9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223555643 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.223555643
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2720430089
Short name T115
Test name
Test status
Simulation time 8357698410 ps
CPU time 605.62 seconds
Started Aug 03 04:46:09 PM PDT 24
Finished Aug 03 04:56:15 PM PDT 24
Peak memory 265556 kb
Host smart-f4a18bba-d206-4414-bc09-a47fada8f86e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720430089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2720430089
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2932561567
Short name T245
Test name
Test status
Simulation time 159448746999 ps
CPU time 2332.77 seconds
Started Aug 03 05:10:27 PM PDT 24
Finished Aug 03 05:49:21 PM PDT 24
Peak memory 272372 kb
Host smart-c0d03c3b-d3cf-4415-a4cb-d157a04cdbdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932561567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2932561567
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2657252697
Short name T118
Test name
Test status
Simulation time 4004380555 ps
CPU time 318.97 seconds
Started Aug 03 04:46:10 PM PDT 24
Finished Aug 03 04:51:29 PM PDT 24
Peak memory 272824 kb
Host smart-30e1104c-1263-4bcc-8b14-b4b56d6082e3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2657252697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2657252697
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3302492388
Short name T22
Test name
Test status
Simulation time 15247608108 ps
CPU time 1235.2 seconds
Started Aug 03 05:10:42 PM PDT 24
Finished Aug 03 05:31:17 PM PDT 24
Peak memory 287704 kb
Host smart-fc511884-df80-4cb7-9e09-187bc1a82351
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302492388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3302492388
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.1043113057
Short name T39
Test name
Test status
Simulation time 3553450467 ps
CPU time 221.66 seconds
Started Aug 03 05:10:17 PM PDT 24
Finished Aug 03 05:13:59 PM PDT 24
Peak memory 256532 kb
Host smart-8e315866-7fc6-433c-a4ce-a268b8942a11
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043113057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.1043113057
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2587114926
Short name T51
Test name
Test status
Simulation time 218770411671 ps
CPU time 2452.72 seconds
Started Aug 03 05:10:45 PM PDT 24
Finished Aug 03 05:51:38 PM PDT 24
Peak memory 289156 kb
Host smart-544654ba-dd9a-4cd0-b5ea-704175d864c4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587114926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2587114926
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.4281521804
Short name T127
Test name
Test status
Simulation time 58042959208 ps
CPU time 873.37 seconds
Started Aug 03 04:46:16 PM PDT 24
Finished Aug 03 05:00:49 PM PDT 24
Peak memory 272640 kb
Host smart-cc6be484-4bc6-44bd-b400-e398a1095aa9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281521804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.4281521804
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2754364640
Short name T94
Test name
Test status
Simulation time 5881119263 ps
CPU time 242.71 seconds
Started Aug 03 05:10:29 PM PDT 24
Finished Aug 03 05:14:32 PM PDT 24
Peak memory 248384 kb
Host smart-b1e1567d-0f9d-4618-849a-2345b4d84825
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754364640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2754364640
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2857791987
Short name T137
Test name
Test status
Simulation time 15295571214 ps
CPU time 1104.35 seconds
Started Aug 03 04:46:39 PM PDT 24
Finished Aug 03 05:05:04 PM PDT 24
Peak memory 265676 kb
Host smart-6b0072f7-9d4d-4319-911b-43bb34096158
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857791987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2857791987
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.1508814621
Short name T101
Test name
Test status
Simulation time 415604356215 ps
CPU time 7278.61 seconds
Started Aug 03 05:11:31 PM PDT 24
Finished Aug 03 07:12:50 PM PDT 24
Peak memory 338232 kb
Host smart-42d3ec61-8de9-44c3-9fb0-88b99265a0b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508814621 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.1508814621
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2063901385
Short name T25
Test name
Test status
Simulation time 1287867346 ps
CPU time 31.97 seconds
Started Aug 03 05:10:29 PM PDT 24
Finished Aug 03 05:11:01 PM PDT 24
Peak memory 255504 kb
Host smart-d612e916-5528-4e58-93ba-3d08132a1816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20639
01385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2063901385
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.463823040
Short name T356
Test name
Test status
Simulation time 19277453 ps
CPU time 1.4 seconds
Started Aug 03 04:46:32 PM PDT 24
Finished Aug 03 04:46:34 PM PDT 24
Peak memory 237660 kb
Host smart-792a1f32-a792-48aa-9b4e-7422ef788460
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=463823040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.463823040
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2673197768
Short name T114
Test name
Test status
Simulation time 29781927525 ps
CPU time 573.48 seconds
Started Aug 03 05:09:58 PM PDT 24
Finished Aug 03 05:19:32 PM PDT 24
Peak memory 248240 kb
Host smart-127e4e8c-8eca-4df5-b110-82b798f7051f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673197768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2673197768
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.4190384861
Short name T120
Test name
Test status
Simulation time 15706955055 ps
CPU time 296.19 seconds
Started Aug 03 04:46:08 PM PDT 24
Finished Aug 03 04:51:05 PM PDT 24
Peak memory 265616 kb
Host smart-78118a2f-3f0e-475c-b30e-08e0662569d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4190384861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.4190384861
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3807310115
Short name T14
Test name
Test status
Simulation time 37635236150 ps
CPU time 2340.61 seconds
Started Aug 03 05:10:03 PM PDT 24
Finished Aug 03 05:49:04 PM PDT 24
Peak memory 288672 kb
Host smart-565247d8-42f3-4225-b8b7-20b3e955d414
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807310115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3807310115
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3000347156
Short name T131
Test name
Test status
Simulation time 111194174889 ps
CPU time 1053.78 seconds
Started Aug 03 04:46:18 PM PDT 24
Finished Aug 03 05:03:52 PM PDT 24
Peak memory 273800 kb
Host smart-a141e60b-672e-4dd2-b5ed-ddb41964d44b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000347156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3000347156
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2686223461
Short name T147
Test name
Test status
Simulation time 17673416715 ps
CPU time 288.97 seconds
Started Aug 03 04:46:41 PM PDT 24
Finished Aug 03 04:51:30 PM PDT 24
Peak memory 265592 kb
Host smart-dff04542-7ae1-4ab7-be95-16b7ecdc0251
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2686223461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2686223461
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.9619857
Short name T312
Test name
Test status
Simulation time 16908784801 ps
CPU time 1223.41 seconds
Started Aug 03 05:10:41 PM PDT 24
Finished Aug 03 05:31:05 PM PDT 24
Peak memory 282596 kb
Host smart-baf1d590-d03e-45b4-ba47-e00f373c1432
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9619857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.9619857
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1694544185
Short name T6
Test name
Test status
Simulation time 12566730241 ps
CPU time 522.9 seconds
Started Aug 03 05:10:53 PM PDT 24
Finished Aug 03 05:19:36 PM PDT 24
Peak memory 248428 kb
Host smart-cd707089-c80b-4299-b16d-a16c15b179b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694544185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1694544185
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2552947775
Short name T5
Test name
Test status
Simulation time 63906862932 ps
CPU time 3784.91 seconds
Started Aug 03 05:10:07 PM PDT 24
Finished Aug 03 06:13:12 PM PDT 24
Peak memory 298948 kb
Host smart-75993382-5fe5-49f9-8129-c140f9c123cb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552947775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2552947775
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2846518728
Short name T243
Test name
Test status
Simulation time 110492859571 ps
CPU time 2949.81 seconds
Started Aug 03 05:10:11 PM PDT 24
Finished Aug 03 05:59:21 PM PDT 24
Peak memory 281136 kb
Host smart-f3148ce4-3a07-4781-9be4-13beda78455e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846518728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2846518728
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3541416445
Short name T123
Test name
Test status
Simulation time 17160446443 ps
CPU time 652.99 seconds
Started Aug 03 04:46:34 PM PDT 24
Finished Aug 03 04:57:27 PM PDT 24
Peak memory 273792 kb
Host smart-90d26371-9291-4d09-af38-67b32514940c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541416445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3541416445
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1016170746
Short name T254
Test name
Test status
Simulation time 13894840208 ps
CPU time 1185.76 seconds
Started Aug 03 05:09:59 PM PDT 24
Finished Aug 03 05:29:45 PM PDT 24
Peak memory 288324 kb
Host smart-ecc0e950-a219-4c31-bad8-64a93965a33c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016170746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1016170746
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.86715501
Short name T249
Test name
Test status
Simulation time 10940233854 ps
CPU time 477.63 seconds
Started Aug 03 05:10:49 PM PDT 24
Finished Aug 03 05:18:46 PM PDT 24
Peak memory 248380 kb
Host smart-4952e9af-9cd5-41c0-b530-e2459ff77c86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86715501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.86715501
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3795199131
Short name T130
Test name
Test status
Simulation time 4634028304 ps
CPU time 298.68 seconds
Started Aug 03 04:46:18 PM PDT 24
Finished Aug 03 04:51:17 PM PDT 24
Peak memory 265656 kb
Host smart-b7b5d487-cd3a-4a6d-a5e9-047387a18948
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3795199131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3795199131
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3949961201
Short name T138
Test name
Test status
Simulation time 3204583018 ps
CPU time 205.09 seconds
Started Aug 03 04:46:28 PM PDT 24
Finished Aug 03 04:49:53 PM PDT 24
Peak memory 265548 kb
Host smart-1e101e3d-2241-44b6-ae8b-674817f9c056
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3949961201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3949961201
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.400377342
Short name T328
Test name
Test status
Simulation time 186808885087 ps
CPU time 434.88 seconds
Started Aug 03 05:11:10 PM PDT 24
Finished Aug 03 05:18:25 PM PDT 24
Peak memory 248204 kb
Host smart-a4c99336-d2ea-4a2a-b9d4-c04c0eb3ce34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400377342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.400377342
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2557082230
Short name T93
Test name
Test status
Simulation time 54602742070 ps
CPU time 1867.56 seconds
Started Aug 03 05:10:44 PM PDT 24
Finished Aug 03 05:41:52 PM PDT 24
Peak memory 284792 kb
Host smart-fb3078ce-64b9-44fe-9a19-4b795dcbdae7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557082230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2557082230
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3941848910
Short name T155
Test name
Test status
Simulation time 609259186 ps
CPU time 21.24 seconds
Started Aug 03 04:46:25 PM PDT 24
Finished Aug 03 04:46:47 PM PDT 24
Peak memory 240624 kb
Host smart-a58a556e-dd63-44b5-b44c-038418c209ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3941848910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3941848910
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.217660640
Short name T343
Test name
Test status
Simulation time 43938584600 ps
CPU time 2581.82 seconds
Started Aug 03 05:10:52 PM PDT 24
Finished Aug 03 05:53:54 PM PDT 24
Peak memory 284152 kb
Host smart-d7e3e897-9d6a-4297-bd88-0733a8da637f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217660640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.217660640
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.473644699
Short name T276
Test name
Test status
Simulation time 536875372618 ps
CPU time 9640.5 seconds
Started Aug 03 05:11:35 PM PDT 24
Finished Aug 03 07:52:16 PM PDT 24
Peak memory 330264 kb
Host smart-91bb4c7d-0073-45a3-8e14-cee57d85b70d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473644699 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.473644699
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1939858210
Short name T674
Test name
Test status
Simulation time 14678642265 ps
CPU time 586.39 seconds
Started Aug 03 05:10:03 PM PDT 24
Finished Aug 03 05:19:55 PM PDT 24
Peak memory 248396 kb
Host smart-eac3286d-1f4b-4d18-9b40-46e0def43741
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939858210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1939858210
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3527828203
Short name T225
Test name
Test status
Simulation time 20996214986 ps
CPU time 665.83 seconds
Started Aug 03 05:10:52 PM PDT 24
Finished Aug 03 05:21:58 PM PDT 24
Peak memory 271216 kb
Host smart-2ab9d80d-7290-452f-835c-27fbbf9bde94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527828203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3527828203
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1787735049
Short name T149
Test name
Test status
Simulation time 24449152616 ps
CPU time 490.37 seconds
Started Aug 03 04:46:48 PM PDT 24
Finished Aug 03 04:54:59 PM PDT 24
Peak memory 265612 kb
Host smart-5d728a64-9c67-4aa8-af74-c8f1a6af07c9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787735049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1787735049
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3144428979
Short name T357
Test name
Test status
Simulation time 8760589 ps
CPU time 1.55 seconds
Started Aug 03 04:46:44 PM PDT 24
Finished Aug 03 04:46:45 PM PDT 24
Peak memory 236820 kb
Host smart-8f50993a-f007-4f13-9559-4d76d82c0970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3144428979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3144428979
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2888367947
Short name T48
Test name
Test status
Simulation time 56884594163 ps
CPU time 1150.88 seconds
Started Aug 03 05:09:54 PM PDT 24
Finished Aug 03 05:29:06 PM PDT 24
Peak memory 289048 kb
Host smart-7200a999-f661-41f1-a379-a4277952c2d2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888367947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2888367947
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3519161536
Short name T198
Test name
Test status
Simulation time 55241342596 ps
CPU time 3052.81 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 06:01:03 PM PDT 24
Peak memory 318292 kb
Host smart-08e96a62-359e-47b1-bf4f-9b5f3a0cbe11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519161536 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3519161536
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3021845076
Short name T247
Test name
Test status
Simulation time 109067071779 ps
CPU time 366.5 seconds
Started Aug 03 05:10:23 PM PDT 24
Finished Aug 03 05:16:29 PM PDT 24
Peak memory 255200 kb
Host smart-85880692-b4cd-425b-9de3-b835896b20d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021845076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3021845076
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.988228530
Short name T346
Test name
Test status
Simulation time 27821843259 ps
CPU time 1687.79 seconds
Started Aug 03 05:09:59 PM PDT 24
Finished Aug 03 05:38:07 PM PDT 24
Peak memory 282504 kb
Host smart-981df691-d6ce-49a3-82fc-4aee04f47e04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988228530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.988228530
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.936038409
Short name T169
Test name
Test status
Simulation time 95955464 ps
CPU time 5.96 seconds
Started Aug 03 04:46:02 PM PDT 24
Finished Aug 03 04:46:08 PM PDT 24
Peak memory 237672 kb
Host smart-4faa1cc2-c53e-4229-a2a8-e40f199cc1e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=936038409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.936038409
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2318389694
Short name T134
Test name
Test status
Simulation time 27188693718 ps
CPU time 281.13 seconds
Started Aug 03 04:46:24 PM PDT 24
Finished Aug 03 04:51:06 PM PDT 24
Peak memory 265596 kb
Host smart-805beab5-1c6e-4a33-9c30-6ebd11d1b7b9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318389694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2318389694
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.433426644
Short name T205
Test name
Test status
Simulation time 23269174 ps
CPU time 3 seconds
Started Aug 03 05:09:56 PM PDT 24
Finished Aug 03 05:09:59 PM PDT 24
Peak memory 248600 kb
Host smart-78193528-35e8-4d66-a0f3-8186332e0361
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=433426644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.433426644
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1316960381
Short name T216
Test name
Test status
Simulation time 39786402 ps
CPU time 2.2 seconds
Started Aug 03 05:09:57 PM PDT 24
Finished Aug 03 05:09:59 PM PDT 24
Peak memory 248600 kb
Host smart-72b790f5-78fb-4b91-b923-969e828314bc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1316960381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1316960381
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2208969045
Short name T203
Test name
Test status
Simulation time 22485953 ps
CPU time 2.73 seconds
Started Aug 03 05:10:08 PM PDT 24
Finished Aug 03 05:10:11 PM PDT 24
Peak memory 248664 kb
Host smart-62b0d952-68a2-473e-8ace-6be653f73aa1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2208969045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2208969045
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2929612512
Short name T213
Test name
Test status
Simulation time 72767469 ps
CPU time 2.72 seconds
Started Aug 03 05:10:37 PM PDT 24
Finished Aug 03 05:10:39 PM PDT 24
Peak memory 248572 kb
Host smart-bf6ae77a-9159-456b-ab45-776259bdff25
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2929612512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2929612512
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2191581805
Short name T19
Test name
Test status
Simulation time 2321289752 ps
CPU time 40.9 seconds
Started Aug 03 05:10:01 PM PDT 24
Finished Aug 03 05:10:42 PM PDT 24
Peak memory 256388 kb
Host smart-666ff2dc-3f01-4e67-bd2e-023044eb57cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21915
81805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2191581805
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2310355126
Short name T342
Test name
Test status
Simulation time 43312705243 ps
CPU time 1266.98 seconds
Started Aug 03 05:10:08 PM PDT 24
Finished Aug 03 05:31:15 PM PDT 24
Peak memory 287168 kb
Host smart-03c99404-a271-44f9-92c8-2af0ed1f4c4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310355126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2310355126
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1869846664
Short name T255
Test name
Test status
Simulation time 134280243099 ps
CPU time 1384.83 seconds
Started Aug 03 05:10:31 PM PDT 24
Finished Aug 03 05:33:36 PM PDT 24
Peak memory 288252 kb
Host smart-cf398020-bd1a-4068-a47f-203ed0e17e6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869846664 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1869846664
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1066882421
Short name T235
Test name
Test status
Simulation time 383286894 ps
CPU time 7.38 seconds
Started Aug 03 05:10:44 PM PDT 24
Finished Aug 03 05:10:52 PM PDT 24
Peak memory 247516 kb
Host smart-9e70520b-4e44-4a39-9b22-727e7d3bb21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10668
82421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1066882421
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3304168048
Short name T56
Test name
Test status
Simulation time 265782521 ps
CPU time 16.58 seconds
Started Aug 03 05:10:00 PM PDT 24
Finished Aug 03 05:10:17 PM PDT 24
Peak memory 248296 kb
Host smart-60d707d4-6cd8-4f97-81e2-5a9cf31d84b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33041
68048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3304168048
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1296800471
Short name T80
Test name
Test status
Simulation time 117771958151 ps
CPU time 2771.44 seconds
Started Aug 03 05:10:47 PM PDT 24
Finished Aug 03 05:56:59 PM PDT 24
Peak memory 288940 kb
Host smart-33dd8c1f-2030-4c92-a423-be52a0b54d1b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296800471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1296800471
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1291456684
Short name T148
Test name
Test status
Simulation time 1271371628 ps
CPU time 136.56 seconds
Started Aug 03 04:46:18 PM PDT 24
Finished Aug 03 04:48:35 PM PDT 24
Peak memory 265452 kb
Host smart-95620bf9-60ed-4388-935f-7bfd014bf75d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1291456684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1291456684
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1367443214
Short name T117
Test name
Test status
Simulation time 10184708417 ps
CPU time 146.83 seconds
Started Aug 03 04:46:42 PM PDT 24
Finished Aug 03 04:49:09 PM PDT 24
Peak memory 265628 kb
Host smart-73b6202c-ad75-445b-a2c2-1df6a4e6996d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1367443214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1367443214
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2467408249
Short name T226
Test name
Test status
Simulation time 10667770129 ps
CPU time 242.09 seconds
Started Aug 03 05:09:57 PM PDT 24
Finished Aug 03 05:13:59 PM PDT 24
Peak memory 248356 kb
Host smart-3d7eb574-6ce1-4f7b-8c62-96f19d956458
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467408249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2467408249
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2646588767
Short name T310
Test name
Test status
Simulation time 588506642 ps
CPU time 37.29 seconds
Started Aug 03 05:09:54 PM PDT 24
Finished Aug 03 05:10:31 PM PDT 24
Peak memory 255864 kb
Host smart-ba3dc57d-7e4c-4620-bb7c-da5af7644d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26465
88767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2646588767
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1340655090
Short name T302
Test name
Test status
Simulation time 29525479910 ps
CPU time 1494.29 seconds
Started Aug 03 05:10:02 PM PDT 24
Finished Aug 03 05:34:57 PM PDT 24
Peak memory 289288 kb
Host smart-411aef39-83f1-49fe-878b-81f36b05ebd0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340655090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1340655090
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1295258732
Short name T47
Test name
Test status
Simulation time 383119929 ps
CPU time 36.85 seconds
Started Aug 03 05:10:02 PM PDT 24
Finished Aug 03 05:10:38 PM PDT 24
Peak memory 249348 kb
Host smart-8e3baafe-a26b-43c7-ac9f-e555ab21e169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12952
58732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1295258732
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.13630078
Short name T79
Test name
Test status
Simulation time 224272578 ps
CPU time 13.34 seconds
Started Aug 03 05:10:13 PM PDT 24
Finished Aug 03 05:10:27 PM PDT 24
Peak memory 253348 kb
Host smart-965f9f71-9869-4a73-aeb6-d957e7ffe938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13630
078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.13630078
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1476126560
Short name T13
Test name
Test status
Simulation time 52321555982 ps
CPU time 3121.24 seconds
Started Aug 03 05:10:24 PM PDT 24
Finished Aug 03 06:02:25 PM PDT 24
Peak memory 288480 kb
Host smart-80f3be76-9dc7-498e-94e9-c14aa43497f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476126560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1476126560
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1607092641
Short name T280
Test name
Test status
Simulation time 859810258 ps
CPU time 27.45 seconds
Started Aug 03 05:09:48 PM PDT 24
Finished Aug 03 05:10:15 PM PDT 24
Peak memory 248232 kb
Host smart-f87b1242-8e99-4114-911d-71223b880272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16070
92641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1607092641
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.645946505
Short name T296
Test name
Test status
Simulation time 33899640897 ps
CPU time 1949.81 seconds
Started Aug 03 05:10:30 PM PDT 24
Finished Aug 03 05:43:00 PM PDT 24
Peak memory 272864 kb
Host smart-0b626ca4-b7b7-4d51-9e15-5f788e53de9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645946505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.645946505
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1043829440
Short name T38
Test name
Test status
Simulation time 1752325942 ps
CPU time 49.58 seconds
Started Aug 03 05:10:13 PM PDT 24
Finished Aug 03 05:11:02 PM PDT 24
Peak memory 247748 kb
Host smart-10b1f5b7-50e4-4763-a5a1-247ddf853b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10438
29440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1043829440
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1124431564
Short name T340
Test name
Test status
Simulation time 120913930046 ps
CPU time 2806.86 seconds
Started Aug 03 05:10:43 PM PDT 24
Finished Aug 03 05:57:31 PM PDT 24
Peak memory 288456 kb
Host smart-7e337116-d3f9-4468-8d81-85b117b488b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124431564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1124431564
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1481921142
Short name T288
Test name
Test status
Simulation time 30014374602 ps
CPU time 1754.95 seconds
Started Aug 03 05:09:52 PM PDT 24
Finished Aug 03 05:39:07 PM PDT 24
Peak memory 281184 kb
Host smart-1abc5648-bca3-4aa1-bb19-a12d2861479f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481921142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1481921142
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1062239760
Short name T351
Test name
Test status
Simulation time 17341741655 ps
CPU time 1268.86 seconds
Started Aug 03 05:10:44 PM PDT 24
Finished Aug 03 05:31:53 PM PDT 24
Peak memory 282180 kb
Host smart-67849b65-f552-44c8-a5e5-1ef9e3d23079
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062239760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1062239760
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1499842288
Short name T251
Test name
Test status
Simulation time 38794195192 ps
CPU time 1068.36 seconds
Started Aug 03 05:10:44 PM PDT 24
Finished Aug 03 05:28:32 PM PDT 24
Peak memory 281184 kb
Host smart-91317052-8859-4e3d-863c-86cf280a9532
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499842288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1499842288
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3966935913
Short name T281
Test name
Test status
Simulation time 1396897707 ps
CPU time 21.68 seconds
Started Aug 03 05:10:58 PM PDT 24
Finished Aug 03 05:11:19 PM PDT 24
Peak memory 248392 kb
Host smart-5c5a2037-c019-4b70-bb94-2458f7f15847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39669
35913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3966935913
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1492186989
Short name T301
Test name
Test status
Simulation time 93823710016 ps
CPU time 2798.74 seconds
Started Aug 03 05:11:09 PM PDT 24
Finished Aug 03 05:57:49 PM PDT 24
Peak memory 301444 kb
Host smart-49ec7baf-46bd-4e72-a931-0139e267cf81
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492186989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1492186989
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1513276258
Short name T298
Test name
Test status
Simulation time 901687188 ps
CPU time 44.47 seconds
Started Aug 03 05:11:28 PM PDT 24
Finished Aug 03 05:12:12 PM PDT 24
Peak memory 248244 kb
Host smart-a1d189d6-df94-4ef7-a255-ecfcb0a3d24f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15132
76258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1513276258
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2594103430
Short name T297
Test name
Test status
Simulation time 8611971446 ps
CPU time 763.11 seconds
Started Aug 03 05:10:02 PM PDT 24
Finished Aug 03 05:22:46 PM PDT 24
Peak memory 272964 kb
Host smart-b54ebb26-93cf-48a4-ae1a-7802a030af26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594103430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2594103430
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.452045682
Short name T107
Test name
Test status
Simulation time 13350596172 ps
CPU time 701.45 seconds
Started Aug 03 05:10:27 PM PDT 24
Finished Aug 03 05:22:09 PM PDT 24
Peak memory 265804 kb
Host smart-84087517-f6ff-4373-99fc-35d3a99fccbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452045682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.452045682
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3371316844
Short name T140
Test name
Test status
Simulation time 10780849850 ps
CPU time 316.25 seconds
Started Aug 03 04:46:39 PM PDT 24
Finished Aug 03 04:51:55 PM PDT 24
Peak memory 265676 kb
Host smart-d1b8f6e5-dcd7-425e-9464-be707de30cc5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3371316844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3371316844
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3154376000
Short name T153
Test name
Test status
Simulation time 656316593 ps
CPU time 3.9 seconds
Started Aug 03 04:46:36 PM PDT 24
Finished Aug 03 04:46:40 PM PDT 24
Peak memory 240580 kb
Host smart-3ed948bc-a387-452f-9ab2-927463f2da48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3154376000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3154376000
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2936978796
Short name T163
Test name
Test status
Simulation time 4165810563 ps
CPU time 45.47 seconds
Started Aug 03 04:46:04 PM PDT 24
Finished Aug 03 04:46:50 PM PDT 24
Peak memory 246368 kb
Host smart-e37fa0f7-afd7-48c7-b2d4-2ac42c41a3d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2936978796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2936978796
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1086307992
Short name T119
Test name
Test status
Simulation time 4667523212 ps
CPU time 321.99 seconds
Started Aug 03 04:46:37 PM PDT 24
Finished Aug 03 04:51:59 PM PDT 24
Peak memory 271912 kb
Host smart-6af96e7e-6b61-4fd9-9d33-a1f8f7ae0e1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1086307992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1086307992
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.568278813
Short name T161
Test name
Test status
Simulation time 2190879274 ps
CPU time 37.82 seconds
Started Aug 03 04:46:19 PM PDT 24
Finished Aug 03 04:46:57 PM PDT 24
Peak memory 240684 kb
Host smart-fa9b9c6d-3305-4800-8d05-b474b126e58f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=568278813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.568278813
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.216096787
Short name T154
Test name
Test status
Simulation time 357599327 ps
CPU time 47.97 seconds
Started Aug 03 04:46:26 PM PDT 24
Finished Aug 03 04:47:14 PM PDT 24
Peak memory 240628 kb
Host smart-db96a002-3e9c-42ec-9acd-a832b795a0ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=216096787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.216096787
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3417713666
Short name T160
Test name
Test status
Simulation time 297531345 ps
CPU time 44.17 seconds
Started Aug 03 04:46:10 PM PDT 24
Finished Aug 03 04:46:54 PM PDT 24
Peak memory 246268 kb
Host smart-3ca4a9d2-ccc1-475f-a606-8ef1f32ae55c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3417713666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3417713666
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.369483595
Short name T164
Test name
Test status
Simulation time 169156567 ps
CPU time 3.67 seconds
Started Aug 03 04:46:15 PM PDT 24
Finished Aug 03 04:46:19 PM PDT 24
Peak memory 236644 kb
Host smart-2740e462-8e8c-4c2a-8ee9-376f6cd51e7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=369483595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.369483595
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2056085306
Short name T162
Test name
Test status
Simulation time 637772709 ps
CPU time 41.73 seconds
Started Aug 03 04:46:40 PM PDT 24
Finished Aug 03 04:47:21 PM PDT 24
Peak memory 246092 kb
Host smart-2014e849-9e8b-4671-884b-dd648d6f832e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2056085306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2056085306
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3018940147
Short name T159
Test name
Test status
Simulation time 1140528723 ps
CPU time 34.57 seconds
Started Aug 03 04:46:08 PM PDT 24
Finished Aug 03 04:46:43 PM PDT 24
Peak memory 240576 kb
Host smart-54d3d063-dc66-4789-b665-587b2960e9bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3018940147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3018940147
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3497219669
Short name T170
Test name
Test status
Simulation time 103189853 ps
CPU time 3.21 seconds
Started Aug 03 04:46:18 PM PDT 24
Finished Aug 03 04:46:21 PM PDT 24
Peak memory 237696 kb
Host smart-75d5af30-5091-4c06-ac8c-17e751af3504
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3497219669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3497219669
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.4261500401
Short name T173
Test name
Test status
Simulation time 244664694 ps
CPU time 2.58 seconds
Started Aug 03 04:46:36 PM PDT 24
Finished Aug 03 04:46:39 PM PDT 24
Peak memory 239616 kb
Host smart-2bc2b2e0-a7f9-4a4f-b675-519e8b71d228
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4261500401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.4261500401
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3077808266
Short name T167
Test name
Test status
Simulation time 98095100 ps
CPU time 2.42 seconds
Started Aug 03 04:46:38 PM PDT 24
Finished Aug 03 04:46:41 PM PDT 24
Peak memory 236804 kb
Host smart-fdb63180-ce6c-4358-803e-d9b69f1d53e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3077808266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3077808266
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1621730387
Short name T166
Test name
Test status
Simulation time 61768357 ps
CPU time 3.91 seconds
Started Aug 03 04:46:38 PM PDT 24
Finished Aug 03 04:46:42 PM PDT 24
Peak memory 237692 kb
Host smart-41bba30c-d898-4fa0-97d8-227423d90424
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1621730387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1621730387
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.2937917795
Short name T28
Test name
Test status
Simulation time 66989543852 ps
CPU time 6639.03 seconds
Started Aug 03 05:10:11 PM PDT 24
Finished Aug 03 07:00:51 PM PDT 24
Peak memory 337720 kb
Host smart-22284e30-0568-4680-bfb3-bf2e6b8ef494
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937917795 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.2937917795
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1824638894
Short name T26
Test name
Test status
Simulation time 20379905252 ps
CPU time 767.18 seconds
Started Aug 03 05:10:16 PM PDT 24
Finished Aug 03 05:23:03 PM PDT 24
Peak memory 272524 kb
Host smart-ae11495d-6877-4e72-aca5-3a4317ac54fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824638894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1824638894
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3888120571
Short name T23
Test name
Test status
Simulation time 58589084639 ps
CPU time 3259.47 seconds
Started Aug 03 05:10:51 PM PDT 24
Finished Aug 03 06:05:11 PM PDT 24
Peak memory 289084 kb
Host smart-4503c3bf-7db9-4c95-9ba9-7370d08e88df
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888120571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3888120571
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2444507288
Short name T727
Test name
Test status
Simulation time 1515934918 ps
CPU time 140.49 seconds
Started Aug 03 04:46:02 PM PDT 24
Finished Aug 03 04:48:22 PM PDT 24
Peak memory 240832 kb
Host smart-b7e4d11f-6490-42f1-92b0-34009c66b8f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2444507288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2444507288
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2443408391
Short name T719
Test name
Test status
Simulation time 11886678548 ps
CPU time 406.72 seconds
Started Aug 03 04:46:06 PM PDT 24
Finished Aug 03 04:52:53 PM PDT 24
Peak memory 237816 kb
Host smart-7f4fa0df-d21c-49ee-8e8a-91b2023d56e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2443408391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2443408391
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1068844868
Short name T760
Test name
Test status
Simulation time 117792434 ps
CPU time 10.13 seconds
Started Aug 03 04:46:02 PM PDT 24
Finished Aug 03 04:46:12 PM PDT 24
Peak memory 249276 kb
Host smart-42b32922-f4dc-469d-b522-7a4b720fd532
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1068844868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1068844868
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.464482494
Short name T815
Test name
Test status
Simulation time 44607673 ps
CPU time 7 seconds
Started Aug 03 04:46:02 PM PDT 24
Finished Aug 03 04:46:10 PM PDT 24
Peak memory 239832 kb
Host smart-4ab4f515-cede-48ab-b4bc-46b88b42514d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464482494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.464482494
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1677138675
Short name T813
Test name
Test status
Simulation time 35234682 ps
CPU time 4.2 seconds
Started Aug 03 04:46:01 PM PDT 24
Finished Aug 03 04:46:06 PM PDT 24
Peak memory 240612 kb
Host smart-83b328a6-7b42-4ffb-93c6-f98b44d6e53a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1677138675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1677138675
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2024715250
Short name T778
Test name
Test status
Simulation time 9816108 ps
CPU time 1.45 seconds
Started Aug 03 04:46:03 PM PDT 24
Finished Aug 03 04:46:04 PM PDT 24
Peak memory 237696 kb
Host smart-84156035-3dd7-4595-963d-976dbe072115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2024715250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2024715250
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.732314740
Short name T185
Test name
Test status
Simulation time 450754325 ps
CPU time 25.67 seconds
Started Aug 03 04:46:07 PM PDT 24
Finished Aug 03 04:46:33 PM PDT 24
Peak memory 245848 kb
Host smart-7e13f68c-e5a5-4dc8-9d3a-e24d69a8ea12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=732314740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.732314740
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.617011410
Short name T144
Test name
Test status
Simulation time 6061621128 ps
CPU time 222.65 seconds
Started Aug 03 04:46:00 PM PDT 24
Finished Aug 03 04:49:43 PM PDT 24
Peak memory 271936 kb
Host smart-8256950e-45cd-483e-b6d2-d9d9ee3c885d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=617011410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.617011410
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1206636576
Short name T808
Test name
Test status
Simulation time 2942002057 ps
CPU time 319.09 seconds
Started Aug 03 04:45:57 PM PDT 24
Finished Aug 03 04:51:16 PM PDT 24
Peak memory 265672 kb
Host smart-53df4c24-d5dd-4486-875b-81f39c4ba5f0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206636576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1206636576
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.913160045
Short name T807
Test name
Test status
Simulation time 425454581 ps
CPU time 8.33 seconds
Started Aug 03 04:46:01 PM PDT 24
Finished Aug 03 04:46:10 PM PDT 24
Peak memory 248836 kb
Host smart-98e6f422-63df-4617-9fdb-d885779ae813
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=913160045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.913160045
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1006168259
Short name T787
Test name
Test status
Simulation time 563653596 ps
CPU time 69.82 seconds
Started Aug 03 04:46:00 PM PDT 24
Finished Aug 03 04:47:10 PM PDT 24
Peak memory 237624 kb
Host smart-1d7fcf01-a746-4857-aaeb-3f4191008984
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1006168259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1006168259
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.577303995
Short name T755
Test name
Test status
Simulation time 4450724746 ps
CPU time 270.35 seconds
Started Aug 03 04:46:02 PM PDT 24
Finished Aug 03 04:50:32 PM PDT 24
Peak memory 237816 kb
Host smart-d759e6b0-cef5-44fa-af34-29effc22dfae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=577303995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.577303995
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2894517981
Short name T721
Test name
Test status
Simulation time 247542305 ps
CPU time 5.89 seconds
Started Aug 03 04:46:04 PM PDT 24
Finished Aug 03 04:46:10 PM PDT 24
Peak memory 248852 kb
Host smart-ab0db85a-0d44-484c-b9ad-748af8eb02ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2894517981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2894517981
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.429673467
Short name T749
Test name
Test status
Simulation time 119249772 ps
CPU time 5.62 seconds
Started Aug 03 04:46:01 PM PDT 24
Finished Aug 03 04:46:07 PM PDT 24
Peak memory 240664 kb
Host smart-442bb200-dc9a-422c-bb6a-15834188ae24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429673467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.429673467
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1961606006
Short name T743
Test name
Test status
Simulation time 94360946 ps
CPU time 4.36 seconds
Started Aug 03 04:46:06 PM PDT 24
Finished Aug 03 04:46:10 PM PDT 24
Peak memory 236812 kb
Host smart-729fbeeb-91e0-4216-a4bd-56af848e88da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1961606006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1961606006
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2989789124
Short name T158
Test name
Test status
Simulation time 8551595 ps
CPU time 1.59 seconds
Started Aug 03 04:46:06 PM PDT 24
Finished Aug 03 04:46:07 PM PDT 24
Peak memory 237716 kb
Host smart-7b85ae39-05b1-47a9-b65f-01bd429f410c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2989789124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2989789124
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1272308359
Short name T735
Test name
Test status
Simulation time 1527287501 ps
CPU time 25.7 seconds
Started Aug 03 04:46:05 PM PDT 24
Finished Aug 03 04:46:31 PM PDT 24
Peak memory 245908 kb
Host smart-51e5cb24-2516-48cd-9f8c-e89621eea4b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1272308359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1272308359
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2473421202
Short name T124
Test name
Test status
Simulation time 11650503539 ps
CPU time 154.92 seconds
Started Aug 03 04:46:04 PM PDT 24
Finished Aug 03 04:48:39 PM PDT 24
Peak memory 265736 kb
Host smart-2ee5fd58-4035-49ab-999f-80f84fd6fec5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2473421202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2473421202
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2425593845
Short name T820
Test name
Test status
Simulation time 6634910422 ps
CPU time 452.47 seconds
Started Aug 03 04:46:01 PM PDT 24
Finished Aug 03 04:53:33 PM PDT 24
Peak memory 265680 kb
Host smart-e7fa7979-66c4-4e0f-ae84-bb459c4fd3c9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425593845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2425593845
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1174621256
Short name T799
Test name
Test status
Simulation time 95322355 ps
CPU time 7.2 seconds
Started Aug 03 04:46:04 PM PDT 24
Finished Aug 03 04:46:11 PM PDT 24
Peak memory 248900 kb
Host smart-76511204-3872-4b64-8372-d75b210efe85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1174621256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1174621256
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.972676582
Short name T786
Test name
Test status
Simulation time 110379768 ps
CPU time 8.26 seconds
Started Aug 03 04:46:30 PM PDT 24
Finished Aug 03 04:46:38 PM PDT 24
Peak memory 243736 kb
Host smart-485aab4a-b667-455d-8685-cb363532ae18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972676582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.972676582
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3160317815
Short name T757
Test name
Test status
Simulation time 114212336 ps
CPU time 8.41 seconds
Started Aug 03 04:46:28 PM PDT 24
Finished Aug 03 04:46:37 PM PDT 24
Peak memory 240592 kb
Host smart-f1094c73-9457-4cc0-a13a-4d3c01bf0d05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3160317815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3160317815
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1872166510
Short name T728
Test name
Test status
Simulation time 304547481 ps
CPU time 20.98 seconds
Started Aug 03 04:46:25 PM PDT 24
Finished Aug 03 04:46:46 PM PDT 24
Peak memory 245008 kb
Host smart-b3607f83-6dbd-4c59-9845-ad18247d3aad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1872166510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1872166510
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.4270404746
Short name T146
Test name
Test status
Simulation time 3426832626 ps
CPU time 222.34 seconds
Started Aug 03 04:46:33 PM PDT 24
Finished Aug 03 04:50:16 PM PDT 24
Peak memory 265612 kb
Host smart-67623a45-23c2-4230-988c-f9a74e0d5f33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4270404746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.4270404746
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1524636331
Short name T129
Test name
Test status
Simulation time 8630505387 ps
CPU time 553.26 seconds
Started Aug 03 04:46:28 PM PDT 24
Finished Aug 03 04:55:41 PM PDT 24
Peak memory 265592 kb
Host smart-ed53b0e8-9146-41bd-a2ff-7d89b9b029b5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524636331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1524636331
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.449800731
Short name T771
Test name
Test status
Simulation time 121276663 ps
CPU time 4.96 seconds
Started Aug 03 04:46:40 PM PDT 24
Finished Aug 03 04:46:45 PM PDT 24
Peak memory 248620 kb
Host smart-e448bba5-3b8d-42a6-8dc0-df2d2d040033
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=449800731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.449800731
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.74160875
Short name T816
Test name
Test status
Simulation time 113501332 ps
CPU time 8.5 seconds
Started Aug 03 04:46:26 PM PDT 24
Finished Aug 03 04:46:34 PM PDT 24
Peak memory 255380 kb
Host smart-97793cd7-6cb9-4cab-827d-be8dc2c44be1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74160875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.alert_handler_csr_mem_rw_with_rand_reset.74160875
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1703489770
Short name T716
Test name
Test status
Simulation time 255928273 ps
CPU time 11.35 seconds
Started Aug 03 04:46:29 PM PDT 24
Finished Aug 03 04:46:40 PM PDT 24
Peak memory 237712 kb
Host smart-7c23353d-125d-4725-b309-e918dc5cc714
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1703489770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1703489770
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2333475484
Short name T736
Test name
Test status
Simulation time 10501765 ps
CPU time 1.27 seconds
Started Aug 03 04:46:26 PM PDT 24
Finished Aug 03 04:46:28 PM PDT 24
Peak memory 235780 kb
Host smart-ab35ca47-44a2-4108-8cac-90ea87651af2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2333475484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2333475484
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2136292502
Short name T821
Test name
Test status
Simulation time 269807895 ps
CPU time 17.63 seconds
Started Aug 03 04:46:36 PM PDT 24
Finished Aug 03 04:46:54 PM PDT 24
Peak memory 245012 kb
Host smart-6399ad8e-379a-4fed-8e27-20cdb8eb05fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2136292502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2136292502
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.475218326
Short name T705
Test name
Test status
Simulation time 239943834 ps
CPU time 8.33 seconds
Started Aug 03 04:46:45 PM PDT 24
Finished Aug 03 04:46:54 PM PDT 24
Peak memory 248724 kb
Host smart-548407d9-3a10-48dc-946e-ab9a97026d04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=475218326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.475218326
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1132823933
Short name T789
Test name
Test status
Simulation time 1511034696 ps
CPU time 8.03 seconds
Started Aug 03 04:46:29 PM PDT 24
Finished Aug 03 04:46:37 PM PDT 24
Peak memory 248772 kb
Host smart-e6bf8cd9-8b21-46ad-a9c9-9eb14fa51f0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132823933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1132823933
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.147273939
Short name T802
Test name
Test status
Simulation time 62570620 ps
CPU time 3.41 seconds
Started Aug 03 04:46:24 PM PDT 24
Finished Aug 03 04:46:28 PM PDT 24
Peak memory 240520 kb
Host smart-2d885fde-b6af-4d05-a8a9-e86c170aed74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=147273939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.147273939
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2454632904
Short name T358
Test name
Test status
Simulation time 50207866 ps
CPU time 1.26 seconds
Started Aug 03 04:46:29 PM PDT 24
Finished Aug 03 04:46:31 PM PDT 24
Peak memory 237660 kb
Host smart-eebfe0c9-f383-405f-83cb-4ada32734c9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2454632904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2454632904
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1589340029
Short name T741
Test name
Test status
Simulation time 795148637 ps
CPU time 26.16 seconds
Started Aug 03 04:46:29 PM PDT 24
Finished Aug 03 04:46:55 PM PDT 24
Peak memory 248748 kb
Host smart-4b64745b-d1af-42ed-8e93-80812ee6a77c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1589340029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1589340029
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.693033442
Short name T748
Test name
Test status
Simulation time 1957512570 ps
CPU time 14.36 seconds
Started Aug 03 04:46:36 PM PDT 24
Finished Aug 03 04:46:51 PM PDT 24
Peak memory 248804 kb
Host smart-f3843dd4-9840-4df3-bd16-ea04209a6ddb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=693033442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.693033442
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1789372784
Short name T290
Test name
Test status
Simulation time 472499046 ps
CPU time 30.79 seconds
Started Aug 03 04:46:26 PM PDT 24
Finished Aug 03 04:46:57 PM PDT 24
Peak memory 240616 kb
Host smart-f90f493b-3082-4736-bbff-214ab7a2e4d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1789372784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1789372784
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.310230240
Short name T770
Test name
Test status
Simulation time 201261591 ps
CPU time 9.18 seconds
Started Aug 03 04:46:32 PM PDT 24
Finished Aug 03 04:46:42 PM PDT 24
Peak memory 240616 kb
Host smart-262b3f79-04b6-4bc5-8acc-99e3987d435f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310230240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.310230240
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3172460856
Short name T188
Test name
Test status
Simulation time 181497201 ps
CPU time 5.04 seconds
Started Aug 03 04:46:40 PM PDT 24
Finished Aug 03 04:46:45 PM PDT 24
Peak memory 240640 kb
Host smart-851398fc-ce54-454a-8cf4-dd6a47f8dd85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3172460856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3172460856
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1613691391
Short name T777
Test name
Test status
Simulation time 10249194 ps
CPU time 1.67 seconds
Started Aug 03 04:46:39 PM PDT 24
Finished Aug 03 04:46:41 PM PDT 24
Peak memory 237664 kb
Host smart-acba1e1d-6c72-46ab-959f-b853f1aea6a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1613691391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1613691391
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3245852247
Short name T817
Test name
Test status
Simulation time 514243001 ps
CPU time 38.88 seconds
Started Aug 03 04:46:32 PM PDT 24
Finished Aug 03 04:47:11 PM PDT 24
Peak memory 245856 kb
Host smart-e07d5e61-2153-4a98-9477-315cfb6ed943
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3245852247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3245852247
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3838353547
Short name T150
Test name
Test status
Simulation time 107815519404 ps
CPU time 910.71 seconds
Started Aug 03 04:46:28 PM PDT 24
Finished Aug 03 05:01:39 PM PDT 24
Peak memory 265552 kb
Host smart-4ac71317-c4d4-46fb-ae1b-1eedca9f6839
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838353547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3838353547
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3107402980
Short name T704
Test name
Test status
Simulation time 409777208 ps
CPU time 14.42 seconds
Started Aug 03 04:46:38 PM PDT 24
Finished Aug 03 04:46:52 PM PDT 24
Peak memory 248804 kb
Host smart-7aaf281a-208f-48f3-8a71-c36bbf350793
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3107402980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3107402980
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3875010657
Short name T723
Test name
Test status
Simulation time 480668428 ps
CPU time 5.21 seconds
Started Aug 03 04:46:25 PM PDT 24
Finished Aug 03 04:46:30 PM PDT 24
Peak memory 248856 kb
Host smart-63e4d2b7-6319-4a00-ba4d-65523389028d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875010657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3875010657
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3896098364
Short name T732
Test name
Test status
Simulation time 19453590 ps
CPU time 4.34 seconds
Started Aug 03 04:46:27 PM PDT 24
Finished Aug 03 04:46:32 PM PDT 24
Peak memory 237684 kb
Host smart-72123f66-81e8-423f-9442-554364af9428
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3896098364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3896098364
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1257584415
Short name T156
Test name
Test status
Simulation time 28788455 ps
CPU time 1.25 seconds
Started Aug 03 04:46:25 PM PDT 24
Finished Aug 03 04:46:26 PM PDT 24
Peak memory 236728 kb
Host smart-77655e1d-7b7e-41dd-98dd-91e69d92e2dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1257584415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1257584415
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.381267588
Short name T764
Test name
Test status
Simulation time 411727869 ps
CPU time 11.69 seconds
Started Aug 03 04:46:47 PM PDT 24
Finished Aug 03 04:46:58 PM PDT 24
Peak memory 245896 kb
Host smart-344d1fe6-dcbb-48e9-921f-62a2c56c79a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=381267588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.381267588
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3594150744
Short name T132
Test name
Test status
Simulation time 15349382126 ps
CPU time 1028.29 seconds
Started Aug 03 04:46:37 PM PDT 24
Finished Aug 03 05:03:46 PM PDT 24
Peak memory 265620 kb
Host smart-e47f3bef-1f3f-4a42-9ef3-dea8ad504657
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594150744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3594150744
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3924805151
Short name T810
Test name
Test status
Simulation time 85794778 ps
CPU time 11.59 seconds
Started Aug 03 04:46:40 PM PDT 24
Finished Aug 03 04:46:52 PM PDT 24
Peak memory 248320 kb
Host smart-2744f723-88f6-4bd7-aaab-8f67c59e3f1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3924805151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3924805151
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3840503703
Short name T291
Test name
Test status
Simulation time 50525033 ps
CPU time 2.78 seconds
Started Aug 03 04:46:41 PM PDT 24
Finished Aug 03 04:46:44 PM PDT 24
Peak memory 237656 kb
Host smart-300cc1c0-63cf-416e-b015-496507181be0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3840503703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3840503703
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2036329923
Short name T737
Test name
Test status
Simulation time 125975355 ps
CPU time 9.22 seconds
Started Aug 03 04:46:28 PM PDT 24
Finished Aug 03 04:46:37 PM PDT 24
Peak memory 248816 kb
Host smart-ab86ec79-f6c1-4ea2-a0a3-123aad199042
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036329923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2036329923
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3868107655
Short name T774
Test name
Test status
Simulation time 96418195 ps
CPU time 8.15 seconds
Started Aug 03 04:46:30 PM PDT 24
Finished Aug 03 04:46:39 PM PDT 24
Peak memory 237664 kb
Host smart-6801a051-04d6-4f9f-b2fa-bbca106b7c48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3868107655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3868107655
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2160061031
Short name T761
Test name
Test status
Simulation time 10647221 ps
CPU time 1.31 seconds
Started Aug 03 04:46:26 PM PDT 24
Finished Aug 03 04:46:28 PM PDT 24
Peak memory 237696 kb
Host smart-b9c13259-6f8d-4691-8259-197bdcda9b54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2160061031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2160061031
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1210161914
Short name T701
Test name
Test status
Simulation time 253698792 ps
CPU time 18.34 seconds
Started Aug 03 04:46:46 PM PDT 24
Finished Aug 03 04:47:05 PM PDT 24
Peak memory 240624 kb
Host smart-d6faf0dd-9483-4c8e-b5e3-b56385f522cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1210161914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1210161914
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1298296843
Short name T145
Test name
Test status
Simulation time 32196533711 ps
CPU time 1115.3 seconds
Started Aug 03 04:46:26 PM PDT 24
Finished Aug 03 05:05:01 PM PDT 24
Peak memory 265604 kb
Host smart-5ad7df4e-31a9-4ba2-b8b1-b186f93f85ae
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298296843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1298296843
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.293736333
Short name T766
Test name
Test status
Simulation time 110944225 ps
CPU time 8.15 seconds
Started Aug 03 04:46:39 PM PDT 24
Finished Aug 03 04:46:48 PM PDT 24
Peak memory 246180 kb
Host smart-0d75b9f5-7ee0-4dbe-9c3d-7f27626d42db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=293736333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.293736333
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4191536432
Short name T793
Test name
Test status
Simulation time 4007735735 ps
CPU time 36.21 seconds
Started Aug 03 04:46:34 PM PDT 24
Finished Aug 03 04:47:11 PM PDT 24
Peak memory 246132 kb
Host smart-8b30a3fb-9320-419b-ae2c-ec3007dc8891
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4191536432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.4191536432
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2247272897
Short name T763
Test name
Test status
Simulation time 176833726 ps
CPU time 4.82 seconds
Started Aug 03 04:46:39 PM PDT 24
Finished Aug 03 04:46:44 PM PDT 24
Peak memory 240568 kb
Host smart-e55985b3-f3ff-4a2c-903c-72d7c0a0421c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247272897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2247272897
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1314462041
Short name T744
Test name
Test status
Simulation time 195196722 ps
CPU time 4.89 seconds
Started Aug 03 04:46:44 PM PDT 24
Finished Aug 03 04:46:49 PM PDT 24
Peak memory 237616 kb
Host smart-4b16fa9b-87ce-46bc-ab46-08a6a6a54963
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1314462041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1314462041
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3462833043
Short name T703
Test name
Test status
Simulation time 9727298 ps
CPU time 1.36 seconds
Started Aug 03 04:46:39 PM PDT 24
Finished Aug 03 04:46:40 PM PDT 24
Peak memory 237664 kb
Host smart-ac25122e-fd81-49c7-ad78-0807e3c84aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3462833043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3462833043
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3479878567
Short name T186
Test name
Test status
Simulation time 989791691 ps
CPU time 36.14 seconds
Started Aug 03 04:46:44 PM PDT 24
Finished Aug 03 04:47:21 PM PDT 24
Peak memory 245732 kb
Host smart-75d2b371-e5fb-4837-9e9a-ff1806d2798a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3479878567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3479878567
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3116887132
Short name T126
Test name
Test status
Simulation time 8291383746 ps
CPU time 327.77 seconds
Started Aug 03 04:46:37 PM PDT 24
Finished Aug 03 04:52:05 PM PDT 24
Peak memory 265772 kb
Host smart-2970b2ba-39f3-41be-9727-03296b10b127
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3116887132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3116887132
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3448693170
Short name T116
Test name
Test status
Simulation time 11648165362 ps
CPU time 518.77 seconds
Started Aug 03 04:46:29 PM PDT 24
Finished Aug 03 04:55:08 PM PDT 24
Peak memory 265784 kb
Host smart-0093c4a9-15e1-4559-990c-3c437e5efbe4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448693170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3448693170
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2363758278
Short name T715
Test name
Test status
Simulation time 357708426 ps
CPU time 10.88 seconds
Started Aug 03 04:46:28 PM PDT 24
Finished Aug 03 04:46:39 PM PDT 24
Peak memory 240668 kb
Host smart-a6e9a960-a81f-47ea-a158-7487ddcf1c5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2363758278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2363758278
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.782483340
Short name T199
Test name
Test status
Simulation time 177671579 ps
CPU time 3.71 seconds
Started Aug 03 04:46:25 PM PDT 24
Finished Aug 03 04:46:29 PM PDT 24
Peak memory 236816 kb
Host smart-bb771896-c45a-4357-96d7-2802e1afd328
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=782483340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.782483340
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2318768299
Short name T800
Test name
Test status
Simulation time 58216656 ps
CPU time 5.64 seconds
Started Aug 03 04:46:45 PM PDT 24
Finished Aug 03 04:46:51 PM PDT 24
Peak memory 240688 kb
Host smart-068b2c0f-8986-42f1-9381-fc90be97fb5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318768299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2318768299
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1021960045
Short name T753
Test name
Test status
Simulation time 132455021 ps
CPU time 5.5 seconds
Started Aug 03 04:46:44 PM PDT 24
Finished Aug 03 04:46:50 PM PDT 24
Peak memory 237600 kb
Host smart-a93411e5-4569-4c72-a133-d0af7491c099
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1021960045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1021960045
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.937328154
Short name T752
Test name
Test status
Simulation time 10609367 ps
CPU time 1.45 seconds
Started Aug 03 04:46:34 PM PDT 24
Finished Aug 03 04:46:36 PM PDT 24
Peak memory 236780 kb
Host smart-c548e5c1-0921-4c00-8227-c1abdf41960d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=937328154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.937328154
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2090444425
Short name T726
Test name
Test status
Simulation time 2584734047 ps
CPU time 42.44 seconds
Started Aug 03 04:46:43 PM PDT 24
Finished Aug 03 04:47:25 PM PDT 24
Peak memory 248896 kb
Host smart-d558d0c0-d658-4961-86c4-ccd90bbe4aa7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2090444425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2090444425
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.638767309
Short name T135
Test name
Test status
Simulation time 1652674559 ps
CPU time 102.74 seconds
Started Aug 03 04:46:41 PM PDT 24
Finished Aug 03 04:48:24 PM PDT 24
Peak memory 265504 kb
Host smart-711c45c2-5fca-4401-b4da-27be1a4cf377
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=638767309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.638767309
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1672541961
Short name T139
Test name
Test status
Simulation time 8368027067 ps
CPU time 625.39 seconds
Started Aug 03 04:46:37 PM PDT 24
Finished Aug 03 04:57:03 PM PDT 24
Peak memory 265836 kb
Host smart-6495ab5e-697e-4bee-a907-9e97594a603d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672541961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1672541961
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.343477285
Short name T754
Test name
Test status
Simulation time 2499990007 ps
CPU time 18.39 seconds
Started Aug 03 04:46:48 PM PDT 24
Finished Aug 03 04:47:06 PM PDT 24
Peak memory 248476 kb
Host smart-27fe3e78-f6ce-4548-a920-0ab0ac0054a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=343477285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.343477285
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3612035103
Short name T784
Test name
Test status
Simulation time 167929330 ps
CPU time 13.02 seconds
Started Aug 03 04:46:43 PM PDT 24
Finished Aug 03 04:46:56 PM PDT 24
Peak memory 255372 kb
Host smart-3b98181f-deec-445b-8cb7-2756e6fccc47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612035103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3612035103
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.89226578
Short name T806
Test name
Test status
Simulation time 380375774 ps
CPU time 9.01 seconds
Started Aug 03 04:46:39 PM PDT 24
Finished Aug 03 04:46:49 PM PDT 24
Peak memory 236728 kb
Host smart-768e6f60-8015-4983-9dff-c42673c23572
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=89226578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.89226578
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3927648680
Short name T720
Test name
Test status
Simulation time 10265791 ps
CPU time 1.34 seconds
Started Aug 03 04:46:39 PM PDT 24
Finished Aug 03 04:46:41 PM PDT 24
Peak memory 237708 kb
Host smart-9b38d58c-bf53-4a8b-8b69-016f1561359d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3927648680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3927648680
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.777972332
Short name T825
Test name
Test status
Simulation time 1336004087 ps
CPU time 24.15 seconds
Started Aug 03 04:46:46 PM PDT 24
Finished Aug 03 04:47:10 PM PDT 24
Peak memory 245880 kb
Host smart-e5857a45-a9b5-4afe-bd13-085d94228602
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=777972332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.777972332
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2528473209
Short name T125
Test name
Test status
Simulation time 2297874397 ps
CPU time 176.04 seconds
Started Aug 03 04:46:34 PM PDT 24
Finished Aug 03 04:49:30 PM PDT 24
Peak memory 257364 kb
Host smart-e35d5154-3654-4afa-876f-696a8b3ca8ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2528473209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2528473209
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2429100691
Short name T143
Test name
Test status
Simulation time 19546916255 ps
CPU time 672.39 seconds
Started Aug 03 04:46:36 PM PDT 24
Finished Aug 03 04:57:48 PM PDT 24
Peak memory 265672 kb
Host smart-b88612a7-5b9f-49fc-b249-66133f48f926
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429100691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2429100691
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.786352477
Short name T798
Test name
Test status
Simulation time 285750536 ps
CPU time 19.99 seconds
Started Aug 03 04:46:40 PM PDT 24
Finished Aug 03 04:47:00 PM PDT 24
Peak memory 248912 kb
Host smart-2b6e67d0-e5ca-4775-9e3b-e7add8ccf0cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=786352477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.786352477
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3466308729
Short name T739
Test name
Test status
Simulation time 513644833 ps
CPU time 9.86 seconds
Started Aug 03 04:46:40 PM PDT 24
Finished Aug 03 04:46:50 PM PDT 24
Peak memory 239812 kb
Host smart-741154b4-ab3e-4cf1-946f-347ed29b66ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466308729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3466308729
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1552327297
Short name T709
Test name
Test status
Simulation time 84561115 ps
CPU time 5.23 seconds
Started Aug 03 04:46:46 PM PDT 24
Finished Aug 03 04:46:51 PM PDT 24
Peak memory 236944 kb
Host smart-ae931970-ef3c-43c8-ab9e-01099fa4bfa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1552327297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1552327297
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3726314435
Short name T758
Test name
Test status
Simulation time 11115113 ps
CPU time 1.4 seconds
Started Aug 03 04:46:46 PM PDT 24
Finished Aug 03 04:46:47 PM PDT 24
Peak memory 237628 kb
Host smart-0d2063e1-2bbd-4ffc-a0d2-f49be469cfd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3726314435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3726314435
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3471667096
Short name T803
Test name
Test status
Simulation time 90616087 ps
CPU time 13.15 seconds
Started Aug 03 04:46:36 PM PDT 24
Finished Aug 03 04:46:49 PM PDT 24
Peak memory 245896 kb
Host smart-7e9271e6-0a28-42dc-86b0-c0a658454c15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3471667096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3471667096
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3479502160
Short name T121
Test name
Test status
Simulation time 4314145275 ps
CPU time 158.91 seconds
Started Aug 03 04:46:41 PM PDT 24
Finished Aug 03 04:49:20 PM PDT 24
Peak memory 265620 kb
Host smart-ff18c6ac-0f96-4038-869f-e3b9515cba97
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3479502160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3479502160
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4068819896
Short name T722
Test name
Test status
Simulation time 360994790 ps
CPU time 22.81 seconds
Started Aug 03 04:46:40 PM PDT 24
Finished Aug 03 04:47:03 PM PDT 24
Peak memory 253092 kb
Host smart-42c28c96-b647-46b6-a257-7d184a0ee41b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4068819896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.4068819896
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1864251051
Short name T171
Test name
Test status
Simulation time 1218807848 ps
CPU time 142.71 seconds
Started Aug 03 04:46:11 PM PDT 24
Finished Aug 03 04:48:34 PM PDT 24
Peak memory 240564 kb
Host smart-6d615e6e-503a-491e-90de-e1160151f467
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1864251051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1864251051
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1396338936
Short name T718
Test name
Test status
Simulation time 1705426542 ps
CPU time 113.01 seconds
Started Aug 03 04:46:09 PM PDT 24
Finished Aug 03 04:48:02 PM PDT 24
Peak memory 237620 kb
Host smart-1ba65575-f4bc-4209-b6bd-c04c2de5ecc4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1396338936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1396338936
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1628086819
Short name T257
Test name
Test status
Simulation time 136353373 ps
CPU time 10.38 seconds
Started Aug 03 04:46:09 PM PDT 24
Finished Aug 03 04:46:20 PM PDT 24
Peak memory 249292 kb
Host smart-568cb884-1be8-4a94-9c7d-c42f3257327e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1628086819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1628086819
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.631974230
Short name T730
Test name
Test status
Simulation time 369972246 ps
CPU time 8.22 seconds
Started Aug 03 04:46:15 PM PDT 24
Finished Aug 03 04:46:23 PM PDT 24
Peak memory 241216 kb
Host smart-34ba7d31-b7e9-451f-a8ac-a71ec181f9bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631974230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.alert_handler_csr_mem_rw_with_rand_reset.631974230
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.38411982
Short name T759
Test name
Test status
Simulation time 21522811 ps
CPU time 3.59 seconds
Started Aug 03 04:46:10 PM PDT 24
Finished Aug 03 04:46:14 PM PDT 24
Peak memory 240648 kb
Host smart-bf37bca3-92f4-48aa-adee-793342808e4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=38411982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.38411982
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1707119237
Short name T822
Test name
Test status
Simulation time 11099295 ps
CPU time 1.33 seconds
Started Aug 03 04:46:18 PM PDT 24
Finished Aug 03 04:46:20 PM PDT 24
Peak memory 235772 kb
Host smart-ee07539f-515a-4d02-b37b-d97a3dd37d53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1707119237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1707119237
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.695583677
Short name T172
Test name
Test status
Simulation time 175280784 ps
CPU time 21.08 seconds
Started Aug 03 04:46:09 PM PDT 24
Finished Aug 03 04:46:30 PM PDT 24
Peak memory 245872 kb
Host smart-7c9fd997-ead6-4761-972d-d0aa69b831d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=695583677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.695583677
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.778534777
Short name T122
Test name
Test status
Simulation time 1069550087 ps
CPU time 100.2 seconds
Started Aug 03 04:46:08 PM PDT 24
Finished Aug 03 04:47:48 PM PDT 24
Peak memory 265492 kb
Host smart-a4399e79-c238-4bbb-9f90-361e9899017c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=778534777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.778534777
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2994601135
Short name T128
Test name
Test status
Simulation time 35250612856 ps
CPU time 1223.93 seconds
Started Aug 03 04:46:02 PM PDT 24
Finished Aug 03 05:06:26 PM PDT 24
Peak memory 265584 kb
Host smart-a57aaaae-6170-42f6-bd84-6e80ac687b48
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994601135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2994601135
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3185025387
Short name T756
Test name
Test status
Simulation time 1293160390 ps
CPU time 15.8 seconds
Started Aug 03 04:46:04 PM PDT 24
Finished Aug 03 04:46:20 PM PDT 24
Peak memory 248912 kb
Host smart-f1e4678d-4e81-4de5-8fe0-b41b9a5c9f22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3185025387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3185025387
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3601301080
Short name T734
Test name
Test status
Simulation time 10641521 ps
CPU time 1.41 seconds
Started Aug 03 04:46:35 PM PDT 24
Finished Aug 03 04:46:37 PM PDT 24
Peak memory 237696 kb
Host smart-6b593613-3235-4472-ab1c-5877e283db7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3601301080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3601301080
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1202491485
Short name T765
Test name
Test status
Simulation time 11709486 ps
CPU time 1.45 seconds
Started Aug 03 04:46:34 PM PDT 24
Finished Aug 03 04:46:36 PM PDT 24
Peak memory 236776 kb
Host smart-593bcabf-6175-4c30-bf55-de2c807e0fae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1202491485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1202491485
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.129212290
Short name T792
Test name
Test status
Simulation time 10217561 ps
CPU time 1.27 seconds
Started Aug 03 04:46:37 PM PDT 24
Finished Aug 03 04:46:39 PM PDT 24
Peak memory 237724 kb
Host smart-42f704ee-8a24-4116-aded-698825ff5395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=129212290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.129212290
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.241776742
Short name T731
Test name
Test status
Simulation time 6685826 ps
CPU time 1.42 seconds
Started Aug 03 04:46:44 PM PDT 24
Finished Aug 03 04:46:46 PM PDT 24
Peak memory 236756 kb
Host smart-ce2fe344-2983-4430-b66f-d225a2935375
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=241776742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.241776742
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1258437880
Short name T359
Test name
Test status
Simulation time 9243737 ps
CPU time 1.55 seconds
Started Aug 03 04:46:44 PM PDT 24
Finished Aug 03 04:46:46 PM PDT 24
Peak memory 236816 kb
Host smart-8f934cb6-70bd-44df-9ce8-d64658e9f67c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1258437880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1258437880
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1964547025
Short name T809
Test name
Test status
Simulation time 11183624 ps
CPU time 1.7 seconds
Started Aug 03 04:46:38 PM PDT 24
Finished Aug 03 04:46:40 PM PDT 24
Peak memory 237848 kb
Host smart-d06799ca-e091-4afa-b1ab-10931de6e945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1964547025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1964547025
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.285354426
Short name T769
Test name
Test status
Simulation time 12632885 ps
CPU time 1.44 seconds
Started Aug 03 04:46:39 PM PDT 24
Finished Aug 03 04:46:40 PM PDT 24
Peak memory 237704 kb
Host smart-a1eca40a-59e2-4426-a252-67eb5bc4f19b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=285354426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.285354426
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2229006855
Short name T712
Test name
Test status
Simulation time 11184594 ps
CPU time 1.64 seconds
Started Aug 03 04:46:40 PM PDT 24
Finished Aug 03 04:46:42 PM PDT 24
Peak memory 237676 kb
Host smart-ed4132a8-ba45-4434-8bf9-57dbc6b26142
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2229006855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2229006855
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2952123608
Short name T790
Test name
Test status
Simulation time 8582029 ps
CPU time 1.54 seconds
Started Aug 03 04:46:35 PM PDT 24
Finished Aug 03 04:46:37 PM PDT 24
Peak memory 236824 kb
Host smart-df9e3bee-6d1a-4fc0-9464-3c0b2ae9b6ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2952123608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2952123608
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.322369924
Short name T796
Test name
Test status
Simulation time 1725052625 ps
CPU time 104.49 seconds
Started Aug 03 04:46:12 PM PDT 24
Finished Aug 03 04:47:57 PM PDT 24
Peak memory 240596 kb
Host smart-dd42313f-58d5-4a6c-a272-8e445135d430
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=322369924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.322369924
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3975290542
Short name T714
Test name
Test status
Simulation time 11901030189 ps
CPU time 350.01 seconds
Started Aug 03 04:46:08 PM PDT 24
Finished Aug 03 04:51:59 PM PDT 24
Peak memory 236940 kb
Host smart-4ee1a9db-0086-40af-bbb8-c1eeff6f1e79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3975290542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3975290542
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3716055096
Short name T266
Test name
Test status
Simulation time 927171825 ps
CPU time 11.54 seconds
Started Aug 03 04:46:08 PM PDT 24
Finished Aug 03 04:46:20 PM PDT 24
Peak memory 249244 kb
Host smart-437d7c7c-3acf-445b-a7e9-0f8664f6d452
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3716055096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3716055096
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3941323588
Short name T773
Test name
Test status
Simulation time 107829366 ps
CPU time 7.83 seconds
Started Aug 03 04:46:09 PM PDT 24
Finished Aug 03 04:46:17 PM PDT 24
Peak memory 238612 kb
Host smart-0cd4e288-0f0b-4856-80d9-a721612ee79d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941323588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3941323588
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1502793826
Short name T788
Test name
Test status
Simulation time 51968612 ps
CPU time 4.84 seconds
Started Aug 03 04:46:07 PM PDT 24
Finished Aug 03 04:46:12 PM PDT 24
Peak memory 237700 kb
Host smart-f88702de-803b-4427-969c-909c5274954a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1502793826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1502793826
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.377035103
Short name T239
Test name
Test status
Simulation time 8888982 ps
CPU time 1.51 seconds
Started Aug 03 04:46:09 PM PDT 24
Finished Aug 03 04:46:11 PM PDT 24
Peak memory 237712 kb
Host smart-9265e123-d55e-4f1f-990d-061ed7eadc4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=377035103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.377035103
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2227086642
Short name T189
Test name
Test status
Simulation time 168305990 ps
CPU time 12.34 seconds
Started Aug 03 04:46:08 PM PDT 24
Finished Aug 03 04:46:21 PM PDT 24
Peak memory 245860 kb
Host smart-5693618b-0d67-48c3-b7ce-079343058c9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2227086642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2227086642
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2140780424
Short name T142
Test name
Test status
Simulation time 161790025249 ps
CPU time 598.76 seconds
Started Aug 03 04:46:09 PM PDT 24
Finished Aug 03 04:56:08 PM PDT 24
Peak memory 265772 kb
Host smart-f685a893-bc6f-4bf1-a29b-a3672fa182fa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140780424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2140780424
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2299121331
Short name T819
Test name
Test status
Simulation time 217404761 ps
CPU time 6.97 seconds
Started Aug 03 04:46:08 PM PDT 24
Finished Aug 03 04:46:15 PM PDT 24
Peak memory 253624 kb
Host smart-7156c680-afeb-4bbd-9d1c-6781806ddf7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2299121331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2299121331
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1762949188
Short name T725
Test name
Test status
Simulation time 9410363 ps
CPU time 1.62 seconds
Started Aug 03 04:46:48 PM PDT 24
Finished Aug 03 04:46:50 PM PDT 24
Peak memory 236640 kb
Host smart-e3eabbbc-491d-4dfd-ab8a-7535436864f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1762949188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1762949188
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.427785566
Short name T780
Test name
Test status
Simulation time 9420605 ps
CPU time 1.43 seconds
Started Aug 03 04:46:35 PM PDT 24
Finished Aug 03 04:46:37 PM PDT 24
Peak memory 235700 kb
Host smart-88de7695-869b-4c92-80af-9ef634898715
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=427785566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.427785566
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3058404080
Short name T772
Test name
Test status
Simulation time 27215708 ps
CPU time 1.54 seconds
Started Aug 03 04:46:42 PM PDT 24
Finished Aug 03 04:46:43 PM PDT 24
Peak memory 237652 kb
Host smart-313f8cc2-6ea5-4894-a2cb-41b68868565a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3058404080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3058404080
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.110973856
Short name T267
Test name
Test status
Simulation time 35291566 ps
CPU time 1.34 seconds
Started Aug 03 04:46:35 PM PDT 24
Finished Aug 03 04:46:37 PM PDT 24
Peak memory 235724 kb
Host smart-8cacb90c-8ea0-4299-9b18-a2e3502e88a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=110973856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.110973856
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2140909415
Short name T711
Test name
Test status
Simulation time 9315249 ps
CPU time 1.27 seconds
Started Aug 03 04:46:36 PM PDT 24
Finished Aug 03 04:46:37 PM PDT 24
Peak memory 237624 kb
Host smart-81411fa8-7ee2-4669-b284-ab79089eea51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2140909415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2140909415
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1286369266
Short name T729
Test name
Test status
Simulation time 6388752 ps
CPU time 1.54 seconds
Started Aug 03 04:46:38 PM PDT 24
Finished Aug 03 04:46:39 PM PDT 24
Peak memory 237732 kb
Host smart-fb0e81ac-4163-4f8f-92b3-2a69b79142e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1286369266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1286369266
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3685640170
Short name T717
Test name
Test status
Simulation time 10235413 ps
CPU time 1.47 seconds
Started Aug 03 04:46:41 PM PDT 24
Finished Aug 03 04:46:43 PM PDT 24
Peak memory 237680 kb
Host smart-9738bb79-60a0-4749-9657-6b73cc5c6887
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3685640170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3685640170
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3981705032
Short name T824
Test name
Test status
Simulation time 8070628 ps
CPU time 1.5 seconds
Started Aug 03 04:46:34 PM PDT 24
Finished Aug 03 04:46:35 PM PDT 24
Peak memory 235732 kb
Host smart-9dfafc59-0ed6-442c-b7a4-543af320cf36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3981705032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3981705032
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1355869404
Short name T767
Test name
Test status
Simulation time 14498414 ps
CPU time 1.55 seconds
Started Aug 03 04:46:36 PM PDT 24
Finished Aug 03 04:46:37 PM PDT 24
Peak memory 237712 kb
Host smart-49bc496b-6059-4676-a87a-90022a342a60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1355869404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1355869404
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.4279152672
Short name T781
Test name
Test status
Simulation time 6628131 ps
CPU time 1.46 seconds
Started Aug 03 04:46:43 PM PDT 24
Finished Aug 03 04:46:45 PM PDT 24
Peak memory 237664 kb
Host smart-5fc16f20-542f-41f6-bea1-a6a0fb23e7c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4279152672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.4279152672
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2779610261
Short name T702
Test name
Test status
Simulation time 1754731370 ps
CPU time 129.43 seconds
Started Aug 03 04:46:15 PM PDT 24
Finished Aug 03 04:48:25 PM PDT 24
Peak memory 237660 kb
Host smart-55a51fbc-f8c8-4cfc-9886-3d468cab991b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2779610261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2779610261
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3319267474
Short name T791
Test name
Test status
Simulation time 6530138576 ps
CPU time 225.29 seconds
Started Aug 03 04:46:17 PM PDT 24
Finished Aug 03 04:50:03 PM PDT 24
Peak memory 237352 kb
Host smart-c4b4475b-6d1b-415f-895f-57f430ca7869
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3319267474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3319267474
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3129630280
Short name T742
Test name
Test status
Simulation time 201263867 ps
CPU time 8.45 seconds
Started Aug 03 04:46:09 PM PDT 24
Finished Aug 03 04:46:18 PM PDT 24
Peak memory 249184 kb
Host smart-c5e102d4-e429-4272-9a2d-8c7f114c8a35
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3129630280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3129630280
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2977746504
Short name T785
Test name
Test status
Simulation time 172335846 ps
CPU time 12.61 seconds
Started Aug 03 04:46:19 PM PDT 24
Finished Aug 03 04:46:32 PM PDT 24
Peak memory 254892 kb
Host smart-5a787f8c-f89e-4064-ac46-2c4f3f174c68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977746504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2977746504
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.4069358553
Short name T797
Test name
Test status
Simulation time 65654838 ps
CPU time 5.82 seconds
Started Aug 03 04:46:15 PM PDT 24
Finished Aug 03 04:46:21 PM PDT 24
Peak memory 240600 kb
Host smart-4ba28e1f-37b9-4f5d-8587-75dcc68868c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4069358553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.4069358553
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2098978916
Short name T355
Test name
Test status
Simulation time 10712866 ps
CPU time 1.31 seconds
Started Aug 03 04:46:12 PM PDT 24
Finished Aug 03 04:46:13 PM PDT 24
Peak memory 237648 kb
Host smart-67b025c9-f0b2-486e-92a6-7052dc2b7a98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2098978916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2098978916
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1331020041
Short name T750
Test name
Test status
Simulation time 277857679 ps
CPU time 19.02 seconds
Started Aug 03 04:46:18 PM PDT 24
Finished Aug 03 04:46:37 PM PDT 24
Peak memory 244988 kb
Host smart-1099e6c8-4549-412a-8769-b0505ef89ddc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1331020041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1331020041
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.820089598
Short name T265
Test name
Test status
Simulation time 1179871694 ps
CPU time 20.81 seconds
Started Aug 03 04:46:08 PM PDT 24
Finished Aug 03 04:46:29 PM PDT 24
Peak memory 248908 kb
Host smart-065c6541-b7a9-4873-8d8c-f030753df22f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=820089598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.820089598
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.240819098
Short name T168
Test name
Test status
Simulation time 68248077 ps
CPU time 2.87 seconds
Started Aug 03 04:46:09 PM PDT 24
Finished Aug 03 04:46:12 PM PDT 24
Peak memory 237648 kb
Host smart-0474e533-40c9-4c81-9372-32035fe7bfa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=240819098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.240819098
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2609685536
Short name T812
Test name
Test status
Simulation time 14368090 ps
CPU time 1.43 seconds
Started Aug 03 04:46:41 PM PDT 24
Finished Aug 03 04:46:42 PM PDT 24
Peak memory 236832 kb
Host smart-8a48aa8b-e46f-445a-81a6-b16dbe2b72c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2609685536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2609685536
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.339130099
Short name T783
Test name
Test status
Simulation time 15544944 ps
CPU time 1.29 seconds
Started Aug 03 04:46:45 PM PDT 24
Finished Aug 03 04:46:46 PM PDT 24
Peak memory 237712 kb
Host smart-0784d7cb-0078-4327-bae4-a67ec5698977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=339130099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.339130099
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2478091027
Short name T768
Test name
Test status
Simulation time 30219839 ps
CPU time 1.28 seconds
Started Aug 03 04:46:44 PM PDT 24
Finished Aug 03 04:46:46 PM PDT 24
Peak memory 236784 kb
Host smart-ef361657-d88e-4dd6-bda6-654e9dc411ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2478091027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2478091027
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.4102781513
Short name T740
Test name
Test status
Simulation time 19118090 ps
CPU time 1.46 seconds
Started Aug 03 04:46:37 PM PDT 24
Finished Aug 03 04:46:39 PM PDT 24
Peak memory 237712 kb
Host smart-52a6237f-8b7f-4a67-a6b3-9d50e8ca8e75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4102781513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.4102781513
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.343952485
Short name T804
Test name
Test status
Simulation time 16777997 ps
CPU time 1.39 seconds
Started Aug 03 04:46:38 PM PDT 24
Finished Aug 03 04:46:39 PM PDT 24
Peak memory 236764 kb
Host smart-43849aa8-6c05-45f0-ab1d-77447b7be575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=343952485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.343952485
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2636557244
Short name T747
Test name
Test status
Simulation time 8497957 ps
CPU time 1.55 seconds
Started Aug 03 04:46:41 PM PDT 24
Finished Aug 03 04:46:43 PM PDT 24
Peak memory 235676 kb
Host smart-3375dc43-8dae-4b50-ae13-9209875b22ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2636557244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2636557244
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1077299553
Short name T794
Test name
Test status
Simulation time 6776262 ps
CPU time 1.42 seconds
Started Aug 03 04:46:44 PM PDT 24
Finished Aug 03 04:46:46 PM PDT 24
Peak memory 236752 kb
Host smart-df4248a6-006f-4532-81c9-9e345bf0fa74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1077299553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1077299553
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3699535510
Short name T795
Test name
Test status
Simulation time 14198074 ps
CPU time 1.38 seconds
Started Aug 03 04:46:40 PM PDT 24
Finished Aug 03 04:46:41 PM PDT 24
Peak memory 236836 kb
Host smart-80b70db8-4a8f-46e2-aead-3f104263f4f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3699535510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3699535510
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2951126012
Short name T805
Test name
Test status
Simulation time 9323490 ps
CPU time 1.32 seconds
Started Aug 03 04:46:40 PM PDT 24
Finished Aug 03 04:46:42 PM PDT 24
Peak memory 235740 kb
Host smart-893ad71e-66f4-4f01-a47b-24d7c71cdfb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2951126012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2951126012
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3647632917
Short name T811
Test name
Test status
Simulation time 6568820 ps
CPU time 1.53 seconds
Started Aug 03 04:46:43 PM PDT 24
Finished Aug 03 04:46:45 PM PDT 24
Peak memory 236828 kb
Host smart-69d4c98a-28ac-469d-827b-39091b32e4cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3647632917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3647632917
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.4214638227
Short name T707
Test name
Test status
Simulation time 311346961 ps
CPU time 7.23 seconds
Started Aug 03 04:46:22 PM PDT 24
Finished Aug 03 04:46:29 PM PDT 24
Peak memory 241160 kb
Host smart-7d8cea5f-559a-4587-9b1b-177f0e58d139
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214638227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.4214638227
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1953661111
Short name T801
Test name
Test status
Simulation time 40512814 ps
CPU time 5.19 seconds
Started Aug 03 04:46:23 PM PDT 24
Finished Aug 03 04:46:28 PM PDT 24
Peak memory 236764 kb
Host smart-e64c8b33-6bf9-4a7a-94a8-a977f1cd14a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1953661111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1953661111
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.162136243
Short name T708
Test name
Test status
Simulation time 7276773 ps
CPU time 1.5 seconds
Started Aug 03 04:46:30 PM PDT 24
Finished Aug 03 04:46:31 PM PDT 24
Peak memory 236836 kb
Host smart-f2457c80-8441-4dff-9318-00807b39c57d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=162136243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.162136243
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.79794749
Short name T190
Test name
Test status
Simulation time 325542910 ps
CPU time 22.54 seconds
Started Aug 03 04:46:17 PM PDT 24
Finished Aug 03 04:46:40 PM PDT 24
Peak memory 248788 kb
Host smart-f4dba522-744e-49e2-92b5-72f9d65e2c2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=79794749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outst
anding.79794749
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.185539640
Short name T823
Test name
Test status
Simulation time 143895749 ps
CPU time 10.09 seconds
Started Aug 03 04:46:15 PM PDT 24
Finished Aug 03 04:46:25 PM PDT 24
Peak memory 253460 kb
Host smart-e04872f0-0501-43aa-a39d-a9eaad217d30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=185539640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.185539640
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1548474186
Short name T782
Test name
Test status
Simulation time 115548453 ps
CPU time 10.2 seconds
Started Aug 03 04:46:15 PM PDT 24
Finished Aug 03 04:46:25 PM PDT 24
Peak memory 242824 kb
Host smart-18229482-4ad3-4ec6-a3ea-3f28a7937519
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548474186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1548474186
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2322297458
Short name T184
Test name
Test status
Simulation time 50391076 ps
CPU time 4.61 seconds
Started Aug 03 04:46:18 PM PDT 24
Finished Aug 03 04:46:23 PM PDT 24
Peak memory 240604 kb
Host smart-7e171410-0806-4db6-8952-abde65a8e2a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2322297458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2322297458
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3193367178
Short name T157
Test name
Test status
Simulation time 14794148 ps
CPU time 1.55 seconds
Started Aug 03 04:46:16 PM PDT 24
Finished Aug 03 04:46:18 PM PDT 24
Peak memory 237692 kb
Host smart-75ba9432-f755-4ca4-b17e-1c2bbfcf408e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3193367178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3193367178
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1087027369
Short name T762
Test name
Test status
Simulation time 1997071756 ps
CPU time 41.03 seconds
Started Aug 03 04:46:20 PM PDT 24
Finished Aug 03 04:47:01 PM PDT 24
Peak memory 245908 kb
Host smart-3c579b75-b4a7-4793-b5f0-ac3883637f81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1087027369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1087027369
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2061884054
Short name T136
Test name
Test status
Simulation time 3205825441 ps
CPU time 124.45 seconds
Started Aug 03 04:46:16 PM PDT 24
Finished Aug 03 04:48:21 PM PDT 24
Peak memory 265612 kb
Host smart-5677555a-8372-455c-8711-f80897d2ffc7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2061884054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2061884054
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.662802703
Short name T713
Test name
Test status
Simulation time 150341381 ps
CPU time 9.51 seconds
Started Aug 03 04:46:17 PM PDT 24
Finished Aug 03 04:46:27 PM PDT 24
Peak memory 254648 kb
Host smart-1743fe10-abc7-4280-a068-731f196ff868
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=662802703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.662802703
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2610698638
Short name T745
Test name
Test status
Simulation time 411096032 ps
CPU time 6.99 seconds
Started Aug 03 04:46:22 PM PDT 24
Finished Aug 03 04:46:29 PM PDT 24
Peak memory 241024 kb
Host smart-519837bb-3d45-4d00-b10d-6b9888c5073f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610698638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2610698638
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2277417625
Short name T775
Test name
Test status
Simulation time 123887220 ps
CPU time 5.6 seconds
Started Aug 03 04:46:22 PM PDT 24
Finished Aug 03 04:46:38 PM PDT 24
Peak memory 237668 kb
Host smart-9ab69d93-0abd-4785-a116-add2dc6c0eb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2277417625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2277417625
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1549831655
Short name T818
Test name
Test status
Simulation time 6775847 ps
CPU time 1.52 seconds
Started Aug 03 04:46:18 PM PDT 24
Finished Aug 03 04:46:20 PM PDT 24
Peak memory 237640 kb
Host smart-94c0b4ac-d7c9-4b7a-8808-3e87b843b7b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1549831655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1549831655
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.921806656
Short name T710
Test name
Test status
Simulation time 94715746 ps
CPU time 11.19 seconds
Started Aug 03 04:46:29 PM PDT 24
Finished Aug 03 04:46:40 PM PDT 24
Peak memory 244988 kb
Host smart-b47ac72e-fb61-4a5c-9bad-b3c4b39848b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=921806656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.921806656
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2391834732
Short name T151
Test name
Test status
Simulation time 2299950286 ps
CPU time 327.85 seconds
Started Aug 03 04:46:17 PM PDT 24
Finished Aug 03 04:51:45 PM PDT 24
Peak memory 270296 kb
Host smart-c83bfa07-0fcb-4eb7-b9aa-2cd9d025f645
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391834732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2391834732
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3490115114
Short name T733
Test name
Test status
Simulation time 136454524 ps
CPU time 10.01 seconds
Started Aug 03 04:46:17 PM PDT 24
Finished Aug 03 04:46:27 PM PDT 24
Peak memory 248444 kb
Host smart-e3e19a3f-2ab7-4983-9f04-745772ac228f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3490115114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3490115114
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2536973175
Short name T738
Test name
Test status
Simulation time 411046755 ps
CPU time 5.62 seconds
Started Aug 03 04:46:18 PM PDT 24
Finished Aug 03 04:46:24 PM PDT 24
Peak memory 240400 kb
Host smart-2e1d4cd4-fba5-4c27-8fba-b2dcddf6bfbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536973175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2536973175
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3277678607
Short name T706
Test name
Test status
Simulation time 55515337 ps
CPU time 5.04 seconds
Started Aug 03 04:46:27 PM PDT 24
Finished Aug 03 04:46:32 PM PDT 24
Peak memory 237620 kb
Host smart-f96959f1-e7ac-457a-8e10-8e68ab910476
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3277678607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3277678607
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.702813473
Short name T779
Test name
Test status
Simulation time 11864233 ps
CPU time 1.56 seconds
Started Aug 03 04:46:25 PM PDT 24
Finished Aug 03 04:46:27 PM PDT 24
Peak memory 237700 kb
Host smart-a143814d-02eb-4205-9892-3ea7cea50627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=702813473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.702813473
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1417448349
Short name T776
Test name
Test status
Simulation time 1217486518 ps
CPU time 44.11 seconds
Started Aug 03 04:46:22 PM PDT 24
Finished Aug 03 04:47:06 PM PDT 24
Peak memory 248844 kb
Host smart-4f480c6b-c0c5-4695-b2eb-47b93002a38d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1417448349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1417448349
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1833414626
Short name T141
Test name
Test status
Simulation time 2297712629 ps
CPU time 158.67 seconds
Started Aug 03 04:46:17 PM PDT 24
Finished Aug 03 04:48:56 PM PDT 24
Peak memory 265592 kb
Host smart-40584419-2004-405f-9d0c-b55411449b52
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1833414626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1833414626
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.473129320
Short name T152
Test name
Test status
Simulation time 7628357679 ps
CPU time 474.23 seconds
Started Aug 03 04:46:15 PM PDT 24
Finished Aug 03 04:54:10 PM PDT 24
Peak memory 265592 kb
Host smart-58f2f108-b918-4d02-8a0f-2c7faf51a5a7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473129320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.473129320
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3207320948
Short name T700
Test name
Test status
Simulation time 329688478 ps
CPU time 9.98 seconds
Started Aug 03 04:46:14 PM PDT 24
Finished Aug 03 04:46:24 PM PDT 24
Peak memory 248744 kb
Host smart-459c745c-5894-4d2a-9c98-f1f1ffd4c4e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3207320948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3207320948
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1331921335
Short name T724
Test name
Test status
Simulation time 275874827 ps
CPU time 11.12 seconds
Started Aug 03 04:46:25 PM PDT 24
Finished Aug 03 04:46:36 PM PDT 24
Peak memory 256328 kb
Host smart-fc61d020-08c9-42ec-933e-bceebbcaa7fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331921335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1331921335
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.4277817732
Short name T187
Test name
Test status
Simulation time 104916250 ps
CPU time 3.67 seconds
Started Aug 03 04:46:31 PM PDT 24
Finished Aug 03 04:46:35 PM PDT 24
Peak memory 237576 kb
Host smart-3b83ed0d-18ea-462c-897f-2dddbc32a13e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4277817732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.4277817732
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.4010678946
Short name T746
Test name
Test status
Simulation time 37098621 ps
CPU time 1.38 seconds
Started Aug 03 04:46:24 PM PDT 24
Finished Aug 03 04:46:25 PM PDT 24
Peak memory 236684 kb
Host smart-89e63a9e-152b-4e7e-ae0d-06611c024982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4010678946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.4010678946
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3052615928
Short name T751
Test name
Test status
Simulation time 8188319695 ps
CPU time 36.21 seconds
Started Aug 03 04:46:26 PM PDT 24
Finished Aug 03 04:47:03 PM PDT 24
Peak memory 244992 kb
Host smart-e2d878d0-448b-472a-baff-00c3bf0fddcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3052615928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3052615928
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.530105605
Short name T133
Test name
Test status
Simulation time 5175462873 ps
CPU time 188.83 seconds
Started Aug 03 04:46:19 PM PDT 24
Finished Aug 03 04:49:28 PM PDT 24
Peak memory 257424 kb
Host smart-b5ae6017-1a78-4bc3-b33a-053c3133d07d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=530105605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.530105605
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4095519227
Short name T814
Test name
Test status
Simulation time 886633664 ps
CPU time 17.69 seconds
Started Aug 03 04:46:23 PM PDT 24
Finished Aug 03 04:46:41 PM PDT 24
Peak memory 247560 kb
Host smart-af5b7fcf-1a3f-431f-8b00-721d0f02e066
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4095519227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.4095519227
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2125931033
Short name T98
Test name
Test status
Simulation time 13412421790 ps
CPU time 1356.23 seconds
Started Aug 03 05:09:45 PM PDT 24
Finished Aug 03 05:32:22 PM PDT 24
Peak memory 289092 kb
Host smart-8eac2be7-fb17-4da5-9674-1955208edbc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125931033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2125931033
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1744323081
Short name T372
Test name
Test status
Simulation time 2396430148 ps
CPU time 27.01 seconds
Started Aug 03 05:10:03 PM PDT 24
Finished Aug 03 05:10:30 PM PDT 24
Peak memory 248296 kb
Host smart-12a85ef6-3bc4-4dc6-aa6b-148717c15e68
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1744323081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1744323081
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2954936131
Short name T463
Test name
Test status
Simulation time 15084624492 ps
CPU time 206.29 seconds
Started Aug 03 05:09:55 PM PDT 24
Finished Aug 03 05:13:22 PM PDT 24
Peak memory 256484 kb
Host smart-4335ac2a-9b1a-48a7-95d7-82178377a96c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29549
36131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2954936131
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.690835257
Short name T183
Test name
Test status
Simulation time 528706768 ps
CPU time 31.81 seconds
Started Aug 03 05:09:44 PM PDT 24
Finished Aug 03 05:10:16 PM PDT 24
Peak memory 248280 kb
Host smart-e7001fe8-1413-4966-8cea-e85a66d6be1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69083
5257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.690835257
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1629183001
Short name T651
Test name
Test status
Simulation time 127170130691 ps
CPU time 1480.74 seconds
Started Aug 03 05:09:54 PM PDT 24
Finished Aug 03 05:34:36 PM PDT 24
Peak memory 272936 kb
Host smart-349d3c29-c546-4dac-a222-f16e432275c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629183001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1629183001
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2463022840
Short name T668
Test name
Test status
Simulation time 97267772957 ps
CPU time 2630.46 seconds
Started Aug 03 05:09:59 PM PDT 24
Finished Aug 03 05:53:50 PM PDT 24
Peak memory 280536 kb
Host smart-f2fa9d2e-faec-4471-aa4a-2bba716cd403
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463022840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2463022840
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2209272507
Short name T409
Test name
Test status
Simulation time 5932067741 ps
CPU time 36.25 seconds
Started Aug 03 05:09:52 PM PDT 24
Finished Aug 03 05:10:28 PM PDT 24
Peak memory 255796 kb
Host smart-17b35490-cfbd-4ee2-9869-507d8bee4d3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22092
72507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2209272507
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.425145497
Short name T8
Test name
Test status
Simulation time 1658874608 ps
CPU time 26 seconds
Started Aug 03 05:10:03 PM PDT 24
Finished Aug 03 05:10:29 PM PDT 24
Peak memory 275656 kb
Host smart-d024d941-4c7a-4631-aaba-5d07b9da10ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=425145497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.425145497
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2024430551
Short name T113
Test name
Test status
Simulation time 761522577 ps
CPU time 41.29 seconds
Started Aug 03 05:09:55 PM PDT 24
Finished Aug 03 05:10:36 PM PDT 24
Peak memory 255768 kb
Host smart-c10683d7-6b7b-4da0-a39b-18289afadfc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20244
30551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2024430551
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1358002065
Short name T628
Test name
Test status
Simulation time 2434583987 ps
CPU time 74.43 seconds
Started Aug 03 05:09:41 PM PDT 24
Finished Aug 03 05:10:57 PM PDT 24
Peak memory 255624 kb
Host smart-2aa9a18c-3565-4403-a602-e054fc6c3918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13580
02065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1358002065
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.809351395
Short name T221
Test name
Test status
Simulation time 11773470004 ps
CPU time 1101.26 seconds
Started Aug 03 05:09:54 PM PDT 24
Finished Aug 03 05:28:16 PM PDT 24
Peak memory 287376 kb
Host smart-077b790e-c01b-4208-9b78-90d91d8630be
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809351395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.809351395
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.4170974382
Short name T570
Test name
Test status
Simulation time 45614601994 ps
CPU time 748.95 seconds
Started Aug 03 05:09:45 PM PDT 24
Finished Aug 03 05:22:15 PM PDT 24
Peak memory 273032 kb
Host smart-e9eb0960-3baa-4154-af0f-6f4047ae8322
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170974382 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.4170974382
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2056408237
Short name T517
Test name
Test status
Simulation time 68856576497 ps
CPU time 1235.05 seconds
Started Aug 03 05:10:01 PM PDT 24
Finished Aug 03 05:30:36 PM PDT 24
Peak memory 264780 kb
Host smart-31861ee3-ef49-44c9-a5e9-b010fb1b8d2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056408237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2056408237
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.954472856
Short name T647
Test name
Test status
Simulation time 217449146 ps
CPU time 11.46 seconds
Started Aug 03 05:09:49 PM PDT 24
Finished Aug 03 05:10:01 PM PDT 24
Peak memory 248336 kb
Host smart-711c9800-910c-4fbb-abd0-ae21157a7d8a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=954472856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.954472856
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2732205297
Short name T499
Test name
Test status
Simulation time 1398415633 ps
CPU time 121.78 seconds
Started Aug 03 05:09:54 PM PDT 24
Finished Aug 03 05:11:57 PM PDT 24
Peak memory 250260 kb
Host smart-6a112390-8b9b-4505-bd62-d00b6d82a804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27322
05297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2732205297
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.331177735
Short name T653
Test name
Test status
Simulation time 476874319 ps
CPU time 25.23 seconds
Started Aug 03 05:09:57 PM PDT 24
Finished Aug 03 05:10:22 PM PDT 24
Peak memory 247912 kb
Host smart-ebb21622-a39b-4123-8ff3-9ebd1ab20703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33117
7735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.331177735
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1067332342
Short name T227
Test name
Test status
Simulation time 14288527315 ps
CPU time 1239.69 seconds
Started Aug 03 05:09:55 PM PDT 24
Finished Aug 03 05:30:35 PM PDT 24
Peak memory 289308 kb
Host smart-27b7d786-1a7c-469e-ad33-fae5bd8cb799
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067332342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1067332342
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2460400450
Short name T392
Test name
Test status
Simulation time 214166158060 ps
CPU time 2218.3 seconds
Started Aug 03 05:10:01 PM PDT 24
Finished Aug 03 05:46:59 PM PDT 24
Peak memory 272936 kb
Host smart-4ccc95b2-565e-4dd2-a18e-7195d33c32e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460400450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2460400450
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.791541560
Short name T231
Test name
Test status
Simulation time 4642272502 ps
CPU time 192.27 seconds
Started Aug 03 05:09:56 PM PDT 24
Finished Aug 03 05:13:09 PM PDT 24
Peak memory 248396 kb
Host smart-5606d5aa-ceac-4033-b664-b9d56cdba39b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791541560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.791541560
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2681696360
Short name T194
Test name
Test status
Simulation time 163055397 ps
CPU time 9.52 seconds
Started Aug 03 05:09:55 PM PDT 24
Finished Aug 03 05:10:05 PM PDT 24
Peak memory 254760 kb
Host smart-9907a6b2-d5b8-4422-9f8b-7123e03bdb0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26816
96360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2681696360
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1948385741
Short name T71
Test name
Test status
Simulation time 214094141 ps
CPU time 9.83 seconds
Started Aug 03 05:10:00 PM PDT 24
Finished Aug 03 05:10:10 PM PDT 24
Peak memory 255396 kb
Host smart-d9f3588b-9d3e-4d93-910d-62e8d43a8450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19483
85741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1948385741
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.409597673
Short name T9
Test name
Test status
Simulation time 1122842501 ps
CPU time 14.01 seconds
Started Aug 03 05:09:59 PM PDT 24
Finished Aug 03 05:10:14 PM PDT 24
Peak memory 269700 kb
Host smart-72836898-67ac-46d7-9839-04125227b2c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=409597673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.409597673
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.895402548
Short name T414
Test name
Test status
Simulation time 34205367 ps
CPU time 2.82 seconds
Started Aug 03 05:09:59 PM PDT 24
Finished Aug 03 05:10:02 PM PDT 24
Peak memory 248656 kb
Host smart-b3fff117-03a3-4bf8-8522-87a878e7343f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89540
2548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.895402548
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3308218742
Short name T682
Test name
Test status
Simulation time 1522336465 ps
CPU time 21.77 seconds
Started Aug 03 05:09:56 PM PDT 24
Finished Aug 03 05:10:18 PM PDT 24
Peak memory 248740 kb
Host smart-617fac73-9e6d-4952-8b64-1455614de832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33082
18742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3308218742
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.840999404
Short name T400
Test name
Test status
Simulation time 92309338375 ps
CPU time 1293.46 seconds
Started Aug 03 05:10:02 PM PDT 24
Finished Aug 03 05:31:36 PM PDT 24
Peak memory 265828 kb
Host smart-ac17bed4-7501-40b4-b3c8-0b1f28f06558
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840999404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.840999404
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.840900750
Short name T625
Test name
Test status
Simulation time 3788980173 ps
CPU time 40.7 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 05:10:51 PM PDT 24
Peak memory 248380 kb
Host smart-be2fa901-e682-43e9-9f12-f52139a632a8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=840900750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.840900750
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3154219628
Short name T481
Test name
Test status
Simulation time 13014569553 ps
CPU time 173.99 seconds
Started Aug 03 05:10:01 PM PDT 24
Finished Aug 03 05:12:55 PM PDT 24
Peak memory 250760 kb
Host smart-2079e1d5-d19c-4a8e-85be-d92138c1e888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31542
19628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3154219628
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3802183284
Short name T593
Test name
Test status
Simulation time 3160357045 ps
CPU time 46.72 seconds
Started Aug 03 05:10:15 PM PDT 24
Finished Aug 03 05:11:02 PM PDT 24
Peak memory 256324 kb
Host smart-ef7a55cb-27be-4d30-9d6f-478eabea0a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38021
83284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3802183284
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.657662296
Short name T666
Test name
Test status
Simulation time 15729491719 ps
CPU time 729.41 seconds
Started Aug 03 05:10:14 PM PDT 24
Finished Aug 03 05:22:24 PM PDT 24
Peak memory 272392 kb
Host smart-4d6d9e29-200c-43d7-986f-c559642f4b60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657662296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.657662296
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1609740797
Short name T656
Test name
Test status
Simulation time 70775916354 ps
CPU time 1401.14 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 05:33:32 PM PDT 24
Peak memory 289000 kb
Host smart-b1fa4d71-1428-4885-b886-467e362e1b4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609740797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1609740797
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.735285093
Short name T46
Test name
Test status
Simulation time 37312409468 ps
CPU time 290.27 seconds
Started Aug 03 05:10:07 PM PDT 24
Finished Aug 03 05:14:57 PM PDT 24
Peak memory 248388 kb
Host smart-edc6f877-eb79-47a9-a344-916cab41c5ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735285093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.735285093
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3433636447
Short name T427
Test name
Test status
Simulation time 4969555554 ps
CPU time 30.86 seconds
Started Aug 03 05:10:00 PM PDT 24
Finished Aug 03 05:10:31 PM PDT 24
Peak memory 256340 kb
Host smart-dc61e9bb-00ab-44d8-8d62-563b717da421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34336
36447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3433636447
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2476346354
Short name T443
Test name
Test status
Simulation time 394454262 ps
CPU time 12.74 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 05:10:23 PM PDT 24
Peak memory 254236 kb
Host smart-923dc03b-23ab-43f8-a367-c8edc83923a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24763
46354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2476346354
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3982779163
Short name T632
Test name
Test status
Simulation time 1582304947 ps
CPU time 43.46 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 05:10:54 PM PDT 24
Peak memory 256468 kb
Host smart-d4d31284-9c55-4fd8-8635-c2451d083c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39827
79163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3982779163
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1068580360
Short name T202
Test name
Test status
Simulation time 65432002 ps
CPU time 2.98 seconds
Started Aug 03 05:10:18 PM PDT 24
Finished Aug 03 05:10:21 PM PDT 24
Peak memory 248580 kb
Host smart-17b13656-8bd6-4027-933d-8c268108acd7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1068580360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1068580360
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1623032467
Short name T561
Test name
Test status
Simulation time 28162309781 ps
CPU time 1796.33 seconds
Started Aug 03 05:10:07 PM PDT 24
Finished Aug 03 05:40:03 PM PDT 24
Peak memory 281632 kb
Host smart-ae3b4e51-a598-4955-9739-d2956745655d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623032467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1623032467
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3414591884
Short name T382
Test name
Test status
Simulation time 1084413735 ps
CPU time 22.45 seconds
Started Aug 03 05:10:20 PM PDT 24
Finished Aug 03 05:10:43 PM PDT 24
Peak memory 248256 kb
Host smart-39c22a79-9379-41c7-83ef-deee4bcfd470
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3414591884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3414591884
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.145505908
Short name T294
Test name
Test status
Simulation time 6337989923 ps
CPU time 182.79 seconds
Started Aug 03 05:10:12 PM PDT 24
Finished Aug 03 05:13:15 PM PDT 24
Peak memory 256528 kb
Host smart-0fb4aa1d-4a9d-491c-ad9a-1de54d65f57c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14550
5908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.145505908
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.734484701
Short name T496
Test name
Test status
Simulation time 377814496 ps
CPU time 39.22 seconds
Started Aug 03 05:10:11 PM PDT 24
Finished Aug 03 05:10:50 PM PDT 24
Peak memory 248220 kb
Host smart-6336958c-ae03-4b0b-ad84-baf6854d7c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73448
4701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.734484701
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.320500055
Short name T350
Test name
Test status
Simulation time 56898418752 ps
CPU time 1144.62 seconds
Started Aug 03 05:10:12 PM PDT 24
Finished Aug 03 05:29:17 PM PDT 24
Peak memory 288348 kb
Host smart-0c0188a7-6362-4384-802e-cf20632e53c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320500055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.320500055
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1161414028
Short name T411
Test name
Test status
Simulation time 9005889318 ps
CPU time 785.95 seconds
Started Aug 03 05:10:12 PM PDT 24
Finished Aug 03 05:23:18 PM PDT 24
Peak memory 272464 kb
Host smart-b9e9b437-c8bc-43b7-9f6b-308efac739b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161414028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1161414028
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3797497820
Short name T383
Test name
Test status
Simulation time 987347275 ps
CPU time 35.86 seconds
Started Aug 03 05:10:03 PM PDT 24
Finished Aug 03 05:10:39 PM PDT 24
Peak memory 255728 kb
Host smart-ed93e7dd-2b1c-422f-a4c7-ce403afa6d5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37974
97820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3797497820
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.4210784569
Short name T453
Test name
Test status
Simulation time 158819088 ps
CPU time 3.21 seconds
Started Aug 03 05:10:11 PM PDT 24
Finished Aug 03 05:10:14 PM PDT 24
Peak memory 240160 kb
Host smart-822237d6-3e07-4220-ba32-a662f2d34af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42107
84569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.4210784569
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1306184044
Short name T654
Test name
Test status
Simulation time 87254085 ps
CPU time 12.34 seconds
Started Aug 03 05:10:20 PM PDT 24
Finished Aug 03 05:10:33 PM PDT 24
Peak memory 247504 kb
Host smart-3f0e5114-1bbd-4290-bb99-6a4fad70aa35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13061
84044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1306184044
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.4222016800
Short name T677
Test name
Test status
Simulation time 955328963 ps
CPU time 41.51 seconds
Started Aug 03 05:10:11 PM PDT 24
Finished Aug 03 05:10:53 PM PDT 24
Peak memory 248464 kb
Host smart-2cac89e7-242a-465a-8c06-e420ef8f78c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42220
16800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.4222016800
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1337049261
Short name T439
Test name
Test status
Simulation time 54201768410 ps
CPU time 1272.92 seconds
Started Aug 03 05:10:08 PM PDT 24
Finished Aug 03 05:31:22 PM PDT 24
Peak memory 287624 kb
Host smart-a1191563-b4f2-4076-b72f-c6662ce874d8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337049261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1337049261
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.4140892402
Short name T217
Test name
Test status
Simulation time 47708591 ps
CPU time 3.86 seconds
Started Aug 03 05:10:08 PM PDT 24
Finished Aug 03 05:10:12 PM PDT 24
Peak memory 248644 kb
Host smart-dd39a614-2369-4300-ae38-85ff9fa6e065
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4140892402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.4140892402
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3553703412
Short name T455
Test name
Test status
Simulation time 198761129 ps
CPU time 11.56 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 05:10:22 PM PDT 24
Peak memory 248292 kb
Host smart-31fd7ca4-9833-4566-889e-c006b433a414
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3553703412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3553703412
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2678420954
Short name T667
Test name
Test status
Simulation time 1494589325 ps
CPU time 130.52 seconds
Started Aug 03 05:10:03 PM PDT 24
Finished Aug 03 05:12:14 PM PDT 24
Peak memory 256076 kb
Host smart-3c112bd9-792b-48c4-a680-4e244facb434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26784
20954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2678420954
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.4181481191
Short name T91
Test name
Test status
Simulation time 1134641691 ps
CPU time 69.2 seconds
Started Aug 03 05:10:14 PM PDT 24
Finished Aug 03 05:11:23 PM PDT 24
Peak memory 256472 kb
Host smart-8211c6b6-818b-4858-8e05-7fc3a9a7b23a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41814
81191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.4181481191
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2091153916
Short name T352
Test name
Test status
Simulation time 105360814036 ps
CPU time 1866.54 seconds
Started Aug 03 05:10:06 PM PDT 24
Finished Aug 03 05:41:13 PM PDT 24
Peak memory 285044 kb
Host smart-5e6cc832-ce52-4592-95ca-77fbac73d9e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091153916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2091153916
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3642967213
Short name T547
Test name
Test status
Simulation time 31913331095 ps
CPU time 2047.09 seconds
Started Aug 03 05:10:18 PM PDT 24
Finished Aug 03 05:44:25 PM PDT 24
Peak memory 283012 kb
Host smart-8e4197c0-c444-40c8-8c3d-e10c4d8ce7ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642967213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3642967213
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.47880971
Short name T314
Test name
Test status
Simulation time 10641302887 ps
CPU time 412.36 seconds
Started Aug 03 05:10:09 PM PDT 24
Finished Aug 03 05:17:02 PM PDT 24
Peak memory 248228 kb
Host smart-34ce2c09-3e27-4064-82aa-ee20f6f226f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47880971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.47880971
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.701017410
Short name T532
Test name
Test status
Simulation time 772686573 ps
CPU time 51.16 seconds
Started Aug 03 05:10:12 PM PDT 24
Finished Aug 03 05:11:03 PM PDT 24
Peak memory 256416 kb
Host smart-b7aeaaf7-922a-46a4-820d-9807467e6ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70101
7410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.701017410
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1118910016
Short name T111
Test name
Test status
Simulation time 4084721350 ps
CPU time 54.27 seconds
Started Aug 03 05:10:08 PM PDT 24
Finished Aug 03 05:11:02 PM PDT 24
Peak memory 248196 kb
Host smart-f0e54d82-6feb-4ceb-a044-2332a92f06c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11189
10016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1118910016
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.713659466
Short name T286
Test name
Test status
Simulation time 4932195744 ps
CPU time 56.95 seconds
Started Aug 03 05:10:17 PM PDT 24
Finished Aug 03 05:11:14 PM PDT 24
Peak memory 248252 kb
Host smart-3d27f959-51b8-4819-a88e-711966f18b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71365
9466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.713659466
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3728460504
Short name T638
Test name
Test status
Simulation time 3334563332 ps
CPU time 51.03 seconds
Started Aug 03 05:10:09 PM PDT 24
Finished Aug 03 05:11:00 PM PDT 24
Peak memory 248404 kb
Host smart-a6eb4a6e-47fe-4a86-ada9-c908674bdcfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37284
60504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3728460504
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.615175450
Short name T380
Test name
Test status
Simulation time 10579770945 ps
CPU time 933.18 seconds
Started Aug 03 05:10:16 PM PDT 24
Finished Aug 03 05:25:49 PM PDT 24
Peak memory 284936 kb
Host smart-04986bc3-edda-401a-9368-a90b5ed38efa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615175450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.615175450
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2597952153
Short name T201
Test name
Test status
Simulation time 58958955 ps
CPU time 2.57 seconds
Started Aug 03 05:10:18 PM PDT 24
Finished Aug 03 05:10:20 PM PDT 24
Peak memory 248572 kb
Host smart-aa27e600-c26b-4421-8938-3e10778beae9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2597952153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2597952153
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2608313279
Short name T520
Test name
Test status
Simulation time 26181834699 ps
CPU time 1667.95 seconds
Started Aug 03 05:10:07 PM PDT 24
Finished Aug 03 05:37:56 PM PDT 24
Peak memory 272912 kb
Host smart-79915b42-52c7-406b-a8d1-801562f13bbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608313279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2608313279
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2031057692
Short name T495
Test name
Test status
Simulation time 204383124 ps
CPU time 11.43 seconds
Started Aug 03 05:10:01 PM PDT 24
Finished Aug 03 05:10:12 PM PDT 24
Peak memory 248356 kb
Host smart-6af385bd-0296-4bfb-942f-22905d20f888
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2031057692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2031057692
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.726803078
Short name T497
Test name
Test status
Simulation time 568625951 ps
CPU time 32.32 seconds
Started Aug 03 05:10:14 PM PDT 24
Finished Aug 03 05:10:46 PM PDT 24
Peak memory 255756 kb
Host smart-202dfc0f-f7e2-423d-8a4c-11f17fbbfedf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72680
3078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.726803078
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3346495931
Short name T436
Test name
Test status
Simulation time 1262370406 ps
CPU time 13.55 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 05:10:24 PM PDT 24
Peak memory 248212 kb
Host smart-c28d3ad4-90da-422c-a546-ced2569ad677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33464
95931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3346495931
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2258952493
Short name T698
Test name
Test status
Simulation time 77405091801 ps
CPU time 2015.47 seconds
Started Aug 03 05:10:13 PM PDT 24
Finished Aug 03 05:43:49 PM PDT 24
Peak memory 272888 kb
Host smart-923c83b7-2076-4c83-8515-f176b257186d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258952493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2258952493
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2311518247
Short name T568
Test name
Test status
Simulation time 35377756713 ps
CPU time 378.95 seconds
Started Aug 03 05:10:07 PM PDT 24
Finished Aug 03 05:16:26 PM PDT 24
Peak memory 248228 kb
Host smart-6e2f5fbc-d72e-442c-b006-6304c742b395
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311518247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2311518247
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1366947333
Short name T21
Test name
Test status
Simulation time 117754504 ps
CPU time 5.7 seconds
Started Aug 03 05:10:14 PM PDT 24
Finished Aug 03 05:10:20 PM PDT 24
Peak memory 248224 kb
Host smart-611a2f4b-5331-4cb4-8e79-45f0659ad112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13669
47333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1366947333
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1363341462
Short name T595
Test name
Test status
Simulation time 206901510 ps
CPU time 16.11 seconds
Started Aug 03 05:10:17 PM PDT 24
Finished Aug 03 05:10:33 PM PDT 24
Peak memory 247604 kb
Host smart-4cf7f7aa-44d5-41b1-9cff-677173d77ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13633
41462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1363341462
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3226476759
Short name T501
Test name
Test status
Simulation time 568960404 ps
CPU time 33.89 seconds
Started Aug 03 05:10:11 PM PDT 24
Finished Aug 03 05:10:45 PM PDT 24
Peak memory 248256 kb
Host smart-f77705a7-639d-41f9-840d-57b24b0aaf86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32264
76759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3226476759
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2074591756
Short name T686
Test name
Test status
Simulation time 1070681404 ps
CPU time 42.05 seconds
Started Aug 03 05:10:18 PM PDT 24
Finished Aug 03 05:11:00 PM PDT 24
Peak memory 248368 kb
Host smart-80e77d4e-2cee-4b30-b5d7-217da97d3f9f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074591756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2074591756
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.784016858
Short name T204
Test name
Test status
Simulation time 74682493 ps
CPU time 3.48 seconds
Started Aug 03 05:10:14 PM PDT 24
Finished Aug 03 05:10:18 PM PDT 24
Peak memory 248508 kb
Host smart-3c077db8-05b1-4af8-9edd-d717905153c4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=784016858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.784016858
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3520392075
Short name T446
Test name
Test status
Simulation time 87900279319 ps
CPU time 1253.59 seconds
Started Aug 03 05:10:05 PM PDT 24
Finished Aug 03 05:30:59 PM PDT 24
Peak memory 272960 kb
Host smart-027bdb51-7359-44af-8814-e3bdbf027b5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520392075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3520392075
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.273164913
Short name T581
Test name
Test status
Simulation time 413300273 ps
CPU time 18.73 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 05:10:29 PM PDT 24
Peak memory 247700 kb
Host smart-deccc4c9-91d3-4e87-96f4-0ed674134649
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=273164913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.273164913
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.877882734
Short name T232
Test name
Test status
Simulation time 91944655 ps
CPU time 11.9 seconds
Started Aug 03 05:10:08 PM PDT 24
Finished Aug 03 05:10:20 PM PDT 24
Peak memory 247656 kb
Host smart-b8780dfc-c65d-4abe-a9be-15893560652f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87788
2734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.877882734
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.4034821745
Short name T604
Test name
Test status
Simulation time 57036623 ps
CPU time 4.38 seconds
Started Aug 03 05:10:11 PM PDT 24
Finished Aug 03 05:10:15 PM PDT 24
Peak memory 247948 kb
Host smart-80d8b0b6-5249-4fff-8404-4d52fa9fcd26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40348
21745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.4034821745
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1781655321
Short name T683
Test name
Test status
Simulation time 166248838125 ps
CPU time 2375.17 seconds
Started Aug 03 05:10:13 PM PDT 24
Finished Aug 03 05:49:49 PM PDT 24
Peak memory 287524 kb
Host smart-ca0c9f1c-2801-4d59-ba11-98aaf5d31411
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781655321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1781655321
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1607360297
Short name T320
Test name
Test status
Simulation time 50558762566 ps
CPU time 309.05 seconds
Started Aug 03 05:10:15 PM PDT 24
Finished Aug 03 05:15:24 PM PDT 24
Peak memory 247072 kb
Host smart-8504c649-6c4f-476e-8585-d8cb1448e210
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607360297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1607360297
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.386930609
Short name T592
Test name
Test status
Simulation time 830825319 ps
CPU time 49.89 seconds
Started Aug 03 05:10:21 PM PDT 24
Finished Aug 03 05:11:11 PM PDT 24
Peak memory 255540 kb
Host smart-2bc2b371-3099-42fa-a167-5404bc2e6f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38693
0609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.386930609
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1362333418
Short name T583
Test name
Test status
Simulation time 964653221 ps
CPU time 22.18 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 05:10:32 PM PDT 24
Peak memory 247828 kb
Host smart-f918c702-58d1-4904-a3dd-2af68c79fb43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13623
33418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1362333418
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2705738039
Short name T429
Test name
Test status
Simulation time 853615615 ps
CPU time 13.45 seconds
Started Aug 03 05:10:14 PM PDT 24
Finished Aug 03 05:10:28 PM PDT 24
Peak memory 248160 kb
Host smart-2c43ce60-f2d1-4b0b-9ced-0a2d584c5a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27057
38039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2705738039
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1300171765
Short name T275
Test name
Test status
Simulation time 20502693497 ps
CPU time 1869.23 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 05:41:20 PM PDT 24
Peak memory 297304 kb
Host smart-876a3473-df59-4a1c-a646-b1dd111d25c0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300171765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1300171765
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.1364885847
Short name T271
Test name
Test status
Simulation time 490192864256 ps
CPU time 3905.94 seconds
Started Aug 03 05:10:12 PM PDT 24
Finished Aug 03 06:15:19 PM PDT 24
Peak memory 305360 kb
Host smart-7c97fc8d-446d-4878-b267-8417cb8227f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364885847 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.1364885847
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1248415105
Short name T208
Test name
Test status
Simulation time 96245979 ps
CPU time 2.13 seconds
Started Aug 03 05:10:18 PM PDT 24
Finished Aug 03 05:10:20 PM PDT 24
Peak memory 248420 kb
Host smart-738954ad-7a61-4459-a1c1-d0f59750c809
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1248415105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1248415105
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1164850934
Short name T512
Test name
Test status
Simulation time 26569647861 ps
CPU time 1371.56 seconds
Started Aug 03 05:10:14 PM PDT 24
Finished Aug 03 05:33:06 PM PDT 24
Peak memory 272440 kb
Host smart-64054c27-8a73-4a7b-a1ca-c1a2b74539ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164850934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1164850934
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3158682998
Short name T223
Test name
Test status
Simulation time 209549816 ps
CPU time 11.14 seconds
Started Aug 03 05:10:15 PM PDT 24
Finished Aug 03 05:10:26 PM PDT 24
Peak memory 248072 kb
Host smart-044692d7-d881-4a65-9df3-2a5c26626843
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3158682998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3158682998
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.685930698
Short name T577
Test name
Test status
Simulation time 2107143643 ps
CPU time 38.18 seconds
Started Aug 03 05:10:15 PM PDT 24
Finished Aug 03 05:10:53 PM PDT 24
Peak memory 256328 kb
Host smart-20e651ff-97c7-47c6-8877-6651279e148d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68593
0698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.685930698
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1577902867
Short name T365
Test name
Test status
Simulation time 810869494 ps
CPU time 51.36 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 05:11:02 PM PDT 24
Peak memory 256540 kb
Host smart-816eb791-89fe-4759-996b-f02ffa9178aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15779
02867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1577902867
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.372250759
Short name T344
Test name
Test status
Simulation time 43953949339 ps
CPU time 930.78 seconds
Started Aug 03 05:10:16 PM PDT 24
Finished Aug 03 05:25:47 PM PDT 24
Peak memory 272132 kb
Host smart-5ea9dd4c-6176-48e1-af12-4766ab5bca0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372250759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.372250759
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.501728461
Short name T396
Test name
Test status
Simulation time 23112427855 ps
CPU time 721.72 seconds
Started Aug 03 05:10:21 PM PDT 24
Finished Aug 03 05:22:23 PM PDT 24
Peak memory 272956 kb
Host smart-db49dded-2013-4197-beb0-0a037f5bb57f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501728461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.501728461
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.765954668
Short name T650
Test name
Test status
Simulation time 4910380121 ps
CPU time 190 seconds
Started Aug 03 05:10:22 PM PDT 24
Finished Aug 03 05:13:32 PM PDT 24
Peak memory 248208 kb
Host smart-4d9be271-8544-4811-84b8-3eb3dbba8984
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765954668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.765954668
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2347569328
Short name T442
Test name
Test status
Simulation time 114624471 ps
CPU time 13.21 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 05:10:24 PM PDT 24
Peak memory 255112 kb
Host smart-c551f301-0d53-49f9-8e1d-2a8e51d81417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23475
69328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2347569328
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1035969618
Short name T513
Test name
Test status
Simulation time 4630012495 ps
CPU time 39.64 seconds
Started Aug 03 05:10:08 PM PDT 24
Finished Aug 03 05:10:47 PM PDT 24
Peak memory 256140 kb
Host smart-5df82e72-75e2-4d89-a21e-d7e98ea53d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10359
69618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1035969618
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.253929329
Short name T313
Test name
Test status
Simulation time 338140371 ps
CPU time 6.72 seconds
Started Aug 03 05:10:07 PM PDT 24
Finished Aug 03 05:10:14 PM PDT 24
Peak memory 251748 kb
Host smart-0d1c2ab0-39ec-40bc-95e3-ae09db6dbb92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25392
9329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.253929329
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1051681496
Short name T621
Test name
Test status
Simulation time 744174887 ps
CPU time 43.62 seconds
Started Aug 03 05:10:05 PM PDT 24
Finished Aug 03 05:10:49 PM PDT 24
Peak memory 255016 kb
Host smart-543c5c47-ddab-4cc2-b840-c328f57b6b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10516
81496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1051681496
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2984938898
Short name T43
Test name
Test status
Simulation time 34570477 ps
CPU time 3.21 seconds
Started Aug 03 05:10:19 PM PDT 24
Finished Aug 03 05:10:22 PM PDT 24
Peak memory 248572 kb
Host smart-31b31d82-539a-4400-b7f2-562021842260
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2984938898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2984938898
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1438535990
Short name T109
Test name
Test status
Simulation time 75816411616 ps
CPU time 1240.57 seconds
Started Aug 03 05:10:22 PM PDT 24
Finished Aug 03 05:31:02 PM PDT 24
Peak memory 272380 kb
Host smart-07f2b679-d745-412b-bacf-fd7d96285da1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438535990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1438535990
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2494277589
Short name T228
Test name
Test status
Simulation time 169293995 ps
CPU time 9.9 seconds
Started Aug 03 05:10:20 PM PDT 24
Finished Aug 03 05:10:30 PM PDT 24
Peak memory 248344 kb
Host smart-0638ae16-fab6-4745-9de2-2c44ca9ff728
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2494277589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2494277589
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3865583703
Short name T441
Test name
Test status
Simulation time 4169545892 ps
CPU time 117.62 seconds
Started Aug 03 05:10:16 PM PDT 24
Finished Aug 03 05:12:14 PM PDT 24
Peak memory 255892 kb
Host smart-bbefef2b-96d7-4c83-9b71-f59a64dd6069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38655
83703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3865583703
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.4138429903
Short name T573
Test name
Test status
Simulation time 2042082068 ps
CPU time 31.33 seconds
Started Aug 03 05:10:15 PM PDT 24
Finished Aug 03 05:10:46 PM PDT 24
Peak memory 248288 kb
Host smart-331b0d92-2b70-48ea-b0d4-33b44689a3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41384
29903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.4138429903
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2965443759
Short name T691
Test name
Test status
Simulation time 71365140474 ps
CPU time 1922.18 seconds
Started Aug 03 05:10:22 PM PDT 24
Finished Aug 03 05:42:25 PM PDT 24
Peak memory 285460 kb
Host smart-bdea4de5-3197-4705-bd2c-4594b4ecfad7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965443759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2965443759
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3899790
Short name T246
Test name
Test status
Simulation time 32089546781 ps
CPU time 2234.87 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 05:47:25 PM PDT 24
Peak memory 287292 kb
Host smart-fd34551a-4d76-422f-a329-3dca48c63519
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3899790
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3929255639
Short name T330
Test name
Test status
Simulation time 28883423518 ps
CPU time 249.38 seconds
Started Aug 03 05:10:17 PM PDT 24
Finished Aug 03 05:14:27 PM PDT 24
Peak memory 248316 kb
Host smart-40ea5736-3b8f-47ef-8010-13a6780db3ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929255639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3929255639
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.588654878
Short name T538
Test name
Test status
Simulation time 546219544 ps
CPU time 33.88 seconds
Started Aug 03 05:10:32 PM PDT 24
Finished Aug 03 05:11:06 PM PDT 24
Peak memory 255772 kb
Host smart-00e8764d-c422-4ace-802d-91293c85a052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58865
4878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.588654878
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.471802360
Short name T59
Test name
Test status
Simulation time 250364115 ps
CPU time 20.33 seconds
Started Aug 03 05:10:31 PM PDT 24
Finished Aug 03 05:10:52 PM PDT 24
Peak memory 247640 kb
Host smart-a935b0e4-6017-4f9f-a1ad-f5a54be4f8dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47180
2360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.471802360
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2117258834
Short name T300
Test name
Test status
Simulation time 135245372 ps
CPU time 18.23 seconds
Started Aug 03 05:10:14 PM PDT 24
Finished Aug 03 05:10:32 PM PDT 24
Peak memory 247640 kb
Host smart-cf84d68c-575b-4e0e-ae29-7983e499ac12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21172
58834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2117258834
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1940906943
Short name T491
Test name
Test status
Simulation time 4280366727 ps
CPU time 42.22 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 05:10:52 PM PDT 24
Peak memory 256440 kb
Host smart-cc9ffba4-93ff-411f-bb61-a718b15a440b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19409
06943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1940906943
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2205154381
Short name T73
Test name
Test status
Simulation time 62423255817 ps
CPU time 1708.14 seconds
Started Aug 03 05:10:17 PM PDT 24
Finished Aug 03 05:38:46 PM PDT 24
Peak memory 283200 kb
Host smart-00d4263b-b5fd-4473-a262-91218ab13273
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205154381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2205154381
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3370798065
Short name T565
Test name
Test status
Simulation time 648127001096 ps
CPU time 10695.2 seconds
Started Aug 03 05:10:15 PM PDT 24
Finished Aug 03 08:08:31 PM PDT 24
Peak memory 436860 kb
Host smart-f442038f-5d9d-45d9-bb54-970464e6afd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370798065 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3370798065
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1328462993
Short name T212
Test name
Test status
Simulation time 17695576 ps
CPU time 2.52 seconds
Started Aug 03 05:10:11 PM PDT 24
Finished Aug 03 05:10:14 PM PDT 24
Peak memory 248676 kb
Host smart-ff319433-86f7-4795-898c-887d3791a2a4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1328462993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1328462993
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2005082161
Short name T390
Test name
Test status
Simulation time 91102698978 ps
CPU time 1381.75 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 05:33:13 PM PDT 24
Peak memory 273000 kb
Host smart-43cb74a2-7bec-403d-bd6a-430d501f2a76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005082161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2005082161
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3784635385
Short name T219
Test name
Test status
Simulation time 365031539 ps
CPU time 18.91 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 05:10:29 PM PDT 24
Peak memory 248248 kb
Host smart-c2430f8c-d457-4aae-ac20-cbe6136800cc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3784635385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3784635385
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.3121948501
Short name T471
Test name
Test status
Simulation time 1865139269 ps
CPU time 74.7 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 05:11:25 PM PDT 24
Peak memory 255968 kb
Host smart-b168ce60-de7e-475f-90ba-011f65728e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31219
48501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3121948501
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1212109887
Short name T74
Test name
Test status
Simulation time 646053148 ps
CPU time 18.13 seconds
Started Aug 03 05:10:22 PM PDT 24
Finished Aug 03 05:10:41 PM PDT 24
Peak memory 252896 kb
Host smart-06959018-5486-495c-b9ae-ea2f896bc192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12121
09887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1212109887
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2337449177
Short name T670
Test name
Test status
Simulation time 93070951853 ps
CPU time 1619.22 seconds
Started Aug 03 05:10:13 PM PDT 24
Finished Aug 03 05:37:13 PM PDT 24
Peak memory 272684 kb
Host smart-b7e9ff66-2c4f-4213-af9d-f076113fe204
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337449177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2337449177
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.2530176559
Short name T504
Test name
Test status
Simulation time 786621493 ps
CPU time 37.07 seconds
Started Aug 03 05:10:32 PM PDT 24
Finished Aug 03 05:11:09 PM PDT 24
Peak memory 248240 kb
Host smart-1f1a9008-9bd7-46ec-8c21-e1582f8ab5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25301
76559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2530176559
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2254738547
Short name T602
Test name
Test status
Simulation time 3262286901 ps
CPU time 48.43 seconds
Started Aug 03 05:10:15 PM PDT 24
Finished Aug 03 05:11:03 PM PDT 24
Peak memory 248300 kb
Host smart-1448be9c-19ca-474c-881f-cf14e0c5c0f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22547
38547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2254738547
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1948651799
Short name T606
Test name
Test status
Simulation time 2317539601 ps
CPU time 44.74 seconds
Started Aug 03 05:10:16 PM PDT 24
Finished Aug 03 05:11:01 PM PDT 24
Peak memory 255608 kb
Host smart-ef48e31c-33e6-4365-b5e1-eebff6c6dff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19486
51799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1948651799
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3599999050
Short name T660
Test name
Test status
Simulation time 381153259 ps
CPU time 27.6 seconds
Started Aug 03 05:10:31 PM PDT 24
Finished Aug 03 05:10:58 PM PDT 24
Peak memory 255888 kb
Host smart-680242f7-297a-43e4-912d-64815bfa02f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35999
99050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3599999050
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1568947371
Short name T182
Test name
Test status
Simulation time 7660836147 ps
CPU time 746.9 seconds
Started Aug 03 05:10:27 PM PDT 24
Finished Aug 03 05:22:54 PM PDT 24
Peak memory 272324 kb
Host smart-1a1f031b-dedc-40bb-a7ee-adfdb46a91f7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568947371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1568947371
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3016080577
Short name T215
Test name
Test status
Simulation time 33411999 ps
CPU time 3.11 seconds
Started Aug 03 05:10:12 PM PDT 24
Finished Aug 03 05:10:16 PM PDT 24
Peak memory 248580 kb
Host smart-51888033-eced-4f8a-974d-b09406355159
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3016080577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3016080577
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1140443437
Short name T582
Test name
Test status
Simulation time 24653670767 ps
CPU time 561.42 seconds
Started Aug 03 05:10:12 PM PDT 24
Finished Aug 03 05:19:34 PM PDT 24
Peak memory 272152 kb
Host smart-ca8b0e19-cb89-46f5-b321-288a469ec633
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140443437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1140443437
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2339753947
Short name T241
Test name
Test status
Simulation time 416420470 ps
CPU time 12.65 seconds
Started Aug 03 05:10:39 PM PDT 24
Finished Aug 03 05:10:52 PM PDT 24
Peak memory 248284 kb
Host smart-c9f5ecd2-fa34-4ca4-a941-4ddd8cfb0201
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2339753947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2339753947
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3961017572
Short name T590
Test name
Test status
Simulation time 8574667755 ps
CPU time 233.76 seconds
Started Aug 03 05:10:35 PM PDT 24
Finished Aug 03 05:14:28 PM PDT 24
Peak memory 256472 kb
Host smart-7bfa5e7e-597a-4793-8dc3-8ddc9709faeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39610
17572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3961017572
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.730336313
Short name T616
Test name
Test status
Simulation time 153992743 ps
CPU time 9.69 seconds
Started Aug 03 05:10:32 PM PDT 24
Finished Aug 03 05:10:42 PM PDT 24
Peak memory 247936 kb
Host smart-2963aebc-1342-4aaf-b496-84fdca3300d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73033
6313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.730336313
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2510517939
Short name T84
Test name
Test status
Simulation time 72479695317 ps
CPU time 1237.12 seconds
Started Aug 03 05:10:16 PM PDT 24
Finished Aug 03 05:30:53 PM PDT 24
Peak memory 272860 kb
Host smart-60cd6885-3ca8-4354-bee5-c323dfad6127
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510517939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2510517939
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3583288340
Short name T323
Test name
Test status
Simulation time 16731239593 ps
CPU time 383.3 seconds
Started Aug 03 05:10:32 PM PDT 24
Finished Aug 03 05:16:56 PM PDT 24
Peak memory 248384 kb
Host smart-c3da31ff-3c42-457c-afb1-ee5feb389b8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583288340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3583288340
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2797240783
Short name T375
Test name
Test status
Simulation time 809579345 ps
CPU time 36.21 seconds
Started Aug 03 05:10:18 PM PDT 24
Finished Aug 03 05:10:55 PM PDT 24
Peak memory 248168 kb
Host smart-552975fb-bbcb-49a0-954b-a376a8d2b010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27972
40783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2797240783
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.4191320694
Short name T502
Test name
Test status
Simulation time 6638658148 ps
CPU time 74.88 seconds
Started Aug 03 05:10:27 PM PDT 24
Finished Aug 03 05:11:42 PM PDT 24
Peak memory 255692 kb
Host smart-de3360f4-1c6e-46bb-a1dc-a2268ba5407c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41913
20694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.4191320694
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1212981996
Short name T626
Test name
Test status
Simulation time 920791208 ps
CPU time 26.4 seconds
Started Aug 03 05:10:16 PM PDT 24
Finished Aug 03 05:10:42 PM PDT 24
Peak memory 248288 kb
Host smart-a63db6d2-d2a0-44ed-8709-ffa6cea9207f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12129
81996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1212981996
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2185992796
Short name T578
Test name
Test status
Simulation time 492515412 ps
CPU time 9.69 seconds
Started Aug 03 05:10:15 PM PDT 24
Finished Aug 03 05:10:25 PM PDT 24
Peak memory 248596 kb
Host smart-77800583-085f-41a3-8674-11b4d9b78136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21859
92796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2185992796
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1573811033
Short name T272
Test name
Test status
Simulation time 728413773713 ps
CPU time 2290.96 seconds
Started Aug 03 05:10:12 PM PDT 24
Finished Aug 03 05:48:24 PM PDT 24
Peak memory 288588 kb
Host smart-5db85c7a-f052-4612-849d-fbddc1ae3c51
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573811033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1573811033
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.276144138
Short name T564
Test name
Test status
Simulation time 153391820306 ps
CPU time 2217.22 seconds
Started Aug 03 05:10:14 PM PDT 24
Finished Aug 03 05:47:12 PM PDT 24
Peak memory 272904 kb
Host smart-528f8d5b-7fb4-4562-a527-57a25c712c2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276144138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.276144138
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1383337131
Short name T620
Test name
Test status
Simulation time 754261323 ps
CPU time 19.29 seconds
Started Aug 03 05:10:42 PM PDT 24
Finished Aug 03 05:11:02 PM PDT 24
Peak memory 248332 kb
Host smart-f161a32a-a8c9-4b16-b2e3-a1041ccb3872
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1383337131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1383337131
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2795638876
Short name T385
Test name
Test status
Simulation time 4546229057 ps
CPU time 248.23 seconds
Started Aug 03 05:10:27 PM PDT 24
Finished Aug 03 05:14:35 PM PDT 24
Peak memory 256580 kb
Host smart-e7ee1b8e-ad3c-4dd6-b457-bedeb11485e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27956
38876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2795638876
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1140292725
Short name T539
Test name
Test status
Simulation time 1988083806 ps
CPU time 27.62 seconds
Started Aug 03 05:10:17 PM PDT 24
Finished Aug 03 05:10:45 PM PDT 24
Peak memory 248148 kb
Host smart-9d13d1d4-f58a-4fa2-8134-c284d3b8fd49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11402
92725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1140292725
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3975961379
Short name T333
Test name
Test status
Simulation time 154777605612 ps
CPU time 950.38 seconds
Started Aug 03 05:10:43 PM PDT 24
Finished Aug 03 05:26:33 PM PDT 24
Peak memory 281088 kb
Host smart-a0b7eeed-8dbc-468f-ad22-5791a95ad3f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975961379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3975961379
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.482677539
Short name T607
Test name
Test status
Simulation time 22688994683 ps
CPU time 1143.78 seconds
Started Aug 03 05:10:37 PM PDT 24
Finished Aug 03 05:29:41 PM PDT 24
Peak memory 272020 kb
Host smart-2a01b7f9-5f8e-431c-bbd1-c784064d97c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482677539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.482677539
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.825057309
Short name T627
Test name
Test status
Simulation time 3906943908 ps
CPU time 162.49 seconds
Started Aug 03 05:10:12 PM PDT 24
Finished Aug 03 05:12:55 PM PDT 24
Peak memory 248216 kb
Host smart-1d09d43e-921f-49e0-baf8-99d03f6d3601
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825057309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.825057309
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.899317603
Short name T516
Test name
Test status
Simulation time 378186137 ps
CPU time 30.19 seconds
Started Aug 03 05:10:28 PM PDT 24
Finished Aug 03 05:10:58 PM PDT 24
Peak memory 255576 kb
Host smart-36674899-5165-4364-ab5b-ab0d585c2d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89931
7603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.899317603
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1062680164
Short name T11
Test name
Test status
Simulation time 354793912 ps
CPU time 22.72 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 05:10:32 PM PDT 24
Peak memory 255928 kb
Host smart-2c04769a-7b77-4451-9c8b-b0da6239fa81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10626
80164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1062680164
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3352240887
Short name T287
Test name
Test status
Simulation time 517524085 ps
CPU time 34.95 seconds
Started Aug 03 05:10:31 PM PDT 24
Finished Aug 03 05:11:06 PM PDT 24
Peak memory 256420 kb
Host smart-c115495d-7ae2-443f-83a4-beb206fc4ec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33522
40887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3352240887
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3744850432
Short name T643
Test name
Test status
Simulation time 1554723356 ps
CPU time 66.52 seconds
Started Aug 03 05:10:11 PM PDT 24
Finished Aug 03 05:11:18 PM PDT 24
Peak memory 255580 kb
Host smart-3b10d8ad-9f43-46ae-b675-f1e29816962e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37448
50432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3744850432
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3054285952
Short name T87
Test name
Test status
Simulation time 33301058927 ps
CPU time 2072.78 seconds
Started Aug 03 05:10:43 PM PDT 24
Finished Aug 03 05:45:16 PM PDT 24
Peak memory 286888 kb
Host smart-4c394331-dfbc-4a53-b303-d8a47437b813
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054285952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3054285952
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1976146285
Short name T210
Test name
Test status
Simulation time 30429502 ps
CPU time 3.31 seconds
Started Aug 03 05:09:58 PM PDT 24
Finished Aug 03 05:10:01 PM PDT 24
Peak memory 248580 kb
Host smart-c955a96c-eb65-43ce-a979-8372af500d53
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1976146285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1976146285
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2300918446
Short name T75
Test name
Test status
Simulation time 27279138891 ps
CPU time 1137.35 seconds
Started Aug 03 05:09:57 PM PDT 24
Finished Aug 03 05:28:55 PM PDT 24
Peak memory 272936 kb
Host smart-1ec0ccee-97ea-4d10-84c2-1e72ef60289f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300918446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2300918446
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1391118287
Short name T611
Test name
Test status
Simulation time 732506008 ps
CPU time 30.24 seconds
Started Aug 03 05:09:53 PM PDT 24
Finished Aug 03 05:10:24 PM PDT 24
Peak memory 248304 kb
Host smart-b2ca0d84-3d6c-4ff8-b946-d6ac386bb407
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1391118287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1391118287
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2526778830
Short name T270
Test name
Test status
Simulation time 17975945468 ps
CPU time 254.35 seconds
Started Aug 03 05:09:40 PM PDT 24
Finished Aug 03 05:13:55 PM PDT 24
Peak memory 256520 kb
Host smart-5ef1e993-6a2a-4e5e-9ae8-c68b7b922be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25267
78830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2526778830
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1642087023
Short name T177
Test name
Test status
Simulation time 2285613636 ps
CPU time 43.93 seconds
Started Aug 03 05:10:07 PM PDT 24
Finished Aug 03 05:10:51 PM PDT 24
Peak memory 256108 kb
Host smart-634d97ad-b4d3-4611-bb05-37e3b514aec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16420
87023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1642087023
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.437738444
Short name T338
Test name
Test status
Simulation time 261967319049 ps
CPU time 1262.92 seconds
Started Aug 03 05:09:53 PM PDT 24
Finished Aug 03 05:30:56 PM PDT 24
Peak memory 272492 kb
Host smart-dc00c879-2c38-4d5a-9d51-7bb377dcb4f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437738444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.437738444
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1505696960
Short name T428
Test name
Test status
Simulation time 64535487667 ps
CPU time 1769.96 seconds
Started Aug 03 05:10:02 PM PDT 24
Finished Aug 03 05:39:32 PM PDT 24
Peak memory 272908 kb
Host smart-9aebca4c-7a30-4d96-aeaf-34b71c1baba7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505696960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1505696960
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1748718714
Short name T63
Test name
Test status
Simulation time 418935231 ps
CPU time 35.24 seconds
Started Aug 03 05:09:37 PM PDT 24
Finished Aug 03 05:10:12 PM PDT 24
Peak memory 249332 kb
Host smart-cfcec614-ba41-474d-bd46-f296cb274dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17487
18714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1748718714
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1397859392
Short name T363
Test name
Test status
Simulation time 376731401 ps
CPU time 20.41 seconds
Started Aug 03 05:09:47 PM PDT 24
Finished Aug 03 05:10:08 PM PDT 24
Peak memory 256012 kb
Host smart-006c457b-d02f-4354-81fa-6fd6f1ef67af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13978
59392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1397859392
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.664947486
Short name T33
Test name
Test status
Simulation time 541374364 ps
CPU time 26.13 seconds
Started Aug 03 05:09:55 PM PDT 24
Finished Aug 03 05:10:21 PM PDT 24
Peak memory 266820 kb
Host smart-f356c176-c7ed-4c2c-981a-aa1a7a92b68e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=664947486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.664947486
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1219364277
Short name T566
Test name
Test status
Simulation time 3816279141 ps
CPU time 31.41 seconds
Started Aug 03 05:09:45 PM PDT 24
Finished Aug 03 05:10:16 PM PDT 24
Peak memory 256376 kb
Host smart-96ba7e54-7047-4891-bdfb-6c7e13a917e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12193
64277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1219364277
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1291651065
Short name T680
Test name
Test status
Simulation time 990783397 ps
CPU time 17.4 seconds
Started Aug 03 05:09:54 PM PDT 24
Finished Aug 03 05:10:12 PM PDT 24
Peak memory 255256 kb
Host smart-8811e003-cd46-4d7c-8fb6-233bbddf3f03
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291651065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1291651065
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1295151566
Short name T697
Test name
Test status
Simulation time 34496821555 ps
CPU time 3510.79 seconds
Started Aug 03 05:09:48 PM PDT 24
Finished Aug 03 06:08:20 PM PDT 24
Peak memory 304876 kb
Host smart-474c9b88-4214-4e1a-b7d0-ab086564ec70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295151566 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1295151566
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2704223807
Short name T646
Test name
Test status
Simulation time 47500317211 ps
CPU time 1188.65 seconds
Started Aug 03 05:10:15 PM PDT 24
Finished Aug 03 05:30:04 PM PDT 24
Peak memory 283916 kb
Host smart-811201d6-9bda-4aa0-8c5e-bcca5d9a4fdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704223807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2704223807
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.4158936882
Short name T45
Test name
Test status
Simulation time 8205339380 ps
CPU time 261.94 seconds
Started Aug 03 05:10:14 PM PDT 24
Finished Aug 03 05:14:36 PM PDT 24
Peak memory 256596 kb
Host smart-09c47e63-3f51-4af2-a2ba-371f08b5bdfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41589
36882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.4158936882
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3850363970
Short name T377
Test name
Test status
Simulation time 2891566691 ps
CPU time 40.2 seconds
Started Aug 03 05:10:18 PM PDT 24
Finished Aug 03 05:10:59 PM PDT 24
Peak memory 248356 kb
Host smart-ee4cd2e6-7ea4-41c4-9659-523a926e101d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38503
63970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3850363970
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3044397372
Short name T347
Test name
Test status
Simulation time 44296493374 ps
CPU time 2477.25 seconds
Started Aug 03 05:10:34 PM PDT 24
Finished Aug 03 05:51:52 PM PDT 24
Peak memory 282136 kb
Host smart-393c1ba8-401b-4a80-8632-784f13df598e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044397372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3044397372
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.423644975
Short name T102
Test name
Test status
Simulation time 34856967153 ps
CPU time 1090.13 seconds
Started Aug 03 05:10:37 PM PDT 24
Finished Aug 03 05:28:47 PM PDT 24
Peak memory 264752 kb
Host smart-919e720e-8217-456f-b178-c5c290ce5fcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423644975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.423644975
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3220096531
Short name T318
Test name
Test status
Simulation time 30102136800 ps
CPU time 289.64 seconds
Started Aug 03 05:10:31 PM PDT 24
Finished Aug 03 05:15:20 PM PDT 24
Peak memory 248396 kb
Host smart-58e23cd7-52f5-4a1c-b67c-7cf10e03d1cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220096531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3220096531
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1826679934
Short name T601
Test name
Test status
Simulation time 2014207705 ps
CPU time 56.02 seconds
Started Aug 03 05:10:38 PM PDT 24
Finished Aug 03 05:11:35 PM PDT 24
Peak memory 255620 kb
Host smart-0c5ab2a9-607e-425a-8e5a-a6eb102a5ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18266
79934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1826679934
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2874076777
Short name T108
Test name
Test status
Simulation time 2525533478 ps
CPU time 29.87 seconds
Started Aug 03 05:10:30 PM PDT 24
Finished Aug 03 05:11:00 PM PDT 24
Peak memory 255872 kb
Host smart-cc3e1fb3-c56e-4323-b13c-f01c89fce5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28740
76777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2874076777
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.462355024
Short name T525
Test name
Test status
Simulation time 2806700202 ps
CPU time 49.41 seconds
Started Aug 03 05:10:14 PM PDT 24
Finished Aug 03 05:11:04 PM PDT 24
Peak memory 256112 kb
Host smart-cdb5bf0d-4daa-48c6-9678-c84e9f8d4b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46235
5024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.462355024
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.906573451
Short name T311
Test name
Test status
Simulation time 8825757879 ps
CPU time 46 seconds
Started Aug 03 05:10:40 PM PDT 24
Finished Aug 03 05:11:26 PM PDT 24
Peak memory 248828 kb
Host smart-95e78be2-c0d7-4b15-8def-90ff9b3b7901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90657
3451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.906573451
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2153069429
Short name T82
Test name
Test status
Simulation time 17585315526 ps
CPU time 1992.49 seconds
Started Aug 03 05:10:15 PM PDT 24
Finished Aug 03 05:43:28 PM PDT 24
Peak memory 305476 kb
Host smart-fd8b9a40-c79f-46ea-9aae-5aae77ad732e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153069429 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2153069429
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1292122488
Short name T460
Test name
Test status
Simulation time 4242794562 ps
CPU time 231.95 seconds
Started Aug 03 05:10:12 PM PDT 24
Finished Aug 03 05:14:05 PM PDT 24
Peak memory 255896 kb
Host smart-237d463a-dd36-4440-a7cb-27e334c3c0c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12921
22488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1292122488
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3270563764
Short name T78
Test name
Test status
Simulation time 673585103 ps
CPU time 40.25 seconds
Started Aug 03 05:10:28 PM PDT 24
Finished Aug 03 05:11:09 PM PDT 24
Peak memory 256544 kb
Host smart-c11bff0c-e4f7-4386-9a12-8f6f694d92f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32705
63764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3270563764
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.540024223
Short name T467
Test name
Test status
Simulation time 15071867048 ps
CPU time 1280.75 seconds
Started Aug 03 05:10:38 PM PDT 24
Finished Aug 03 05:31:59 PM PDT 24
Peak memory 287464 kb
Host smart-3462037c-cf07-4e64-96ff-2c269ea2f20a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540024223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.540024223
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.988945579
Short name T112
Test name
Test status
Simulation time 56982026457 ps
CPU time 1282.7 seconds
Started Aug 03 05:10:31 PM PDT 24
Finished Aug 03 05:31:54 PM PDT 24
Peak memory 285980 kb
Host smart-2446dfd5-78b9-4907-be3d-690aeeb57aae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988945579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.988945579
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1128920745
Short name T309
Test name
Test status
Simulation time 3203215697 ps
CPU time 133.04 seconds
Started Aug 03 05:10:21 PM PDT 24
Finished Aug 03 05:12:34 PM PDT 24
Peak memory 254708 kb
Host smart-4f9f8cdf-c762-48d7-87df-fa6483e66f39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128920745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1128920745
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3810732484
Short name T678
Test name
Test status
Simulation time 801067646 ps
CPU time 50.94 seconds
Started Aug 03 05:10:39 PM PDT 24
Finished Aug 03 05:11:30 PM PDT 24
Peak memory 256432 kb
Host smart-7d7fa6fb-14b1-40d9-b960-24b62ed29c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38107
32484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3810732484
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1886812219
Short name T92
Test name
Test status
Simulation time 5859181172 ps
CPU time 76.62 seconds
Started Aug 03 05:10:34 PM PDT 24
Finished Aug 03 05:11:50 PM PDT 24
Peak memory 249588 kb
Host smart-a9810bae-88dc-489a-9e25-fdb72cb45a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18868
12219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1886812219
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.810711667
Short name T100
Test name
Test status
Simulation time 1601997534 ps
CPU time 47.19 seconds
Started Aug 03 05:10:14 PM PDT 24
Finished Aug 03 05:11:02 PM PDT 24
Peak memory 247856 kb
Host smart-0660afa0-9e22-4313-98f7-385de30972c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81071
1667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.810711667
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3166131780
Short name T366
Test name
Test status
Simulation time 1352947847 ps
CPU time 19.95 seconds
Started Aug 03 05:10:13 PM PDT 24
Finished Aug 03 05:10:33 PM PDT 24
Peak memory 256076 kb
Host smart-aa673f34-e917-4192-a95b-8afac57dfd2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31661
31780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3166131780
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3390613676
Short name T60
Test name
Test status
Simulation time 14758534996 ps
CPU time 1514.31 seconds
Started Aug 03 05:10:30 PM PDT 24
Finished Aug 03 05:35:45 PM PDT 24
Peak memory 289284 kb
Host smart-69dfd9ff-04ee-4a0a-b3b3-b7d3bcebe7f4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390613676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3390613676
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.3555792349
Short name T95
Test name
Test status
Simulation time 44897428011 ps
CPU time 4650.42 seconds
Started Aug 03 05:10:16 PM PDT 24
Finished Aug 03 06:27:47 PM PDT 24
Peak memory 335536 kb
Host smart-b2663471-d5c4-446c-9d7b-953baa98e4e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555792349 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.3555792349
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3414076678
Short name T62
Test name
Test status
Simulation time 158889619958 ps
CPU time 2346.58 seconds
Started Aug 03 05:10:32 PM PDT 24
Finished Aug 03 05:49:39 PM PDT 24
Peak memory 289000 kb
Host smart-bc0e4df1-682e-4c6b-902c-d993d9c779a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414076678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3414076678
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.497106654
Short name T447
Test name
Test status
Simulation time 6338340393 ps
CPU time 100.92 seconds
Started Aug 03 05:10:13 PM PDT 24
Finished Aug 03 05:11:54 PM PDT 24
Peak memory 256428 kb
Host smart-4451ffb7-0252-49ac-ba27-8b00ee525e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49710
6654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.497106654
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2425719975
Short name T696
Test name
Test status
Simulation time 161895925 ps
CPU time 16.36 seconds
Started Aug 03 05:10:18 PM PDT 24
Finished Aug 03 05:10:34 PM PDT 24
Peak memory 248112 kb
Host smart-72634694-ecad-4add-a95c-9f4f24fd49a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24257
19975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2425719975
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3446283040
Short name T580
Test name
Test status
Simulation time 45750948273 ps
CPU time 1269.17 seconds
Started Aug 03 05:10:14 PM PDT 24
Finished Aug 03 05:31:23 PM PDT 24
Peak memory 283332 kb
Host smart-be5eb357-24c6-4635-bdbf-e89f5d044b14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446283040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3446283040
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2586109010
Short name T597
Test name
Test status
Simulation time 4030223113 ps
CPU time 99.81 seconds
Started Aug 03 05:10:14 PM PDT 24
Finished Aug 03 05:11:54 PM PDT 24
Peak memory 247280 kb
Host smart-aa59d4b0-7654-4bff-957b-adf231a3e4cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586109010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2586109010
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.725337814
Short name T42
Test name
Test status
Simulation time 1718352093 ps
CPU time 50.72 seconds
Started Aug 03 05:10:33 PM PDT 24
Finished Aug 03 05:11:23 PM PDT 24
Peak memory 248268 kb
Host smart-fbef7245-6508-4284-9815-e635b54457fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72533
7814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.725337814
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1145542398
Short name T295
Test name
Test status
Simulation time 1616102299 ps
CPU time 27.89 seconds
Started Aug 03 05:10:15 PM PDT 24
Finished Aug 03 05:10:43 PM PDT 24
Peak memory 256088 kb
Host smart-3e3679fa-35ae-414c-83d2-b152b1eeda7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11455
42398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1145542398
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.581619915
Short name T672
Test name
Test status
Simulation time 413505008 ps
CPU time 32.7 seconds
Started Aug 03 05:10:33 PM PDT 24
Finished Aug 03 05:11:06 PM PDT 24
Peak memory 248300 kb
Host smart-c670ca99-a454-48cb-8de3-7edc0942bb1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58161
9915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.581619915
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3337502054
Short name T237
Test name
Test status
Simulation time 2192352491 ps
CPU time 18.58 seconds
Started Aug 03 05:10:34 PM PDT 24
Finished Aug 03 05:10:53 PM PDT 24
Peak memory 248804 kb
Host smart-8dc8af48-f247-404c-a90c-99f1a73a5383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33375
02054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3337502054
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1329678443
Short name T579
Test name
Test status
Simulation time 8295112101 ps
CPU time 118.37 seconds
Started Aug 03 05:10:32 PM PDT 24
Finished Aug 03 05:12:30 PM PDT 24
Peak memory 256524 kb
Host smart-b7a3a78c-3e88-4984-8d10-7e3dfb81e061
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329678443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1329678443
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.2936094740
Short name T57
Test name
Test status
Simulation time 27668614247 ps
CPU time 1839.61 seconds
Started Aug 03 05:10:11 PM PDT 24
Finished Aug 03 05:40:52 PM PDT 24
Peak memory 288956 kb
Host smart-ef2b0eef-ded7-4791-93f5-a016729757fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936094740 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.2936094740
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1770383405
Short name T477
Test name
Test status
Simulation time 17518568658 ps
CPU time 1576.41 seconds
Started Aug 03 05:10:14 PM PDT 24
Finished Aug 03 05:36:31 PM PDT 24
Peak memory 288580 kb
Host smart-a5f0a43c-cfd3-4a72-8247-c82f7e74d366
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770383405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1770383405
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3217101461
Short name T193
Test name
Test status
Simulation time 858264792 ps
CPU time 55.73 seconds
Started Aug 03 05:10:31 PM PDT 24
Finished Aug 03 05:11:27 PM PDT 24
Peak memory 256444 kb
Host smart-29d00ba9-7b10-4566-85ff-c3b2ffe0cbaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32171
01461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3217101461
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.305901875
Short name T230
Test name
Test status
Simulation time 1344113381 ps
CPU time 34.63 seconds
Started Aug 03 05:10:21 PM PDT 24
Finished Aug 03 05:10:55 PM PDT 24
Peak memory 248300 kb
Host smart-8c3004b8-5e8b-450d-be1f-53492bfab5f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30590
1875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.305901875
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1956404130
Short name T264
Test name
Test status
Simulation time 20388625904 ps
CPU time 1194.47 seconds
Started Aug 03 05:10:16 PM PDT 24
Finished Aug 03 05:30:10 PM PDT 24
Peak memory 285724 kb
Host smart-4a8ec3ad-ed74-45e6-b5f5-eed084934ed4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956404130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1956404130
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3090664074
Short name T407
Test name
Test status
Simulation time 221703205321 ps
CPU time 3430.01 seconds
Started Aug 03 05:10:41 PM PDT 24
Finished Aug 03 06:07:52 PM PDT 24
Peak memory 289320 kb
Host smart-424cc59f-d8c1-4cc9-ab00-9dfa12ea04af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090664074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3090664074
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.53672915
Short name T369
Test name
Test status
Simulation time 1269215058 ps
CPU time 66.94 seconds
Started Aug 03 05:10:13 PM PDT 24
Finished Aug 03 05:11:20 PM PDT 24
Peak memory 255748 kb
Host smart-22d496ac-9e0a-49c4-9d02-bbe495c9f88d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53672
915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.53672915
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3240668098
Short name T412
Test name
Test status
Simulation time 2186652909 ps
CPU time 31.55 seconds
Started Aug 03 05:10:29 PM PDT 24
Finished Aug 03 05:11:00 PM PDT 24
Peak memory 256104 kb
Host smart-ae836c67-3137-4b42-835b-e24c2d10a057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32406
68098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3240668098
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.886668947
Short name T462
Test name
Test status
Simulation time 609824395 ps
CPU time 35.16 seconds
Started Aug 03 05:10:37 PM PDT 24
Finished Aug 03 05:11:13 PM PDT 24
Peak memory 255724 kb
Host smart-0890b4c6-92ac-4824-adb1-def06e9e2ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88666
8947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.886668947
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.91154422
Short name T35
Test name
Test status
Simulation time 4478601165 ps
CPU time 148.66 seconds
Started Aug 03 05:10:21 PM PDT 24
Finished Aug 03 05:12:50 PM PDT 24
Peak memory 250688 kb
Host smart-3ea5e37c-d030-43e6-97a9-596ba74fd917
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91154422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_hand
ler_stress_all.91154422
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3284993217
Short name T52
Test name
Test status
Simulation time 34253393378 ps
CPU time 1863.66 seconds
Started Aug 03 05:10:26 PM PDT 24
Finished Aug 03 05:41:30 PM PDT 24
Peak memory 287984 kb
Host smart-472eafbf-2dd9-42a8-ae8c-4fa913e5ff84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284993217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3284993217
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1412939626
Short name T556
Test name
Test status
Simulation time 399018398 ps
CPU time 34.41 seconds
Started Aug 03 05:10:36 PM PDT 24
Finished Aug 03 05:11:10 PM PDT 24
Peak memory 256016 kb
Host smart-da3297b1-18f8-43e7-970b-f3980aa4ba71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14129
39626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1412939626
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1628801964
Short name T533
Test name
Test status
Simulation time 319357301 ps
CPU time 19.33 seconds
Started Aug 03 05:10:19 PM PDT 24
Finished Aug 03 05:10:38 PM PDT 24
Peak memory 247964 kb
Host smart-fe7efd97-291a-4c44-b9ef-9b6460207dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16288
01964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1628801964
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.3090936744
Short name T640
Test name
Test status
Simulation time 28234089743 ps
CPU time 1131.32 seconds
Started Aug 03 05:10:19 PM PDT 24
Finished Aug 03 05:29:11 PM PDT 24
Peak memory 284348 kb
Host smart-43b9c3ba-3be2-4756-a481-8c7ac1d27f97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090936744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3090936744
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1505286579
Short name T432
Test name
Test status
Simulation time 135437306087 ps
CPU time 2080.93 seconds
Started Aug 03 05:10:24 PM PDT 24
Finished Aug 03 05:45:05 PM PDT 24
Peak memory 289192 kb
Host smart-cf438693-e3dd-4d55-bfe9-2dceab2883ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505286579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1505286579
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.705836914
Short name T244
Test name
Test status
Simulation time 7845209850 ps
CPU time 316.01 seconds
Started Aug 03 05:10:40 PM PDT 24
Finished Aug 03 05:15:56 PM PDT 24
Peak memory 248252 kb
Host smart-e01a0160-916c-44af-8287-fca18c99a2b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705836914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.705836914
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.651506430
Short name T454
Test name
Test status
Simulation time 4602362592 ps
CPU time 43.58 seconds
Started Aug 03 05:10:38 PM PDT 24
Finished Aug 03 05:11:21 PM PDT 24
Peak memory 248340 kb
Host smart-c76978f2-c64e-41b1-a9ed-30af736a9b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65150
6430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.651506430
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2903990198
Short name T376
Test name
Test status
Simulation time 383555751 ps
CPU time 34.44 seconds
Started Aug 03 05:10:20 PM PDT 24
Finished Aug 03 05:10:54 PM PDT 24
Peak memory 247668 kb
Host smart-d87c55b5-f54d-4e77-a02e-41ed641d3a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29039
90198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2903990198
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.746384958
Short name T574
Test name
Test status
Simulation time 449794427 ps
CPU time 21.07 seconds
Started Aug 03 05:10:18 PM PDT 24
Finished Aug 03 05:10:40 PM PDT 24
Peak memory 256432 kb
Host smart-0118a9f0-6cc9-463a-8a38-9d2e4df60825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74638
4958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.746384958
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2776333837
Short name T522
Test name
Test status
Simulation time 812346085 ps
CPU time 10.21 seconds
Started Aug 03 05:10:27 PM PDT 24
Finished Aug 03 05:10:37 PM PDT 24
Peak memory 254448 kb
Host smart-c0774d55-f39f-484a-b099-42760b043fc8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776333837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2776333837
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.418858391
Short name T40
Test name
Test status
Simulation time 104529892457 ps
CPU time 1721.54 seconds
Started Aug 03 05:10:40 PM PDT 24
Finished Aug 03 05:39:22 PM PDT 24
Peak memory 289068 kb
Host smart-b45cff4e-8650-49bd-9cf0-5f71234e52d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418858391 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.418858391
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1821107776
Short name T181
Test name
Test status
Simulation time 67204051957 ps
CPU time 2391.73 seconds
Started Aug 03 05:10:43 PM PDT 24
Finished Aug 03 05:50:35 PM PDT 24
Peak memory 285180 kb
Host smart-eea04a3f-c1b2-4c7b-a8a4-aaa34a818ec5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821107776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1821107776
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3006123782
Short name T630
Test name
Test status
Simulation time 2054044317 ps
CPU time 42.11 seconds
Started Aug 03 05:10:32 PM PDT 24
Finished Aug 03 05:11:14 PM PDT 24
Peak memory 255876 kb
Host smart-3bfa2feb-83a0-4a44-bff2-04e8bccca1dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30061
23782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3006123782
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2064811176
Short name T553
Test name
Test status
Simulation time 106496130 ps
CPU time 2.7 seconds
Started Aug 03 05:10:41 PM PDT 24
Finished Aug 03 05:10:44 PM PDT 24
Peak memory 240068 kb
Host smart-b2cbec91-1314-43a4-a58e-866c791005a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20648
11176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2064811176
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.111374929
Short name T598
Test name
Test status
Simulation time 25976478168 ps
CPU time 1562.41 seconds
Started Aug 03 05:10:35 PM PDT 24
Finished Aug 03 05:36:38 PM PDT 24
Peak memory 264860 kb
Host smart-f383ae5b-2683-4c5d-8bb3-2cbe57c74e96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111374929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.111374929
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3035746701
Short name T618
Test name
Test status
Simulation time 39149176324 ps
CPU time 1009.79 seconds
Started Aug 03 05:10:18 PM PDT 24
Finished Aug 03 05:27:09 PM PDT 24
Peak memory 281120 kb
Host smart-1cceec05-4508-469a-8018-2c2a20772bde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035746701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3035746701
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1476891962
Short name T316
Test name
Test status
Simulation time 7821609488 ps
CPU time 95.01 seconds
Started Aug 03 05:10:20 PM PDT 24
Finished Aug 03 05:11:55 PM PDT 24
Peak memory 248348 kb
Host smart-d8215d30-39df-4cbc-b4b1-1ef6c6de53bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476891962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1476891962
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3883502345
Short name T576
Test name
Test status
Simulation time 347534784 ps
CPU time 7.22 seconds
Started Aug 03 05:10:21 PM PDT 24
Finished Aug 03 05:10:29 PM PDT 24
Peak memory 252136 kb
Host smart-ad91cdda-df5f-4a38-8ff5-e5aa92847d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38835
02345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3883502345
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.197921601
Short name T652
Test name
Test status
Simulation time 498559207 ps
CPU time 31.69 seconds
Started Aug 03 05:10:37 PM PDT 24
Finished Aug 03 05:11:09 PM PDT 24
Peak memory 256068 kb
Host smart-30e9a926-b870-4185-ab76-f0b6ae9dddbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19792
1601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.197921601
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1666095473
Short name T519
Test name
Test status
Simulation time 119891801 ps
CPU time 13.92 seconds
Started Aug 03 05:10:33 PM PDT 24
Finished Aug 03 05:10:47 PM PDT 24
Peak memory 255772 kb
Host smart-553eba28-3698-4ea9-b11e-caa330b58a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16660
95473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1666095473
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2668831595
Short name T509
Test name
Test status
Simulation time 369421612 ps
CPU time 31.2 seconds
Started Aug 03 05:10:39 PM PDT 24
Finished Aug 03 05:11:10 PM PDT 24
Peak memory 256492 kb
Host smart-205cf218-33c4-4ab0-8b77-6f3234fc200f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26688
31595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2668831595
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2698934365
Short name T285
Test name
Test status
Simulation time 181422175944 ps
CPU time 2884 seconds
Started Aug 03 05:10:40 PM PDT 24
Finished Aug 03 05:58:45 PM PDT 24
Peak memory 297244 kb
Host smart-fec01029-6d77-4412-b4ca-48c1f99a9832
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698934365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2698934365
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.115602674
Short name T695
Test name
Test status
Simulation time 39716792235 ps
CPU time 745.65 seconds
Started Aug 03 05:10:40 PM PDT 24
Finished Aug 03 05:23:06 PM PDT 24
Peak memory 272872 kb
Host smart-a4496c60-fa3f-4450-92e8-9e787f6db6ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115602674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.115602674
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1918632399
Short name T178
Test name
Test status
Simulation time 1107250259 ps
CPU time 65.16 seconds
Started Aug 03 05:10:47 PM PDT 24
Finished Aug 03 05:11:52 PM PDT 24
Peak memory 256012 kb
Host smart-dcf87532-06e2-49d2-97de-112e0b38f8c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19186
32399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1918632399
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1404997692
Short name T669
Test name
Test status
Simulation time 44861754 ps
CPU time 2.91 seconds
Started Aug 03 05:10:40 PM PDT 24
Finished Aug 03 05:10:43 PM PDT 24
Peak memory 240140 kb
Host smart-2d25a252-2701-4bfb-84c1-56a0cad2ab4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14049
97692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1404997692
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1899147423
Short name T353
Test name
Test status
Simulation time 170798040759 ps
CPU time 2508.49 seconds
Started Aug 03 05:10:40 PM PDT 24
Finished Aug 03 05:52:29 PM PDT 24
Peak memory 286988 kb
Host smart-017be6b7-e4c2-4ad9-98ca-2ebe25b54441
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899147423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1899147423
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1817433658
Short name T438
Test name
Test status
Simulation time 7742894915 ps
CPU time 977.36 seconds
Started Aug 03 05:10:44 PM PDT 24
Finished Aug 03 05:27:01 PM PDT 24
Peak memory 282424 kb
Host smart-116bc2d9-02cf-49ab-b3ac-312df4d82500
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817433658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1817433658
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2792751709
Short name T641
Test name
Test status
Simulation time 43103065821 ps
CPU time 130.15 seconds
Started Aug 03 05:10:40 PM PDT 24
Finished Aug 03 05:12:50 PM PDT 24
Peak memory 247144 kb
Host smart-5e7f1e4d-c15b-49bc-8222-6f3438c47b55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792751709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2792751709
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3667280858
Short name T571
Test name
Test status
Simulation time 154068070 ps
CPU time 10.97 seconds
Started Aug 03 05:10:46 PM PDT 24
Finished Aug 03 05:10:57 PM PDT 24
Peak memory 248328 kb
Host smart-36d646e0-6aff-49fe-a152-aaa3f0bcd5f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36672
80858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3667280858
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3823950654
Short name T36
Test name
Test status
Simulation time 176553868 ps
CPU time 12.3 seconds
Started Aug 03 05:10:38 PM PDT 24
Finished Aug 03 05:10:50 PM PDT 24
Peak memory 247792 kb
Host smart-4e67f7bc-ae06-4f02-97ca-0021ed3de2d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38239
50654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3823950654
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1634347912
Short name T64
Test name
Test status
Simulation time 447438634 ps
CPU time 32.79 seconds
Started Aug 03 05:10:41 PM PDT 24
Finished Aug 03 05:11:14 PM PDT 24
Peak memory 248864 kb
Host smart-4391e8d4-eeac-43a8-abb1-50c2aef8bb3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16343
47912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1634347912
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2042326400
Short name T549
Test name
Test status
Simulation time 60448283 ps
CPU time 4.93 seconds
Started Aug 03 05:10:20 PM PDT 24
Finished Aug 03 05:10:25 PM PDT 24
Peak memory 250428 kb
Host smart-82f25613-ebcb-4d6c-934f-9eee7aa664c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20423
26400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2042326400
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1875291146
Short name T544
Test name
Test status
Simulation time 6922544016 ps
CPU time 94.9 seconds
Started Aug 03 05:10:34 PM PDT 24
Finished Aug 03 05:12:09 PM PDT 24
Peak memory 255292 kb
Host smart-e21015da-a3b4-4a1c-8d91-15345a73e538
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875291146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1875291146
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.4114583448
Short name T72
Test name
Test status
Simulation time 58891684984 ps
CPU time 2915.68 seconds
Started Aug 03 05:10:39 PM PDT 24
Finished Aug 03 05:59:15 PM PDT 24
Peak memory 297040 kb
Host smart-a9129479-2dc1-4a4c-bf1b-c5ca15e9a706
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114583448 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.4114583448
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1302477487
Short name T240
Test name
Test status
Simulation time 10632080229 ps
CPU time 1035.32 seconds
Started Aug 03 05:10:45 PM PDT 24
Finished Aug 03 05:28:01 PM PDT 24
Peak memory 288732 kb
Host smart-2ba56b05-f3ca-4905-bae9-5c9c72fbe979
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302477487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1302477487
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.4263995735
Short name T403
Test name
Test status
Simulation time 1669894510 ps
CPU time 24.04 seconds
Started Aug 03 05:10:40 PM PDT 24
Finished Aug 03 05:11:04 PM PDT 24
Peak memory 256004 kb
Host smart-472d28d1-9a6d-4529-800b-0663fd9cc603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42639
95735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.4263995735
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2347608238
Short name T373
Test name
Test status
Simulation time 665217144 ps
CPU time 40.83 seconds
Started Aug 03 05:10:45 PM PDT 24
Finished Aug 03 05:11:26 PM PDT 24
Peak memory 248352 kb
Host smart-986b69f4-f7ec-41a1-a8ad-616587bf8a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23476
08238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2347608238
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1980803091
Short name T253
Test name
Test status
Simulation time 194372023074 ps
CPU time 1630.27 seconds
Started Aug 03 05:10:42 PM PDT 24
Finished Aug 03 05:37:53 PM PDT 24
Peak memory 272944 kb
Host smart-3860b0e0-0599-4475-a57c-91087f412792
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980803091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1980803091
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.419453045
Short name T389
Test name
Test status
Simulation time 18609796169 ps
CPU time 965.37 seconds
Started Aug 03 05:10:41 PM PDT 24
Finished Aug 03 05:26:47 PM PDT 24
Peak memory 272248 kb
Host smart-3a2b4586-cdf4-456f-9d4d-dddb375c0cff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419453045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.419453045
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3761261027
Short name T252
Test name
Test status
Simulation time 3996932393 ps
CPU time 157.14 seconds
Started Aug 03 05:10:32 PM PDT 24
Finished Aug 03 05:13:10 PM PDT 24
Peak memory 248184 kb
Host smart-776bf19f-3442-4297-972c-c951f5fdf337
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761261027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3761261027
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3014606798
Short name T492
Test name
Test status
Simulation time 215451774 ps
CPU time 7.1 seconds
Started Aug 03 05:10:45 PM PDT 24
Finished Aug 03 05:10:52 PM PDT 24
Peak memory 248316 kb
Host smart-93a2cb64-f04b-437c-a3d0-eadda4ccd5e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30146
06798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3014606798
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2528775446
Short name T440
Test name
Test status
Simulation time 32732144 ps
CPU time 2.73 seconds
Started Aug 03 05:10:48 PM PDT 24
Finished Aug 03 05:10:50 PM PDT 24
Peak memory 239644 kb
Host smart-90f265ae-7a91-4026-8a99-f1814bb7c71c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25287
75446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2528775446
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2878403245
Short name T68
Test name
Test status
Simulation time 1364168953 ps
CPU time 6.66 seconds
Started Aug 03 05:10:45 PM PDT 24
Finished Aug 03 05:10:52 PM PDT 24
Peak memory 252228 kb
Host smart-eb48797b-b772-4806-b76b-85cfd82f6df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28784
03245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2878403245
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2277799220
Short name T489
Test name
Test status
Simulation time 53189320 ps
CPU time 4.72 seconds
Started Aug 03 05:10:40 PM PDT 24
Finished Aug 03 05:10:45 PM PDT 24
Peak memory 250568 kb
Host smart-c3af2469-e8d0-4194-a77d-5e0c5e129a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22777
99220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2277799220
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1945107935
Short name T27
Test name
Test status
Simulation time 41699385213 ps
CPU time 2350.44 seconds
Started Aug 03 05:10:41 PM PDT 24
Finished Aug 03 05:49:52 PM PDT 24
Peak memory 286048 kb
Host smart-db972234-5a75-48ed-a795-86d003625e9a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945107935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1945107935
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1385493231
Short name T415
Test name
Test status
Simulation time 13218215490 ps
CPU time 1163.61 seconds
Started Aug 03 05:10:44 PM PDT 24
Finished Aug 03 05:30:08 PM PDT 24
Peak memory 289224 kb
Host smart-c0daaf3f-0095-4e35-b5fd-f19d41d4c9b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385493231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1385493231
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2506182141
Short name T535
Test name
Test status
Simulation time 3515939674 ps
CPU time 181.9 seconds
Started Aug 03 05:10:44 PM PDT 24
Finished Aug 03 05:13:46 PM PDT 24
Peak memory 256112 kb
Host smart-124678df-d6ba-4382-821a-323f4e6edf6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25061
82141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2506182141
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.928778697
Short name T97
Test name
Test status
Simulation time 632699480 ps
CPU time 37.86 seconds
Started Aug 03 05:10:46 PM PDT 24
Finished Aug 03 05:11:24 PM PDT 24
Peak memory 248296 kb
Host smart-3d52be82-a966-4b82-a574-a538fb6c3ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92877
8697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.928778697
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.184112249
Short name T37
Test name
Test status
Simulation time 22111197450 ps
CPU time 1243.68 seconds
Started Aug 03 05:10:44 PM PDT 24
Finished Aug 03 05:31:28 PM PDT 24
Peak memory 281144 kb
Host smart-143a7b6d-6e2d-4258-9ff9-b04a48867054
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184112249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.184112249
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.681658124
Short name T83
Test name
Test status
Simulation time 140443601115 ps
CPU time 2155.43 seconds
Started Aug 03 05:10:46 PM PDT 24
Finished Aug 03 05:46:42 PM PDT 24
Peak memory 284012 kb
Host smart-6c6a0079-2b69-4640-8ae2-76ef14a459a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681658124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.681658124
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2707886402
Short name T233
Test name
Test status
Simulation time 11542169591 ps
CPU time 127.46 seconds
Started Aug 03 05:10:44 PM PDT 24
Finished Aug 03 05:12:51 PM PDT 24
Peak memory 247328 kb
Host smart-1991afc3-084b-48e0-8ed6-9538f4b44540
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707886402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2707886402
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3024591384
Short name T600
Test name
Test status
Simulation time 152960636 ps
CPU time 21.84 seconds
Started Aug 03 05:10:56 PM PDT 24
Finished Aug 03 05:11:18 PM PDT 24
Peak memory 256388 kb
Host smart-b30f8e6f-21fa-415b-b0fc-e7a300ad8a62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30245
91384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3024591384
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2401155670
Short name T437
Test name
Test status
Simulation time 2642413830 ps
CPU time 47.81 seconds
Started Aug 03 05:10:44 PM PDT 24
Finished Aug 03 05:11:32 PM PDT 24
Peak memory 256140 kb
Host smart-c09907d6-ec85-4ddb-bbd5-3b76f3e5f725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24011
55670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2401155670
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1562828855
Short name T284
Test name
Test status
Simulation time 3977575517 ps
CPU time 63.65 seconds
Started Aug 03 05:10:45 PM PDT 24
Finished Aug 03 05:11:49 PM PDT 24
Peak memory 248020 kb
Host smart-9166d116-fb62-4210-8ec8-408e9666cc47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15628
28855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1562828855
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3091149007
Short name T419
Test name
Test status
Simulation time 1207933742 ps
CPU time 69.6 seconds
Started Aug 03 05:10:45 PM PDT 24
Finished Aug 03 05:11:55 PM PDT 24
Peak memory 256468 kb
Host smart-13ff9bc5-5e01-4053-b161-a3b23608d097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30911
49007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3091149007
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.4232349225
Short name T613
Test name
Test status
Simulation time 61487406685 ps
CPU time 3279.21 seconds
Started Aug 03 05:10:44 PM PDT 24
Finished Aug 03 06:05:24 PM PDT 24
Peak memory 321932 kb
Host smart-cacd18df-95e1-40fc-a272-5d4bc5634d7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232349225 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.4232349225
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2699770349
Short name T58
Test name
Test status
Simulation time 99211276123 ps
CPU time 1541.39 seconds
Started Aug 03 05:10:47 PM PDT 24
Finished Aug 03 05:36:29 PM PDT 24
Peak memory 272524 kb
Host smart-dc8f87f4-1e67-425e-bb0a-863da98a130d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699770349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2699770349
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.608912649
Short name T569
Test name
Test status
Simulation time 3242759115 ps
CPU time 190.57 seconds
Started Aug 03 05:10:49 PM PDT 24
Finished Aug 03 05:14:00 PM PDT 24
Peak memory 256020 kb
Host smart-8c7a0fec-09c3-40ff-a309-da475fed5b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60891
2649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.608912649
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3451570747
Short name T575
Test name
Test status
Simulation time 850424260 ps
CPU time 60.12 seconds
Started Aug 03 05:10:43 PM PDT 24
Finished Aug 03 05:11:44 PM PDT 24
Peak memory 248288 kb
Host smart-5ef762f4-694a-4037-93fb-47ca3854dfa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34515
70747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3451570747
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.4178216242
Short name T2
Test name
Test status
Simulation time 13099545747 ps
CPU time 1333.57 seconds
Started Aug 03 05:10:44 PM PDT 24
Finished Aug 03 05:32:58 PM PDT 24
Peak memory 288516 kb
Host smart-ee621cf6-1419-481a-9373-7359074d2627
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178216242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.4178216242
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.715538364
Short name T661
Test name
Test status
Simulation time 10778894423 ps
CPU time 393.76 seconds
Started Aug 03 05:10:39 PM PDT 24
Finished Aug 03 05:17:13 PM PDT 24
Peak memory 248320 kb
Host smart-2ff80146-beef-4fe5-9298-ee931ddb815e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715538364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.715538364
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2637664803
Short name T458
Test name
Test status
Simulation time 274380902 ps
CPU time 35.17 seconds
Started Aug 03 05:10:44 PM PDT 24
Finished Aug 03 05:11:19 PM PDT 24
Peak memory 248292 kb
Host smart-a415d32f-cb27-43b7-8760-a9e0a37d663c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26376
64803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2637664803
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.335456813
Short name T279
Test name
Test status
Simulation time 468726939 ps
CPU time 30.88 seconds
Started Aug 03 05:10:49 PM PDT 24
Finished Aug 03 05:11:20 PM PDT 24
Peak memory 255224 kb
Host smart-6fdb72f2-1861-4d04-a08f-befaa2e6e28e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33545
6813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.335456813
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3332975972
Short name T49
Test name
Test status
Simulation time 800618313 ps
CPU time 49.22 seconds
Started Aug 03 05:10:45 PM PDT 24
Finished Aug 03 05:11:35 PM PDT 24
Peak memory 256464 kb
Host smart-f382e986-0efd-41c7-a7cd-48cc4ef502a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33329
75972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3332975972
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.38066391
Short name T174
Test name
Test status
Simulation time 327307152557 ps
CPU time 5426.85 seconds
Started Aug 03 05:10:41 PM PDT 24
Finished Aug 03 06:41:09 PM PDT 24
Peak memory 305744 kb
Host smart-f8de1791-1895-49c4-9ca8-d2bc1a5ea340
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38066391 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.38066391
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3867898803
Short name T206
Test name
Test status
Simulation time 118707669 ps
CPU time 2.99 seconds
Started Aug 03 05:09:59 PM PDT 24
Finished Aug 03 05:10:02 PM PDT 24
Peak memory 248596 kb
Host smart-cd6e2fae-0a1d-42af-b83d-be8cf53f4ae1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3867898803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3867898803
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1556777592
Short name T85
Test name
Test status
Simulation time 13221788799 ps
CPU time 1123.44 seconds
Started Aug 03 05:09:56 PM PDT 24
Finished Aug 03 05:28:40 PM PDT 24
Peak memory 281152 kb
Host smart-e7218b92-ded0-4137-b000-22fa507fb878
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556777592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1556777592
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.4053008678
Short name T609
Test name
Test status
Simulation time 192706428 ps
CPU time 10.75 seconds
Started Aug 03 05:10:01 PM PDT 24
Finished Aug 03 05:10:11 PM PDT 24
Peak memory 248260 kb
Host smart-068884f6-da10-488a-9c64-d6cafea1b15d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4053008678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.4053008678
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.378219997
Short name T387
Test name
Test status
Simulation time 3232215360 ps
CPU time 129.9 seconds
Started Aug 03 05:09:50 PM PDT 24
Finished Aug 03 05:12:00 PM PDT 24
Peak memory 251484 kb
Host smart-c9cc425c-c17f-496b-9e2b-a5823f86bbc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37821
9997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.378219997
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3917975682
Short name T399
Test name
Test status
Simulation time 164667006 ps
CPU time 18.8 seconds
Started Aug 03 05:09:54 PM PDT 24
Finished Aug 03 05:10:14 PM PDT 24
Peak memory 248144 kb
Host smart-5e86322f-c895-4121-9850-12c5fbf2565c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39179
75682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3917975682
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1782998201
Short name T341
Test name
Test status
Simulation time 18803405332 ps
CPU time 809.75 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 05:23:40 PM PDT 24
Peak memory 272968 kb
Host smart-196398a1-ac11-46b5-87a0-59c149da226b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782998201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1782998201
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2510007360
Short name T567
Test name
Test status
Simulation time 35105281466 ps
CPU time 812.19 seconds
Started Aug 03 05:09:54 PM PDT 24
Finished Aug 03 05:23:27 PM PDT 24
Peak memory 272544 kb
Host smart-d87cd35a-2aa5-4bd7-a53e-53945ffd3a03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510007360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2510007360
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1058427078
Short name T222
Test name
Test status
Simulation time 65343027890 ps
CPU time 721.23 seconds
Started Aug 03 05:09:56 PM PDT 24
Finished Aug 03 05:21:57 PM PDT 24
Peak memory 248048 kb
Host smart-0028f774-a56c-43f6-bc04-e1b53038a42b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058427078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1058427078
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1376103403
Short name T612
Test name
Test status
Simulation time 644851979 ps
CPU time 10.69 seconds
Started Aug 03 05:09:57 PM PDT 24
Finished Aug 03 05:10:08 PM PDT 24
Peak memory 253980 kb
Host smart-41558963-f5b9-4473-ab4a-811634bb5d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13761
03403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1376103403
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1417645095
Short name T636
Test name
Test status
Simulation time 1064828927 ps
CPU time 63.51 seconds
Started Aug 03 05:10:04 PM PDT 24
Finished Aug 03 05:11:13 PM PDT 24
Peak memory 248280 kb
Host smart-86ee38f9-807a-4e9d-b4cc-ade83a2245f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14176
45095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1417645095
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2935208295
Short name T479
Test name
Test status
Simulation time 471288276 ps
CPU time 12.22 seconds
Started Aug 03 05:09:59 PM PDT 24
Finished Aug 03 05:10:11 PM PDT 24
Peak memory 255416 kb
Host smart-b19bd653-3d18-4aef-ba9e-7a90579311e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29352
08295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2935208295
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.2734140631
Short name T289
Test name
Test status
Simulation time 34412694457 ps
CPU time 3713.87 seconds
Started Aug 03 05:09:55 PM PDT 24
Finished Aug 03 06:11:50 PM PDT 24
Peak memory 322180 kb
Host smart-ed5284ba-5c06-4b44-961a-4c56777d7982
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734140631 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.2734140631
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2735656383
Short name T449
Test name
Test status
Simulation time 30522127652 ps
CPU time 875.1 seconds
Started Aug 03 05:10:45 PM PDT 24
Finished Aug 03 05:25:20 PM PDT 24
Peak memory 284624 kb
Host smart-bb8f9be6-58d3-4dda-b05b-950100eae295
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735656383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2735656383
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2517271348
Short name T394
Test name
Test status
Simulation time 2839383268 ps
CPU time 186.54 seconds
Started Aug 03 05:10:44 PM PDT 24
Finished Aug 03 05:13:51 PM PDT 24
Peak memory 256616 kb
Host smart-1112f117-9c27-4249-8d7d-514d22f5b3c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25172
71348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2517271348
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1792531710
Short name T523
Test name
Test status
Simulation time 3730694093 ps
CPU time 37.42 seconds
Started Aug 03 05:10:37 PM PDT 24
Finished Aug 03 05:11:15 PM PDT 24
Peak memory 256460 kb
Host smart-016ef53b-f7a0-4a2b-853e-c6ca9ac83cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17925
31710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1792531710
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2893516484
Short name T306
Test name
Test status
Simulation time 38785226436 ps
CPU time 1138.65 seconds
Started Aug 03 05:10:43 PM PDT 24
Finished Aug 03 05:29:41 PM PDT 24
Peak memory 272796 kb
Host smart-6211d156-282b-459c-ae78-c173a2081432
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893516484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2893516484
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.4016333489
Short name T655
Test name
Test status
Simulation time 20701893483 ps
CPU time 416.46 seconds
Started Aug 03 05:10:47 PM PDT 24
Finished Aug 03 05:17:43 PM PDT 24
Peak memory 248176 kb
Host smart-a819f3df-030e-4688-93bf-2a955ed7adb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016333489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.4016333489
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1053245116
Short name T664
Test name
Test status
Simulation time 106237112 ps
CPU time 4.22 seconds
Started Aug 03 05:10:39 PM PDT 24
Finished Aug 03 05:10:44 PM PDT 24
Peak memory 240092 kb
Host smart-99ce9371-5ce7-4676-ad06-449bfa64b24b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10532
45116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1053245116
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2727464004
Short name T494
Test name
Test status
Simulation time 628447906 ps
CPU time 7.94 seconds
Started Aug 03 05:10:41 PM PDT 24
Finished Aug 03 05:10:49 PM PDT 24
Peak memory 247876 kb
Host smart-2f88adac-92ab-4335-b5ec-362be187a4da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27274
64004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2727464004
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3151236556
Short name T10
Test name
Test status
Simulation time 517133003 ps
CPU time 39.61 seconds
Started Aug 03 05:10:44 PM PDT 24
Finished Aug 03 05:11:24 PM PDT 24
Peak memory 248288 kb
Host smart-b72c2927-c920-4bf1-8057-ac27883e4493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31512
36556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3151236556
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.21044876
Short name T371
Test name
Test status
Simulation time 3687769119 ps
CPU time 54.27 seconds
Started Aug 03 05:10:45 PM PDT 24
Finished Aug 03 05:11:39 PM PDT 24
Peak memory 256576 kb
Host smart-b84a1f6f-bfad-4df5-8cd6-545135463418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21044
876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.21044876
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1676238230
Short name T659
Test name
Test status
Simulation time 8163086245 ps
CPU time 317.6 seconds
Started Aug 03 05:10:43 PM PDT 24
Finished Aug 03 05:16:00 PM PDT 24
Peak memory 256628 kb
Host smart-22afaa1f-3ff9-4323-b18b-e5c65515c756
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676238230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1676238230
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2421506866
Short name T262
Test name
Test status
Simulation time 47167363410 ps
CPU time 4177.11 seconds
Started Aug 03 05:10:42 PM PDT 24
Finished Aug 03 06:20:20 PM PDT 24
Peak memory 304488 kb
Host smart-09dfd91f-b862-476f-a102-118f15853ad1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421506866 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2421506866
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3258285097
Short name T642
Test name
Test status
Simulation time 769911683503 ps
CPU time 2135.61 seconds
Started Aug 03 05:10:52 PM PDT 24
Finished Aug 03 05:46:28 PM PDT 24
Peak memory 282372 kb
Host smart-5a36537f-f7f2-42f8-8793-d72759fd177d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258285097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3258285097
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1599820534
Short name T486
Test name
Test status
Simulation time 9914874394 ps
CPU time 138.74 seconds
Started Aug 03 05:10:45 PM PDT 24
Finished Aug 03 05:13:04 PM PDT 24
Peak memory 256516 kb
Host smart-47433bfd-ae1d-4762-98d9-932889c8b15b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15998
20534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1599820534
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2535581989
Short name T395
Test name
Test status
Simulation time 9197888668 ps
CPU time 63.48 seconds
Started Aug 03 05:10:50 PM PDT 24
Finished Aug 03 05:11:53 PM PDT 24
Peak memory 255944 kb
Host smart-6fb8f104-2c64-460e-a102-be764cc4710f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25355
81989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2535581989
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.2537075024
Short name T586
Test name
Test status
Simulation time 21392993672 ps
CPU time 1107.7 seconds
Started Aug 03 05:10:46 PM PDT 24
Finished Aug 03 05:29:14 PM PDT 24
Peak memory 272080 kb
Host smart-e56f17e2-2a07-4571-8939-3f5f9bd9e70c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537075024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2537075024
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1716308289
Short name T461
Test name
Test status
Simulation time 176074148036 ps
CPU time 2395.14 seconds
Started Aug 03 05:10:45 PM PDT 24
Finished Aug 03 05:50:40 PM PDT 24
Peak memory 281088 kb
Host smart-544fe45b-0f7e-4a0f-aa40-952987b97887
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716308289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1716308289
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2018494698
Short name T367
Test name
Test status
Simulation time 2851682968 ps
CPU time 44.32 seconds
Started Aug 03 05:10:42 PM PDT 24
Finished Aug 03 05:11:26 PM PDT 24
Peak memory 255960 kb
Host smart-4ae17865-0aaf-40cd-8afb-86a5f6b5272d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20184
94698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2018494698
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3093232321
Short name T530
Test name
Test status
Simulation time 591304006 ps
CPU time 30.13 seconds
Started Aug 03 05:10:45 PM PDT 24
Finished Aug 03 05:11:15 PM PDT 24
Peak memory 256448 kb
Host smart-2ad29fd3-2f2d-45b5-ba6c-2c0e9601e9dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30932
32321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3093232321
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1364582288
Short name T562
Test name
Test status
Simulation time 491057530 ps
CPU time 6.5 seconds
Started Aug 03 05:10:56 PM PDT 24
Finished Aug 03 05:11:03 PM PDT 24
Peak memory 248772 kb
Host smart-2e3a4e6a-545d-48d1-94e3-006584eed031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13645
82288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1364582288
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.4285668296
Short name T484
Test name
Test status
Simulation time 237947017 ps
CPU time 25.75 seconds
Started Aug 03 05:10:43 PM PDT 24
Finished Aug 03 05:11:09 PM PDT 24
Peak memory 255908 kb
Host smart-743ec517-9516-44dd-95b4-a8ec42cadcf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42856
68296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.4285668296
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1732089030
Short name T478
Test name
Test status
Simulation time 109551862244 ps
CPU time 1750.95 seconds
Started Aug 03 05:10:46 PM PDT 24
Finished Aug 03 05:39:57 PM PDT 24
Peak memory 288092 kb
Host smart-81cc0b58-9bb3-460f-a13a-a8e5f7781c55
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732089030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1732089030
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2257611677
Short name T433
Test name
Test status
Simulation time 10799219600 ps
CPU time 1245.47 seconds
Started Aug 03 05:10:46 PM PDT 24
Finished Aug 03 05:31:32 PM PDT 24
Peak memory 288548 kb
Host smart-30174b54-9954-4df2-8ee3-78dfb81bf3c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257611677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2257611677
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2323555864
Short name T269
Test name
Test status
Simulation time 1201156590 ps
CPU time 25.19 seconds
Started Aug 03 05:10:47 PM PDT 24
Finished Aug 03 05:11:12 PM PDT 24
Peak memory 256524 kb
Host smart-016bfbc6-4c0c-4888-bee4-2b98f43a1f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23235
55864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2323555864
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2518421180
Short name T663
Test name
Test status
Simulation time 184883451 ps
CPU time 12.94 seconds
Started Aug 03 05:10:43 PM PDT 24
Finished Aug 03 05:10:56 PM PDT 24
Peak memory 247828 kb
Host smart-b5dd4b6b-9d91-4c44-bd15-7bb3ae1ac071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25184
21180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2518421180
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.648515003
Short name T614
Test name
Test status
Simulation time 64847713560 ps
CPU time 1957.8 seconds
Started Aug 03 05:10:43 PM PDT 24
Finished Aug 03 05:43:21 PM PDT 24
Peak memory 283932 kb
Host smart-32f361bc-5946-43e6-9360-a2d0af5dcb84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648515003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.648515003
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2001788868
Short name T685
Test name
Test status
Simulation time 3337077356 ps
CPU time 107.29 seconds
Started Aug 03 05:10:44 PM PDT 24
Finished Aug 03 05:12:31 PM PDT 24
Peak memory 247148 kb
Host smart-dc280562-d98a-4477-8f5a-043c52bcbc0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001788868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2001788868
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3191795103
Short name T54
Test name
Test status
Simulation time 1179833844 ps
CPU time 37.16 seconds
Started Aug 03 05:10:54 PM PDT 24
Finished Aug 03 05:11:32 PM PDT 24
Peak memory 256172 kb
Host smart-f50b960d-05eb-4779-9873-ae482f6cb658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31917
95103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3191795103
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.857905620
Short name T662
Test name
Test status
Simulation time 851747166 ps
CPU time 24.1 seconds
Started Aug 03 05:10:43 PM PDT 24
Finished Aug 03 05:11:08 PM PDT 24
Peak memory 247908 kb
Host smart-d052f331-bb91-4b83-837d-60915b7643b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85790
5620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.857905620
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.905925384
Short name T435
Test name
Test status
Simulation time 229635054 ps
CPU time 25.89 seconds
Started Aug 03 05:10:46 PM PDT 24
Finished Aug 03 05:11:12 PM PDT 24
Peak memory 248216 kb
Host smart-f6f62ba6-a33d-4cf5-92c9-c15971cde796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90592
5384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.905925384
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2944087846
Short name T540
Test name
Test status
Simulation time 8546789265 ps
CPU time 33 seconds
Started Aug 03 05:10:39 PM PDT 24
Finished Aug 03 05:11:12 PM PDT 24
Peak memory 255528 kb
Host smart-c0614751-e9b8-4181-a643-c1c5049e679f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29440
87846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2944087846
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3082206879
Short name T430
Test name
Test status
Simulation time 38819021656 ps
CPU time 2295.43 seconds
Started Aug 03 05:10:45 PM PDT 24
Finished Aug 03 05:49:01 PM PDT 24
Peak memory 289292 kb
Host smart-0f006eff-ce8e-4580-a685-fb56985f5fa5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082206879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3082206879
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.259909026
Short name T423
Test name
Test status
Simulation time 1353853886 ps
CPU time 124.07 seconds
Started Aug 03 05:10:45 PM PDT 24
Finished Aug 03 05:12:49 PM PDT 24
Peak memory 256108 kb
Host smart-c897a663-c125-42ca-a851-192476413aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25990
9026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.259909026
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3029229828
Short name T510
Test name
Test status
Simulation time 401874139 ps
CPU time 17.32 seconds
Started Aug 03 05:10:47 PM PDT 24
Finished Aug 03 05:11:05 PM PDT 24
Peak memory 248296 kb
Host smart-03d60c62-d002-4de7-8617-3bcb6f3ad8a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30292
29828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3029229828
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3549464690
Short name T448
Test name
Test status
Simulation time 30598403435 ps
CPU time 2114.68 seconds
Started Aug 03 05:10:49 PM PDT 24
Finished Aug 03 05:46:04 PM PDT 24
Peak memory 287068 kb
Host smart-a68d21e9-3ad0-438c-b959-3523b834b8ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549464690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3549464690
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3291218514
Short name T315
Test name
Test status
Simulation time 7157877179 ps
CPU time 280.56 seconds
Started Aug 03 05:10:45 PM PDT 24
Finished Aug 03 05:15:26 PM PDT 24
Peak memory 248376 kb
Host smart-66f2f282-175a-4895-a8e0-4bba45640f31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291218514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3291218514
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.44948356
Short name T29
Test name
Test status
Simulation time 120079951 ps
CPU time 14.8 seconds
Started Aug 03 05:10:47 PM PDT 24
Finished Aug 03 05:11:02 PM PDT 24
Peak memory 255816 kb
Host smart-a4ae0008-7ffc-4c1d-8ef7-391eebf6ac45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44948
356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.44948356
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2648626723
Short name T676
Test name
Test status
Simulation time 392121598 ps
CPU time 24.55 seconds
Started Aug 03 05:10:49 PM PDT 24
Finished Aug 03 05:11:14 PM PDT 24
Peak memory 247692 kb
Host smart-abee5ab9-0a45-4cea-a539-5b33339a5cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26486
26723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2648626723
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.210871372
Short name T90
Test name
Test status
Simulation time 46299059 ps
CPU time 7.44 seconds
Started Aug 03 05:10:47 PM PDT 24
Finished Aug 03 05:10:55 PM PDT 24
Peak memory 247804 kb
Host smart-cffbea58-6117-49a7-9c4e-6b52fb24a795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21087
1372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.210871372
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2101277387
Short name T397
Test name
Test status
Simulation time 629013348 ps
CPU time 38.59 seconds
Started Aug 03 05:10:47 PM PDT 24
Finished Aug 03 05:11:26 PM PDT 24
Peak memory 256400 kb
Host smart-709c26b7-f049-4cb0-9665-e8d70c2d926f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21012
77387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2101277387
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1156800466
Short name T657
Test name
Test status
Simulation time 9058259859 ps
CPU time 932.85 seconds
Started Aug 03 05:10:43 PM PDT 24
Finished Aug 03 05:26:16 PM PDT 24
Peak memory 272844 kb
Host smart-4bb4f5b8-26fb-4b75-86ba-40672ca08825
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156800466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1156800466
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.418529529
Short name T304
Test name
Test status
Simulation time 48560589206 ps
CPU time 680.79 seconds
Started Aug 03 05:10:45 PM PDT 24
Finished Aug 03 05:22:06 PM PDT 24
Peak memory 272964 kb
Host smart-f427bc94-af48-4f79-8cf2-694402bcf7ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418529529 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.418529529
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3719169833
Short name T61
Test name
Test status
Simulation time 208582683914 ps
CPU time 1207.1 seconds
Started Aug 03 05:10:41 PM PDT 24
Finished Aug 03 05:30:48 PM PDT 24
Peak memory 272708 kb
Host smart-f703b81f-388a-4486-b82e-5229057a0634
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719169833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3719169833
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1232101248
Short name T599
Test name
Test status
Simulation time 1872616359 ps
CPU time 158.97 seconds
Started Aug 03 05:10:41 PM PDT 24
Finished Aug 03 05:13:20 PM PDT 24
Peak memory 256432 kb
Host smart-c1fef4af-2ab5-4dd5-a0dd-ed715fab3698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12321
01248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1232101248
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3965831164
Short name T472
Test name
Test status
Simulation time 570263038 ps
CPU time 16.4 seconds
Started Aug 03 05:10:41 PM PDT 24
Finished Aug 03 05:10:57 PM PDT 24
Peak memory 248016 kb
Host smart-d02b4645-b1d9-45f7-9feb-3251f33a1a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39658
31164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3965831164
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3155660272
Short name T248
Test name
Test status
Simulation time 23689190659 ps
CPU time 1195.28 seconds
Started Aug 03 05:10:43 PM PDT 24
Finished Aug 03 05:30:38 PM PDT 24
Peak memory 283488 kb
Host smart-7cf48cea-ec88-494a-b998-af28b22ccb9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155660272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3155660272
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1194177372
Short name T459
Test name
Test status
Simulation time 26571458208 ps
CPU time 1575.08 seconds
Started Aug 03 05:10:49 PM PDT 24
Finished Aug 03 05:37:05 PM PDT 24
Peak memory 284952 kb
Host smart-24ed2817-4863-45f8-86e6-828b17b58af7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194177372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1194177372
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.776774884
Short name T684
Test name
Test status
Simulation time 21103738485 ps
CPU time 226.33 seconds
Started Aug 03 05:10:42 PM PDT 24
Finished Aug 03 05:14:28 PM PDT 24
Peak memory 248396 kb
Host smart-9d09ccc9-72b7-4caf-90c2-11c0a055cecf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776774884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.776774884
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3337782633
Short name T559
Test name
Test status
Simulation time 160655722 ps
CPU time 14.75 seconds
Started Aug 03 05:10:44 PM PDT 24
Finished Aug 03 05:10:59 PM PDT 24
Peak memory 248320 kb
Host smart-20a6fc3e-cf11-45ae-8fc8-1de75ee39f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33377
82633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3337782633
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.345223497
Short name T422
Test name
Test status
Simulation time 360528514 ps
CPU time 5.26 seconds
Started Aug 03 05:10:41 PM PDT 24
Finished Aug 03 05:10:46 PM PDT 24
Peak memory 240124 kb
Host smart-2e0560fa-ca91-41f3-92ce-109b0aaea2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34522
3497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.345223497
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2583328697
Short name T507
Test name
Test status
Simulation time 607897418 ps
CPU time 29.67 seconds
Started Aug 03 05:10:41 PM PDT 24
Finished Aug 03 05:11:11 PM PDT 24
Peak memory 247424 kb
Host smart-385ae09c-899d-4918-a80e-6e89448d00f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25833
28697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2583328697
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3127795445
Short name T468
Test name
Test status
Simulation time 254176137 ps
CPU time 8.58 seconds
Started Aug 03 05:10:45 PM PDT 24
Finished Aug 03 05:10:53 PM PDT 24
Peak memory 248532 kb
Host smart-6f4bfd03-2402-4ae1-9d83-e64ab74d2694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31277
95445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3127795445
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2766691038
Short name T557
Test name
Test status
Simulation time 4882803935 ps
CPU time 274.46 seconds
Started Aug 03 05:10:49 PM PDT 24
Finished Aug 03 05:15:23 PM PDT 24
Peak memory 253308 kb
Host smart-d9cc45bc-a54d-44a4-9842-5a98793dba82
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766691038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2766691038
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2478204369
Short name T299
Test name
Test status
Simulation time 183206787261 ps
CPU time 3909.04 seconds
Started Aug 03 05:10:47 PM PDT 24
Finished Aug 03 06:15:57 PM PDT 24
Peak memory 347888 kb
Host smart-bbc22170-cc0e-4189-9267-7258f865f39f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478204369 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2478204369
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.3444617992
Short name T681
Test name
Test status
Simulation time 25893167469 ps
CPU time 1273.94 seconds
Started Aug 03 05:10:47 PM PDT 24
Finished Aug 03 05:32:01 PM PDT 24
Peak memory 287124 kb
Host smart-9b543d6d-c767-4e2e-8cc1-808fb57b1a39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444617992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3444617992
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.330001151
Short name T498
Test name
Test status
Simulation time 7607690923 ps
CPU time 105.51 seconds
Started Aug 03 05:10:50 PM PDT 24
Finished Aug 03 05:12:36 PM PDT 24
Peak memory 256572 kb
Host smart-d58138f0-08fe-4a7f-9a82-8b89eebe2528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33000
1151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.330001151
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3570701941
Short name T665
Test name
Test status
Simulation time 658227416 ps
CPU time 22.59 seconds
Started Aug 03 05:10:47 PM PDT 24
Finished Aug 03 05:11:10 PM PDT 24
Peak memory 247988 kb
Host smart-b4792036-3ec6-46a5-aace-99ca5d2ff29b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35707
01941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3570701941
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3804191276
Short name T480
Test name
Test status
Simulation time 6815068396 ps
CPU time 739.38 seconds
Started Aug 03 05:10:49 PM PDT 24
Finished Aug 03 05:23:08 PM PDT 24
Peak memory 272916 kb
Host smart-2e590cfa-30a9-4459-bfc1-ee85ade41ba7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804191276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3804191276
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3150048621
Short name T679
Test name
Test status
Simulation time 116360475312 ps
CPU time 3159.49 seconds
Started Aug 03 05:10:46 PM PDT 24
Finished Aug 03 06:03:26 PM PDT 24
Peak memory 289096 kb
Host smart-b8c74aba-11a5-4204-81d6-ec4024cafdd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150048621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3150048621
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1002497854
Short name T384
Test name
Test status
Simulation time 3967121770 ps
CPU time 53.3 seconds
Started Aug 03 05:10:49 PM PDT 24
Finished Aug 03 05:11:42 PM PDT 24
Peak memory 248388 kb
Host smart-f66de8ae-55e4-4919-afda-336b63b66e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10024
97854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1002497854
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.13548836
Short name T31
Test name
Test status
Simulation time 207960671 ps
CPU time 19.24 seconds
Started Aug 03 05:10:52 PM PDT 24
Finished Aug 03 05:11:11 PM PDT 24
Peak memory 248216 kb
Host smart-946bac4f-0191-4cd5-b178-90fc6b422c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13548
836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.13548836
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.986516254
Short name T89
Test name
Test status
Simulation time 330109358 ps
CPU time 24.7 seconds
Started Aug 03 05:10:47 PM PDT 24
Finished Aug 03 05:11:12 PM PDT 24
Peak memory 248256 kb
Host smart-60737210-683f-443f-8b60-96feaf927703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98651
6254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.986516254
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1923163899
Short name T393
Test name
Test status
Simulation time 218985562 ps
CPU time 4.07 seconds
Started Aug 03 05:10:46 PM PDT 24
Finished Aug 03 05:10:50 PM PDT 24
Peak memory 250460 kb
Host smart-8408a51e-ea5b-49e1-987a-1cc5ab44f026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19231
63899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1923163899
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1064099633
Short name T197
Test name
Test status
Simulation time 135559260439 ps
CPU time 1908.53 seconds
Started Aug 03 05:10:51 PM PDT 24
Finished Aug 03 05:42:40 PM PDT 24
Peak memory 289200 kb
Host smart-3b84d643-348e-42fa-96f0-6dfc01d488c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064099633 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1064099633
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1262243994
Short name T585
Test name
Test status
Simulation time 72548159557 ps
CPU time 1485.56 seconds
Started Aug 03 05:10:57 PM PDT 24
Finished Aug 03 05:35:43 PM PDT 24
Peak memory 289084 kb
Host smart-a1f0a339-49e6-42ba-8542-2151c1b1cc7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262243994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1262243994
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2890613446
Short name T410
Test name
Test status
Simulation time 9523160297 ps
CPU time 146.56 seconds
Started Aug 03 05:10:48 PM PDT 24
Finished Aug 03 05:13:15 PM PDT 24
Peak memory 256548 kb
Host smart-d0d5413c-71f2-428c-b68d-abffec0ac73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28906
13446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2890613446
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1858801898
Short name T543
Test name
Test status
Simulation time 2073511689 ps
CPU time 25.98 seconds
Started Aug 03 05:11:01 PM PDT 24
Finished Aug 03 05:11:27 PM PDT 24
Peak memory 248100 kb
Host smart-ae011171-1abd-4cfd-99a0-c932314ffc65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18588
01898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1858801898
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2555422229
Short name T617
Test name
Test status
Simulation time 26352257921 ps
CPU time 1372.48 seconds
Started Aug 03 05:10:55 PM PDT 24
Finished Aug 03 05:33:48 PM PDT 24
Peak memory 272308 kb
Host smart-f8ce73ae-e09b-4892-be14-82294599d052
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555422229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2555422229
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1954859675
Short name T326
Test name
Test status
Simulation time 10403070018 ps
CPU time 434.2 seconds
Started Aug 03 05:10:56 PM PDT 24
Finished Aug 03 05:18:10 PM PDT 24
Peak memory 248424 kb
Host smart-0c64be8f-b603-4c4a-b626-ab4523196b9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954859675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1954859675
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1565927937
Short name T541
Test name
Test status
Simulation time 708329637 ps
CPU time 20.17 seconds
Started Aug 03 05:10:47 PM PDT 24
Finished Aug 03 05:11:07 PM PDT 24
Peak memory 248368 kb
Host smart-42264887-42a8-450f-83ee-7e3b0c1236ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15659
27937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1565927937
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3841473816
Short name T88
Test name
Test status
Simulation time 88651826 ps
CPU time 11.3 seconds
Started Aug 03 05:10:47 PM PDT 24
Finished Aug 03 05:10:58 PM PDT 24
Peak memory 247788 kb
Host smart-cc280d2d-8651-4adc-9f5b-5b7332d3d886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38414
73816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3841473816
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.4112259471
Short name T408
Test name
Test status
Simulation time 619233902 ps
CPU time 42.38 seconds
Started Aug 03 05:10:47 PM PDT 24
Finished Aug 03 05:11:30 PM PDT 24
Peak memory 255704 kb
Host smart-b733e563-627d-480f-b6a9-0140905dff93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41122
59471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.4112259471
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1474018746
Short name T465
Test name
Test status
Simulation time 199617642 ps
CPU time 12.67 seconds
Started Aug 03 05:10:48 PM PDT 24
Finished Aug 03 05:11:01 PM PDT 24
Peak memory 254560 kb
Host smart-2f329fd3-3637-472f-b381-787cbad22ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14740
18746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1474018746
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.942371455
Short name T175
Test name
Test status
Simulation time 220572206090 ps
CPU time 5021.23 seconds
Started Aug 03 05:11:02 PM PDT 24
Finished Aug 03 06:34:43 PM PDT 24
Peak memory 338188 kb
Host smart-f805e64b-c8e6-4448-b6c5-9f079bab7eae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942371455 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.942371455
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1676281254
Short name T99
Test name
Test status
Simulation time 25870831881 ps
CPU time 1118.49 seconds
Started Aug 03 05:10:55 PM PDT 24
Finished Aug 03 05:29:34 PM PDT 24
Peak memory 283148 kb
Host smart-d1bdfcaa-9d48-4529-9d34-53b59ef6ca8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676281254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1676281254
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2924346656
Short name T689
Test name
Test status
Simulation time 18294401942 ps
CPU time 242.95 seconds
Started Aug 03 05:10:47 PM PDT 24
Finished Aug 03 05:14:50 PM PDT 24
Peak memory 251496 kb
Host smart-6dabcdd8-a87e-47b7-874c-b93afc71979e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29243
46656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2924346656
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.640500566
Short name T76
Test name
Test status
Simulation time 450148956 ps
CPU time 38.85 seconds
Started Aug 03 05:10:58 PM PDT 24
Finished Aug 03 05:11:37 PM PDT 24
Peak memory 256028 kb
Host smart-a14e5ccd-180e-40b6-8a05-e34638204cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64050
0566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.640500566
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.653042845
Short name T608
Test name
Test status
Simulation time 50617903613 ps
CPU time 1253.67 seconds
Started Aug 03 05:10:47 PM PDT 24
Finished Aug 03 05:31:41 PM PDT 24
Peak memory 287492 kb
Host smart-81867be2-d6ac-4801-8b03-6ea953350e22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653042845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.653042845
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.665675785
Short name T503
Test name
Test status
Simulation time 14473003512 ps
CPU time 668.66 seconds
Started Aug 03 05:10:49 PM PDT 24
Finished Aug 03 05:21:58 PM PDT 24
Peak memory 272240 kb
Host smart-3f89802d-d9c6-4e41-83e1-109da29bab1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665675785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.665675785
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3951086043
Short name T325
Test name
Test status
Simulation time 33325479582 ps
CPU time 336.61 seconds
Started Aug 03 05:10:47 PM PDT 24
Finished Aug 03 05:16:24 PM PDT 24
Peak memory 248220 kb
Host smart-470c355b-3b42-40b3-a471-e24321fa7808
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951086043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3951086043
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3456365199
Short name T444
Test name
Test status
Simulation time 207450442 ps
CPU time 14.16 seconds
Started Aug 03 05:10:52 PM PDT 24
Finished Aug 03 05:11:06 PM PDT 24
Peak memory 255736 kb
Host smart-1c87bf4e-9adf-47b1-8cf7-6189bf60627b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34563
65199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3456365199
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.975471537
Short name T86
Test name
Test status
Simulation time 3325659078 ps
CPU time 11.7 seconds
Started Aug 03 05:10:53 PM PDT 24
Finished Aug 03 05:11:05 PM PDT 24
Peak memory 254680 kb
Host smart-4fbb9668-58ca-4a0b-89a1-3d94449bf16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97547
1537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.975471537
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.14722887
Short name T12
Test name
Test status
Simulation time 473871716 ps
CPU time 16.95 seconds
Started Aug 03 05:10:56 PM PDT 24
Finished Aug 03 05:11:13 PM PDT 24
Peak memory 247888 kb
Host smart-3140f3c8-cd9f-402d-861f-f9f7b2aa802d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14722
887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.14722887
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1461071751
Short name T508
Test name
Test status
Simulation time 1218907653 ps
CPU time 29.84 seconds
Started Aug 03 05:10:59 PM PDT 24
Finished Aug 03 05:11:29 PM PDT 24
Peak memory 256496 kb
Host smart-c60ce26f-dbea-4996-86b5-de3c898084a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14610
71751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1461071751
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2819215142
Short name T391
Test name
Test status
Simulation time 9185421313 ps
CPU time 244.97 seconds
Started Aug 03 05:11:00 PM PDT 24
Finished Aug 03 05:15:05 PM PDT 24
Peak memory 256520 kb
Host smart-1f07526b-9fd2-4ad4-9a6e-db0e634eab36
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819215142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2819215142
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.3105761567
Short name T552
Test name
Test status
Simulation time 61665979477 ps
CPU time 1539.48 seconds
Started Aug 03 05:10:55 PM PDT 24
Finished Aug 03 05:36:35 PM PDT 24
Peak memory 297332 kb
Host smart-b97c8a0d-73a8-4a69-bb82-b9d64f51b507
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105761567 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.3105761567
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.4262598741
Short name T634
Test name
Test status
Simulation time 224352735914 ps
CPU time 3075.03 seconds
Started Aug 03 05:10:58 PM PDT 24
Finished Aug 03 06:02:14 PM PDT 24
Peak memory 289112 kb
Host smart-2fb03aea-229d-4203-ba33-eb362f25ba91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262598741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.4262598741
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.401685761
Short name T485
Test name
Test status
Simulation time 4854074896 ps
CPU time 105.85 seconds
Started Aug 03 05:10:53 PM PDT 24
Finished Aug 03 05:12:39 PM PDT 24
Peak memory 255944 kb
Host smart-dc8eb6b8-d19c-4f6f-93e8-c23637f80551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40168
5761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.401685761
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1959656929
Short name T490
Test name
Test status
Simulation time 4123790347 ps
CPU time 60.27 seconds
Started Aug 03 05:11:00 PM PDT 24
Finished Aug 03 05:12:01 PM PDT 24
Peak memory 256604 kb
Host smart-52424398-6a7d-4b1d-a980-8408575a9535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19596
56929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1959656929
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3156833402
Short name T345
Test name
Test status
Simulation time 79695655469 ps
CPU time 1238.96 seconds
Started Aug 03 05:10:54 PM PDT 24
Finished Aug 03 05:31:33 PM PDT 24
Peak memory 272960 kb
Host smart-1dcd331d-4a61-43f7-95da-bc5ced45b65c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156833402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3156833402
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3731052014
Short name T476
Test name
Test status
Simulation time 25282038814 ps
CPU time 1133.56 seconds
Started Aug 03 05:10:57 PM PDT 24
Finished Aug 03 05:29:51 PM PDT 24
Peak memory 272872 kb
Host smart-c386121c-cc0e-46f0-b498-2912efcaa60b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731052014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3731052014
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.291701054
Short name T639
Test name
Test status
Simulation time 4147288008 ps
CPU time 172.11 seconds
Started Aug 03 05:10:55 PM PDT 24
Finished Aug 03 05:13:47 PM PDT 24
Peak memory 248388 kb
Host smart-cb47b3ec-ecd1-4eae-a825-5c3be40a92ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291701054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.291701054
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2836642044
Short name T292
Test name
Test status
Simulation time 104258136 ps
CPU time 4.82 seconds
Started Aug 03 05:10:57 PM PDT 24
Finished Aug 03 05:11:02 PM PDT 24
Peak memory 248336 kb
Host smart-5d383746-89c0-4be9-84f1-ecd93eefc691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28366
42044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2836642044
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1261591482
Short name T106
Test name
Test status
Simulation time 4922247868 ps
CPU time 57.86 seconds
Started Aug 03 05:10:58 PM PDT 24
Finished Aug 03 05:11:56 PM PDT 24
Peak memory 255816 kb
Host smart-f8203a30-a536-436b-aa9d-7a092e3da9c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12615
91482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1261591482
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.173516229
Short name T293
Test name
Test status
Simulation time 1487991614 ps
CPU time 26.7 seconds
Started Aug 03 05:10:56 PM PDT 24
Finished Aug 03 05:11:22 PM PDT 24
Peak memory 254504 kb
Host smart-bf7aa035-d04d-47a7-a833-902448012416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17351
6229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.173516229
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3709619891
Short name T537
Test name
Test status
Simulation time 347465302 ps
CPU time 11.53 seconds
Started Aug 03 05:10:54 PM PDT 24
Finished Aug 03 05:11:06 PM PDT 24
Peak memory 254480 kb
Host smart-3ffc38d1-1761-4dcf-b7d3-29d1d6bc72a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37096
19891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3709619891
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.4017435314
Short name T550
Test name
Test status
Simulation time 63290245690 ps
CPU time 1316.26 seconds
Started Aug 03 05:10:59 PM PDT 24
Finished Aug 03 05:32:56 PM PDT 24
Peak memory 288776 kb
Host smart-db044c7d-cc6e-45e7-9b53-3306ae92508f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017435314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.4017435314
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.4100418903
Short name T505
Test name
Test status
Simulation time 11061203373 ps
CPU time 905.97 seconds
Started Aug 03 05:10:56 PM PDT 24
Finished Aug 03 05:26:02 PM PDT 24
Peak memory 270880 kb
Host smart-9e85ffad-fc67-4b4f-9951-79b9e51325db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100418903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.4100418903
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.4128397728
Short name T362
Test name
Test status
Simulation time 969918512 ps
CPU time 61.96 seconds
Started Aug 03 05:10:55 PM PDT 24
Finished Aug 03 05:11:57 PM PDT 24
Peak memory 256512 kb
Host smart-5eb0b79e-cc42-485e-8dcd-eae56dbe3ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41283
97728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.4128397728
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.208612728
Short name T526
Test name
Test status
Simulation time 263057051 ps
CPU time 28.42 seconds
Started Aug 03 05:10:54 PM PDT 24
Finished Aug 03 05:11:23 PM PDT 24
Peak memory 256144 kb
Host smart-46944812-5b82-4d77-8b35-0a9745dde236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20861
2728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.208612728
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1288455161
Short name T176
Test name
Test status
Simulation time 262974902537 ps
CPU time 2220.65 seconds
Started Aug 03 05:11:00 PM PDT 24
Finished Aug 03 05:48:01 PM PDT 24
Peak memory 286396 kb
Host smart-79075f83-8c78-497d-b785-f77fe5b4f56f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288455161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1288455161
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3881716194
Short name T15
Test name
Test status
Simulation time 23729685303 ps
CPU time 252.87 seconds
Started Aug 03 05:10:53 PM PDT 24
Finished Aug 03 05:15:06 PM PDT 24
Peak memory 248400 kb
Host smart-9744946c-b511-44d2-8a62-6361f7108bdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881716194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3881716194
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2028109897
Short name T482
Test name
Test status
Simulation time 325939566 ps
CPU time 7.32 seconds
Started Aug 03 05:10:53 PM PDT 24
Finished Aug 03 05:11:00 PM PDT 24
Peak memory 248184 kb
Host smart-c56e3797-e055-4346-b869-b6528717ce0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20281
09897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2028109897
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2077765797
Short name T524
Test name
Test status
Simulation time 277811833 ps
CPU time 30.7 seconds
Started Aug 03 05:10:55 PM PDT 24
Finished Aug 03 05:11:26 PM PDT 24
Peak memory 256156 kb
Host smart-f97fbe4a-6168-4207-9971-bcd549482cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20777
65797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2077765797
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2339813798
Short name T545
Test name
Test status
Simulation time 51883315 ps
CPU time 4.52 seconds
Started Aug 03 05:10:58 PM PDT 24
Finished Aug 03 05:11:03 PM PDT 24
Peak memory 240148 kb
Host smart-170e984f-0301-4077-8c07-3593e8dd5602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23398
13798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2339813798
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.1813131365
Short name T30
Test name
Test status
Simulation time 1951834637 ps
CPU time 54.45 seconds
Started Aug 03 05:10:53 PM PDT 24
Finished Aug 03 05:11:48 PM PDT 24
Peak memory 255536 kb
Host smart-7509ed69-0132-4a3f-8583-cc7720fc4964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18131
31365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1813131365
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3255445343
Short name T200
Test name
Test status
Simulation time 53598185 ps
CPU time 3.56 seconds
Started Aug 03 05:09:57 PM PDT 24
Finished Aug 03 05:10:01 PM PDT 24
Peak memory 248604 kb
Host smart-eb4aabbf-d71d-403f-90b7-caa81c6dc5c3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3255445343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3255445343
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2204124459
Short name T105
Test name
Test status
Simulation time 34991696025 ps
CPU time 1771.04 seconds
Started Aug 03 05:09:59 PM PDT 24
Finished Aug 03 05:39:31 PM PDT 24
Peak memory 281160 kb
Host smart-37641b96-cc5b-4faf-a5bb-4914afb540c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204124459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2204124459
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.216995739
Short name T191
Test name
Test status
Simulation time 733887439 ps
CPU time 33.19 seconds
Started Aug 03 05:10:00 PM PDT 24
Finished Aug 03 05:10:33 PM PDT 24
Peak memory 248240 kb
Host smart-8b5bfa91-7130-4edb-9798-6b3552970add
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=216995739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.216995739
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3780568550
Short name T180
Test name
Test status
Simulation time 180970644 ps
CPU time 5.83 seconds
Started Aug 03 05:10:04 PM PDT 24
Finished Aug 03 05:10:10 PM PDT 24
Peak memory 254064 kb
Host smart-ee423c92-c98a-4b7b-8821-3b14eb5bbb78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37805
68550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3780568550
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.4007553445
Short name T675
Test name
Test status
Simulation time 834088453 ps
CPU time 17.81 seconds
Started Aug 03 05:09:51 PM PDT 24
Finished Aug 03 05:10:09 PM PDT 24
Peak memory 247808 kb
Host smart-70dd93b3-824e-43b8-bb8f-caa4b5dd99ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40075
53445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.4007553445
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1826857656
Short name T456
Test name
Test status
Simulation time 11218739686 ps
CPU time 950.31 seconds
Started Aug 03 05:10:02 PM PDT 24
Finished Aug 03 05:25:53 PM PDT 24
Peak memory 272452 kb
Host smart-71289580-4561-4e5d-af1e-08297fdb646d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826857656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1826857656
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2428015851
Short name T104
Test name
Test status
Simulation time 32578629082 ps
CPU time 323.74 seconds
Started Aug 03 05:10:05 PM PDT 24
Finished Aug 03 05:15:29 PM PDT 24
Peak memory 248352 kb
Host smart-fe8107f7-4498-4cf0-9162-6b304555c482
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428015851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2428015851
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.221915216
Short name T259
Test name
Test status
Simulation time 2963416638 ps
CPU time 44.33 seconds
Started Aug 03 05:09:55 PM PDT 24
Finished Aug 03 05:10:40 PM PDT 24
Peak memory 255704 kb
Host smart-9adf8871-3639-4a22-b4ca-ff41b33ea611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22191
5216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.221915216
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1086604764
Short name T195
Test name
Test status
Simulation time 4869360094 ps
CPU time 39.92 seconds
Started Aug 03 05:10:00 PM PDT 24
Finished Aug 03 05:10:40 PM PDT 24
Peak memory 255628 kb
Host smart-6d3a347e-9c8b-45d0-8d21-49fa661de5c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10866
04764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1086604764
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1103539474
Short name T32
Test name
Test status
Simulation time 863024256 ps
CPU time 13.66 seconds
Started Aug 03 05:10:01 PM PDT 24
Finished Aug 03 05:10:15 PM PDT 24
Peak memory 270892 kb
Host smart-5b994a0f-921f-4f66-8ad7-5422714aeee8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1103539474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1103539474
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1556177934
Short name T548
Test name
Test status
Simulation time 613769818 ps
CPU time 7.91 seconds
Started Aug 03 05:10:06 PM PDT 24
Finished Aug 03 05:10:14 PM PDT 24
Peak memory 252128 kb
Host smart-5b4cb258-e510-4b27-9326-3a2839b147ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15561
77934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1556177934
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3651986932
Short name T401
Test name
Test status
Simulation time 115119224 ps
CPU time 8.71 seconds
Started Aug 03 05:09:58 PM PDT 24
Finished Aug 03 05:10:07 PM PDT 24
Peak memory 248240 kb
Host smart-79b18f61-7e5f-49d1-bc0e-fe6c822f9286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36519
86932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3651986932
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3443559104
Short name T277
Test name
Test status
Simulation time 155392316744 ps
CPU time 1764.89 seconds
Started Aug 03 05:10:06 PM PDT 24
Finished Aug 03 05:39:31 PM PDT 24
Peak memory 282188 kb
Host smart-21788e33-0ecb-4bc8-99fe-7a7fd650b4bb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443559104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3443559104
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2464606142
Short name T250
Test name
Test status
Simulation time 77624398954 ps
CPU time 1235.09 seconds
Started Aug 03 05:10:59 PM PDT 24
Finished Aug 03 05:31:34 PM PDT 24
Peak memory 272932 kb
Host smart-c9595f75-d6ca-4f24-9ad6-284ecdab1008
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464606142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2464606142
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.359854433
Short name T635
Test name
Test status
Simulation time 9118986087 ps
CPU time 115.2 seconds
Started Aug 03 05:11:00 PM PDT 24
Finished Aug 03 05:12:55 PM PDT 24
Peak memory 256592 kb
Host smart-3b4e16c8-0444-4bea-944f-7d6a0c3bcbb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35985
4433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.359854433
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.4277622182
Short name T518
Test name
Test status
Simulation time 891202208 ps
CPU time 53.72 seconds
Started Aug 03 05:10:58 PM PDT 24
Finished Aug 03 05:11:52 PM PDT 24
Peak memory 255752 kb
Host smart-29f8c479-2a51-4a47-ad17-5902b30091af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42776
22182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.4277622182
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2619285371
Short name T584
Test name
Test status
Simulation time 18333885602 ps
CPU time 1262.52 seconds
Started Aug 03 05:11:02 PM PDT 24
Finished Aug 03 05:32:05 PM PDT 24
Peak memory 286740 kb
Host smart-735767f4-52e1-43c0-aecc-c2fe4212cffe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619285371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2619285371
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1740448531
Short name T263
Test name
Test status
Simulation time 33876356211 ps
CPU time 2036.99 seconds
Started Aug 03 05:11:03 PM PDT 24
Finished Aug 03 05:45:00 PM PDT 24
Peak memory 288528 kb
Host smart-81c4fac0-c45a-4089-92b1-0d6812806ab3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740448531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1740448531
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1572090616
Short name T596
Test name
Test status
Simulation time 12302538578 ps
CPU time 505.94 seconds
Started Aug 03 05:10:58 PM PDT 24
Finished Aug 03 05:19:24 PM PDT 24
Peak memory 248260 kb
Host smart-6e4603d6-d989-46de-a03e-5f0b9d381ee7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572090616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1572090616
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.4224387117
Short name T196
Test name
Test status
Simulation time 125414951 ps
CPU time 5.86 seconds
Started Aug 03 05:10:59 PM PDT 24
Finished Aug 03 05:11:05 PM PDT 24
Peak memory 248312 kb
Host smart-bbd8a9bb-2fb4-4150-9e28-a83f983985e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42243
87117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.4224387117
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2222717183
Short name T268
Test name
Test status
Simulation time 3304243952 ps
CPU time 63.55 seconds
Started Aug 03 05:10:58 PM PDT 24
Finished Aug 03 05:12:02 PM PDT 24
Peak memory 256400 kb
Host smart-420136cc-ed94-4340-9203-309b67c977db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22227
17183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2222717183
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3605176121
Short name T192
Test name
Test status
Simulation time 84181559 ps
CPU time 4.27 seconds
Started Aug 03 05:11:01 PM PDT 24
Finished Aug 03 05:11:05 PM PDT 24
Peak memory 250508 kb
Host smart-ed360096-d881-4238-8a92-a9edfdf775e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36051
76121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3605176121
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2110791638
Short name T379
Test name
Test status
Simulation time 819401850 ps
CPU time 54.89 seconds
Started Aug 03 05:11:00 PM PDT 24
Finished Aug 03 05:11:55 PM PDT 24
Peak memory 256156 kb
Host smart-353e1845-826e-4ad1-9805-cedf01091fd5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110791638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2110791638
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.3392132308
Short name T283
Test name
Test status
Simulation time 21337124035 ps
CPU time 1430.96 seconds
Started Aug 03 05:10:58 PM PDT 24
Finished Aug 03 05:34:49 PM PDT 24
Peak memory 284340 kb
Host smart-9913d141-b546-4511-843a-e2c20eb35ab0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392132308 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.3392132308
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.695111969
Short name T103
Test name
Test status
Simulation time 243262925628 ps
CPU time 3393.88 seconds
Started Aug 03 05:11:07 PM PDT 24
Finished Aug 03 06:07:42 PM PDT 24
Peak memory 288852 kb
Host smart-ed62084a-cb8b-400b-a8d5-198989b91010
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695111969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.695111969
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.453315968
Short name T554
Test name
Test status
Simulation time 7848694192 ps
CPU time 213.22 seconds
Started Aug 03 05:10:58 PM PDT 24
Finished Aug 03 05:14:31 PM PDT 24
Peak memory 256428 kb
Host smart-c01a8f04-d8a7-41b6-b58b-7dc74c9a49ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45331
5968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.453315968
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1019362003
Short name T398
Test name
Test status
Simulation time 274275313 ps
CPU time 6.18 seconds
Started Aug 03 05:11:02 PM PDT 24
Finished Aug 03 05:11:08 PM PDT 24
Peak memory 240144 kb
Host smart-67cdf2e5-ac35-494a-aa0b-927b1b11f6aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10193
62003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1019362003
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2245246127
Short name T238
Test name
Test status
Simulation time 120164138547 ps
CPU time 1978.04 seconds
Started Aug 03 05:11:10 PM PDT 24
Finished Aug 03 05:44:09 PM PDT 24
Peak memory 272652 kb
Host smart-cf5a93f3-230e-457d-819b-0828f2e71103
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245246127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2245246127
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.4103313170
Short name T470
Test name
Test status
Simulation time 218674294344 ps
CPU time 1902.53 seconds
Started Aug 03 05:11:10 PM PDT 24
Finished Aug 03 05:42:52 PM PDT 24
Peak memory 288236 kb
Host smart-770ef767-4877-4e53-b970-72fea28fcc44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103313170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.4103313170
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1495877181
Short name T65
Test name
Test status
Simulation time 1596880796 ps
CPU time 21.7 seconds
Started Aug 03 05:10:57 PM PDT 24
Finished Aug 03 05:11:19 PM PDT 24
Peak memory 248224 kb
Host smart-f6dbaf0b-a8ce-4f8d-a7f9-087a93607f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14958
77181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1495877181
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.4039869294
Short name T370
Test name
Test status
Simulation time 49275600 ps
CPU time 3.79 seconds
Started Aug 03 05:11:03 PM PDT 24
Finished Aug 03 05:11:07 PM PDT 24
Peak memory 239592 kb
Host smart-3795acae-896a-46ab-b03e-7ce89ba657df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40398
69294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.4039869294
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.364412641
Short name T44
Test name
Test status
Simulation time 174899544 ps
CPU time 26.03 seconds
Started Aug 03 05:11:00 PM PDT 24
Finished Aug 03 05:11:26 PM PDT 24
Peak memory 247636 kb
Host smart-188db44c-86b3-4ddc-ab19-c2d863e55787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36441
2641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.364412641
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1797070750
Short name T364
Test name
Test status
Simulation time 44821993 ps
CPU time 6.08 seconds
Started Aug 03 05:10:58 PM PDT 24
Finished Aug 03 05:11:04 PM PDT 24
Peak memory 248784 kb
Host smart-6567888c-8e41-4a14-ba10-27a61d786f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17970
70750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1797070750
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1460654753
Short name T179
Test name
Test status
Simulation time 58039277106 ps
CPU time 3042.49 seconds
Started Aug 03 05:11:06 PM PDT 24
Finished Aug 03 06:01:49 PM PDT 24
Peak memory 289372 kb
Host smart-50a32193-b2d9-477d-b74a-1d519d826110
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460654753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1460654753
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3969328047
Short name T273
Test name
Test status
Simulation time 2346019350 ps
CPU time 72.03 seconds
Started Aug 03 05:11:09 PM PDT 24
Finished Aug 03 05:12:22 PM PDT 24
Peak memory 256116 kb
Host smart-4cdc66e2-3afd-480e-a7c1-7168809ab77c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39693
28047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3969328047
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2341186532
Short name T278
Test name
Test status
Simulation time 1675397448 ps
CPU time 45.71 seconds
Started Aug 03 05:11:05 PM PDT 24
Finished Aug 03 05:11:51 PM PDT 24
Peak memory 247672 kb
Host smart-596609ca-1be0-4282-9645-c4d496164a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23411
86532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2341186532
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.4229610083
Short name T324
Test name
Test status
Simulation time 44754317134 ps
CPU time 1560.39 seconds
Started Aug 03 05:11:10 PM PDT 24
Finished Aug 03 05:37:11 PM PDT 24
Peak memory 289344 kb
Host smart-7ce6e4a4-0a0b-4d92-aa24-074b6dc323b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229610083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.4229610083
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3182936321
Short name T622
Test name
Test status
Simulation time 28427972668 ps
CPU time 1840.38 seconds
Started Aug 03 05:11:09 PM PDT 24
Finished Aug 03 05:41:50 PM PDT 24
Peak memory 284272 kb
Host smart-0fad2c18-cd1a-409b-a4ec-b55b20f67d51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182936321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3182936321
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3735779057
Short name T321
Test name
Test status
Simulation time 12929410404 ps
CPU time 477.63 seconds
Started Aug 03 05:11:07 PM PDT 24
Finished Aug 03 05:19:05 PM PDT 24
Peak memory 248164 kb
Host smart-10c0e648-43e0-4691-bbf9-4aa0c2442cf3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735779057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3735779057
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3038772423
Short name T236
Test name
Test status
Simulation time 519417410 ps
CPU time 14.48 seconds
Started Aug 03 05:11:03 PM PDT 24
Finished Aug 03 05:11:17 PM PDT 24
Peak memory 248340 kb
Host smart-2a5192fd-c973-43a2-b5ca-6a9908af3a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30387
72423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3038772423
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1964194638
Short name T378
Test name
Test status
Simulation time 134327867 ps
CPU time 10.23 seconds
Started Aug 03 05:11:12 PM PDT 24
Finished Aug 03 05:11:22 PM PDT 24
Peak memory 247808 kb
Host smart-5e45e48c-0808-446e-b7cf-91d84e3a2b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19641
94638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1964194638
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2324953921
Short name T673
Test name
Test status
Simulation time 2974248522 ps
CPU time 53.52 seconds
Started Aug 03 05:11:10 PM PDT 24
Finished Aug 03 05:12:03 PM PDT 24
Peak memory 256456 kb
Host smart-063ece9d-fe08-4094-b9d0-5ae83d8d5dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23249
53921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2324953921
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.681797735
Short name T416
Test name
Test status
Simulation time 318833503 ps
CPU time 17.06 seconds
Started Aug 03 05:11:05 PM PDT 24
Finished Aug 03 05:11:22 PM PDT 24
Peak memory 255576 kb
Host smart-5c20d8f3-b78c-4ca7-a99d-c41b13ed0d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68179
7735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.681797735
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2839406514
Short name T603
Test name
Test status
Simulation time 36525881252 ps
CPU time 1548.68 seconds
Started Aug 03 05:11:08 PM PDT 24
Finished Aug 03 05:36:57 PM PDT 24
Peak memory 288680 kb
Host smart-6d0e3a61-a706-4699-b11f-0738cddfeb39
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839406514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2839406514
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1087844205
Short name T475
Test name
Test status
Simulation time 45468433055 ps
CPU time 1412.62 seconds
Started Aug 03 05:11:10 PM PDT 24
Finished Aug 03 05:34:43 PM PDT 24
Peak memory 289004 kb
Host smart-caac1d84-6fcb-43a4-a1c6-2030a5471c35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087844205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1087844205
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3456877796
Short name T426
Test name
Test status
Simulation time 242929276 ps
CPU time 7.04 seconds
Started Aug 03 05:11:11 PM PDT 24
Finished Aug 03 05:11:18 PM PDT 24
Peak memory 247464 kb
Host smart-033eec48-53b0-48ab-ac2a-ef048526907d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34568
77796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3456877796
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.840140972
Short name T536
Test name
Test status
Simulation time 1775685018 ps
CPU time 51.49 seconds
Started Aug 03 05:11:09 PM PDT 24
Finished Aug 03 05:12:01 PM PDT 24
Peak memory 247980 kb
Host smart-1e6e1eb6-6a80-4701-961e-928e9c530f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84014
0972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.840140972
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.290396051
Short name T349
Test name
Test status
Simulation time 32312729827 ps
CPU time 646.21 seconds
Started Aug 03 05:11:09 PM PDT 24
Finished Aug 03 05:21:56 PM PDT 24
Peak memory 270852 kb
Host smart-1e94c886-f4b4-49e7-9fde-5bef941a386e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290396051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.290396051
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.132432023
Short name T693
Test name
Test status
Simulation time 354721081303 ps
CPU time 1874.47 seconds
Started Aug 03 05:11:11 PM PDT 24
Finished Aug 03 05:42:25 PM PDT 24
Peak memory 286256 kb
Host smart-64dece2d-9411-4b1a-ae57-09e80ce880b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132432023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.132432023
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2059639901
Short name T335
Test name
Test status
Simulation time 37147107353 ps
CPU time 387.01 seconds
Started Aug 03 05:11:09 PM PDT 24
Finished Aug 03 05:17:36 PM PDT 24
Peak memory 248356 kb
Host smart-de8da8cf-f27a-47df-a105-65c58a01b150
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059639901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2059639901
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2397390413
Short name T488
Test name
Test status
Simulation time 1505468156 ps
CPU time 35.66 seconds
Started Aug 03 05:11:06 PM PDT 24
Finished Aug 03 05:11:42 PM PDT 24
Peak memory 255548 kb
Host smart-ec4a9ca0-6469-47e3-9c45-a8f8005e7c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23973
90413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2397390413
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3194839028
Short name T452
Test name
Test status
Simulation time 2999703728 ps
CPU time 52.51 seconds
Started Aug 03 05:11:10 PM PDT 24
Finished Aug 03 05:12:03 PM PDT 24
Peak memory 255868 kb
Host smart-bdc34f1c-924c-4ac5-843f-ded61f7e8c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31948
39028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3194839028
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2911502022
Short name T34
Test name
Test status
Simulation time 106704246 ps
CPU time 11.03 seconds
Started Aug 03 05:11:12 PM PDT 24
Finished Aug 03 05:11:23 PM PDT 24
Peak memory 248332 kb
Host smart-ad8f139c-534b-4de5-a772-7a38ed97c27f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29115
02022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2911502022
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1631678942
Short name T260
Test name
Test status
Simulation time 67381308 ps
CPU time 7.08 seconds
Started Aug 03 05:11:06 PM PDT 24
Finished Aug 03 05:11:13 PM PDT 24
Peak memory 254552 kb
Host smart-8ae27883-bb97-4e3b-b86f-1242d41ffd14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16316
78942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1631678942
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3554279334
Short name T531
Test name
Test status
Simulation time 13162909475 ps
CPU time 769.91 seconds
Started Aug 03 05:11:13 PM PDT 24
Finished Aug 03 05:24:03 PM PDT 24
Peak memory 272920 kb
Host smart-86d1294d-0c09-4ea4-95f9-dfb86f10e210
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554279334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3554279334
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3098784355
Short name T631
Test name
Test status
Simulation time 550927793148 ps
CPU time 2702.83 seconds
Started Aug 03 05:11:12 PM PDT 24
Finished Aug 03 05:56:15 PM PDT 24
Peak memory 289344 kb
Host smart-487b68ba-811f-4173-bcf3-63a060e1a127
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098784355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3098784355
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2101268386
Short name T18
Test name
Test status
Simulation time 1647559413 ps
CPU time 73.99 seconds
Started Aug 03 05:11:11 PM PDT 24
Finished Aug 03 05:12:25 PM PDT 24
Peak memory 255864 kb
Host smart-c4e159b2-f723-4f61-9226-004a74779027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21012
68386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2101268386
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2629364204
Short name T368
Test name
Test status
Simulation time 570994705 ps
CPU time 34.32 seconds
Started Aug 03 05:11:12 PM PDT 24
Finished Aug 03 05:11:46 PM PDT 24
Peak memory 256076 kb
Host smart-7db706b1-601f-4e39-be45-6695a93d76cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26293
64204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2629364204
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.26923773
Short name T332
Test name
Test status
Simulation time 11418149265 ps
CPU time 888.16 seconds
Started Aug 03 05:11:10 PM PDT 24
Finished Aug 03 05:25:59 PM PDT 24
Peak memory 272424 kb
Host smart-74dcfd22-3e75-465f-9b69-c73c69117a98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26923773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.26923773
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1738936305
Short name T551
Test name
Test status
Simulation time 30142401564 ps
CPU time 1710.17 seconds
Started Aug 03 05:11:20 PM PDT 24
Finished Aug 03 05:39:50 PM PDT 24
Peak memory 284500 kb
Host smart-f1ac43e4-b107-487d-811e-f0d6d332464c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738936305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1738936305
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3459106386
Short name T337
Test name
Test status
Simulation time 11066550499 ps
CPU time 485.58 seconds
Started Aug 03 05:11:10 PM PDT 24
Finished Aug 03 05:19:15 PM PDT 24
Peak memory 247248 kb
Host smart-e1cb7639-b637-43ed-955c-60b32c887af4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459106386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3459106386
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2481569026
Short name T361
Test name
Test status
Simulation time 227458486 ps
CPU time 4.83 seconds
Started Aug 03 05:11:10 PM PDT 24
Finished Aug 03 05:11:15 PM PDT 24
Peak memory 240044 kb
Host smart-0f382328-bde2-436a-99a6-7c83e7715c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24815
69026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2481569026
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3133699560
Short name T404
Test name
Test status
Simulation time 3635381352 ps
CPU time 26.54 seconds
Started Aug 03 05:11:12 PM PDT 24
Finished Aug 03 05:11:38 PM PDT 24
Peak memory 247944 kb
Host smart-21be7840-680f-4073-b056-fc7dd1dd131a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31336
99560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3133699560
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.598697930
Short name T69
Test name
Test status
Simulation time 2214427056 ps
CPU time 31.68 seconds
Started Aug 03 05:11:12 PM PDT 24
Finished Aug 03 05:11:43 PM PDT 24
Peak memory 255952 kb
Host smart-32f0ece4-3166-4c41-b8ad-c9b49bb69eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59869
7930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.598697930
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1177702156
Short name T381
Test name
Test status
Simulation time 805268680 ps
CPU time 18.8 seconds
Started Aug 03 05:11:08 PM PDT 24
Finished Aug 03 05:11:27 PM PDT 24
Peak memory 255488 kb
Host smart-f8f274fd-133f-4384-a508-9b8def17fa8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11777
02156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1177702156
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3149716620
Short name T413
Test name
Test status
Simulation time 50630404013 ps
CPU time 1146.36 seconds
Started Aug 03 05:11:18 PM PDT 24
Finished Aug 03 05:30:25 PM PDT 24
Peak memory 281116 kb
Host smart-308b7a5f-d2f3-4876-bc62-7841e4e165bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149716620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3149716620
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1391563462
Short name T515
Test name
Test status
Simulation time 911871980 ps
CPU time 82.25 seconds
Started Aug 03 05:11:17 PM PDT 24
Finished Aug 03 05:12:39 PM PDT 24
Peak memory 255852 kb
Host smart-caafc4b3-2341-42d0-a892-b4667fff51bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13915
63462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1391563462
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.698981798
Short name T542
Test name
Test status
Simulation time 189315281 ps
CPU time 12.2 seconds
Started Aug 03 05:11:15 PM PDT 24
Finished Aug 03 05:11:28 PM PDT 24
Peak memory 247908 kb
Host smart-e7908d70-7bf4-43ca-a6ca-869b9f330eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69898
1798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.698981798
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.1488698971
Short name T354
Test name
Test status
Simulation time 27040673703 ps
CPU time 1024.33 seconds
Started Aug 03 05:11:16 PM PDT 24
Finished Aug 03 05:28:21 PM PDT 24
Peak memory 283400 kb
Host smart-ce5643b3-cfca-4752-8e2b-8535ab385873
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488698971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1488698971
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1767188151
Short name T645
Test name
Test status
Simulation time 87529437553 ps
CPU time 2607.83 seconds
Started Aug 03 05:11:18 PM PDT 24
Finished Aug 03 05:54:46 PM PDT 24
Peak memory 281016 kb
Host smart-d4e48010-9a6a-4e24-bdce-bac950ecc5b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767188151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1767188151
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.244466643
Short name T16
Test name
Test status
Simulation time 40331969852 ps
CPU time 238.49 seconds
Started Aug 03 05:11:16 PM PDT 24
Finished Aug 03 05:15:14 PM PDT 24
Peak memory 248352 kb
Host smart-325fb2de-873a-4122-8685-4fed66c20e0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244466643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.244466643
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3921041179
Short name T20
Test name
Test status
Simulation time 299452441 ps
CPU time 18.03 seconds
Started Aug 03 05:11:16 PM PDT 24
Finished Aug 03 05:11:34 PM PDT 24
Peak memory 255532 kb
Host smart-2e08e70f-54ca-413a-a187-28eaf0e31fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39210
41179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3921041179
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3266064699
Short name T234
Test name
Test status
Simulation time 3810330100 ps
CPU time 50.72 seconds
Started Aug 03 05:11:17 PM PDT 24
Finished Aug 03 05:12:07 PM PDT 24
Peak memory 256544 kb
Host smart-b27e54a7-742d-46ab-b765-747583d67d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32660
64699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3266064699
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1011737141
Short name T493
Test name
Test status
Simulation time 74369695 ps
CPU time 4.4 seconds
Started Aug 03 05:11:16 PM PDT 24
Finished Aug 03 05:11:21 PM PDT 24
Peak memory 240100 kb
Host smart-5282b812-a2da-4669-87a1-3bfe2eac3067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10117
37141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1011737141
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1088148671
Short name T474
Test name
Test status
Simulation time 127623585 ps
CPU time 11.87 seconds
Started Aug 03 05:11:17 PM PDT 24
Finished Aug 03 05:11:29 PM PDT 24
Peak memory 255488 kb
Host smart-db3b4cc2-5a7c-43b2-8f12-89dd5b322479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10881
48671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1088148671
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.4119836730
Short name T96
Test name
Test status
Simulation time 24974420030 ps
CPU time 711.43 seconds
Started Aug 03 05:11:32 PM PDT 24
Finished Aug 03 05:23:23 PM PDT 24
Peak memory 265728 kb
Host smart-291af946-0912-47e8-a9d7-627b5691f451
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119836730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.4119836730
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1086472243
Short name T629
Test name
Test status
Simulation time 4810655660 ps
CPU time 136.6 seconds
Started Aug 03 05:11:30 PM PDT 24
Finished Aug 03 05:13:47 PM PDT 24
Peak memory 255900 kb
Host smart-5663b68f-9edb-442d-8ed8-af976d2076da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10864
72243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1086472243
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1615545541
Short name T348
Test name
Test status
Simulation time 73891127956 ps
CPU time 1276.03 seconds
Started Aug 03 05:11:31 PM PDT 24
Finished Aug 03 05:32:47 PM PDT 24
Peak memory 272180 kb
Host smart-c7a1ab67-bb49-4ff7-87fe-2f8232b23faa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615545541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1615545541
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.4215341048
Short name T623
Test name
Test status
Simulation time 6636548787 ps
CPU time 822.72 seconds
Started Aug 03 05:11:30 PM PDT 24
Finished Aug 03 05:25:13 PM PDT 24
Peak memory 272608 kb
Host smart-744e5912-8d00-4fc4-9167-2620dc94d175
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215341048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.4215341048
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3512100813
Short name T331
Test name
Test status
Simulation time 33119448494 ps
CPU time 420.62 seconds
Started Aug 03 05:11:29 PM PDT 24
Finished Aug 03 05:18:29 PM PDT 24
Peak memory 255264 kb
Host smart-93cd5add-d62c-485d-977a-61bf33a96ad5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512100813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3512100813
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2425987462
Short name T534
Test name
Test status
Simulation time 1332994670 ps
CPU time 35.65 seconds
Started Aug 03 05:11:27 PM PDT 24
Finished Aug 03 05:12:03 PM PDT 24
Peak memory 255896 kb
Host smart-6ac66a09-4906-4a50-8464-707d848ee6b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24259
87462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2425987462
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3771305608
Short name T649
Test name
Test status
Simulation time 898677434 ps
CPU time 16.66 seconds
Started Aug 03 05:11:31 PM PDT 24
Finished Aug 03 05:11:48 PM PDT 24
Peak memory 254264 kb
Host smart-01edddf0-de11-488b-ac97-b45dee8d78cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37713
05608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3771305608
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.15362644
Short name T687
Test name
Test status
Simulation time 508073591 ps
CPU time 7.91 seconds
Started Aug 03 05:11:33 PM PDT 24
Finished Aug 03 05:11:41 PM PDT 24
Peak memory 251336 kb
Host smart-ffd01e77-b7ae-46a5-9886-ce36bf219b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15362
644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.15362644
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.4010173555
Short name T402
Test name
Test status
Simulation time 74714951 ps
CPU time 4.55 seconds
Started Aug 03 05:11:29 PM PDT 24
Finished Aug 03 05:11:34 PM PDT 24
Peak memory 248316 kb
Host smart-73af54e0-36a8-4a11-9093-7f9c5543b6aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40101
73555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.4010173555
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2437223308
Short name T555
Test name
Test status
Simulation time 40217609651 ps
CPU time 540.33 seconds
Started Aug 03 05:11:31 PM PDT 24
Finished Aug 03 05:20:32 PM PDT 24
Peak memory 256524 kb
Host smart-e719a0b7-27d1-4e3f-9c22-6cb994030090
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437223308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2437223308
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.4014942607
Short name T256
Test name
Test status
Simulation time 112141219137 ps
CPU time 3422.08 seconds
Started Aug 03 05:11:34 PM PDT 24
Finished Aug 03 06:08:37 PM PDT 24
Peak memory 305644 kb
Host smart-254d9871-5bdd-4ba1-9ad1-bb29602be800
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014942607 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.4014942607
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1451840280
Short name T303
Test name
Test status
Simulation time 34238077480 ps
CPU time 2318.93 seconds
Started Aug 03 05:11:29 PM PDT 24
Finished Aug 03 05:50:09 PM PDT 24
Peak memory 281096 kb
Host smart-719e5a4c-8471-4ce6-b1e2-c46fa17530ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451840280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1451840280
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.517803862
Short name T594
Test name
Test status
Simulation time 8001177895 ps
CPU time 240.73 seconds
Started Aug 03 05:11:28 PM PDT 24
Finished Aug 03 05:15:29 PM PDT 24
Peak memory 256184 kb
Host smart-b5ecce35-4ecc-48d4-9b6f-7331dffbc474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51780
3862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.517803862
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3910237591
Short name T431
Test name
Test status
Simulation time 1484957562 ps
CPU time 21.85 seconds
Started Aug 03 05:11:33 PM PDT 24
Finished Aug 03 05:11:54 PM PDT 24
Peak memory 256140 kb
Host smart-7f2a37c9-264e-480b-9e6d-ac96f841140d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39102
37591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3910237591
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.870315861
Short name T506
Test name
Test status
Simulation time 27096569587 ps
CPU time 617 seconds
Started Aug 03 05:11:30 PM PDT 24
Finished Aug 03 05:21:48 PM PDT 24
Peak memory 272920 kb
Host smart-35732ec7-b5d3-4841-969a-4c22006ea7c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870315861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.870315861
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3136944254
Short name T589
Test name
Test status
Simulation time 191760084002 ps
CPU time 1392.5 seconds
Started Aug 03 05:11:33 PM PDT 24
Finished Aug 03 05:34:46 PM PDT 24
Peak memory 272220 kb
Host smart-56b3c062-1dca-449e-bbbb-26fd3898774b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136944254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3136944254
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2668704796
Short name T336
Test name
Test status
Simulation time 7084739409 ps
CPU time 307.06 seconds
Started Aug 03 05:11:32 PM PDT 24
Finished Aug 03 05:16:39 PM PDT 24
Peak memory 248312 kb
Host smart-494b38e4-0daf-4be1-bc3d-941f6b8c6376
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668704796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2668704796
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3386747435
Short name T67
Test name
Test status
Simulation time 2660983280 ps
CPU time 44.9 seconds
Started Aug 03 05:11:33 PM PDT 24
Finished Aug 03 05:12:18 PM PDT 24
Peak memory 255804 kb
Host smart-58279a95-ebc5-42ff-846b-8a1e472c3714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33867
47435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3386747435
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.4286627327
Short name T483
Test name
Test status
Simulation time 762440160 ps
CPU time 19.35 seconds
Started Aug 03 05:11:30 PM PDT 24
Finished Aug 03 05:11:49 PM PDT 24
Peak memory 247864 kb
Host smart-db834052-125b-4fe9-a358-3cf6d17013ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42866
27327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.4286627327
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1196014712
Short name T386
Test name
Test status
Simulation time 717898241 ps
CPU time 39.46 seconds
Started Aug 03 05:11:28 PM PDT 24
Finished Aug 03 05:12:08 PM PDT 24
Peak memory 255600 kb
Host smart-d5839581-97d8-4e94-8340-d0f596096481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11960
14712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1196014712
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.76090542
Short name T53
Test name
Test status
Simulation time 59463883232 ps
CPU time 2204.67 seconds
Started Aug 03 05:11:30 PM PDT 24
Finished Aug 03 05:48:15 PM PDT 24
Peak memory 305236 kb
Host smart-03b0e6a7-ee34-4014-b172-762db7832f1d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76090542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_hand
ler_stress_all.76090542
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3459738623
Short name T242
Test name
Test status
Simulation time 49182618612 ps
CPU time 1039.36 seconds
Started Aug 03 05:11:30 PM PDT 24
Finished Aug 03 05:28:50 PM PDT 24
Peak memory 288640 kb
Host smart-6ebff11b-69e1-4db6-b20e-65a498d0866d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459738623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3459738623
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.887956593
Short name T521
Test name
Test status
Simulation time 10410907097 ps
CPU time 261.84 seconds
Started Aug 03 05:11:29 PM PDT 24
Finished Aug 03 05:15:51 PM PDT 24
Peak memory 256188 kb
Host smart-f7db4c94-730d-4d91-9630-020136a7f677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88795
6593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.887956593
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.93077344
Short name T77
Test name
Test status
Simulation time 2728201763 ps
CPU time 63.43 seconds
Started Aug 03 05:11:30 PM PDT 24
Finished Aug 03 05:12:33 PM PDT 24
Peak memory 248292 kb
Host smart-a0b56b9c-84de-4227-a716-ce0607692cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93077
344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.93077344
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.958828121
Short name T327
Test name
Test status
Simulation time 99849224516 ps
CPU time 2916.28 seconds
Started Aug 03 05:11:31 PM PDT 24
Finished Aug 03 06:00:07 PM PDT 24
Peak memory 281056 kb
Host smart-9e7e3bf1-efc7-4d96-9a3c-1a7d54358b42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958828121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.958828121
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1134269300
Short name T420
Test name
Test status
Simulation time 127481599436 ps
CPU time 1858.42 seconds
Started Aug 03 05:11:28 PM PDT 24
Finished Aug 03 05:42:27 PM PDT 24
Peak memory 289308 kb
Host smart-4506c384-f970-4f49-ac89-df2adc166163
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134269300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1134269300
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3967614114
Short name T317
Test name
Test status
Simulation time 11676550221 ps
CPU time 385.21 seconds
Started Aug 03 05:11:30 PM PDT 24
Finished Aug 03 05:17:56 PM PDT 24
Peak memory 254976 kb
Host smart-f63a8adf-67ed-4f43-82c5-4be4aee85a5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967614114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3967614114
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3624052982
Short name T220
Test name
Test status
Simulation time 550881143 ps
CPU time 20.51 seconds
Started Aug 03 05:11:30 PM PDT 24
Finished Aug 03 05:11:51 PM PDT 24
Peak memory 248352 kb
Host smart-61d54495-8862-4003-9302-d44ef1ce41ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36240
52982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3624052982
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2642767624
Short name T451
Test name
Test status
Simulation time 1512474679 ps
CPU time 33.44 seconds
Started Aug 03 05:11:31 PM PDT 24
Finished Aug 03 05:12:04 PM PDT 24
Peak memory 255740 kb
Host smart-42779125-1d24-4faa-9cb7-3f264c308484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26427
67624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2642767624
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.292834975
Short name T258
Test name
Test status
Simulation time 1052967413 ps
CPU time 31.11 seconds
Started Aug 03 05:11:34 PM PDT 24
Finished Aug 03 05:12:06 PM PDT 24
Peak memory 248264 kb
Host smart-0a53fb2b-8078-413d-869b-c04d55c6afa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29283
4975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.292834975
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2894508338
Short name T671
Test name
Test status
Simulation time 430785614 ps
CPU time 24.65 seconds
Started Aug 03 05:11:33 PM PDT 24
Finished Aug 03 05:11:58 PM PDT 24
Peak memory 256492 kb
Host smart-a002fc60-b717-40fc-96e7-b3a25bdf79be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28945
08338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2894508338
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.3438695823
Short name T624
Test name
Test status
Simulation time 2472469876 ps
CPU time 54.68 seconds
Started Aug 03 05:11:29 PM PDT 24
Finished Aug 03 05:12:23 PM PDT 24
Peak memory 256524 kb
Host smart-d4f662a7-fbc7-41b4-88c3-ff18dba4f766
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438695823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.3438695823
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2765129756
Short name T658
Test name
Test status
Simulation time 67653584530 ps
CPU time 1272.33 seconds
Started Aug 03 05:11:34 PM PDT 24
Finished Aug 03 05:32:47 PM PDT 24
Peak memory 272496 kb
Host smart-3a06aeb6-a5a9-4610-991e-9c4cec653368
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765129756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2765129756
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.542967364
Short name T644
Test name
Test status
Simulation time 2122223720 ps
CPU time 106.32 seconds
Started Aug 03 05:11:32 PM PDT 24
Finished Aug 03 05:13:19 PM PDT 24
Peak memory 255980 kb
Host smart-70bcc43a-70b9-4e18-8a5e-91c89f83b17f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54296
7364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.542967364
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1407115239
Short name T469
Test name
Test status
Simulation time 326007796 ps
CPU time 8.48 seconds
Started Aug 03 05:11:33 PM PDT 24
Finished Aug 03 05:11:41 PM PDT 24
Peak memory 247748 kb
Host smart-0fdc39f4-8778-4561-a993-84fc39e1c7ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14071
15239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1407115239
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3725205625
Short name T307
Test name
Test status
Simulation time 29979534543 ps
CPU time 1701.25 seconds
Started Aug 03 05:11:33 PM PDT 24
Finished Aug 03 05:39:54 PM PDT 24
Peak memory 272384 kb
Host smart-9add57ca-397a-4fcc-ae4b-6395209a1210
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725205625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3725205625
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2007412917
Short name T229
Test name
Test status
Simulation time 57395139544 ps
CPU time 1698.45 seconds
Started Aug 03 05:11:32 PM PDT 24
Finished Aug 03 05:39:50 PM PDT 24
Peak memory 267792 kb
Host smart-22f033cf-28dd-439c-b292-4810adbd3d2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007412917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2007412917
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.723710904
Short name T688
Test name
Test status
Simulation time 228635561607 ps
CPU time 640.57 seconds
Started Aug 03 05:11:32 PM PDT 24
Finished Aug 03 05:22:13 PM PDT 24
Peak memory 248000 kb
Host smart-1c8de9ef-5dda-4eb5-94ac-923a192cc574
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723710904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.723710904
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1435488615
Short name T450
Test name
Test status
Simulation time 3508483607 ps
CPU time 58.71 seconds
Started Aug 03 05:11:30 PM PDT 24
Finished Aug 03 05:12:29 PM PDT 24
Peak memory 255812 kb
Host smart-7215e1e8-eb79-4222-9312-e8a7bb1e439e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14354
88615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1435488615
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.4016072178
Short name T406
Test name
Test status
Simulation time 678024301 ps
CPU time 34.41 seconds
Started Aug 03 05:11:34 PM PDT 24
Finished Aug 03 05:12:08 PM PDT 24
Peak memory 248304 kb
Host smart-d38eb2f0-4625-4714-bf20-bb51a3e50d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40160
72178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.4016072178
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3289938559
Short name T425
Test name
Test status
Simulation time 2139139361 ps
CPU time 34.47 seconds
Started Aug 03 05:11:32 PM PDT 24
Finished Aug 03 05:12:06 PM PDT 24
Peak memory 248944 kb
Host smart-5e49eec8-029c-48ec-a8f6-5be6357ddf66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32899
38559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3289938559
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3660018977
Short name T692
Test name
Test status
Simulation time 428380233 ps
CPU time 13.34 seconds
Started Aug 03 05:11:28 PM PDT 24
Finished Aug 03 05:11:41 PM PDT 24
Peak memory 255184 kb
Host smart-de4293b7-f78e-4f94-896d-ad744f648e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36600
18977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3660018977
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.608920537
Short name T528
Test name
Test status
Simulation time 41469155813 ps
CPU time 323.25 seconds
Started Aug 03 05:11:32 PM PDT 24
Finished Aug 03 05:16:56 PM PDT 24
Peak memory 251928 kb
Host smart-4c77ef73-65ba-4e50-9edd-501442f3493c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608920537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.608920537
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.460097955
Short name T214
Test name
Test status
Simulation time 39786874 ps
CPU time 3.44 seconds
Started Aug 03 05:09:55 PM PDT 24
Finished Aug 03 05:09:59 PM PDT 24
Peak memory 248588 kb
Host smart-af84b4c8-b22f-44d1-b76b-a518a6ad845e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=460097955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.460097955
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.453234892
Short name T418
Test name
Test status
Simulation time 99319502742 ps
CPU time 1455.63 seconds
Started Aug 03 05:09:59 PM PDT 24
Finished Aug 03 05:34:15 PM PDT 24
Peak memory 264788 kb
Host smart-f542b0ff-874c-4999-88b5-599400fbfde1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453234892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.453234892
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.204550588
Short name T421
Test name
Test status
Simulation time 2594485587 ps
CPU time 25.05 seconds
Started Aug 03 05:10:03 PM PDT 24
Finished Aug 03 05:10:28 PM PDT 24
Peak memory 248344 kb
Host smart-e47e7d2b-29c4-412e-8f25-c1dfce75b784
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=204550588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.204550588
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3788373632
Short name T405
Test name
Test status
Simulation time 3079808935 ps
CPU time 71 seconds
Started Aug 03 05:10:05 PM PDT 24
Finished Aug 03 05:11:16 PM PDT 24
Peak memory 255888 kb
Host smart-73b5fd0f-5ca1-4ee5-b65e-d4d078dc31fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37883
73632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3788373632
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.4041832409
Short name T587
Test name
Test status
Simulation time 363017138 ps
CPU time 33.68 seconds
Started Aug 03 05:09:53 PM PDT 24
Finished Aug 03 05:10:27 PM PDT 24
Peak memory 255712 kb
Host smart-b96a0b0d-9cf8-4883-bad5-8c846c93b5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40418
32409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.4041832409
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3044539767
Short name T511
Test name
Test status
Simulation time 345971561589 ps
CPU time 2841.49 seconds
Started Aug 03 05:10:08 PM PDT 24
Finished Aug 03 05:57:30 PM PDT 24
Peak memory 287256 kb
Host smart-fdd653d9-6bec-49b1-ac1e-2d7311561b4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044539767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3044539767
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3012886288
Short name T334
Test name
Test status
Simulation time 114220627085 ps
CPU time 424.59 seconds
Started Aug 03 05:09:51 PM PDT 24
Finished Aug 03 05:16:55 PM PDT 24
Peak memory 248352 kb
Host smart-538e2f0c-b2c1-4529-8e25-fbb4aca4e82d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012886288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3012886288
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3430226805
Short name T615
Test name
Test status
Simulation time 3578213813 ps
CPU time 48.52 seconds
Started Aug 03 05:09:51 PM PDT 24
Finished Aug 03 05:10:40 PM PDT 24
Peak memory 256496 kb
Host smart-722830b6-2369-4a5d-b65b-7b699c45a9f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34302
26805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3430226805
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3267940146
Short name T224
Test name
Test status
Simulation time 417836294 ps
CPU time 10.4 seconds
Started Aug 03 05:09:52 PM PDT 24
Finished Aug 03 05:10:02 PM PDT 24
Peak memory 247992 kb
Host smart-c46bc8b1-be1b-45d2-9c76-720d25893bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32679
40146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3267940146
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.556427074
Short name T24
Test name
Test status
Simulation time 538202680 ps
CPU time 10.51 seconds
Started Aug 03 05:09:59 PM PDT 24
Finished Aug 03 05:10:10 PM PDT 24
Peak memory 248276 kb
Host smart-096554b2-221d-4d49-8700-252218d38f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55642
7074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.556427074
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.201058741
Short name T633
Test name
Test status
Simulation time 1304429321 ps
CPU time 20.41 seconds
Started Aug 03 05:10:05 PM PDT 24
Finished Aug 03 05:10:25 PM PDT 24
Peak memory 254920 kb
Host smart-eea9030f-3804-4a02-aaee-1cbbe4ced9ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20105
8741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.201058741
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1892534189
Short name T55
Test name
Test status
Simulation time 76218983025 ps
CPU time 2573.54 seconds
Started Aug 03 05:10:01 PM PDT 24
Finished Aug 03 05:52:55 PM PDT 24
Peak memory 289328 kb
Host smart-36f78a0d-97d7-4419-b573-3539afa39a61
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892534189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1892534189
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1459933521
Short name T207
Test name
Test status
Simulation time 23082061 ps
CPU time 2.4 seconds
Started Aug 03 05:09:54 PM PDT 24
Finished Aug 03 05:09:58 PM PDT 24
Peak memory 248552 kb
Host smart-a891e5eb-f75e-40ba-83c9-0c841e63978a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1459933521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1459933521
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1871197892
Short name T563
Test name
Test status
Simulation time 27641673956 ps
CPU time 1675.94 seconds
Started Aug 03 05:09:59 PM PDT 24
Finished Aug 03 05:37:55 PM PDT 24
Peak memory 284184 kb
Host smart-69beae60-bd44-4512-997f-988f019496e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871197892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1871197892
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1833367965
Short name T466
Test name
Test status
Simulation time 239925019 ps
CPU time 12.21 seconds
Started Aug 03 05:09:57 PM PDT 24
Finished Aug 03 05:10:09 PM PDT 24
Peak memory 248284 kb
Host smart-0ad6ee63-56f0-4828-a532-4376891aae69
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1833367965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1833367965
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1311136681
Short name T434
Test name
Test status
Simulation time 1430270188 ps
CPU time 124.21 seconds
Started Aug 03 05:10:08 PM PDT 24
Finished Aug 03 05:12:12 PM PDT 24
Peak memory 255688 kb
Host smart-f6c9368b-bd42-4b1e-8b0a-0f57b3be1995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13111
36681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1311136681
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.4061169733
Short name T360
Test name
Test status
Simulation time 169676200 ps
CPU time 16.03 seconds
Started Aug 03 05:10:03 PM PDT 24
Finished Aug 03 05:10:19 PM PDT 24
Peak memory 247872 kb
Host smart-c31993c3-ea15-4157-8b46-aa56706d9f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40611
69733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.4061169733
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2817559950
Short name T648
Test name
Test status
Simulation time 84450554248 ps
CPU time 1249.54 seconds
Started Aug 03 05:09:58 PM PDT 24
Finished Aug 03 05:30:48 PM PDT 24
Peak memory 272032 kb
Host smart-cecc8f29-e1fa-4101-ac44-86c317f11e3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817559950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2817559950
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.4258250435
Short name T591
Test name
Test status
Simulation time 16355833315 ps
CPU time 1494.3 seconds
Started Aug 03 05:09:59 PM PDT 24
Finished Aug 03 05:34:54 PM PDT 24
Peak memory 289172 kb
Host smart-de189e08-2402-4ed9-86f4-91374e5e4db2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258250435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.4258250435
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3847438068
Short name T690
Test name
Test status
Simulation time 18184317094 ps
CPU time 334.83 seconds
Started Aug 03 05:09:53 PM PDT 24
Finished Aug 03 05:15:28 PM PDT 24
Peak memory 248368 kb
Host smart-500967ff-6ffa-4f81-9861-9e8eb65ad10f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847438068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3847438068
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3773673823
Short name T500
Test name
Test status
Simulation time 5121792967 ps
CPU time 33.42 seconds
Started Aug 03 05:09:56 PM PDT 24
Finished Aug 03 05:10:30 PM PDT 24
Peak memory 256552 kb
Host smart-b618f38d-4182-41a5-b221-3e97cb30ac1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37736
73823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3773673823
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1408073178
Short name T70
Test name
Test status
Simulation time 186366272 ps
CPU time 12.18 seconds
Started Aug 03 05:09:55 PM PDT 24
Finished Aug 03 05:10:08 PM PDT 24
Peak memory 247828 kb
Host smart-07423660-40b7-4288-8fa1-4042a195f721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14080
73178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1408073178
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.3697469225
Short name T637
Test name
Test status
Simulation time 461553882 ps
CPU time 13.2 seconds
Started Aug 03 05:09:58 PM PDT 24
Finished Aug 03 05:10:11 PM PDT 24
Peak memory 248336 kb
Host smart-641a2f00-6f24-4ae3-8745-1fecaeb0377a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36974
69225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3697469225
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3542580342
Short name T388
Test name
Test status
Simulation time 793877425 ps
CPU time 11.5 seconds
Started Aug 03 05:10:06 PM PDT 24
Finished Aug 03 05:10:17 PM PDT 24
Peak memory 248348 kb
Host smart-2136d9e6-9a20-4c6f-aafd-c5fbcdc35ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35425
80342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3542580342
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.4145714467
Short name T619
Test name
Test status
Simulation time 43935297691 ps
CPU time 1327.82 seconds
Started Aug 03 05:09:55 PM PDT 24
Finished Aug 03 05:32:03 PM PDT 24
Peak memory 272956 kb
Host smart-a9c72687-35ac-47e2-9dcb-9706cd49b658
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145714467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.4145714467
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.398934781
Short name T218
Test name
Test status
Simulation time 285294988 ps
CPU time 3.64 seconds
Started Aug 03 05:10:10 PM PDT 24
Finished Aug 03 05:10:14 PM PDT 24
Peak memory 248588 kb
Host smart-af169acb-6d0c-43f5-996d-45cfae3548b1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=398934781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.398934781
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2941068930
Short name T261
Test name
Test status
Simulation time 146738975303 ps
CPU time 744.53 seconds
Started Aug 03 05:10:11 PM PDT 24
Finished Aug 03 05:22:36 PM PDT 24
Peak memory 272920 kb
Host smart-e1d3f29e-7573-44b4-9c90-a7c2369fc926
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941068930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2941068930
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.269768308
Short name T417
Test name
Test status
Simulation time 2058210887 ps
CPU time 23.5 seconds
Started Aug 03 05:10:01 PM PDT 24
Finished Aug 03 05:10:25 PM PDT 24
Peak memory 248244 kb
Host smart-a3765784-7191-4554-9172-e7a425e709c5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=269768308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.269768308
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.4010975419
Short name T274
Test name
Test status
Simulation time 10833718170 ps
CPU time 162.82 seconds
Started Aug 03 05:10:02 PM PDT 24
Finished Aug 03 05:12:45 PM PDT 24
Peak memory 256048 kb
Host smart-0652a201-3627-4eb5-a330-99e3bf279aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40109
75419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.4010975419
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2427829637
Short name T699
Test name
Test status
Simulation time 1352153806 ps
CPU time 40.85 seconds
Started Aug 03 05:10:11 PM PDT 24
Finished Aug 03 05:10:52 PM PDT 24
Peak memory 256120 kb
Host smart-d5911920-f2f1-454b-855c-f2e72a1940e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24278
29637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2427829637
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3857538218
Short name T558
Test name
Test status
Simulation time 24457291634 ps
CPU time 1532.05 seconds
Started Aug 03 05:10:06 PM PDT 24
Finished Aug 03 05:35:38 PM PDT 24
Peak memory 272268 kb
Host smart-4fec648a-1ac7-4d86-9d01-86ab1a2a4821
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857538218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3857538218
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1954271951
Short name T322
Test name
Test status
Simulation time 3962267969 ps
CPU time 167.01 seconds
Started Aug 03 05:10:07 PM PDT 24
Finished Aug 03 05:12:54 PM PDT 24
Peak memory 248188 kb
Host smart-23a6f28f-252d-40f9-8fbc-f2f4208db53f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954271951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1954271951
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.619047507
Short name T41
Test name
Test status
Simulation time 1558075590 ps
CPU time 40.94 seconds
Started Aug 03 05:09:56 PM PDT 24
Finished Aug 03 05:10:38 PM PDT 24
Peak memory 255888 kb
Host smart-0276c5ff-460a-4c15-aa1c-2c760853235b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61904
7507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.619047507
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.767692725
Short name T110
Test name
Test status
Simulation time 255663640 ps
CPU time 27.3 seconds
Started Aug 03 05:10:04 PM PDT 24
Finished Aug 03 05:10:31 PM PDT 24
Peak memory 248336 kb
Host smart-b7abed31-ea63-411c-a6ca-6367128c27b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76769
2725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.767692725
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.465631761
Short name T1
Test name
Test status
Simulation time 311166672 ps
CPU time 8.98 seconds
Started Aug 03 05:10:05 PM PDT 24
Finished Aug 03 05:10:14 PM PDT 24
Peak memory 247640 kb
Host smart-690aa2eb-d1f8-487d-8e69-fd5bc6f7dc4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46563
1761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.465631761
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3203603464
Short name T464
Test name
Test status
Simulation time 778154105 ps
CPU time 56.76 seconds
Started Aug 03 05:10:11 PM PDT 24
Finished Aug 03 05:11:09 PM PDT 24
Peak memory 248348 kb
Host smart-d2ac1d1e-c165-4970-85b8-e45f9185e443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32036
03464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3203603464
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1252284859
Short name T282
Test name
Test status
Simulation time 152302630124 ps
CPU time 2118.62 seconds
Started Aug 03 05:10:11 PM PDT 24
Finished Aug 03 05:45:29 PM PDT 24
Peak memory 288652 kb
Host smart-69546b85-1d38-457e-87b1-a3c1691713ad
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252284859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1252284859
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.794867105
Short name T211
Test name
Test status
Simulation time 37063918 ps
CPU time 2.09 seconds
Started Aug 03 05:10:01 PM PDT 24
Finished Aug 03 05:10:04 PM PDT 24
Peak memory 248624 kb
Host smart-fe83a5a8-5d49-4497-9a69-0152063d507e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=794867105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.794867105
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.931654883
Short name T546
Test name
Test status
Simulation time 175701102804 ps
CPU time 1480.82 seconds
Started Aug 03 05:10:08 PM PDT 24
Finished Aug 03 05:34:49 PM PDT 24
Peak memory 264788 kb
Host smart-38c7779b-d375-4680-8801-2d94f3c7209a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931654883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.931654883
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3452987376
Short name T694
Test name
Test status
Simulation time 3181469068 ps
CPU time 13.95 seconds
Started Aug 03 05:10:04 PM PDT 24
Finished Aug 03 05:10:19 PM PDT 24
Peak memory 248388 kb
Host smart-aac0f86a-f837-4db7-b61f-41e8334ac72c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3452987376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3452987376
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2758146627
Short name T514
Test name
Test status
Simulation time 2850886022 ps
CPU time 96.16 seconds
Started Aug 03 05:10:03 PM PDT 24
Finished Aug 03 05:11:39 PM PDT 24
Peak memory 256552 kb
Host smart-c50380a1-bd34-461f-b141-006942641076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27581
46627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2758146627
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3269814925
Short name T66
Test name
Test status
Simulation time 479632394 ps
CPU time 11.9 seconds
Started Aug 03 05:10:00 PM PDT 24
Finished Aug 03 05:10:12 PM PDT 24
Peak memory 247768 kb
Host smart-656c145d-d9ca-4a19-96bc-7cc530f4fa98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32698
14925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3269814925
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.770681546
Short name T339
Test name
Test status
Simulation time 43634302533 ps
CPU time 2820.38 seconds
Started Aug 03 05:10:05 PM PDT 24
Finished Aug 03 05:57:06 PM PDT 24
Peak memory 288760 kb
Host smart-43799828-6e82-43e5-ac6b-efd702f17486
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770681546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.770681546
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1895718656
Short name T610
Test name
Test status
Simulation time 91249249496 ps
CPU time 1487.56 seconds
Started Aug 03 05:09:58 PM PDT 24
Finished Aug 03 05:34:46 PM PDT 24
Peak memory 272852 kb
Host smart-07054bd1-3006-469e-98c7-d24c15a50e6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895718656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1895718656
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1654425619
Short name T319
Test name
Test status
Simulation time 15616686430 ps
CPU time 321.87 seconds
Started Aug 03 05:10:07 PM PDT 24
Finished Aug 03 05:15:29 PM PDT 24
Peak memory 255388 kb
Host smart-2fb0e15f-b08d-47a6-b53f-afa74371d8f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654425619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1654425619
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2445910488
Short name T605
Test name
Test status
Simulation time 861722309 ps
CPU time 20.07 seconds
Started Aug 03 05:10:07 PM PDT 24
Finished Aug 03 05:10:27 PM PDT 24
Peak memory 248352 kb
Host smart-fd1e9364-ed23-4c4f-b038-5957a5c8974d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24459
10488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2445910488
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2834748582
Short name T457
Test name
Test status
Simulation time 1004134163 ps
CPU time 21.2 seconds
Started Aug 03 05:10:08 PM PDT 24
Finished Aug 03 05:10:30 PM PDT 24
Peak memory 255988 kb
Host smart-e7c9bdf1-f703-45e4-aac1-f0e01733f665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28347
48582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2834748582
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.2663772224
Short name T572
Test name
Test status
Simulation time 963710154 ps
CPU time 30.22 seconds
Started Aug 03 05:10:05 PM PDT 24
Finished Aug 03 05:10:35 PM PDT 24
Peak memory 255700 kb
Host smart-71733e80-851f-45d3-a8fb-b72f4b0936f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26637
72224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2663772224
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.4279182282
Short name T424
Test name
Test status
Simulation time 1314883871 ps
CPU time 44.61 seconds
Started Aug 03 05:10:11 PM PDT 24
Finished Aug 03 05:10:56 PM PDT 24
Peak memory 256544 kb
Host smart-3e23a9bc-8b96-4caf-a3c7-703ed2a951ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42791
82282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.4279182282
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2618035433
Short name T305
Test name
Test status
Simulation time 242100942449 ps
CPU time 3637.97 seconds
Started Aug 03 05:10:12 PM PDT 24
Finished Aug 03 06:10:51 PM PDT 24
Peak memory 304992 kb
Host smart-1c040ff3-d7d0-452d-b5d8-1fdb36c9bf1b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618035433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2618035433
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3234823610
Short name T209
Test name
Test status
Simulation time 447921433 ps
CPU time 3.79 seconds
Started Aug 03 05:10:14 PM PDT 24
Finished Aug 03 05:10:18 PM PDT 24
Peak memory 248652 kb
Host smart-f8630584-a322-4626-92a8-732835c46a3e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3234823610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3234823610
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2987463259
Short name T308
Test name
Test status
Simulation time 42476902448 ps
CPU time 932.49 seconds
Started Aug 03 05:10:08 PM PDT 24
Finished Aug 03 05:25:41 PM PDT 24
Peak memory 281168 kb
Host smart-ccf8673d-b612-41c5-950e-9b8c532a151f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987463259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2987463259
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.934822637
Short name T560
Test name
Test status
Simulation time 380480186 ps
CPU time 16.88 seconds
Started Aug 03 05:10:03 PM PDT 24
Finished Aug 03 05:10:20 PM PDT 24
Peak memory 248272 kb
Host smart-482c790c-f421-40d9-85fb-531175a505ec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=934822637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.934822637
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.759235916
Short name T527
Test name
Test status
Simulation time 2108194872 ps
CPU time 131.27 seconds
Started Aug 03 05:10:02 PM PDT 24
Finished Aug 03 05:12:14 PM PDT 24
Peak memory 249352 kb
Host smart-8376861b-6bf0-420c-a463-3093285a848a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75923
5916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.759235916
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.508357761
Short name T445
Test name
Test status
Simulation time 3309203336 ps
CPU time 53.24 seconds
Started Aug 03 05:10:05 PM PDT 24
Finished Aug 03 05:10:59 PM PDT 24
Peak memory 256440 kb
Host smart-f65e214d-41ca-4ad5-afd7-698468a77ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50835
7761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.508357761
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.544959848
Short name T529
Test name
Test status
Simulation time 74778705769 ps
CPU time 1108.42 seconds
Started Aug 03 05:10:25 PM PDT 24
Finished Aug 03 05:28:53 PM PDT 24
Peak memory 284760 kb
Host smart-a37cb511-d049-4fdc-9202-18e4f1978ba1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544959848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.544959848
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3431267072
Short name T329
Test name
Test status
Simulation time 55572930775 ps
CPU time 555.35 seconds
Started Aug 03 05:10:09 PM PDT 24
Finished Aug 03 05:19:25 PM PDT 24
Peak memory 248384 kb
Host smart-b368e162-9d80-4f50-9f12-3d7295c6494e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431267072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3431267072
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3757662840
Short name T473
Test name
Test status
Simulation time 151705015 ps
CPU time 14.93 seconds
Started Aug 03 05:10:12 PM PDT 24
Finished Aug 03 05:10:27 PM PDT 24
Peak memory 255680 kb
Host smart-8370c777-1781-414f-904a-dede00dc566b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37576
62840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3757662840
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2931011100
Short name T588
Test name
Test status
Simulation time 449165324 ps
CPU time 20.01 seconds
Started Aug 03 05:10:09 PM PDT 24
Finished Aug 03 05:10:30 PM PDT 24
Peak memory 256532 kb
Host smart-82fe4aa1-7bca-4c9e-924c-965f006fb85b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29310
11100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2931011100
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3459142419
Short name T487
Test name
Test status
Simulation time 1348885022 ps
CPU time 28.02 seconds
Started Aug 03 05:10:07 PM PDT 24
Finished Aug 03 05:10:35 PM PDT 24
Peak memory 247840 kb
Host smart-7266ad2a-420b-4845-8c42-97e7ce9769ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34591
42419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3459142419
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2421317651
Short name T374
Test name
Test status
Simulation time 123896573 ps
CPU time 4.3 seconds
Started Aug 03 05:10:04 PM PDT 24
Finished Aug 03 05:10:09 PM PDT 24
Peak memory 248320 kb
Host smart-942b2d5d-c026-4c2a-a0a5-5e88ed59445a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24213
17651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2421317651
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.3368146446
Short name T17
Test name
Test status
Simulation time 41596997344 ps
CPU time 4337.09 seconds
Started Aug 03 05:10:09 PM PDT 24
Finished Aug 03 06:22:27 PM PDT 24
Peak memory 337316 kb
Host smart-2ff64424-418f-4451-8719-0287e31c3461
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368146446 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.3368146446
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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