Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	71033	1			T1	81		T3	87		T7	2
class_i[0x1]	56382	1			T17	4		T18	15		T35	112
class_i[0x2]	67072	1			T1	255		T7	15		T8	4150
class_i[0x3]	74693	1			T1	27		T7	15		T23	787

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	65917	1			T1	33		T7	9		T8	1047
alert[0x1]	68111	1			T1	6		T3	5		T7	10
alert[0x2]	65399	1			T1	265		T3	78		T7	11
alert[0x3]	69753	1			T1	59		T3	4		T7	2

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

268906

1

T1

363

T3

87

T7

21

esc_ping_fail

274

1

T7

11

T17

4

T18

7

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	65833	1			T1	33		T7	6		T8	1047
esc_integrity_fail	alert[0x1]	68037	1			T1	6		T3	5		T7	6
esc_integrity_fail	alert[0x2]	65333	1			T1	265		T3	78		T7	8
esc_integrity_fail	alert[0x3]	69703	1			T1	59		T3	4		T7	1
esc_ping_fail	alert[0x0]	84	1			T7	3		T17	2		T18	2
esc_ping_fail	alert[0x1]	74	1			T7	4		T18	3		T20	3
esc_ping_fail	alert[0x2]	66	1			T7	3		T17	1		T18	1
esc_ping_fail	alert[0x3]	50	1			T7	1		T17	1		T18	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	70935	1			T1	81		T3	87		T7	2
esc_integrity_fail	class_i[0x1]	56318	1			T18	15		T35	112		T118	1850
esc_integrity_fail	class_i[0x2]	67042	1			T1	255		T7	15		T8	4150
esc_integrity_fail	class_i[0x3]	74611	1			T1	27		T7	4		T23	787
esc_ping_fail	class_i[0x0]	98	1			T18	7		T212	11		T115	2
esc_ping_fail	class_i[0x1]	64	1			T17	4		T212	1		T319	8
esc_ping_fail	class_i[0x2]	30	1			T347	1		T331	3		T328	1
esc_ping_fail	class_i[0x3]	82	1			T7	11		T20	12		T211	1