Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	662233319	0	0	624
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	662233319	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	662233319	662073766	0	0
tb.dut.CheckAccuCntDw	0	0	624	624	0	0
tb.dut.CheckEscCntDw	0	0	624	624	0	0
tb.dut.CheckNAlerts	0	0	624	624	0	0
tb.dut.CheckNClasses	0	0	624	624	0	0
tb.dut.CheckNEscSev	0	0	624	624	0	0
tb.dut.CrashdumpKnownO_A	0	0	662233319	662073766	0	0
tb.dut.EdnKnownO_A	0	0	662233319	662073766	0	0
tb.dut.EscPKnownO_A	0	0	662233319	662073766	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	662233319	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	662233319	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	662233319	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	662233319	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	662233319	70	0	0
tb.dut.IrqAKnownO_A	0	0	662233319	662073766	0	0
tb.dut.IrqBKnownO_A	0	0	662233319	662073766	0	0
tb.dut.IrqCKnownO_A	0	0	662233319	662073766	0	0
tb.dut.IrqDKnownO_A	0	0	662233319	662073766	0	0
tb.dut.TlAReadyKnownO_A	0	0	662233319	662073766	0	0
tb.dut.TlDValidKnownO_A	0	0	662233319	662073766	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	688696741	3064126	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	688696741	15232	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	688696741	15053	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	688696741	13778	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	688696741	15124	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	688696741	16077	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	688696741	15086	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	688696741	15119	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	688696741	14546	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	688696741	14163	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	688696741	14727	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	688696741	15720	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	688696741	14115	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	688696741	15065	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	688696741	17188	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	688696741	15228	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	688696741	16791	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	688696741	14701	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	688696741	13902	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	688696741	15064	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	688696741	14472	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	688696741	14939	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	688696741	15018	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	688696741	15366	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	688696741	14673	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	688696741	16529	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	688696741	16313	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	688696741	14809	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	688696741	15614	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	688696741	15168	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	688696741	13949	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	688696741	14034	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	688696741	15041	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	688696741	14740	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	688696741	15519	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	688696741	15017	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	688696741	13724	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	688696741	13921	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	688696741	14965	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	688696741	15695	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	688696741	14884	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	688696741	14467	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	688696741	15257	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	688696741	15600	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	688696741	15277	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	688696741	14878	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	688696741	14679	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	688696741	15483	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	688696741	15642	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	688696741	14835	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	688696741	14214	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	688696741	14436	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	688696741	15167	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	688696741	15777	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	688696741	14956	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	688696741	13784	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	688696741	14721	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	688696741	14166	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	688696741	13662	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	688696741	14714	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	688696741	16758	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	688696741	15283	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	688696741	13852	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	688696741	15207	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	688696741	14965	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	688696741	13905	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	688696741	15227	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	688696741	14189	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	688696741	15628	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	688696741	15776	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	688696741	28246	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	688696741	15703	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	688696741	16328	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	688696741	15294	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	688696741	14517	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	688696741	15026	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	688696741	16223	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	688696741	13938	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	688696741	14540	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	662233319	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	662233319	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	662233319	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	662233319	3302	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	662233319	217419	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	662233319	335170915	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	662233319	173	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	662233319	796	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	662233319	56	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	662233319	384	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	662102540	253489053	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	662233319	904	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	662233319	888	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	662233319	867	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	662233319	848	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	662233319	1269	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	662233319	139206	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	662233319	1137	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	662233319	75	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	662233319	1072	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	662233319	862	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	662101016	662030898	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	662233319	662073766	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	662233319	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	662233319	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	662233319	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	662233319	3312	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	662233319	245346	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	662233319	336019442	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	662233319	209	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	662233319	474	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	662233319	16	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	662233319	195	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	662102540	255914480	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	662233319	554	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	662233319	541	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	662233319	531	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	662233319	524	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	662233319	1682	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	662233319	133640	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	662233319	1594	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	662233319	72	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	662233319	1148	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	662233319	938	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	662101016	662030898	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	662233319	662073766	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	662233319	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	662233319	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	662233319	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	662233319	3541	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	662233319	187846	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	662233319	381997006	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	662233319	176	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	662233319	482	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	662233319	24	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	662233319	199	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	662102540	282791788	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	662233319	551	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	662233319	543	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	662233319	532	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	662233319	524	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	662233319	1237	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	662233319	131959	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	662233319	1162	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	662233319	50	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	662233319	1153	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	662233319	943	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	662101016	662030898	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	662233319	662073766	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	662233319	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	662233319	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	662233319	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	662233319	2713	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	662233319	235755	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	662233319	324171149	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	662233319	224	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	662233319	522	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	662233319	20	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	662233319	224	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	662102540	265056305	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	662233319	579	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	662233319	568	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	662233319	556	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	662233319	541	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	662233319	1067	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	662233319	114557	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	662233319	1002	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	662233319	45	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	662233319	1187	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	662233319	977	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	662101016	662030898	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	662233319	662073766	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	688696741	138612004	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	688696741	687982983	0	0
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