Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	75	1			T12	1		T14	1		T23	1
class_index[0x1]	72	1			T3	1		T21	1		T67	2
class_index[0x2]	50	1			T23	1		T50	1		T82	1
class_index[0x3]	45	1			T23	1		T35	1		T87	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	94	1			T14	1		T21	1		T23	2
intr_timeout_cnt[1]	46	1			T12	1		T67	2		T50	2
intr_timeout_cnt[2]	30	1			T3	1		T84	1		T82	1
intr_timeout_cnt[3]	20	1			T89	1		T91	1		T30	1
intr_timeout_cnt[4]	15	1			T187	1		T58	1		T97	6
intr_timeout_cnt[5]	9	1			T23	1		T83	2		T96	1
intr_timeout_cnt[6]	9	1			T108	1		T272	2		T273	1
intr_timeout_cnt[7]	5	1			T90	1		T53	2		T274	2
intr_timeout_cnt[8]	6	1			T35	1		T108	1		T99	1
intr_timeout_cnt[9]	8	1			T29	1		T271	1		T275	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	33	1			T14	1		T23	1		T29	3
class_index[0x0]	intr_timeout_cnt[1]	15	1			T12	1		T50	2		T56	1
class_index[0x0]	intr_timeout_cnt[2]	12	1			T84	1		T90	1		T30	1
class_index[0x0]	intr_timeout_cnt[3]	1	1			T113	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[4]	4	1			T187	1		T274	1		T276	1
class_index[0x0]	intr_timeout_cnt[5]	2	1			T277	1		T273	1		-	-
class_index[0x0]	intr_timeout_cnt[6]	2	1			T272	1		T278	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T53	2		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	4	1			T215	1		T279	2		T280	1
class_index[0x1]	intr_timeout_cnt[0]	23	1			T21	1		T56	1		T92	1
class_index[0x1]	intr_timeout_cnt[1]	15	1			T67	2		T82	1		T91	1
class_index[0x1]	intr_timeout_cnt[2]	7	1			T3	1		T100	1		T113	1
class_index[0x1]	intr_timeout_cnt[3]	8	1			T36	1		T99	2		T281	1
class_index[0x1]	intr_timeout_cnt[4]	8	1			T97	6		T276	2		-	-
class_index[0x1]	intr_timeout_cnt[5]	3	1			T83	2		T282	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	3	1			T273	1		T283	1		T279	1
class_index[0x1]	intr_timeout_cnt[7]	2	1			T274	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T108	1		T284	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T275	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	17	1			T23	1		T50	1		T55	1
class_index[0x2]	intr_timeout_cnt[1]	11	1			T116	1		T39	2		T108	2
class_index[0x2]	intr_timeout_cnt[2]	7	1			T82	1		T117	1		T285	1
class_index[0x2]	intr_timeout_cnt[3]	5	1			T89	1		T30	1		T99	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T58	1		T104	1		T286	1
class_index[0x2]	intr_timeout_cnt[5]	2	1			T96	1		T272	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T276	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	1	1			T90	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	3	1			T99	1		T287	1		T288	1
class_index[0x3]	intr_timeout_cnt[0]	21	1			T87	1		T116	1		T123	1
class_index[0x3]	intr_timeout_cnt[1]	5	1			T90	1		T26	1		T251	2
class_index[0x3]	intr_timeout_cnt[2]	4	1			T122	1		T30	1		T55	1
class_index[0x3]	intr_timeout_cnt[3]	6	1			T91	1		T289	4		T290	1
class_index[0x3]	intr_timeout_cnt[5]	2	1			T23	1		T291	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	3	1			T108	1		T272	1		T280	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T35	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	3	1			T29	1		T271	1		T283	1