Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	363878	1			T1	8		T2	31		T3	10
all_values[1]	363878	1			T1	8		T2	31		T3	10
all_values[2]	363878	1			T1	8		T2	31		T3	10
all_values[3]	363878	1			T1	8		T2	31		T3	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

727278

1

T1

19

T2

53

T3

21

auto[1]

728234

1

T1

13

T2

71

T3

19

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

865070

1

T1

7

T2

64

T3

7

auto[1]

590442

1

T1

25

T2

60

T3

33

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	104183	1			T1	1		T2	5		T13	1
all_values[0]	auto[0]	auto[1]	77637	1			T1	5		T2	5		T3	6
all_values[0]	auto[1]	auto[0]	104763	1			T2	11		T3	1		T7	44
all_values[0]	auto[1]	auto[1]	77295	1			T1	2		T2	10		T3	3
all_values[1]	auto[0]	auto[0]	109287	1			T1	1		T2	8		T3	2
all_values[1]	auto[0]	auto[1]	72851	1			T1	4		T2	8		T3	6
all_values[1]	auto[1]	auto[0]	109318	1			T2	8		T7	58		T13	1
all_values[1]	auto[1]	auto[1]	72422	1			T1	3		T2	7		T3	2
all_values[2]	auto[0]	auto[0]	109208	1			T1	1		T2	7		T13	1
all_values[2]	auto[0]	auto[1]	72314	1			T1	2		T2	7		T3	3
all_values[2]	auto[1]	auto[0]	110195	1			T1	2		T2	9		T3	2
all_values[2]	auto[1]	auto[1]	72161	1			T1	3		T2	8		T3	5
all_values[3]	auto[0]	auto[0]	108902	1			T2	7		T3	1		T13	1
all_values[3]	auto[0]	auto[1]	72896	1			T1	5		T2	6		T3	3
all_values[3]	auto[1]	auto[0]	109214	1			T1	2		T2	9		T3	1
all_values[3]	auto[1]	auto[1]	72866	1			T1	1		T2	9		T3	5