Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	363878	1			T1	8		T2	31		T3	10
all_pins[1]	363878	1			T1	8		T2	31		T3	10
all_pins[2]	363878	1			T1	8		T2	31		T3	10
all_pins[3]	363878	1			T1	8		T2	31		T3	10

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1160768	1			T1	23		T2	90		T3	25
values[0x1]	294744	1			T1	9		T2	34		T3	15
transitions[0x0=>0x1]	195749	1			T1	6		T2	19		T3	11
transitions[0x1=>0x0]	196005	1			T1	7		T2	20		T3	11

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	286583	1			T1	6		T2	21		T3	7
all_pins[0]	values[0x1]	77295	1			T1	2		T2	10		T3	3
all_pins[0]	transitions[0x0=>0x1]	76605	1			T1	1		T2	9		T3	2
all_pins[0]	transitions[0x1=>0x0]	72432	1			T1	1		T2	9		T3	4
all_pins[1]	values[0x0]	291456	1			T1	5		T2	24		T3	8
all_pins[1]	values[0x1]	72422	1			T1	3		T2	7		T3	2
all_pins[1]	transitions[0x0=>0x1]	39442	1			T1	2		T2	1		T3	1
all_pins[1]	transitions[0x1=>0x0]	44315	1			T1	1		T2	4		T3	2
all_pins[2]	values[0x0]	291717	1			T1	5		T2	23		T3	5
all_pins[2]	values[0x1]	72161	1			T1	3		T2	8		T3	5
all_pins[2]	transitions[0x0=>0x1]	39759	1			T1	3		T2	4		T3	5
all_pins[2]	transitions[0x1=>0x0]	40020	1			T1	3		T2	3		T3	2
all_pins[3]	values[0x0]	291012	1			T1	7		T2	22		T3	5
all_pins[3]	values[0x1]	72866	1			T1	1		T2	9		T3	5
all_pins[3]	transitions[0x0=>0x1]	39943	1			T2	5		T3	3		T7	4
all_pins[3]	transitions[0x1=>0x0]	39238	1			T1	2		T2	4		T3	3