Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1			T164	4		T165	4		T166	7
all_values[1]	281	1			T164	4		T165	4		T166	7
all_values[2]	281	1			T164	4		T165	4		T166	7
all_values[3]	281	1			T164	4		T165	4		T166	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

626

1

T164

7

T165

9

T166

20

auto[1]

498

1

T164

9

T165

7

T166

8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

445

1

T164

6

T165

6

T166

13

auto[1]

679

1

T164

10

T165

10

T166

15

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

655

1

T164

10

T165

9

T166

16

auto[1]

469

1

T164

6

T165

7

T166

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

72

1

T164

1

T165

1

T166

2

all_values[0]

auto[0]

auto[0]

auto[1]

32

1

T165

1

T166

1

T369

1

all_values[0]

auto[0]

auto[1]

auto[0]

44

1

T166

1

T369

1

T370

1

all_values[0]

auto[0]

auto[1]

auto[1]

18

1

T164

2

T370

1

T371

1

all_values[0]

auto[1]

auto[0]

auto[1]

64

1

T164

1

T165

1

T166

3

all_values[0]

auto[1]

auto[1]

auto[1]

51

1

T165

1

T369

1

T370

1

all_values[1]

auto[0]

auto[0]

auto[0]

66

1

T164

1

T165

1

T369

2

all_values[1]

auto[0]

auto[0]

auto[1]

35

1

T165

1

T166

1

T372

1

all_values[1]

auto[0]

auto[1]

auto[0]

43

1

T164

3

T165

1

T166

2

all_values[1]

auto[0]

auto[1]

auto[1]

21

1

T371

2

T373

1

T267

3

all_values[1]

auto[1]

auto[0]

auto[1]

71

1

T166

4

T371

2

T372

1

all_values[1]

auto[1]

auto[1]

auto[1]

45

1

T165

1

T369

1

T370

1

all_values[2]

auto[0]

auto[0]

auto[0]

55

1

T164

1

T369

1

T370

2

all_values[2]

auto[0]

auto[0]

auto[1]

22

1

T164

1

T166

1

T369

1

all_values[2]

auto[0]

auto[1]

auto[0]

56

1

T166

2

T369

1

T371

4

all_values[2]

auto[0]

auto[1]

auto[1]

25

1

T165

1

T373

2

T374

1

all_values[2]

auto[1]

auto[0]

auto[1]

61

1

T164

2

T165

1

T166

3

all_values[2]

auto[1]

auto[1]

auto[1]

62

1

T165

2

T166

1

T369

2

all_values[3]

auto[0]

auto[0]

auto[0]

62

1

T165

2

T166

4

T375

1

all_values[3]

auto[0]

auto[0]

auto[1]

30

1

T369

2

T370

1

T372

1

all_values[3]

auto[0]

auto[1]

auto[0]

47

1

T165

1

T166

2

T371

1

all_values[3]

auto[0]

auto[1]

auto[1]

27

1

T164

1

T369

1

T371

3

all_values[3]

auto[1]

auto[0]

auto[1]

56

1

T165

1

T166

1

T369

2

all_values[3]

auto[1]

auto[1]

auto[1]

59

1

T164

3

T369

2

T370

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal