Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	99031	1			T8	683		T19	130		T6	160
accum_cnt_1000	255200	1			T1	9		T8	880		T22	71
accum_cnt_100	28379	1			T1	1		T8	56		T22	74
accum_cnt_50	67430	1			T1	6		T2	14		T7	4
accum_cnt_10	185802	1			T1	12		T2	18		T3	29
accum_cnt_0	392926	1			T1	16		T2	88		T3	31

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	269128	1			T1	11		T2	30		T3	15
class_index[0x1]	269128	1			T1	11		T2	30		T3	15
class_index[0x2]	269128	1			T1	11		T2	30		T3	15
class_index[0x3]	269128	1			T1	11		T2	30		T3	15

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	24501	1			T8	438		T6	48		T34	127
class_index[0x0]	accum_cnt_1000	65973	1			T8	670		T22	28		T19	521
class_index[0x0]	accum_cnt_100	9649	1			T1	1		T8	42		T22	19
class_index[0x0]	accum_cnt_50	20430	1			T1	6		T8	31		T21	26
class_index[0x0]	accum_cnt_10	46317	1			T1	4		T3	8		T8	9
class_index[0x0]	accum_cnt_0	92225	1			T2	30		T3	7		T7	43
class_index[0x1]	accum_cnt_2000	27908	1			T34	271		T69	317		T32	468
class_index[0x1]	accum_cnt_1000	61475	1			T22	43		T5	63		T34	733
class_index[0x1]	accum_cnt_100	6072	1			T22	17		T5	18		T34	48
class_index[0x1]	accum_cnt_50	16039	1			T22	13		T23	4		T19	596
class_index[0x1]	accum_cnt_10	47992	1			T1	8		T3	15		T7	35
class_index[0x1]	accum_cnt_0	94644	1			T1	3		T2	30		T7	8
class_index[0x2]	accum_cnt_2000	21926	1			T8	245		T19	130		T118	335
class_index[0x2]	accum_cnt_1000	59799	1			T1	9		T8	210		T19	414
class_index[0x2]	accum_cnt_100	6090	1			T8	14		T22	38		T19	23
class_index[0x2]	accum_cnt_50	20347	1			T2	14		T8	12		T21	20
class_index[0x2]	accum_cnt_10	45749	1			T2	16		T13	1		T8	2
class_index[0x2]	accum_cnt_0	107350	1			T1	2		T3	15		T7	43
class_index[0x3]	accum_cnt_2000	24696	1			T6	112		T118	378		T51	248
class_index[0x3]	accum_cnt_1000	67953	1			T23	2		T6	453		T34	980
class_index[0x3]	accum_cnt_100	6568	1			T6	44		T34	47		T65	14
class_index[0x3]	accum_cnt_50	10614	1			T7	4		T21	18		T6	159
class_index[0x3]	accum_cnt_10	45744	1			T2	2		T3	6		T7	35
class_index[0x3]	accum_cnt_0	98707	1			T1	11		T2	28		T3	9