Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4982	1			T20	1		T6	90		T69	199
alert[0x1]	3813	1			T8	23		T19	59		T17	1
alert[0x2]	7679	1			T8	508		T19	87		T118	14
alert[0x3]	6302	1			T36	1		T56	3		T318	1
alert[0x4]	4841	1			T51	430		T29	2		T297	2
alert[0x5]	2628	1			T19	96		T17	1		T69	227
alert[0x6]	5377	1			T19	247		T18	1		T6	686
alert[0x7]	6092	1			T8	426		T18	1		T6	17
alert[0x8]	13164	1			T19	53		T35	7		T69	10
alert[0x9]	14851	1			T18	1		T20	1		T6	412
alert[0xa]	4383	1			T8	52		T17	1		T20	1
alert[0xb]	11270	1			T8	25		T19	39		T6	169
alert[0xc]	2794	1			T23	8		T6	12		T118	22
alert[0xd]	7749	1			T7	2		T18	1		T6	106
alert[0xe]	7087	1			T7	1		T8	30		T19	217
alert[0xf]	9271	1			T19	129		T35	2		T69	28
alert[0x10]	7625	1			T8	21		T6	23		T74	1
alert[0x11]	12025	1			T17	1		T51	312		T29	1
alert[0x12]	6961	1			T7	1		T17	1		T20	1
alert[0x13]	5541	1			T6	30		T66	1		T90	2
alert[0x14]	6798	1			T7	1		T15	1		T211	1
alert[0x15]	7349	1			T19	33		T17	1		T83	1
alert[0x16]	5521	1			T19	8		T17	1		T18	1
alert[0x17]	7074	1			T19	633		T6	279		T118	2
alert[0x18]	3429	1			T7	1		T8	65		T19	3
alert[0x19]	5220	1			T19	13		T20	1		T6	2046
alert[0x1a]	2962	1			T17	1		T69	28		T74	1
alert[0x1b]	5179	1			T7	2		T17	1		T78	4
alert[0x1c]	8456	1			T7	2		T8	100		T19	20
alert[0x1d]	5073	1			T7	1		T8	177		T17	1
alert[0x1e]	6273	1			T13	3		T8	14		T51	74
alert[0x1f]	4536	1			T6	173		T69	382		T319	1
alert[0x20]	7391	1			T19	10		T20	1		T6	28
alert[0x21]	11094	1			T8	57		T17	1		T20	1
alert[0x22]	10376	1			T8	37		T19	753		T17	1
alert[0x23]	8981	1			T19	24		T6	22		T74	1
alert[0x24]	3737	1			T1	1		T7	1		T8	28
alert[0x25]	12051	1			T7	1		T8	57		T19	52
alert[0x26]	9197	1			T1	6		T19	125		T6	78
alert[0x27]	3538	1			T7	1		T19	2		T6	11
alert[0x28]	5399	1			T8	3		T53	11		T30	5
alert[0x29]	10398	1			T8	25		T6	75		T118	23
alert[0x2a]	5644	1			T8	1093		T118	40		T29	4
alert[0x2b]	5824	1			T8	94		T19	6		T6	13
alert[0x2c]	11159	1			T7	1		T19	440		T20	1
alert[0x2d]	10035	1			T19	301		T17	2		T20	2
alert[0x2e]	7416	1			T8	13		T17	1		T20	1
alert[0x2f]	6608	1			T7	2		T29	3		T319	1
alert[0x30]	9579	1			T7	1		T6	106		T69	1
alert[0x31]	5300	1			T8	86		T19	16		T18	1
alert[0x32]	9717	1			T6	10		T118	5		T205	1
alert[0x33]	8319	1			T17	1		T18	1		T69	21
alert[0x34]	5370	1			T7	2		T8	98		T19	107
alert[0x35]	9234	1			T8	132		T35	6		T69	106
alert[0x36]	6499	1			T1	2		T8	156		T19	74
alert[0x37]	2789	1			T8	61		T6	49		T319	1
alert[0x38]	6236	1			T19	53		T118	341		T29	238
alert[0x39]	15599	1			T19	45		T6	490		T118	7029
alert[0x3a]	4660	1			T8	277		T19	17		T51	117
alert[0x3b]	4467	1			T8	67		T17	1		T6	22
alert[0x3c]	14968	1			T8	177		T23	7		T18	1
alert[0x3d]	6586	1			T8	61		T19	16		T18	2
alert[0x3e]	10650	1			T7	1		T17	1		T6	1223
alert[0x3f]	4487	1			T8	211		T19	191		T18	1
alert[0x40]	5711	1			T6	719		T51	6		T29	11

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	93266	1			T7	16		T13	3		T8	7
class_i[0x1]	179032	1			T1	9		T7	3		T8	4167
class_i[0x2]	109570	1			T7	2		T23	15		T18	11
class_i[0x3]	89456	1			T6	6290		T66	1		T74	33

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

470688

1

T1

9

T13

3

T8

4174

alert_ping_fail

636

1

T7

21

T15

1

T17

18

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4975	1			T6	90		T69	199		T118	153
alert_integrity_fail	alert[0x1]	3799	1			T8	23		T19	59		T6	29
alert_integrity_fail	alert[0x2]	7673	1			T8	508		T19	87		T118	14
alert_integrity_fail	alert[0x3]	6290	1			T36	1		T56	3		T96	31
alert_integrity_fail	alert[0x4]	4832	1			T51	430		T29	2		T187	349
alert_integrity_fail	alert[0x5]	2622	1			T19	96		T69	227		T51	2
alert_integrity_fail	alert[0x6]	5369	1			T19	247		T6	686		T29	3
alert_integrity_fail	alert[0x7]	6081	1			T8	426		T6	17		T29	1
alert_integrity_fail	alert[0x8]	13154	1			T19	53		T35	7		T69	10
alert_integrity_fail	alert[0x9]	14842	1			T6	412		T53	82		T310	1
alert_integrity_fail	alert[0xa]	4370	1			T8	52		T69	24		T54	166
alert_integrity_fail	alert[0xb]	11258	1			T8	25		T19	39		T6	169
alert_integrity_fail	alert[0xc]	2789	1			T23	8		T6	12		T118	22
alert_integrity_fail	alert[0xd]	7732	1			T6	106		T53	88		T116	1
alert_integrity_fail	alert[0xe]	7082	1			T8	30		T19	217		T74	25
alert_integrity_fail	alert[0xf]	9266	1			T19	129		T35	2		T69	28
alert_integrity_fail	alert[0x10]	7621	1			T8	21		T6	23		T74	1
alert_integrity_fail	alert[0x11]	12014	1			T51	312		T29	1		T90	8
alert_integrity_fail	alert[0x12]	6951	1			T6	306		T51	416		T110	8
alert_integrity_fail	alert[0x13]	5527	1			T6	30		T90	2		T53	481
alert_integrity_fail	alert[0x14]	6780	1			T90	9		T110	8		T55	26
alert_integrity_fail	alert[0x15]	7332	1			T19	33		T83	1		T118	192
alert_integrity_fail	alert[0x16]	5506	1			T19	8		T6	315		T118	29
alert_integrity_fail	alert[0x17]	7067	1			T19	633		T6	279		T118	2
alert_integrity_fail	alert[0x18]	3419	1			T8	65		T19	3		T6	17
alert_integrity_fail	alert[0x19]	5211	1			T19	13		T6	2046		T69	4
alert_integrity_fail	alert[0x1a]	2956	1			T69	28		T74	1		T29	6
alert_integrity_fail	alert[0x1b]	5163	1			T78	4		T29	8		T90	2
alert_integrity_fail	alert[0x1c]	8444	1			T8	100		T19	20		T6	174
alert_integrity_fail	alert[0x1d]	5062	1			T8	177		T5	1		T6	5
alert_integrity_fail	alert[0x1e]	6265	1			T13	3		T8	14		T51	74
alert_integrity_fail	alert[0x1f]	4529	1			T6	173		T69	382		T91	5
alert_integrity_fail	alert[0x20]	7376	1			T19	10		T6	28		T29	4
alert_integrity_fail	alert[0x21]	11085	1			T8	57		T29	1		T90	1
alert_integrity_fail	alert[0x22]	10363	1			T8	37		T19	753		T6	31
alert_integrity_fail	alert[0x23]	8975	1			T19	24		T6	22		T74	1
alert_integrity_fail	alert[0x24]	3725	1			T1	1		T8	28		T19	35
alert_integrity_fail	alert[0x25]	12043	1			T8	57		T19	52		T69	108
alert_integrity_fail	alert[0x26]	9188	1			T1	6		T19	125		T6	78
alert_integrity_fail	alert[0x27]	3526	1			T19	2		T6	11		T118	3
alert_integrity_fail	alert[0x28]	5391	1			T8	3		T53	11		T30	5
alert_integrity_fail	alert[0x29]	10395	1			T8	25		T6	75		T118	23
alert_integrity_fail	alert[0x2a]	5640	1			T8	1093		T118	40		T29	4
alert_integrity_fail	alert[0x2b]	5816	1			T8	94		T19	6		T6	13
alert_integrity_fail	alert[0x2c]	11150	1			T19	440		T118	48		T51	19
alert_integrity_fail	alert[0x2d]	10023	1			T19	301		T90	4		T54	1230
alert_integrity_fail	alert[0x2e]	7405	1			T8	13		T56	17		T96	34
alert_integrity_fail	alert[0x2f]	6590	1			T29	3		T54	1		T36	10
alert_integrity_fail	alert[0x30]	9568	1			T6	106		T69	1		T51	44
alert_integrity_fail	alert[0x31]	5291	1			T8	86		T19	16		T6	56
alert_integrity_fail	alert[0x32]	9707	1			T6	10		T118	5		T205	1
alert_integrity_fail	alert[0x33]	8306	1			T69	21		T90	3		T54	1982
alert_integrity_fail	alert[0x34]	5361	1			T8	98		T19	107		T35	3
alert_integrity_fail	alert[0x35]	9228	1			T8	132		T35	6		T69	106
alert_integrity_fail	alert[0x36]	6486	1			T1	2		T8	156		T19	74
alert_integrity_fail	alert[0x37]	2777	1			T8	61		T6	49		T53	123
alert_integrity_fail	alert[0x38]	6232	1			T19	53		T118	341		T29	238
alert_integrity_fail	alert[0x39]	15594	1			T19	45		T6	490		T118	7029
alert_integrity_fail	alert[0x3a]	4648	1			T8	277		T19	17		T51	117
alert_integrity_fail	alert[0x3b]	4458	1			T8	67		T6	22		T118	31
alert_integrity_fail	alert[0x3c]	14955	1			T8	177		T23	7		T118	244
alert_integrity_fail	alert[0x3d]	6575	1			T8	61		T19	16		T6	521
alert_integrity_fail	alert[0x3e]	10641	1			T6	1223		T118	107		T51	121
alert_integrity_fail	alert[0x3f]	4482	1			T8	211		T19	191		T69	232
alert_integrity_fail	alert[0x40]	5707	1			T6	719		T51	6		T29	11
alert_ping_fail	alert[0x0]	7	1			T20	1		T212	2		T297	1
alert_ping_fail	alert[0x1]	14	1			T17	1		T20	1		T297	2
alert_ping_fail	alert[0x2]	6	1			T297	1		T320	1		T321	2
alert_ping_fail	alert[0x3]	12	1			T318	1		T322	1		T323	2
alert_ping_fail	alert[0x4]	9	1			T297	2		T254	1		T323	1
alert_ping_fail	alert[0x5]	6	1			T17	1		T212	1		T320	1
alert_ping_fail	alert[0x6]	8	1			T18	1		T324	2		T325	1
alert_ping_fail	alert[0x7]	11	1			T18	1		T326	1		T320	2
alert_ping_fail	alert[0x8]	10	1			T327	1		T40	1		T320	1
alert_ping_fail	alert[0x9]	9	1			T18	1		T20	1		T326	1
alert_ping_fail	alert[0xa]	13	1			T17	1		T20	1		T328	1
alert_ping_fail	alert[0xb]	12	1			T297	2		T328	1		T324	1
alert_ping_fail	alert[0xc]	5	1			T254	1		T323	1		T329	1
alert_ping_fail	alert[0xd]	17	1			T7	2		T18	1		T212	1
alert_ping_fail	alert[0xe]	5	1			T7	1		T212	1		T319	1
alert_ping_fail	alert[0xf]	5	1			T318	1		T320	1		T254	1
alert_ping_fail	alert[0x10]	4	1			T328	1		T330	1		T321	1
alert_ping_fail	alert[0x11]	11	1			T17	1		T115	1		T331	1
alert_ping_fail	alert[0x12]	10	1			T7	1		T17	1		T20	1
alert_ping_fail	alert[0x13]	14	1			T66	1		T332	3		T41	1
alert_ping_fail	alert[0x14]	18	1			T7	1		T15	1		T211	1
alert_ping_fail	alert[0x15]	17	1			T17	1		T212	1		T115	1
alert_ping_fail	alert[0x16]	15	1			T17	1		T18	1		T324	2
alert_ping_fail	alert[0x17]	7	1			T211	1		T320	1		T333	1
alert_ping_fail	alert[0x18]	10	1			T7	1		T20	1		T326	1
alert_ping_fail	alert[0x19]	9	1			T20	1		T297	1		T328	1
alert_ping_fail	alert[0x1a]	6	1			T17	1		T297	1		T334	1
alert_ping_fail	alert[0x1b]	16	1			T7	2		T17	1		T319	2
alert_ping_fail	alert[0x1c]	12	1			T7	2		T20	1		T335	1
alert_ping_fail	alert[0x1d]	11	1			T7	1		T17	1		T115	1
alert_ping_fail	alert[0x1e]	8	1			T319	1		T336	1		T337	1
alert_ping_fail	alert[0x1f]	7	1			T319	1		T297	1		T326	1
alert_ping_fail	alert[0x20]	15	1			T20	1		T212	2		T40	1
alert_ping_fail	alert[0x21]	9	1			T17	1		T20	1		T328	1
alert_ping_fail	alert[0x22]	13	1			T17	1		T18	1		T20	1
alert_ping_fail	alert[0x23]	6	1			T324	1		T334	1		T338	1
alert_ping_fail	alert[0x24]	12	1			T7	1		T297	1		T337	1
alert_ping_fail	alert[0x25]	8	1			T7	1		T319	1		T318	1
alert_ping_fail	alert[0x26]	9	1			T319	1		T326	1		T332	1
alert_ping_fail	alert[0x27]	12	1			T7	1		T319	1		T332	1
alert_ping_fail	alert[0x28]	8	1			T339	1		T336	1		T300	1
alert_ping_fail	alert[0x29]	3	1			T211	1		T212	1		T318	1
alert_ping_fail	alert[0x2a]	4	1			T318	1		T340	2		T341	1
alert_ping_fail	alert[0x2b]	8	1			T342	1		T343	1		T344	1
alert_ping_fail	alert[0x2c]	9	1			T7	1		T20	1		T345	1
alert_ping_fail	alert[0x2d]	12	1			T17	2		T20	2		T319	2
alert_ping_fail	alert[0x2e]	11	1			T17	1		T20	1		T326	1
alert_ping_fail	alert[0x2f]	18	1			T7	2		T319	1		T327	1
alert_ping_fail	alert[0x30]	11	1			T7	1		T297	2		T322	1
alert_ping_fail	alert[0x31]	9	1			T18	1		T211	1		T212	1
alert_ping_fail	alert[0x32]	10	1			T319	2		T331	1		T336	1
alert_ping_fail	alert[0x33]	13	1			T17	1		T18	1		T328	1
alert_ping_fail	alert[0x34]	9	1			T7	2		T20	1		T319	1
alert_ping_fail	alert[0x35]	6	1			T319	2		T338	1		T196	1
alert_ping_fail	alert[0x36]	13	1			T20	1		T318	2		T324	1
alert_ping_fail	alert[0x37]	12	1			T319	1		T324	1		T343	1
alert_ping_fail	alert[0x38]	4	1			T318	1		T320	1		T345	1
alert_ping_fail	alert[0x39]	5	1			T326	1		T320	1		T346	1
alert_ping_fail	alert[0x3a]	12	1			T212	1		T297	2		T318	2
alert_ping_fail	alert[0x3b]	9	1			T17	1		T297	1		T347	1
alert_ping_fail	alert[0x3c]	13	1			T18	1		T115	1		T320	1
alert_ping_fail	alert[0x3d]	11	1			T18	2		T319	1		T297	1
alert_ping_fail	alert[0x3e]	9	1			T7	1		T17	1		T297	1
alert_ping_fail	alert[0x3f]	5	1			T18	1		T328	1		T348	1
alert_ping_fail	alert[0x40]	4	1			T334	1		T349	1		T350	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	93110	1			T13	3		T8	7		T19	1
alert_integrity_fail	class_i[0x1]	178804	1			T1	9		T8	4167		T19	3903
alert_integrity_fail	class_i[0x2]	109451	1			T23	15		T6	30		T35	9
alert_integrity_fail	class_i[0x3]	89323	1			T6	6290		T74	33		T53	1
alert_ping_fail	class_i[0x0]	156	1			T7	16		T15	1		T20	17
alert_ping_fail	class_i[0x1]	228	1			T7	3		T17	18		T18	1
alert_ping_fail	class_i[0x2]	119	1			T7	2		T18	11		T212	1
alert_ping_fail	class_i[0x3]	133	1			T66	1		T319	19		T95	2