Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.25 99.99 98.71 97.09 100.00 100.00 99.38 99.56


Total test records in report: 829
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T158 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.644829528 Aug 04 05:35:05 PM PDT 24 Aug 04 05:44:48 PM PDT 24 4784345982 ps
T771 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.303401070 Aug 04 05:34:46 PM PDT 24 Aug 04 05:34:51 PM PDT 24 200307527 ps
T772 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3701301797 Aug 04 05:35:07 PM PDT 24 Aug 04 05:35:20 PM PDT 24 562301902 ps
T178 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3109277756 Aug 04 05:35:19 PM PDT 24 Aug 04 05:36:45 PM PDT 24 7332401981 ps
T773 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.358755431 Aug 04 05:34:45 PM PDT 24 Aug 04 05:34:57 PM PDT 24 86243930 ps
T774 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2913401749 Aug 04 05:35:15 PM PDT 24 Aug 04 05:35:38 PM PDT 24 690821003 ps
T775 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1816336300 Aug 04 05:35:18 PM PDT 24 Aug 04 05:35:22 PM PDT 24 50039471 ps
T776 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.291134438 Aug 04 05:34:42 PM PDT 24 Aug 04 05:37:00 PM PDT 24 4448597673 ps
T143 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2768850828 Aug 04 05:35:06 PM PDT 24 Aug 04 05:40:13 PM PDT 24 4395550833 ps
T777 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3731542762 Aug 04 05:34:59 PM PDT 24 Aug 04 05:37:48 PM PDT 24 11457918116 ps
T778 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.117176981 Aug 04 05:35:16 PM PDT 24 Aug 04 05:35:18 PM PDT 24 13187064 ps
T779 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3071869841 Aug 04 05:34:58 PM PDT 24 Aug 04 05:35:03 PM PDT 24 59029068 ps
T780 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2389108934 Aug 04 05:34:41 PM PDT 24 Aug 04 05:34:42 PM PDT 24 16112107 ps
T781 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.420370456 Aug 04 05:35:06 PM PDT 24 Aug 04 05:35:19 PM PDT 24 477266600 ps
T782 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3377757788 Aug 04 05:35:12 PM PDT 24 Aug 04 05:35:16 PM PDT 24 35615506 ps
T783 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3884275887 Aug 04 05:34:55 PM PDT 24 Aug 04 05:34:57 PM PDT 24 8396408 ps
T784 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.663798959 Aug 04 05:35:15 PM PDT 24 Aug 04 05:35:20 PM PDT 24 41526712 ps
T155 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1114399240 Aug 04 05:35:01 PM PDT 24 Aug 04 05:41:00 PM PDT 24 22303332549 ps
T785 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.646133627 Aug 04 05:34:55 PM PDT 24 Aug 04 05:35:20 PM PDT 24 168946659 ps
T786 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2799343823 Aug 04 05:35:19 PM PDT 24 Aug 04 05:35:25 PM PDT 24 115887967 ps
T156 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1120774634 Aug 04 05:35:07 PM PDT 24 Aug 04 05:51:26 PM PDT 24 13948718452 ps
T787 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.427801180 Aug 04 05:35:19 PM PDT 24 Aug 04 05:35:21 PM PDT 24 10176828 ps
T788 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1445503171 Aug 04 05:34:57 PM PDT 24 Aug 04 05:35:49 PM PDT 24 2975630398 ps
T789 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2310755165 Aug 04 05:35:23 PM PDT 24 Aug 04 05:35:25 PM PDT 24 25308093 ps
T790 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.4163394513 Aug 04 05:35:15 PM PDT 24 Aug 04 05:35:17 PM PDT 24 9113420 ps
T791 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1075863689 Aug 04 05:35:02 PM PDT 24 Aug 04 05:35:21 PM PDT 24 290061636 ps
T792 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1302450353 Aug 04 05:34:53 PM PDT 24 Aug 04 05:34:58 PM PDT 24 53275226 ps
T793 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2296012443 Aug 04 05:34:46 PM PDT 24 Aug 04 05:35:11 PM PDT 24 704578900 ps
T168 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1036004146 Aug 04 05:35:09 PM PDT 24 Aug 04 05:35:12 PM PDT 24 171065888 ps
T794 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.373613751 Aug 04 05:35:16 PM PDT 24 Aug 04 05:35:22 PM PDT 24 66215026 ps
T795 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3580797970 Aug 04 05:35:14 PM PDT 24 Aug 04 05:35:16 PM PDT 24 9208273 ps
T796 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1610076551 Aug 04 05:35:06 PM PDT 24 Aug 04 05:35:11 PM PDT 24 158661164 ps
T797 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1392502933 Aug 04 05:35:08 PM PDT 24 Aug 04 05:35:20 PM PDT 24 317692480 ps
T176 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.402386241 Aug 04 05:35:12 PM PDT 24 Aug 04 05:35:16 PM PDT 24 68533041 ps
T180 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3186173512 Aug 04 05:34:52 PM PDT 24 Aug 04 05:34:56 PM PDT 24 143228513 ps
T798 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3837205476 Aug 04 05:35:14 PM PDT 24 Aug 04 05:35:27 PM PDT 24 93942238 ps
T170 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2290008860 Aug 04 05:35:17 PM PDT 24 Aug 04 05:35:20 PM PDT 24 113897030 ps
T799 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1540679775 Aug 04 05:35:12 PM PDT 24 Aug 04 05:35:34 PM PDT 24 666500863 ps
T800 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2441047693 Aug 04 05:35:12 PM PDT 24 Aug 04 05:35:20 PM PDT 24 420812407 ps
T801 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3969942584 Aug 04 05:35:17 PM PDT 24 Aug 04 05:35:18 PM PDT 24 8199189 ps
T802 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1237873327 Aug 04 05:34:53 PM PDT 24 Aug 04 05:35:04 PM PDT 24 296688622 ps
T151 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2249467871 Aug 04 05:34:54 PM PDT 24 Aug 04 05:41:34 PM PDT 24 9090183823 ps
T179 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2377064015 Aug 04 05:34:59 PM PDT 24 Aug 04 05:35:02 PM PDT 24 115325306 ps
T803 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2296414139 Aug 04 05:35:17 PM PDT 24 Aug 04 05:35:19 PM PDT 24 8000819 ps
T173 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3629284367 Aug 04 05:35:00 PM PDT 24 Aug 04 05:35:23 PM PDT 24 606743335 ps
T804 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1219568631 Aug 04 05:35:08 PM PDT 24 Aug 04 05:35:10 PM PDT 24 10804613 ps
T805 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.4148223051 Aug 04 05:35:05 PM PDT 24 Aug 04 05:35:13 PM PDT 24 666136798 ps
T806 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.714492868 Aug 04 05:34:57 PM PDT 24 Aug 04 05:34:58 PM PDT 24 17213369 ps
T807 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.557090193 Aug 04 05:34:54 PM PDT 24 Aug 04 05:35:02 PM PDT 24 259956849 ps
T157 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.590625292 Aug 04 05:34:54 PM PDT 24 Aug 04 05:40:49 PM PDT 24 5294509783 ps
T808 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3905475343 Aug 04 05:35:17 PM PDT 24 Aug 04 05:35:19 PM PDT 24 9453158 ps
T809 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.4068404080 Aug 04 05:35:12 PM PDT 24 Aug 04 05:35:24 PM PDT 24 167513784 ps
T159 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.510224448 Aug 04 05:35:08 PM PDT 24 Aug 04 05:52:37 PM PDT 24 16266764782 ps
T810 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.716197384 Aug 04 05:35:01 PM PDT 24 Aug 04 05:35:22 PM PDT 24 315755519 ps
T811 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1319288783 Aug 04 05:35:18 PM PDT 24 Aug 04 05:35:20 PM PDT 24 6415478 ps
T812 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3886162262 Aug 04 05:34:52 PM PDT 24 Aug 04 05:34:53 PM PDT 24 16573916 ps
T154 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2151397256 Aug 04 05:35:00 PM PDT 24 Aug 04 05:51:38 PM PDT 24 49978676427 ps
T813 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2032504306 Aug 04 05:35:23 PM PDT 24 Aug 04 05:35:25 PM PDT 24 38245523 ps
T814 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.178179334 Aug 04 05:35:11 PM PDT 24 Aug 04 05:35:14 PM PDT 24 32551454 ps
T815 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2824332456 Aug 04 05:35:12 PM PDT 24 Aug 04 05:35:20 PM PDT 24 67099084 ps
T816 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2291405839 Aug 04 05:35:14 PM PDT 24 Aug 04 05:40:39 PM PDT 24 4435415117 ps
T177 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2746895434 Aug 04 05:34:46 PM PDT 24 Aug 04 05:35:20 PM PDT 24 460002477 ps
T817 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3551242186 Aug 04 05:35:11 PM PDT 24 Aug 04 05:35:22 PM PDT 24 160798755 ps
T818 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.4210631890 Aug 04 05:34:47 PM PDT 24 Aug 04 05:34:50 PM PDT 24 173814581 ps
T174 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3861283384 Aug 04 05:34:54 PM PDT 24 Aug 04 05:34:57 PM PDT 24 91242790 ps
T819 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2045012045 Aug 04 05:35:14 PM PDT 24 Aug 04 05:35:16 PM PDT 24 11751464 ps
T820 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.42312628 Aug 04 05:34:58 PM PDT 24 Aug 04 05:35:05 PM PDT 24 48741517 ps
T384 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1295525678 Aug 04 05:35:18 PM PDT 24 Aug 04 05:53:58 PM PDT 24 137432027163 ps
T821 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1217287094 Aug 04 05:35:25 PM PDT 24 Aug 04 05:35:27 PM PDT 24 7863746 ps
T822 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1822976690 Aug 04 05:35:16 PM PDT 24 Aug 04 05:35:24 PM PDT 24 107383150 ps
T823 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.102289728 Aug 04 05:35:15 PM PDT 24 Aug 04 05:35:16 PM PDT 24 25887422 ps
T824 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.88097751 Aug 04 05:35:19 PM PDT 24 Aug 04 05:35:41 PM PDT 24 245845889 ps
T825 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1855085400 Aug 04 05:35:03 PM PDT 24 Aug 04 05:35:24 PM PDT 24 782158064 ps
T826 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.690820939 Aug 04 05:35:18 PM PDT 24 Aug 04 05:35:19 PM PDT 24 21851774 ps
T827 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2515797444 Aug 04 05:35:13 PM PDT 24 Aug 04 05:35:15 PM PDT 24 6596850 ps
T385 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1387336135 Aug 04 05:35:19 PM PDT 24 Aug 04 05:41:03 PM PDT 24 9678119737 ps
T828 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2383725166 Aug 04 05:35:12 PM PDT 24 Aug 04 05:35:13 PM PDT 24 6166278 ps
T160 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3419946661 Aug 04 05:35:17 PM PDT 24 Aug 04 05:39:53 PM PDT 24 14264447293 ps
T829 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2213348963 Aug 04 05:35:18 PM PDT 24 Aug 04 05:35:20 PM PDT 24 10109607 ps

Test location /workspace/coverage/default/48.alert_handler_entropy.1273831491
Short name T8
Test name
Test status
Simulation time 33658551284 ps
CPU time 1272.02 seconds
Started Aug 04 04:47:21 PM PDT 24
Finished Aug 04 05:08:34 PM PDT 24
Peak memory 285112 kb
Host smart-57aac3d7-85d0-44a1-a993-62f5db9d0f93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273831491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1273831491
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2594609294
Short name T6
Test name
Test status
Simulation time 21748765381 ps
CPU time 2380.41 seconds
Started Aug 04 04:45:04 PM PDT 24
Finished Aug 04 05:24:45 PM PDT 24
Peak memory 301128 kb
Host smart-4ac47c4b-fd89-4d1f-8ba9-e7822406a986
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594609294 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2594609294
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1589378143
Short name T9
Test name
Test status
Simulation time 178442570 ps
CPU time 11.54 seconds
Started Aug 04 04:43:05 PM PDT 24
Finished Aug 04 04:43:16 PM PDT 24
Peak memory 269216 kb
Host smart-b4685adb-bb2d-40d9-ab51-8b0e41a3730f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1589378143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1589378143
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.1750885348
Short name T50
Test name
Test status
Simulation time 5565329474 ps
CPU time 304.36 seconds
Started Aug 04 04:44:04 PM PDT 24
Finished Aug 04 04:49:09 PM PDT 24
Peak memory 256384 kb
Host smart-7ba89b28-b4ab-4377-9fdf-d41a5a5f5b62
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750885348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1750885348
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2708841046
Short name T184
Test name
Test status
Simulation time 441189779 ps
CPU time 9 seconds
Started Aug 04 05:35:02 PM PDT 24
Finished Aug 04 05:35:11 PM PDT 24
Peak memory 236832 kb
Host smart-66f1a35e-82b4-4068-a366-937e31b7efc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2708841046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2708841046
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1554420707
Short name T4
Test name
Test status
Simulation time 179579920 ps
CPU time 5.64 seconds
Started Aug 04 04:43:55 PM PDT 24
Finished Aug 04 04:44:01 PM PDT 24
Peak memory 248292 kb
Host smart-53c6c530-5d2d-4854-baf2-001f52ec5d47
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1554420707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1554420707
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1689365145
Short name T130
Test name
Test status
Simulation time 9466482565 ps
CPU time 656.97 seconds
Started Aug 04 05:35:14 PM PDT 24
Finished Aug 04 05:46:11 PM PDT 24
Peak memory 265660 kb
Host smart-a0c3dd7e-5213-4304-8f46-4a3b34cbce19
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689365145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1689365145
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1896529562
Short name T29
Test name
Test status
Simulation time 102117480946 ps
CPU time 2698.07 seconds
Started Aug 04 04:43:49 PM PDT 24
Finished Aug 04 05:28:48 PM PDT 24
Peak memory 301440 kb
Host smart-d09a123e-8b41-43fa-8ccd-8f1ec3b65fb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896529562 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1896529562
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1276775219
Short name T95
Test name
Test status
Simulation time 94962287830 ps
CPU time 2693.8 seconds
Started Aug 04 04:46:11 PM PDT 24
Finished Aug 04 05:31:05 PM PDT 24
Peak memory 288744 kb
Host smart-d9fceec1-97c8-480f-a8e4-c8490bbe7b3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276775219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1276775219
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3491069438
Short name T30
Test name
Test status
Simulation time 74584662844 ps
CPU time 1555.38 seconds
Started Aug 04 04:46:39 PM PDT 24
Finished Aug 04 05:12:34 PM PDT 24
Peak memory 289244 kb
Host smart-98c88ab0-6340-43d9-9417-e5a6e927108e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491069438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3491069438
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.862820684
Short name T25
Test name
Test status
Simulation time 876149445 ps
CPU time 63.34 seconds
Started Aug 04 04:45:29 PM PDT 24
Finished Aug 04 04:46:33 PM PDT 24
Peak memory 255472 kb
Host smart-6823ef48-e65a-4f7d-8bd1-cad587ab103e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86282
0684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.862820684
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3126711524
Short name T134
Test name
Test status
Simulation time 8630771537 ps
CPU time 661.78 seconds
Started Aug 04 05:34:57 PM PDT 24
Finished Aug 04 05:45:59 PM PDT 24
Peak memory 265800 kb
Host smart-110cfded-8746-4f5a-b36d-f2df0e7553b9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126711524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3126711524
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2400692483
Short name T97
Test name
Test status
Simulation time 80583363929 ps
CPU time 1846.24 seconds
Started Aug 04 04:42:42 PM PDT 24
Finished Aug 04 05:13:28 PM PDT 24
Peak memory 297532 kb
Host smart-c8ecf485-a499-4006-8832-a468422671c3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400692483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2400692483
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.3959405853
Short name T276
Test name
Test status
Simulation time 1195258858817 ps
CPU time 8554.93 seconds
Started Aug 04 04:46:30 PM PDT 24
Finished Aug 04 07:09:06 PM PDT 24
Peak memory 354416 kb
Host smart-d468394c-6676-4c9d-b7d0-d03c6ac60b16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959405853 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.3959405853
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.17691848
Short name T144
Test name
Test status
Simulation time 7640299182 ps
CPU time 188.04 seconds
Started Aug 04 05:34:42 PM PDT 24
Finished Aug 04 05:37:51 PM PDT 24
Peak memory 265656 kb
Host smart-c5de2c1c-8414-4bef-b5ca-82838163ca8a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=17691848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors
.17691848
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1629772046
Short name T118
Test name
Test status
Simulation time 198598131336 ps
CPU time 5228.22 seconds
Started Aug 04 04:44:47 PM PDT 24
Finished Aug 04 06:11:56 PM PDT 24
Peak memory 354328 kb
Host smart-fe4ad25e-7b7a-4a30-a1e8-0c49d2f16108
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629772046 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1629772046
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1817771287
Short name T132
Test name
Test status
Simulation time 66759268264 ps
CPU time 1112.3 seconds
Started Aug 04 05:35:00 PM PDT 24
Finished Aug 04 05:53:33 PM PDT 24
Peak memory 265600 kb
Host smart-35886864-6127-41eb-ba64-7f21ea8dfbcb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817771287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1817771287
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1105425031
Short name T7
Test name
Test status
Simulation time 52383328118 ps
CPU time 595.63 seconds
Started Aug 04 04:44:37 PM PDT 24
Finished Aug 04 04:54:33 PM PDT 24
Peak memory 248096 kb
Host smart-3468d109-1a0f-4491-b923-43df7201a173
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105425031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1105425031
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3925584936
Short name T135
Test name
Test status
Simulation time 14018856726 ps
CPU time 244.23 seconds
Started Aug 04 05:35:12 PM PDT 24
Finished Aug 04 05:39:16 PM PDT 24
Peak memory 265676 kb
Host smart-24cb0bb2-83c8-4868-a6fa-27b47e2bb879
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3925584936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3925584936
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2894584160
Short name T372
Test name
Test status
Simulation time 34127946 ps
CPU time 1.34 seconds
Started Aug 04 05:34:46 PM PDT 24
Finished Aug 04 05:34:47 PM PDT 24
Peak memory 237684 kb
Host smart-04d589b0-0b0c-44d1-9298-418e7271f0db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2894584160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2894584160
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3939190130
Short name T133
Test name
Test status
Simulation time 29915788126 ps
CPU time 296.52 seconds
Started Aug 04 05:35:08 PM PDT 24
Finished Aug 04 05:40:05 PM PDT 24
Peak memory 265692 kb
Host smart-607901bc-0b41-4941-8bc5-7f8f0497b9a5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939190130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3939190130
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.565685944
Short name T21
Test name
Test status
Simulation time 2315523892 ps
CPU time 64.28 seconds
Started Aug 04 04:43:17 PM PDT 24
Finished Aug 04 04:44:22 PM PDT 24
Peak memory 248444 kb
Host smart-1dbd5a23-b349-411f-8bab-12caa18829c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56568
5944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.565685944
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3727385084
Short name T351
Test name
Test status
Simulation time 92278150933 ps
CPU time 2420.01 seconds
Started Aug 04 04:44:32 PM PDT 24
Finished Aug 04 05:24:52 PM PDT 24
Peak memory 288960 kb
Host smart-e579d1b6-4e95-41fb-b78c-fb818f109085
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727385084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3727385084
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2735508067
Short name T125
Test name
Test status
Simulation time 16138788805 ps
CPU time 174.55 seconds
Started Aug 04 05:35:09 PM PDT 24
Finished Aug 04 05:38:04 PM PDT 24
Peak memory 265552 kb
Host smart-4e01eb5c-2b6b-40c3-b26a-b02f6aa6e123
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2735508067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2735508067
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1083511404
Short name T17
Test name
Test status
Simulation time 21980118386 ps
CPU time 464.93 seconds
Started Aug 04 04:42:30 PM PDT 24
Finished Aug 04 04:50:15 PM PDT 24
Peak memory 248120 kb
Host smart-956bdd9b-1cff-401d-a3db-6e1e1846e55d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083511404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1083511404
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1920254431
Short name T339
Test name
Test status
Simulation time 43363284784 ps
CPU time 1323.01 seconds
Started Aug 04 04:46:01 PM PDT 24
Finished Aug 04 05:08:04 PM PDT 24
Peak memory 272108 kb
Host smart-ac811a25-a5cf-4551-8466-c6b030d951a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920254431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1920254431
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2258143902
Short name T138
Test name
Test status
Simulation time 17656623798 ps
CPU time 607.37 seconds
Started Aug 04 05:34:51 PM PDT 24
Finished Aug 04 05:44:58 PM PDT 24
Peak memory 265640 kb
Host smart-ffb87cdb-7122-4a28-b9e2-dbcb48e278ff
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258143902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2258143902
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1321989939
Short name T32
Test name
Test status
Simulation time 182774724398 ps
CPU time 2720.87 seconds
Started Aug 04 04:46:56 PM PDT 24
Finished Aug 04 05:32:17 PM PDT 24
Peak memory 284100 kb
Host smart-cf87bbf3-22a2-402b-bae9-42765b600efc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321989939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1321989939
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1907130347
Short name T320
Test name
Test status
Simulation time 37499596628 ps
CPU time 608.02 seconds
Started Aug 04 04:47:01 PM PDT 24
Finished Aug 04 04:57:09 PM PDT 24
Peak memory 247188 kb
Host smart-938b769d-35f1-4c5a-bfbb-071b146029f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907130347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1907130347
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.69951144
Short name T167
Test name
Test status
Simulation time 367656971 ps
CPU time 39.57 seconds
Started Aug 04 05:34:54 PM PDT 24
Finished Aug 04 05:35:34 PM PDT 24
Peak memory 240644 kb
Host smart-5b8f96af-61c4-477c-92d4-dfdb4c0276c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=69951144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.69951144
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1114399240
Short name T155
Test name
Test status
Simulation time 22303332549 ps
CPU time 358.37 seconds
Started Aug 04 05:35:01 PM PDT 24
Finished Aug 04 05:41:00 PM PDT 24
Peak memory 265676 kb
Host smart-6ca36da0-57d1-443a-b9f7-0af6a84b1cd0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1114399240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1114399240
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.3388492688
Short name T187
Test name
Test status
Simulation time 205898045039 ps
CPU time 8067.88 seconds
Started Aug 04 04:44:30 PM PDT 24
Finished Aug 04 06:58:59 PM PDT 24
Peak memory 391448 kb
Host smart-eb389f9d-dfb2-4ef5-8c16-13a966249f15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388492688 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.3388492688
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3045438085
Short name T16
Test name
Test status
Simulation time 243089501016 ps
CPU time 2525.61 seconds
Started Aug 04 04:44:37 PM PDT 24
Finished Aug 04 05:26:43 PM PDT 24
Peak memory 282472 kb
Host smart-589c71e7-2e69-4d2f-bb70-478ee34e3dc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045438085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3045438085
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2227915810
Short name T150
Test name
Test status
Simulation time 50942232582 ps
CPU time 905.11 seconds
Started Aug 04 05:34:45 PM PDT 24
Finished Aug 04 05:49:51 PM PDT 24
Peak memory 265624 kb
Host smart-d043b81b-abd0-4c40-827f-aad6faa6dca2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227915810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2227915810
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2786418737
Short name T321
Test name
Test status
Simulation time 22178471809 ps
CPU time 493.35 seconds
Started Aug 04 04:44:24 PM PDT 24
Finished Aug 04 04:52:37 PM PDT 24
Peak memory 247164 kb
Host smart-8ab616a2-43af-44ea-92ab-23c21c66c1c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786418737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2786418737
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3946729901
Short name T108
Test name
Test status
Simulation time 28280081152 ps
CPU time 1530.74 seconds
Started Aug 04 04:44:28 PM PDT 24
Finished Aug 04 05:09:59 PM PDT 24
Peak memory 289052 kb
Host smart-ad55de2c-7083-4e77-bb54-32aa1e8f793e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946729901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3946729901
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1015114972
Short name T127
Test name
Test status
Simulation time 1908031567 ps
CPU time 114.64 seconds
Started Aug 04 05:35:06 PM PDT 24
Finished Aug 04 05:37:00 PM PDT 24
Peak memory 265548 kb
Host smart-59b0dd9a-d6a3-4098-b133-9eaf6b675a45
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1015114972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1015114972
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3275919997
Short name T142
Test name
Test status
Simulation time 3546037806 ps
CPU time 218.81 seconds
Started Aug 04 05:34:46 PM PDT 24
Finished Aug 04 05:38:25 PM PDT 24
Peak memory 265552 kb
Host smart-122e6ba9-02a4-4a51-82e0-397e7f2033d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3275919997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3275919997
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1295613584
Short name T683
Test name
Test status
Simulation time 146634975974 ps
CPU time 1661.02 seconds
Started Aug 04 04:42:37 PM PDT 24
Finished Aug 04 05:10:19 PM PDT 24
Peak memory 272476 kb
Host smart-5a967853-447b-42ce-a1eb-626c67098acf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295613584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1295613584
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1531557832
Short name T289
Test name
Test status
Simulation time 117689355733 ps
CPU time 3029.17 seconds
Started Aug 04 04:44:32 PM PDT 24
Finished Aug 04 05:35:01 PM PDT 24
Peak memory 304952 kb
Host smart-2f22fb71-632d-408a-94f3-3590b3444c65
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531557832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1531557832
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3180879488
Short name T343
Test name
Test status
Simulation time 11695383346 ps
CPU time 419.55 seconds
Started Aug 04 04:45:33 PM PDT 24
Finished Aug 04 04:52:33 PM PDT 24
Peak memory 248140 kb
Host smart-40afd7ef-f04d-4c01-9653-aa4c6ddac44c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180879488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3180879488
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1092670067
Short name T287
Test name
Test status
Simulation time 14497744981 ps
CPU time 1399.25 seconds
Started Aug 04 04:45:40 PM PDT 24
Finished Aug 04 05:09:00 PM PDT 24
Peak memory 288536 kb
Host smart-2cacacc9-8ea4-4e15-a77d-c15940eee871
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092670067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1092670067
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2579938861
Short name T374
Test name
Test status
Simulation time 11316395 ps
CPU time 1.68 seconds
Started Aug 04 05:35:18 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 237724 kb
Host smart-5c9c191c-17ea-4e3a-9524-c8e70ccd3605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2579938861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2579938861
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.39103506
Short name T248
Test name
Test status
Simulation time 52951156526 ps
CPU time 3060.84 seconds
Started Aug 04 04:44:11 PM PDT 24
Finished Aug 04 05:35:13 PM PDT 24
Peak memory 288828 kb
Host smart-33596c4a-5f8c-43c7-bfc6-b88258a09f7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39103506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.39103506
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1124744266
Short name T96
Test name
Test status
Simulation time 222311570840 ps
CPU time 3188.33 seconds
Started Aug 04 04:46:54 PM PDT 24
Finished Aug 04 05:40:03 PM PDT 24
Peak memory 289228 kb
Host smart-c57e3bd7-ee27-4d93-83e9-13bb12b63b34
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124744266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1124744266
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3380835491
Short name T163
Test name
Test status
Simulation time 56475756 ps
CPU time 3.24 seconds
Started Aug 04 05:35:08 PM PDT 24
Finished Aug 04 05:35:11 PM PDT 24
Peak memory 237728 kb
Host smart-a7bf2d89-33f9-4e83-92fd-c1bd335331b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3380835491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3380835491
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1046088215
Short name T22
Test name
Test status
Simulation time 6032736554 ps
CPU time 130.74 seconds
Started Aug 04 04:44:47 PM PDT 24
Finished Aug 04 04:46:58 PM PDT 24
Peak memory 255692 kb
Host smart-73c25718-64e2-4ec2-828b-e1a71e1d98f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10460
88215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1046088215
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.4136178231
Short name T329
Test name
Test status
Simulation time 12576948613 ps
CPU time 489.71 seconds
Started Aug 04 04:45:14 PM PDT 24
Finished Aug 04 04:53:24 PM PDT 24
Peak memory 247156 kb
Host smart-9be26f81-2c88-440b-93a0-861532179490
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136178231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.4136178231
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3952302068
Short name T90
Test name
Test status
Simulation time 1040960067 ps
CPU time 26.24 seconds
Started Aug 04 04:46:17 PM PDT 24
Finished Aug 04 04:46:43 PM PDT 24
Peak memory 247344 kb
Host smart-678e08d3-ce57-432e-8f87-9cdeb5cdabf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39523
02068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3952302068
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.644829528
Short name T158
Test name
Test status
Simulation time 4784345982 ps
CPU time 582.25 seconds
Started Aug 04 05:35:05 PM PDT 24
Finished Aug 04 05:44:48 PM PDT 24
Peak memory 270816 kb
Host smart-da7cad08-5994-4571-9547-848a91db51ca
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644829528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.644829528
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.698257373
Short name T353
Test name
Test status
Simulation time 251776900489 ps
CPU time 3227.8 seconds
Started Aug 04 04:43:58 PM PDT 24
Finished Aug 04 05:37:46 PM PDT 24
Peak memory 288600 kb
Host smart-1a6d0900-9ef5-4635-a943-993736f064f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698257373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.698257373
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2879161270
Short name T273
Test name
Test status
Simulation time 633165539 ps
CPU time 42.26 seconds
Started Aug 04 04:44:05 PM PDT 24
Finished Aug 04 04:44:48 PM PDT 24
Peak memory 255772 kb
Host smart-36f9c454-f46b-4a44-b89a-c238ddd3edcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28791
61270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2879161270
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3339709153
Short name T39
Test name
Test status
Simulation time 232381764324 ps
CPU time 3409.93 seconds
Started Aug 04 04:42:49 PM PDT 24
Finished Aug 04 05:39:40 PM PDT 24
Peak memory 305284 kb
Host smart-669469ee-0da7-4338-8887-9d12570bda31
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339709153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3339709153
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.426001186
Short name T313
Test name
Test status
Simulation time 22504855129 ps
CPU time 1374.57 seconds
Started Aug 04 04:43:10 PM PDT 24
Finished Aug 04 05:06:05 PM PDT 24
Peak memory 269132 kb
Host smart-7bc020f5-477c-46ce-a5c3-621eccb45f4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426001186 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.426001186
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2010369891
Short name T128
Test name
Test status
Simulation time 6959710177 ps
CPU time 114.78 seconds
Started Aug 04 05:35:12 PM PDT 24
Finished Aug 04 05:37:07 PM PDT 24
Peak memory 265616 kb
Host smart-7755b194-2c45-4a10-9225-f1d931cfd0c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2010369891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2010369891
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2114098173
Short name T153
Test name
Test status
Simulation time 50357469832 ps
CPU time 1017.91 seconds
Started Aug 04 05:34:42 PM PDT 24
Finished Aug 04 05:51:40 PM PDT 24
Peak memory 265780 kb
Host smart-d44dab43-2c2e-4e2d-9598-c4faa707d7e3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114098173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2114098173
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.238772947
Short name T232
Test name
Test status
Simulation time 27992813 ps
CPU time 2.74 seconds
Started Aug 04 04:42:35 PM PDT 24
Finished Aug 04 04:42:38 PM PDT 24
Peak memory 248584 kb
Host smart-08aca133-e7c0-4291-9df5-b3b017266f39
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=238772947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.238772947
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3576532285
Short name T229
Test name
Test status
Simulation time 16011315 ps
CPU time 2.57 seconds
Started Aug 04 04:42:41 PM PDT 24
Finished Aug 04 04:42:43 PM PDT 24
Peak memory 248480 kb
Host smart-b13adb71-cf8d-43b0-b2a2-319a65e81c58
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3576532285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3576532285
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.504826604
Short name T224
Test name
Test status
Simulation time 63967832 ps
CPU time 3.14 seconds
Started Aug 04 04:43:37 PM PDT 24
Finished Aug 04 04:43:40 PM PDT 24
Peak memory 248584 kb
Host smart-8aa991b2-99e8-4613-93bd-b46a592873ab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=504826604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.504826604
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.232267138
Short name T220
Test name
Test status
Simulation time 272232905 ps
CPU time 3.55 seconds
Started Aug 04 04:43:47 PM PDT 24
Finished Aug 04 04:43:51 PM PDT 24
Peak memory 248544 kb
Host smart-fb8012ff-a84d-4ebd-b63b-1eadde63bfd9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=232267138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.232267138
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3236997653
Short name T726
Test name
Test status
Simulation time 9724162 ps
CPU time 1.55 seconds
Started Aug 04 05:35:15 PM PDT 24
Finished Aug 04 05:35:17 PM PDT 24
Peak memory 236732 kb
Host smart-9e2b5c5a-3215-43fd-aaf3-13fff83da313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3236997653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3236997653
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.713811979
Short name T334
Test name
Test status
Simulation time 21294788963 ps
CPU time 491.08 seconds
Started Aug 04 04:44:05 PM PDT 24
Finished Aug 04 04:52:16 PM PDT 24
Peak memory 248172 kb
Host smart-8565ff9d-58fd-4fc7-ae96-04fc45dbe405
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713811979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.713811979
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.306778394
Short name T1
Test name
Test status
Simulation time 2532507342 ps
CPU time 28.24 seconds
Started Aug 04 04:44:25 PM PDT 24
Finished Aug 04 04:44:53 PM PDT 24
Peak memory 255060 kb
Host smart-5256bba1-14c8-4bbf-9e3c-1f5e1bae7d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30677
8394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.306778394
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1592356631
Short name T318
Test name
Test status
Simulation time 201467860957 ps
CPU time 402.42 seconds
Started Aug 04 04:44:31 PM PDT 24
Finished Aug 04 04:51:14 PM PDT 24
Peak memory 248308 kb
Host smart-4befe924-3fbc-42a1-9b52-fb105059c5e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592356631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1592356631
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1249150324
Short name T274
Test name
Test status
Simulation time 92705273783 ps
CPU time 2653.34 seconds
Started Aug 04 04:46:00 PM PDT 24
Finished Aug 04 05:30:14 PM PDT 24
Peak memory 288276 kb
Host smart-888fba6c-5bd5-4961-a3f3-3fe75dc04c98
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249150324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1249150324
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3576626271
Short name T66
Test name
Test status
Simulation time 63368146285 ps
CPU time 2690.8 seconds
Started Aug 04 04:46:24 PM PDT 24
Finished Aug 04 05:31:15 PM PDT 24
Peak memory 288948 kb
Host smart-1d55422f-e69b-4105-9a47-3556c5625bc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576626271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3576626271
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1418439201
Short name T319
Test name
Test status
Simulation time 31124696251 ps
CPU time 642.83 seconds
Started Aug 04 04:46:32 PM PDT 24
Finished Aug 04 04:57:15 PM PDT 24
Peak memory 248292 kb
Host smart-966d8415-45e9-4859-bf58-e9cc186ad587
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418439201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1418439201
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.4279969091
Short name T35
Test name
Test status
Simulation time 4256094436 ps
CPU time 30.4 seconds
Started Aug 04 04:42:43 PM PDT 24
Finished Aug 04 04:43:14 PM PDT 24
Peak memory 247916 kb
Host smart-ed743712-b54c-4406-959f-b953ed9985b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42799
69091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.4279969091
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.590625292
Short name T157
Test name
Test status
Simulation time 5294509783 ps
CPU time 354 seconds
Started Aug 04 05:34:54 PM PDT 24
Finished Aug 04 05:40:49 PM PDT 24
Peak memory 273828 kb
Host smart-cbee3233-5b59-483e-a353-769a7a936490
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=590625292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.590625292
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3086000448
Short name T149
Test name
Test status
Simulation time 8835126804 ps
CPU time 612.87 seconds
Started Aug 04 05:35:16 PM PDT 24
Finished Aug 04 05:45:29 PM PDT 24
Peak memory 265576 kb
Host smart-88b35f42-e2dc-4ba8-acdd-ac526cf373d9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086000448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3086000448
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2432845351
Short name T104
Test name
Test status
Simulation time 242170576 ps
CPU time 14.51 seconds
Started Aug 04 04:42:37 PM PDT 24
Finished Aug 04 04:42:51 PM PDT 24
Peak memory 247720 kb
Host smart-e9ef0d51-6760-4a93-8d12-716131fdb43d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24328
45351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2432845351
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.180018206
Short name T295
Test name
Test status
Simulation time 3353464808 ps
CPU time 45.73 seconds
Started Aug 04 04:43:45 PM PDT 24
Finished Aug 04 04:44:30 PM PDT 24
Peak memory 256472 kb
Host smart-8ba5eae3-1ef0-44ab-ac1c-d3df4d0aea2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18001
8206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.180018206
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2735467951
Short name T358
Test name
Test status
Simulation time 101690886766 ps
CPU time 2024.67 seconds
Started Aug 04 04:43:53 PM PDT 24
Finished Aug 04 05:17:38 PM PDT 24
Peak memory 282540 kb
Host smart-24ce60c8-998e-4cd9-88d5-cb41524f834e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735467951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2735467951
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.436615765
Short name T113
Test name
Test status
Simulation time 195831571295 ps
CPU time 3430.86 seconds
Started Aug 04 04:44:05 PM PDT 24
Finished Aug 04 05:41:16 PM PDT 24
Peak memory 297484 kb
Host smart-5b20d1e9-cf6c-4a17-9f82-8f1192e836b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436615765 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.436615765
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2921894998
Short name T304
Test name
Test status
Simulation time 220017057 ps
CPU time 21.9 seconds
Started Aug 04 04:44:04 PM PDT 24
Finished Aug 04 04:44:26 PM PDT 24
Peak memory 248164 kb
Host smart-de561d33-c5c9-47c2-8fa3-32e984ce7c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29218
94998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2921894998
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3621052322
Short name T81
Test name
Test status
Simulation time 383655837 ps
CPU time 24.16 seconds
Started Aug 04 04:44:21 PM PDT 24
Finished Aug 04 04:44:45 PM PDT 24
Peak memory 256488 kb
Host smart-176f8874-6b04-4b70-a7fe-3d354c72da15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36210
52322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3621052322
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.494151420
Short name T291
Test name
Test status
Simulation time 35240327320 ps
CPU time 3709.25 seconds
Started Aug 04 04:42:47 PM PDT 24
Finished Aug 04 05:44:37 PM PDT 24
Peak memory 336976 kb
Host smart-e743b367-18fd-4802-a7c5-9a12d9e75141
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494151420 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.494151420
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.609660028
Short name T53
Test name
Test status
Simulation time 444185666181 ps
CPU time 1919.38 seconds
Started Aug 04 04:44:38 PM PDT 24
Finished Aug 04 05:16:37 PM PDT 24
Peak memory 289584 kb
Host smart-4fbac1b6-7055-4fa7-8d75-beabf29d2ac4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609660028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_han
dler_stress_all.609660028
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.495955375
Short name T280
Test name
Test status
Simulation time 180721152574 ps
CPU time 2129.82 seconds
Started Aug 04 04:44:49 PM PDT 24
Finished Aug 04 05:20:19 PM PDT 24
Peak memory 286968 kb
Host smart-27e8b30b-3d48-4e88-9928-b3c12506031a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495955375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.495955375
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.155924486
Short name T278
Test name
Test status
Simulation time 2259530582 ps
CPU time 35.77 seconds
Started Aug 04 04:45:04 PM PDT 24
Finished Aug 04 04:45:40 PM PDT 24
Peak memory 247720 kb
Host smart-fef8cbc2-d5e2-4d2c-a6a7-9084ed138eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15592
4486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.155924486
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.3086817186
Short name T296
Test name
Test status
Simulation time 95230307783 ps
CPU time 2496.31 seconds
Started Aug 04 04:45:10 PM PDT 24
Finished Aug 04 05:26:47 PM PDT 24
Peak memory 313408 kb
Host smart-e1bee730-6518-4142-991b-966e1f58f401
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086817186 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.3086817186
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.23928093
Short name T292
Test name
Test status
Simulation time 11668863516 ps
CPU time 1320.05 seconds
Started Aug 04 04:45:14 PM PDT 24
Finished Aug 04 05:07:14 PM PDT 24
Peak memory 288604 kb
Host smart-ea199d16-6e6b-42b1-b53c-d6a23a7c0c0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23928093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.23928093
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.288871648
Short name T275
Test name
Test status
Simulation time 8972821013 ps
CPU time 599.31 seconds
Started Aug 04 04:45:29 PM PDT 24
Finished Aug 04 04:55:28 PM PDT 24
Peak memory 273328 kb
Host smart-bbf43b03-6634-4d91-9745-cb89e6585773
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288871648 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.288871648
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2680318543
Short name T193
Test name
Test status
Simulation time 19775814299 ps
CPU time 1757.62 seconds
Started Aug 04 04:45:41 PM PDT 24
Finished Aug 04 05:14:59 PM PDT 24
Peak memory 288684 kb
Host smart-79af518c-9789-4815-8f30-bda4ae38322c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680318543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2680318543
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1729087102
Short name T355
Test name
Test status
Simulation time 41086958377 ps
CPU time 2378.13 seconds
Started Aug 04 04:45:52 PM PDT 24
Finished Aug 04 05:25:31 PM PDT 24
Peak memory 289188 kb
Host smart-3aa34b60-90b4-416d-9da7-fd3066351032
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729087102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1729087102
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2185393478
Short name T282
Test name
Test status
Simulation time 3405543455 ps
CPU time 25.14 seconds
Started Aug 04 04:43:00 PM PDT 24
Finished Aug 04 04:43:25 PM PDT 24
Peak memory 248712 kb
Host smart-cb2b07d6-d890-4908-a573-f00a3cae56bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21853
93478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2185393478
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1036004146
Short name T168
Test name
Test status
Simulation time 171065888 ps
CPU time 2.95 seconds
Started Aug 04 05:35:09 PM PDT 24
Finished Aug 04 05:35:12 PM PDT 24
Peak memory 238096 kb
Host smart-f6e326cb-438d-41f9-b471-9d6c1f4ecccb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1036004146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1036004146
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3109277756
Short name T178
Test name
Test status
Simulation time 7332401981 ps
CPU time 85.92 seconds
Started Aug 04 05:35:19 PM PDT 24
Finished Aug 04 05:36:45 PM PDT 24
Peak memory 240764 kb
Host smart-5c161de2-ce47-4e1a-9dfc-df20e4984a62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3109277756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3109277756
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2290008860
Short name T170
Test name
Test status
Simulation time 113897030 ps
CPU time 3.01 seconds
Started Aug 04 05:35:17 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 238008 kb
Host smart-fdb7e089-6bb2-4188-afd0-f72d1e67c2dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2290008860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2290008860
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3186173512
Short name T180
Test name
Test status
Simulation time 143228513 ps
CPU time 2.98 seconds
Started Aug 04 05:34:52 PM PDT 24
Finished Aug 04 05:34:56 PM PDT 24
Peak memory 237976 kb
Host smart-0582d631-d279-4ee9-b354-9c6d85ced1be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3186173512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3186173512
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2593890815
Short name T175
Test name
Test status
Simulation time 2398500372 ps
CPU time 43.11 seconds
Started Aug 04 05:35:08 PM PDT 24
Finished Aug 04 05:35:51 PM PDT 24
Peak memory 240664 kb
Host smart-25fc276f-e2ad-43f2-af69-e630aa74982c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2593890815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2593890815
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2768850828
Short name T143
Test name
Test status
Simulation time 4395550833 ps
CPU time 306.83 seconds
Started Aug 04 05:35:06 PM PDT 24
Finished Aug 04 05:40:13 PM PDT 24
Peak memory 273120 kb
Host smart-cc3114f5-2eef-4cbd-b4c7-f74479ea6972
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2768850828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2768850828
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.735495100
Short name T161
Test name
Test status
Simulation time 492520877 ps
CPU time 4.4 seconds
Started Aug 04 05:35:06 PM PDT 24
Finished Aug 04 05:35:11 PM PDT 24
Peak memory 237444 kb
Host smart-c7472d8b-4e60-4386-b72b-1fc1865d1875
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=735495100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.735495100
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.402386241
Short name T176
Test name
Test status
Simulation time 68533041 ps
CPU time 4.63 seconds
Started Aug 04 05:35:12 PM PDT 24
Finished Aug 04 05:35:16 PM PDT 24
Peak memory 237724 kb
Host smart-c8672f2f-e093-4fc7-86be-a3263c525ed2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=402386241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.402386241
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2397659647
Short name T145
Test name
Test status
Simulation time 6293125167 ps
CPU time 180.81 seconds
Started Aug 04 05:35:16 PM PDT 24
Finished Aug 04 05:38:17 PM PDT 24
Peak memory 265544 kb
Host smart-4dc7ae29-24fb-4d86-b11f-4a6a35c62229
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2397659647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2397659647
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3515618667
Short name T172
Test name
Test status
Simulation time 56890980 ps
CPU time 3.64 seconds
Started Aug 04 05:34:47 PM PDT 24
Finished Aug 04 05:34:51 PM PDT 24
Peak memory 237724 kb
Host smart-c10e604c-d32e-4f3a-9e6b-66e0b80d7090
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3515618667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3515618667
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3861283384
Short name T174
Test name
Test status
Simulation time 91242790 ps
CPU time 2.69 seconds
Started Aug 04 05:34:54 PM PDT 24
Finished Aug 04 05:34:57 PM PDT 24
Peak memory 237712 kb
Host smart-209e9c3f-e441-482a-aab7-bd81e1873ad0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3861283384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3861283384
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.316687446
Short name T171
Test name
Test status
Simulation time 176742242 ps
CPU time 2.34 seconds
Started Aug 04 05:34:42 PM PDT 24
Finished Aug 04 05:34:45 PM PDT 24
Peak memory 237564 kb
Host smart-134e4b66-e1dc-4582-a6da-0ac3f6451c46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=316687446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.316687446
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.4076039467
Short name T216
Test name
Test status
Simulation time 14258382461 ps
CPU time 197.84 seconds
Started Aug 04 05:34:50 PM PDT 24
Finished Aug 04 05:38:08 PM PDT 24
Peak memory 236964 kb
Host smart-467f5449-d194-47a4-a7ac-28cb78e87217
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4076039467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.4076039467
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2746895434
Short name T177
Test name
Test status
Simulation time 460002477 ps
CPU time 33.74 seconds
Started Aug 04 05:34:46 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 240660 kb
Host smart-b7815b3f-705f-4ab1-b73c-6b9be7ed50a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2746895434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2746895434
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1040607634
Short name T186
Test name
Test status
Simulation time 4980543578 ps
CPU time 41.5 seconds
Started Aug 04 05:35:05 PM PDT 24
Finished Aug 04 05:35:46 PM PDT 24
Peak memory 240764 kb
Host smart-60d40af4-03bf-41fe-b20b-c1512cacacd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1040607634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1040607634
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2330078684
Short name T162
Test name
Test status
Simulation time 380378329 ps
CPU time 2.38 seconds
Started Aug 04 05:35:09 PM PDT 24
Finished Aug 04 05:35:11 PM PDT 24
Peak memory 237520 kb
Host smart-43058da5-a270-4344-b08e-bab93d983ed6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2330078684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2330078684
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.348497560
Short name T185
Test name
Test status
Simulation time 191993533 ps
CPU time 2.53 seconds
Started Aug 04 05:34:58 PM PDT 24
Finished Aug 04 05:35:01 PM PDT 24
Peak memory 237720 kb
Host smart-25330b6c-9b1b-42ec-ac14-85f778a1546d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=348497560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.348497560
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2377064015
Short name T179
Test name
Test status
Simulation time 115325306 ps
CPU time 3.01 seconds
Started Aug 04 05:34:59 PM PDT 24
Finished Aug 04 05:35:02 PM PDT 24
Peak memory 237696 kb
Host smart-620c3a8e-54c4-4174-85c7-90b0a0d54e01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2377064015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2377064015
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.765970428
Short name T27
Test name
Test status
Simulation time 153515116020 ps
CPU time 1965.92 seconds
Started Aug 04 04:42:31 PM PDT 24
Finished Aug 04 05:15:17 PM PDT 24
Peak memory 272792 kb
Host smart-1c70348f-612b-42f6-8d6f-c68754eb553c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765970428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.765970428
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2456461326
Short name T28
Test name
Test status
Simulation time 816766235 ps
CPU time 44.86 seconds
Started Aug 04 04:44:42 PM PDT 24
Finished Aug 04 04:45:27 PM PDT 24
Peak memory 256384 kb
Host smart-5fafa419-3348-40a2-924b-0215811703b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24564
61326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2456461326
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.291134438
Short name T776
Test name
Test status
Simulation time 4448597673 ps
CPU time 137.99 seconds
Started Aug 04 05:34:42 PM PDT 24
Finished Aug 04 05:37:00 PM PDT 24
Peak memory 240780 kb
Host smart-6d98e200-8cfc-43fe-a2d8-e436294956bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=291134438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.291134438
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2037814200
Short name T746
Test name
Test status
Simulation time 3268438057 ps
CPU time 183.95 seconds
Started Aug 04 05:34:43 PM PDT 24
Finished Aug 04 05:37:48 PM PDT 24
Peak memory 240668 kb
Host smart-4a1bae2e-46e2-4dc1-8a34-446816077376
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2037814200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2037814200
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1047262378
Short name T249
Test name
Test status
Simulation time 81187703 ps
CPU time 3.45 seconds
Started Aug 04 05:34:40 PM PDT 24
Finished Aug 04 05:34:43 PM PDT 24
Peak memory 248828 kb
Host smart-3ce5958f-2ff4-4905-b994-ff31cc196b65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1047262378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1047262378
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.45167508
Short name T745
Test name
Test status
Simulation time 115099552 ps
CPU time 9.05 seconds
Started Aug 04 05:34:41 PM PDT 24
Finished Aug 04 05:34:51 PM PDT 24
Peak memory 253156 kb
Host smart-f0c0b65c-0e4e-4ade-96e4-ddb7258178b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45167508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.alert_handler_csr_mem_rw_with_rand_reset.45167508
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.4110340613
Short name T266
Test name
Test status
Simulation time 70406469 ps
CPU time 5.59 seconds
Started Aug 04 05:34:45 PM PDT 24
Finished Aug 04 05:34:50 PM PDT 24
Peak memory 237568 kb
Host smart-d51ed8a5-2654-427c-ad5a-c9dacab9a86a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4110340613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.4110340613
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2389108934
Short name T780
Test name
Test status
Simulation time 16112107 ps
CPU time 1.5 seconds
Started Aug 04 05:34:41 PM PDT 24
Finished Aug 04 05:34:42 PM PDT 24
Peak memory 237664 kb
Host smart-96c723f5-21ff-4f18-a2db-c7e1d4d15b83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2389108934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2389108934
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.358755431
Short name T773
Test name
Test status
Simulation time 86243930 ps
CPU time 12.12 seconds
Started Aug 04 05:34:45 PM PDT 24
Finished Aug 04 05:34:57 PM PDT 24
Peak memory 245916 kb
Host smart-83ccadbb-6d09-4f26-a9a0-6fd5b6dd64fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=358755431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.358755431
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2296012443
Short name T793
Test name
Test status
Simulation time 704578900 ps
CPU time 24.5 seconds
Started Aug 04 05:34:46 PM PDT 24
Finished Aug 04 05:35:11 PM PDT 24
Peak memory 253996 kb
Host smart-93537957-a6dc-4fb5-b2c5-8ae6515607f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2296012443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2296012443
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3898720638
Short name T202
Test name
Test status
Simulation time 4489389833 ps
CPU time 118.31 seconds
Started Aug 04 05:34:52 PM PDT 24
Finished Aug 04 05:36:50 PM PDT 24
Peak memory 237928 kb
Host smart-eea07f1b-2724-420a-b3d1-5346366ca8a2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3898720638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3898720638
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.303401070
Short name T771
Test name
Test status
Simulation time 200307527 ps
CPU time 4.67 seconds
Started Aug 04 05:34:46 PM PDT 24
Finished Aug 04 05:34:51 PM PDT 24
Peak memory 240568 kb
Host smart-f8ef83f5-0e1c-44e5-b1e2-8db39e9436e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=303401070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.303401070
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3357536292
Short name T380
Test name
Test status
Simulation time 335861610 ps
CPU time 6.19 seconds
Started Aug 04 05:34:47 PM PDT 24
Finished Aug 04 05:34:54 PM PDT 24
Peak memory 256648 kb
Host smart-af95132b-9b17-4adc-9178-92104e4c2c8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357536292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3357536292
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3823887824
Short name T381
Test name
Test status
Simulation time 20774291 ps
CPU time 3.57 seconds
Started Aug 04 05:34:47 PM PDT 24
Finished Aug 04 05:34:50 PM PDT 24
Peak memory 237688 kb
Host smart-95903167-c56e-4905-8d30-15b9341a8799
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3823887824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3823887824
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1011943928
Short name T738
Test name
Test status
Simulation time 752214397 ps
CPU time 18.86 seconds
Started Aug 04 05:34:46 PM PDT 24
Finished Aug 04 05:35:05 PM PDT 24
Peak memory 248876 kb
Host smart-c5a31bbc-a784-4dbf-96c8-5973ad3d9fb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1011943928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1011943928
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.531373422
Short name T146
Test name
Test status
Simulation time 2326259382 ps
CPU time 161.79 seconds
Started Aug 04 05:34:42 PM PDT 24
Finished Aug 04 05:37:24 PM PDT 24
Peak memory 265600 kb
Host smart-5b5ba0b6-c87d-46dd-987e-a30b751c2640
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=531373422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.531373422
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2199886956
Short name T743
Test name
Test status
Simulation time 247809912 ps
CPU time 16.26 seconds
Started Aug 04 05:34:47 PM PDT 24
Finished Aug 04 05:35:03 PM PDT 24
Peak memory 248960 kb
Host smart-f8696fda-aa22-42a7-8276-9a117d9a54cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2199886956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2199886956
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.4068404080
Short name T809
Test name
Test status
Simulation time 167513784 ps
CPU time 12.53 seconds
Started Aug 04 05:35:12 PM PDT 24
Finished Aug 04 05:35:24 PM PDT 24
Peak memory 251952 kb
Host smart-3f5a65a3-977a-4a6d-93a8-f98aa70342cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068404080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.4068404080
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1610076551
Short name T796
Test name
Test status
Simulation time 158661164 ps
CPU time 5.24 seconds
Started Aug 04 05:35:06 PM PDT 24
Finished Aug 04 05:35:11 PM PDT 24
Peak memory 240560 kb
Host smart-5eea2eb0-95c8-43f2-a8ff-484fc987694e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1610076551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1610076551
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3730524363
Short name T753
Test name
Test status
Simulation time 15889175 ps
CPU time 1.37 seconds
Started Aug 04 05:35:03 PM PDT 24
Finished Aug 04 05:35:05 PM PDT 24
Peak memory 237728 kb
Host smart-5f9b9a4e-6a54-4c0b-ae11-eeace463c01a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3730524363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3730524363
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.919203892
Short name T203
Test name
Test status
Simulation time 256025311 ps
CPU time 17.45 seconds
Started Aug 04 05:35:04 PM PDT 24
Finished Aug 04 05:35:21 PM PDT 24
Peak memory 245012 kb
Host smart-78410e70-899b-48b6-9ddb-926087dcfaa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=919203892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.919203892
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.717747511
Short name T263
Test name
Test status
Simulation time 578486576 ps
CPU time 9.3 seconds
Started Aug 04 05:35:07 PM PDT 24
Finished Aug 04 05:35:17 PM PDT 24
Peak memory 248824 kb
Host smart-fd4ed26d-1128-4d96-90be-c74074067c8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=717747511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.717747511
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.420370456
Short name T781
Test name
Test status
Simulation time 477266600 ps
CPU time 12.89 seconds
Started Aug 04 05:35:06 PM PDT 24
Finished Aug 04 05:35:19 PM PDT 24
Peak memory 251976 kb
Host smart-c0101fea-4a6e-4450-a38f-8748b36fc713
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420370456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.alert_handler_csr_mem_rw_with_rand_reset.420370456
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.4148223051
Short name T805
Test name
Test status
Simulation time 666136798 ps
CPU time 7.58 seconds
Started Aug 04 05:35:05 PM PDT 24
Finished Aug 04 05:35:13 PM PDT 24
Peak memory 236796 kb
Host smart-0fa91f9a-c1d2-4b62-baf5-74bc5d1cdc8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4148223051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.4148223051
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1219568631
Short name T804
Test name
Test status
Simulation time 10804613 ps
CPU time 1.38 seconds
Started Aug 04 05:35:08 PM PDT 24
Finished Aug 04 05:35:10 PM PDT 24
Peak memory 237692 kb
Host smart-f344138c-d883-4376-992e-4215ce84eaa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1219568631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1219568631
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4293643177
Short name T727
Test name
Test status
Simulation time 646791078 ps
CPU time 21.51 seconds
Started Aug 04 05:35:10 PM PDT 24
Finished Aug 04 05:35:32 PM PDT 24
Peak memory 245020 kb
Host smart-24044427-e2aa-4c82-8c0d-730c761e33d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4293643177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.4293643177
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.510224448
Short name T159
Test name
Test status
Simulation time 16266764782 ps
CPU time 1048.11 seconds
Started Aug 04 05:35:08 PM PDT 24
Finished Aug 04 05:52:37 PM PDT 24
Peak memory 265812 kb
Host smart-a548011d-44e6-4dea-8db6-efad46375471
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510224448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.510224448
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1392502933
Short name T797
Test name
Test status
Simulation time 317692480 ps
CPU time 11.97 seconds
Started Aug 04 05:35:08 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 253688 kb
Host smart-53ccc333-d503-4838-b430-09e71ad62676
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1392502933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1392502933
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1454348542
Short name T382
Test name
Test status
Simulation time 183560877 ps
CPU time 12.44 seconds
Started Aug 04 05:35:14 PM PDT 24
Finished Aug 04 05:35:27 PM PDT 24
Peak memory 252760 kb
Host smart-2b3582bb-c7a9-45ba-9d61-2aa4640892b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454348542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1454348542
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.332601245
Short name T766
Test name
Test status
Simulation time 528042137 ps
CPU time 9.61 seconds
Started Aug 04 05:35:09 PM PDT 24
Finished Aug 04 05:35:19 PM PDT 24
Peak memory 240504 kb
Host smart-efb8e9ad-2592-482e-8161-cf7ae166f119
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=332601245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.332601245
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2137748372
Short name T747
Test name
Test status
Simulation time 27325483 ps
CPU time 1.63 seconds
Started Aug 04 05:35:11 PM PDT 24
Finished Aug 04 05:35:13 PM PDT 24
Peak memory 237724 kb
Host smart-1d3a029a-3366-4da9-8673-216ffcd9455f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2137748372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2137748372
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2486163192
Short name T181
Test name
Test status
Simulation time 686231828 ps
CPU time 23.48 seconds
Started Aug 04 05:35:11 PM PDT 24
Finished Aug 04 05:35:35 PM PDT 24
Peak memory 245852 kb
Host smart-4635bf7b-2d2b-4095-93aa-e700e67a7ba4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2486163192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2486163192
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2556532331
Short name T148
Test name
Test status
Simulation time 4616045873 ps
CPU time 117.24 seconds
Started Aug 04 05:35:09 PM PDT 24
Finished Aug 04 05:37:07 PM PDT 24
Peak memory 267860 kb
Host smart-371425b5-c03b-4231-b712-762b417a4624
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2556532331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2556532331
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2913401749
Short name T774
Test name
Test status
Simulation time 690821003 ps
CPU time 22.86 seconds
Started Aug 04 05:35:15 PM PDT 24
Finished Aug 04 05:35:38 PM PDT 24
Peak memory 248792 kb
Host smart-de5beba3-e7ca-4ac3-8dbf-da6cf38d90b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2913401749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2913401749
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1702110
Short name T169
Test name
Test status
Simulation time 38820190 ps
CPU time 3.28 seconds
Started Aug 04 05:35:15 PM PDT 24
Finished Aug 04 05:35:19 PM PDT 24
Peak memory 238052 kb
Host smart-fb1b9f52-166d-49c4-ae6b-2dadc7fc97fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1702110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1702110
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2212368745
Short name T724
Test name
Test status
Simulation time 211561968 ps
CPU time 4.99 seconds
Started Aug 04 05:35:10 PM PDT 24
Finished Aug 04 05:35:15 PM PDT 24
Peak memory 240700 kb
Host smart-6feebff6-2279-445b-88a0-8431e8743ff5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212368745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2212368745
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1822976690
Short name T822
Test name
Test status
Simulation time 107383150 ps
CPU time 7.18 seconds
Started Aug 04 05:35:16 PM PDT 24
Finished Aug 04 05:35:24 PM PDT 24
Peak memory 240624 kb
Host smart-f5e250d5-23f9-4b69-9ade-b8cc036f2e6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1822976690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1822976690
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1123591657
Short name T741
Test name
Test status
Simulation time 9659133 ps
CPU time 1.38 seconds
Started Aug 04 05:35:09 PM PDT 24
Finished Aug 04 05:35:11 PM PDT 24
Peak memory 235728 kb
Host smart-0c9b620f-35e6-4f28-935c-b60d8e7c9c43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1123591657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1123591657
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.88097751
Short name T824
Test name
Test status
Simulation time 245845889 ps
CPU time 21.6 seconds
Started Aug 04 05:35:19 PM PDT 24
Finished Aug 04 05:35:41 PM PDT 24
Peak memory 245828 kb
Host smart-5da247f3-4994-4dae-b49e-6152e699bb3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=88097751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_outs
tanding.88097751
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2291405839
Short name T816
Test name
Test status
Simulation time 4435415117 ps
CPU time 325.13 seconds
Started Aug 04 05:35:14 PM PDT 24
Finished Aug 04 05:40:39 PM PDT 24
Peak memory 265664 kb
Host smart-f06fd82a-f973-40a7-8066-b34706f409f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2291405839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2291405839
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3551242186
Short name T817
Test name
Test status
Simulation time 160798755 ps
CPU time 10.8 seconds
Started Aug 04 05:35:11 PM PDT 24
Finished Aug 04 05:35:22 PM PDT 24
Peak memory 247772 kb
Host smart-5bbf9fdc-72eb-460c-9ba3-faa71d1c992e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3551242186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3551242186
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3382239174
Short name T377
Test name
Test status
Simulation time 55807424 ps
CPU time 8.26 seconds
Started Aug 04 05:35:16 PM PDT 24
Finished Aug 04 05:35:25 PM PDT 24
Peak memory 256824 kb
Host smart-42f8c53c-01c8-466b-87e0-cd71c07b8177
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382239174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3382239174
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2517525809
Short name T200
Test name
Test status
Simulation time 50441080 ps
CPU time 5.19 seconds
Started Aug 04 05:35:11 PM PDT 24
Finished Aug 04 05:35:16 PM PDT 24
Peak memory 240088 kb
Host smart-a890c57a-e4f5-4247-83fb-4783adfc0eb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2517525809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2517525809
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2383725166
Short name T828
Test name
Test status
Simulation time 6166278 ps
CPU time 1.42 seconds
Started Aug 04 05:35:12 PM PDT 24
Finished Aug 04 05:35:13 PM PDT 24
Peak memory 235700 kb
Host smart-a83f2e34-1f6e-4d75-ac48-930c52420a84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2383725166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2383725166
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2650450999
Short name T183
Test name
Test status
Simulation time 658614938 ps
CPU time 37.61 seconds
Started Aug 04 05:35:10 PM PDT 24
Finished Aug 04 05:35:47 PM PDT 24
Peak memory 244968 kb
Host smart-2eb590b9-bf17-40b0-aae2-0a6b815ce99f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2650450999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2650450999
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.55030905
Short name T734
Test name
Test status
Simulation time 557704944 ps
CPU time 10.13 seconds
Started Aug 04 05:35:11 PM PDT 24
Finished Aug 04 05:35:22 PM PDT 24
Peak memory 254384 kb
Host smart-b4cece54-0354-43cc-a61c-ac59be12a57a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=55030905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.55030905
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1406970351
Short name T265
Test name
Test status
Simulation time 270212975 ps
CPU time 10.19 seconds
Started Aug 04 05:35:19 PM PDT 24
Finished Aug 04 05:35:29 PM PDT 24
Peak memory 240340 kb
Host smart-42be51bd-ae80-4dc5-a2ef-f95878329550
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406970351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1406970351
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.373613751
Short name T794
Test name
Test status
Simulation time 66215026 ps
CPU time 5.4 seconds
Started Aug 04 05:35:16 PM PDT 24
Finished Aug 04 05:35:22 PM PDT 24
Peak memory 237924 kb
Host smart-30cfa4fe-73aa-4ea7-bef2-e056142a5da8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=373613751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.373613751
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.4163394513
Short name T790
Test name
Test status
Simulation time 9113420 ps
CPU time 1.33 seconds
Started Aug 04 05:35:15 PM PDT 24
Finished Aug 04 05:35:17 PM PDT 24
Peak memory 235760 kb
Host smart-fd56ffeb-1759-4387-8ffa-ca5f3875377d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4163394513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.4163394513
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1540679775
Short name T799
Test name
Test status
Simulation time 666500863 ps
CPU time 22.08 seconds
Started Aug 04 05:35:12 PM PDT 24
Finished Aug 04 05:35:34 PM PDT 24
Peak memory 245956 kb
Host smart-461a72db-a63b-4e67-a34e-127f2a0d39dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1540679775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1540679775
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3419946661
Short name T160
Test name
Test status
Simulation time 14264447293 ps
CPU time 276.01 seconds
Started Aug 04 05:35:17 PM PDT 24
Finished Aug 04 05:39:53 PM PDT 24
Peak memory 265620 kb
Host smart-8bcce8d5-e834-48ca-92b1-79bf258523a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3419946661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3419946661
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3796907913
Short name T126
Test name
Test status
Simulation time 8864330074 ps
CPU time 321.1 seconds
Started Aug 04 05:35:14 PM PDT 24
Finished Aug 04 05:40:35 PM PDT 24
Peak memory 265852 kb
Host smart-1d9f7e5a-3f2d-4ff4-81e9-487b57e52e25
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796907913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3796907913
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3343574998
Short name T750
Test name
Test status
Simulation time 432546098 ps
CPU time 13.05 seconds
Started Aug 04 05:35:15 PM PDT 24
Finished Aug 04 05:35:28 PM PDT 24
Peak memory 248880 kb
Host smart-3cff4376-e630-4126-959f-a0ef1a67db24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3343574998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3343574998
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2441047693
Short name T800
Test name
Test status
Simulation time 420812407 ps
CPU time 8.59 seconds
Started Aug 04 05:35:12 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 256692 kb
Host smart-98cbdae2-4a87-4f0d-85ed-7f47eb1bda76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441047693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2441047693
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2799343823
Short name T786
Test name
Test status
Simulation time 115887967 ps
CPU time 5.79 seconds
Started Aug 04 05:35:19 PM PDT 24
Finished Aug 04 05:35:25 PM PDT 24
Peak memory 237720 kb
Host smart-067c39c2-b79f-4004-b00f-f1aacedc924a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2799343823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2799343823
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1832603280
Short name T725
Test name
Test status
Simulation time 14526325 ps
CPU time 1.75 seconds
Started Aug 04 05:35:16 PM PDT 24
Finished Aug 04 05:35:18 PM PDT 24
Peak memory 237052 kb
Host smart-e01d52ff-707c-408b-a5ed-c8b538fd8d92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1832603280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1832603280
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.519962556
Short name T198
Test name
Test status
Simulation time 708989593 ps
CPU time 49.74 seconds
Started Aug 04 05:35:20 PM PDT 24
Finished Aug 04 05:36:10 PM PDT 24
Peak memory 245832 kb
Host smart-cbd882dc-73d1-43cc-8eee-bdd840bcd234
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=519962556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.519962556
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.666877977
Short name T139
Test name
Test status
Simulation time 28486041230 ps
CPU time 423.67 seconds
Started Aug 04 05:35:16 PM PDT 24
Finished Aug 04 05:42:20 PM PDT 24
Peak memory 270732 kb
Host smart-d2cd3b14-b1ed-4b55-ac8d-62dac6338cf2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666877977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.666877977
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2824332456
Short name T815
Test name
Test status
Simulation time 67099084 ps
CPU time 8.2 seconds
Started Aug 04 05:35:12 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 253216 kb
Host smart-aec7224b-762c-4233-a027-536091ce8bc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2824332456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2824332456
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1598373309
Short name T748
Test name
Test status
Simulation time 97895408 ps
CPU time 7.69 seconds
Started Aug 04 05:35:15 PM PDT 24
Finished Aug 04 05:35:22 PM PDT 24
Peak memory 241208 kb
Host smart-bb9e83a9-3bd5-486f-a2af-2b3e7c05149e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598373309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1598373309
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3377757788
Short name T782
Test name
Test status
Simulation time 35615506 ps
CPU time 3.58 seconds
Started Aug 04 05:35:12 PM PDT 24
Finished Aug 04 05:35:16 PM PDT 24
Peak memory 240536 kb
Host smart-21af9e21-fc74-4972-94de-715c77a4afb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3377757788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3377757788
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2515797444
Short name T827
Test name
Test status
Simulation time 6596850 ps
CPU time 1.46 seconds
Started Aug 04 05:35:13 PM PDT 24
Finished Aug 04 05:35:15 PM PDT 24
Peak memory 237676 kb
Host smart-1a7ad7e5-3b28-49a4-9aca-1870ea392731
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2515797444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2515797444
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3899073798
Short name T760
Test name
Test status
Simulation time 171091353 ps
CPU time 12.78 seconds
Started Aug 04 05:35:19 PM PDT 24
Finished Aug 04 05:35:32 PM PDT 24
Peak memory 244940 kb
Host smart-0ad776e8-7193-41ce-8570-567de73826eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3899073798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3899073798
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1295525678
Short name T384
Test name
Test status
Simulation time 137432027163 ps
CPU time 1120.3 seconds
Started Aug 04 05:35:18 PM PDT 24
Finished Aug 04 05:53:58 PM PDT 24
Peak memory 273068 kb
Host smart-c29d7424-fce0-4ee3-9aef-a3156cb2bb00
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295525678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1295525678
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3439099569
Short name T719
Test name
Test status
Simulation time 360645665 ps
CPU time 13.56 seconds
Started Aug 04 05:35:11 PM PDT 24
Finished Aug 04 05:35:25 PM PDT 24
Peak memory 255064 kb
Host smart-c3e2f2cf-0dc2-44ab-ae5c-66275560b5e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3439099569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3439099569
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2026529731
Short name T383
Test name
Test status
Simulation time 50213790 ps
CPU time 5.04 seconds
Started Aug 04 05:35:18 PM PDT 24
Finished Aug 04 05:35:23 PM PDT 24
Peak memory 240660 kb
Host smart-6ae327ae-fe7e-4f7a-a558-6cbd09f6adf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026529731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2026529731
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.663798959
Short name T784
Test name
Test status
Simulation time 41526712 ps
CPU time 5.43 seconds
Started Aug 04 05:35:15 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 237604 kb
Host smart-2d42dfad-c1d8-4f3a-8950-afb8db4a8c6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=663798959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.663798959
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.182787683
Short name T267
Test name
Test status
Simulation time 14297828 ps
CPU time 1.63 seconds
Started Aug 04 05:35:19 PM PDT 24
Finished Aug 04 05:35:21 PM PDT 24
Peak memory 236756 kb
Host smart-21600786-fa97-466d-9067-cdf0e5410c05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=182787683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.182787683
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3837205476
Short name T798
Test name
Test status
Simulation time 93942238 ps
CPU time 13.01 seconds
Started Aug 04 05:35:14 PM PDT 24
Finished Aug 04 05:35:27 PM PDT 24
Peak memory 245804 kb
Host smart-ece8784a-ff75-45ff-811a-479109abd833
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3837205476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3837205476
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3447419113
Short name T137
Test name
Test status
Simulation time 4122350795 ps
CPU time 288.78 seconds
Started Aug 04 05:35:18 PM PDT 24
Finished Aug 04 05:40:07 PM PDT 24
Peak memory 272816 kb
Host smart-f2b17299-8ed6-45dd-8244-0fa96b9e60f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3447419113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3447419113
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1387336135
Short name T385
Test name
Test status
Simulation time 9678119737 ps
CPU time 344.35 seconds
Started Aug 04 05:35:19 PM PDT 24
Finished Aug 04 05:41:03 PM PDT 24
Peak memory 265544 kb
Host smart-07e79597-17a6-4415-a9de-0cb49f7c13ca
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387336135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1387336135
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2363695875
Short name T765
Test name
Test status
Simulation time 490232064 ps
CPU time 15.66 seconds
Started Aug 04 05:35:18 PM PDT 24
Finished Aug 04 05:35:34 PM PDT 24
Peak memory 254644 kb
Host smart-a6fb8315-951d-4310-9404-0d7069e54fab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2363695875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2363695875
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.178179334
Short name T814
Test name
Test status
Simulation time 32551454 ps
CPU time 2.72 seconds
Started Aug 04 05:35:11 PM PDT 24
Finished Aug 04 05:35:14 PM PDT 24
Peak memory 236800 kb
Host smart-da367d5d-c930-4d97-8384-1b54c4234d50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=178179334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.178179334
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1926379115
Short name T764
Test name
Test status
Simulation time 325789965 ps
CPU time 10.61 seconds
Started Aug 04 05:35:18 PM PDT 24
Finished Aug 04 05:35:28 PM PDT 24
Peak memory 253080 kb
Host smart-70140e31-74fd-4620-b437-8c5e39746887
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926379115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1926379115
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1816336300
Short name T775
Test name
Test status
Simulation time 50039471 ps
CPU time 4.68 seconds
Started Aug 04 05:35:18 PM PDT 24
Finished Aug 04 05:35:22 PM PDT 24
Peak memory 236808 kb
Host smart-af4146b5-eb1f-4628-9d5f-eba6b0cec8d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1816336300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1816336300
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.941244116
Short name T736
Test name
Test status
Simulation time 33533074 ps
CPU time 1.33 seconds
Started Aug 04 05:35:16 PM PDT 24
Finished Aug 04 05:35:18 PM PDT 24
Peak memory 237600 kb
Host smart-52bea79a-7ad3-4e8a-b157-c018dd4abdca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=941244116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.941244116
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4246287404
Short name T201
Test name
Test status
Simulation time 885985022 ps
CPU time 11.83 seconds
Started Aug 04 05:35:25 PM PDT 24
Finished Aug 04 05:35:37 PM PDT 24
Peak memory 245748 kb
Host smart-166498da-8a4d-4103-b882-88a8b951cc8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4246287404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.4246287404
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.967469010
Short name T136
Test name
Test status
Simulation time 4845896551 ps
CPU time 662.56 seconds
Started Aug 04 05:35:11 PM PDT 24
Finished Aug 04 05:46:14 PM PDT 24
Peak memory 265572 kb
Host smart-74b2e394-e1b0-4af9-b6ee-924a485f6498
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967469010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.967469010
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3607279323
Short name T755
Test name
Test status
Simulation time 285548674 ps
CPU time 8.77 seconds
Started Aug 04 05:35:17 PM PDT 24
Finished Aug 04 05:35:25 PM PDT 24
Peak memory 248892 kb
Host smart-1843dc96-8c31-497c-86d8-3552dda3c314
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3607279323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3607279323
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.4073866015
Short name T264
Test name
Test status
Simulation time 12782646265 ps
CPU time 115.41 seconds
Started Aug 04 05:34:46 PM PDT 24
Finished Aug 04 05:36:41 PM PDT 24
Peak memory 240768 kb
Host smart-960b4202-5bee-4624-9a14-5db6ab8406a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4073866015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.4073866015
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.226939610
Short name T737
Test name
Test status
Simulation time 81496412828 ps
CPU time 384.57 seconds
Started Aug 04 05:34:47 PM PDT 24
Finished Aug 04 05:41:11 PM PDT 24
Peak memory 237700 kb
Host smart-083711a0-5d15-40c4-b37a-9856528fc288
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=226939610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.226939610
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1237873327
Short name T802
Test name
Test status
Simulation time 296688622 ps
CPU time 10.76 seconds
Started Aug 04 05:34:53 PM PDT 24
Finished Aug 04 05:35:04 PM PDT 24
Peak memory 249316 kb
Host smart-eee87852-3dbb-4dfd-91c2-988eac37eb43
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1237873327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1237873327
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.667869621
Short name T756
Test name
Test status
Simulation time 147891540 ps
CPU time 4.36 seconds
Started Aug 04 05:34:51 PM PDT 24
Finished Aug 04 05:34:55 PM PDT 24
Peak memory 239620 kb
Host smart-615dee3a-26cb-420c-9fe4-98205b3cb6db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667869621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.alert_handler_csr_mem_rw_with_rand_reset.667869621
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.4210631890
Short name T818
Test name
Test status
Simulation time 173814581 ps
CPU time 3.28 seconds
Started Aug 04 05:34:47 PM PDT 24
Finished Aug 04 05:34:50 PM PDT 24
Peak memory 236684 kb
Host smart-b302f125-f658-42aa-abe8-9c94d4e41de4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4210631890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.4210631890
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3886162262
Short name T812
Test name
Test status
Simulation time 16573916 ps
CPU time 1.53 seconds
Started Aug 04 05:34:52 PM PDT 24
Finished Aug 04 05:34:53 PM PDT 24
Peak memory 236724 kb
Host smart-430ecef0-5330-4ccc-95e9-18c0936c3e81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3886162262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3886162262
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2063336039
Short name T769
Test name
Test status
Simulation time 1874416595 ps
CPU time 21.84 seconds
Started Aug 04 05:34:48 PM PDT 24
Finished Aug 04 05:35:09 PM PDT 24
Peak memory 245020 kb
Host smart-6dda6c7f-cee3-4c0c-af6c-9685cae5d544
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2063336039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2063336039
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.4084020588
Short name T129
Test name
Test status
Simulation time 5875275270 ps
CPU time 477.88 seconds
Started Aug 04 05:34:46 PM PDT 24
Finished Aug 04 05:42:44 PM PDT 24
Peak memory 265668 kb
Host smart-e713f5af-cc74-4618-a8f3-d9e16d928286
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084020588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.4084020588
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1379034072
Short name T744
Test name
Test status
Simulation time 221048451 ps
CPU time 12.52 seconds
Started Aug 04 05:34:48 PM PDT 24
Finished Aug 04 05:35:00 PM PDT 24
Peak memory 254480 kb
Host smart-8b2d0454-3416-46cf-b6ea-94490d7942f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1379034072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1379034072
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1584241676
Short name T371
Test name
Test status
Simulation time 40903698 ps
CPU time 1.4 seconds
Started Aug 04 05:35:24 PM PDT 24
Finished Aug 04 05:35:25 PM PDT 24
Peak memory 237732 kb
Host smart-f1b1d937-227d-4665-ade5-74fa70831e02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1584241676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1584241676
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1580495503
Short name T164
Test name
Test status
Simulation time 7348412 ps
CPU time 1.47 seconds
Started Aug 04 05:35:17 PM PDT 24
Finished Aug 04 05:35:18 PM PDT 24
Peak memory 236788 kb
Host smart-5b8593f3-2ce7-486f-a4ff-1368a2860ac9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1580495503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1580495503
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2045012045
Short name T819
Test name
Test status
Simulation time 11751464 ps
CPU time 1.3 seconds
Started Aug 04 05:35:14 PM PDT 24
Finished Aug 04 05:35:16 PM PDT 24
Peak memory 236752 kb
Host smart-8a387c15-9e77-4bf1-82e0-dade95896586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2045012045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2045012045
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3905475343
Short name T808
Test name
Test status
Simulation time 9453158 ps
CPU time 1.28 seconds
Started Aug 04 05:35:17 PM PDT 24
Finished Aug 04 05:35:19 PM PDT 24
Peak memory 235804 kb
Host smart-40702c00-8f98-4507-9790-788a3ca54f58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3905475343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3905475343
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.117176981
Short name T778
Test name
Test status
Simulation time 13187064 ps
CPU time 1.46 seconds
Started Aug 04 05:35:16 PM PDT 24
Finished Aug 04 05:35:18 PM PDT 24
Peak memory 237716 kb
Host smart-cfd72057-a469-47ba-b452-3505ff46d359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=117176981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.117176981
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3580797970
Short name T795
Test name
Test status
Simulation time 9208273 ps
CPU time 1.53 seconds
Started Aug 04 05:35:14 PM PDT 24
Finished Aug 04 05:35:16 PM PDT 24
Peak memory 236844 kb
Host smart-d5d2ee03-f8c1-42d9-bb7a-c91d6486a5a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3580797970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3580797970
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2310755165
Short name T789
Test name
Test status
Simulation time 25308093 ps
CPU time 1.5 seconds
Started Aug 04 05:35:23 PM PDT 24
Finished Aug 04 05:35:25 PM PDT 24
Peak memory 236788 kb
Host smart-e63abb62-41cf-4ceb-80e8-024fc0848596
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2310755165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2310755165
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.102289728
Short name T823
Test name
Test status
Simulation time 25887422 ps
CPU time 1.31 seconds
Started Aug 04 05:35:15 PM PDT 24
Finished Aug 04 05:35:16 PM PDT 24
Peak memory 237704 kb
Host smart-af3d26ea-1e26-4f3a-8010-a77ff9202c47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=102289728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.102289728
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.690820939
Short name T826
Test name
Test status
Simulation time 21851774 ps
CPU time 1.41 seconds
Started Aug 04 05:35:18 PM PDT 24
Finished Aug 04 05:35:19 PM PDT 24
Peak memory 237704 kb
Host smart-4a5013aa-2fd7-4615-b58b-a6197e412837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=690820939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.690820939
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3845127644
Short name T370
Test name
Test status
Simulation time 6427342 ps
CPU time 1.37 seconds
Started Aug 04 05:35:17 PM PDT 24
Finished Aug 04 05:35:18 PM PDT 24
Peak memory 237616 kb
Host smart-705acbf3-8d03-4df6-9b8b-3a332cc33a74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3845127644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3845127644
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2158655337
Short name T732
Test name
Test status
Simulation time 3323573296 ps
CPU time 252.87 seconds
Started Aug 04 05:34:53 PM PDT 24
Finished Aug 04 05:39:06 PM PDT 24
Peak memory 239352 kb
Host smart-5e275859-0436-414a-a8e9-f115299dd066
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2158655337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2158655337
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.853643729
Short name T757
Test name
Test status
Simulation time 3334887358 ps
CPU time 214.76 seconds
Started Aug 04 05:34:50 PM PDT 24
Finished Aug 04 05:38:25 PM PDT 24
Peak memory 237724 kb
Host smart-37e90e7a-dd7a-474a-9d24-f1dc9c44738d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=853643729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.853643729
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1302450353
Short name T792
Test name
Test status
Simulation time 53275226 ps
CPU time 5.28 seconds
Started Aug 04 05:34:53 PM PDT 24
Finished Aug 04 05:34:58 PM PDT 24
Peak memory 248844 kb
Host smart-573edb9c-d709-48e4-8925-eb063eebe2d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1302450353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1302450353
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3642415938
Short name T379
Test name
Test status
Simulation time 156698432 ps
CPU time 6.73 seconds
Started Aug 04 05:34:53 PM PDT 24
Finished Aug 04 05:35:00 PM PDT 24
Peak memory 241068 kb
Host smart-dcf594f0-2816-46f6-bebf-312a2d751ef7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642415938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3642415938
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.4182166580
Short name T728
Test name
Test status
Simulation time 232247933 ps
CPU time 6.12 seconds
Started Aug 04 05:34:54 PM PDT 24
Finished Aug 04 05:35:00 PM PDT 24
Peak memory 240844 kb
Host smart-30d511ca-d269-4ca6-997c-027db47f0183
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4182166580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.4182166580
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2464159285
Short name T768
Test name
Test status
Simulation time 12899561 ps
CPU time 1.45 seconds
Started Aug 04 05:34:50 PM PDT 24
Finished Aug 04 05:34:52 PM PDT 24
Peak memory 237740 kb
Host smart-338c2328-c775-4b78-8690-d3675904a176
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2464159285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2464159285
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2487757565
Short name T752
Test name
Test status
Simulation time 2387458893 ps
CPU time 21.17 seconds
Started Aug 04 05:34:53 PM PDT 24
Finished Aug 04 05:35:14 PM PDT 24
Peak memory 245980 kb
Host smart-c1df24dc-036c-43f8-966f-6a56012774d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2487757565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2487757565
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1288498647
Short name T141
Test name
Test status
Simulation time 5262734624 ps
CPU time 348.81 seconds
Started Aug 04 05:34:50 PM PDT 24
Finished Aug 04 05:40:39 PM PDT 24
Peak memory 265108 kb
Host smart-25820d3c-bf2d-4f49-b416-b7b592eed691
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1288498647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1288498647
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3856739832
Short name T723
Test name
Test status
Simulation time 145490910 ps
CPU time 6.27 seconds
Started Aug 04 05:34:48 PM PDT 24
Finished Aug 04 05:34:54 PM PDT 24
Peak memory 254640 kb
Host smart-927c19e4-a38c-43f8-b00c-a3a1215c10eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3856739832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3856739832
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2460967092
Short name T730
Test name
Test status
Simulation time 9182097 ps
CPU time 1.59 seconds
Started Aug 04 05:35:16 PM PDT 24
Finished Aug 04 05:35:18 PM PDT 24
Peak memory 237700 kb
Host smart-26d697b2-4e9e-4089-9b5e-02a5b3a34c80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2460967092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2460967092
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1420780956
Short name T369
Test name
Test status
Simulation time 18945323 ps
CPU time 1.42 seconds
Started Aug 04 05:35:17 PM PDT 24
Finished Aug 04 05:35:18 PM PDT 24
Peak memory 236804 kb
Host smart-92b71aea-f5b4-4128-8a05-7e9e87a9352c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1420780956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1420780956
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3969942584
Short name T801
Test name
Test status
Simulation time 8199189 ps
CPU time 1.21 seconds
Started Aug 04 05:35:17 PM PDT 24
Finished Aug 04 05:35:18 PM PDT 24
Peak memory 236700 kb
Host smart-ef4208eb-3430-429d-990e-e9629ced72e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3969942584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3969942584
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.998251058
Short name T165
Test name
Test status
Simulation time 15263798 ps
CPU time 1.41 seconds
Started Aug 04 05:35:28 PM PDT 24
Finished Aug 04 05:35:29 PM PDT 24
Peak memory 235764 kb
Host smart-d8eb71b9-591b-4c55-a321-2ddfbe3f3dc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=998251058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.998251058
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3065271124
Short name T767
Test name
Test status
Simulation time 6424605 ps
CPU time 1.46 seconds
Started Aug 04 05:35:18 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 237700 kb
Host smart-22c1f27d-ebd9-4a40-859e-f116847d9bee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3065271124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3065271124
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1312188702
Short name T731
Test name
Test status
Simulation time 8104012 ps
CPU time 1.43 seconds
Started Aug 04 05:35:20 PM PDT 24
Finished Aug 04 05:35:22 PM PDT 24
Peak memory 237596 kb
Host smart-17ff5e31-e016-452a-b05f-1b0c280cac79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1312188702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1312188702
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1582025093
Short name T722
Test name
Test status
Simulation time 13733005 ps
CPU time 1.25 seconds
Started Aug 04 05:35:20 PM PDT 24
Finished Aug 04 05:35:22 PM PDT 24
Peak memory 236716 kb
Host smart-4a20a8ad-1185-44bc-b5f1-f694036e2cf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1582025093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1582025093
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1319288783
Short name T811
Test name
Test status
Simulation time 6415478 ps
CPU time 1.42 seconds
Started Aug 04 05:35:18 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 237708 kb
Host smart-4094e685-ceea-4d11-9870-48afd5720462
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1319288783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1319288783
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2296414139
Short name T803
Test name
Test status
Simulation time 8000819 ps
CPU time 1.26 seconds
Started Aug 04 05:35:17 PM PDT 24
Finished Aug 04 05:35:19 PM PDT 24
Peak memory 235700 kb
Host smart-65f395b8-8304-47d7-89e6-e7f82b8516fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2296414139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2296414139
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.4159589548
Short name T204
Test name
Test status
Simulation time 47238509123 ps
CPU time 336.14 seconds
Started Aug 04 05:34:57 PM PDT 24
Finished Aug 04 05:40:33 PM PDT 24
Peak memory 240764 kb
Host smart-201423fe-c980-45aa-bbce-179fac177057
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4159589548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.4159589548
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3333915853
Short name T761
Test name
Test status
Simulation time 21374836921 ps
CPU time 271.37 seconds
Started Aug 04 05:34:53 PM PDT 24
Finished Aug 04 05:39:24 PM PDT 24
Peak memory 237824 kb
Host smart-f980df73-0a72-478f-adfc-1b76faaa3866
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3333915853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3333915853
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2959998095
Short name T740
Test name
Test status
Simulation time 39092206 ps
CPU time 5.93 seconds
Started Aug 04 05:34:54 PM PDT 24
Finished Aug 04 05:35:00 PM PDT 24
Peak memory 249244 kb
Host smart-4a20e33a-9fc1-49f8-9c92-edc96f8a7e28
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2959998095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2959998095
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2326507431
Short name T376
Test name
Test status
Simulation time 122123284 ps
CPU time 4.92 seconds
Started Aug 04 05:34:56 PM PDT 24
Finished Aug 04 05:35:01 PM PDT 24
Peak memory 241296 kb
Host smart-5b9e38ab-b095-4aab-9d63-919d9d5f82a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326507431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2326507431
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1479874026
Short name T378
Test name
Test status
Simulation time 1982864243 ps
CPU time 8.98 seconds
Started Aug 04 05:34:57 PM PDT 24
Finished Aug 04 05:35:06 PM PDT 24
Peak memory 240644 kb
Host smart-6cb9faf8-0807-4440-8dc4-2f91bbf7f487
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1479874026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1479874026
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.505896531
Short name T735
Test name
Test status
Simulation time 14772243 ps
CPU time 1.33 seconds
Started Aug 04 05:34:56 PM PDT 24
Finished Aug 04 05:34:57 PM PDT 24
Peak memory 237716 kb
Host smart-a4711629-82b5-4fb1-be8d-3ce5823abfb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=505896531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.505896531
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2051504879
Short name T182
Test name
Test status
Simulation time 1352153264 ps
CPU time 27.46 seconds
Started Aug 04 05:34:53 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 245872 kb
Host smart-32bb49fb-9126-4fdb-9759-82f969b16bc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2051504879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2051504879
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2249467871
Short name T151
Test name
Test status
Simulation time 9090183823 ps
CPU time 400.33 seconds
Started Aug 04 05:34:54 PM PDT 24
Finished Aug 04 05:41:34 PM PDT 24
Peak memory 265784 kb
Host smart-3865f20b-dfc5-4113-bbb3-d5973a9ad64d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2249467871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2249467871
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.244502534
Short name T147
Test name
Test status
Simulation time 14581750877 ps
CPU time 647.48 seconds
Started Aug 04 05:34:51 PM PDT 24
Finished Aug 04 05:45:38 PM PDT 24
Peak memory 265672 kb
Host smart-2c5defcd-10bd-4a5f-9010-ceb8ac34043e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244502534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.244502534
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1814927594
Short name T721
Test name
Test status
Simulation time 97359383 ps
CPU time 7.81 seconds
Started Aug 04 05:34:51 PM PDT 24
Finished Aug 04 05:34:59 PM PDT 24
Peak memory 252996 kb
Host smart-d9656bc5-7af1-472c-9272-8734c0d573fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1814927594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1814927594
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.4219744810
Short name T375
Test name
Test status
Simulation time 11464387 ps
CPU time 1.66 seconds
Started Aug 04 05:35:18 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 237700 kb
Host smart-43f5f449-7e9a-4bf6-9e22-e2ed073d692d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4219744810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.4219744810
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2213348963
Short name T829
Test name
Test status
Simulation time 10109607 ps
CPU time 1.58 seconds
Started Aug 04 05:35:18 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 236812 kb
Host smart-a5146762-4950-4f02-8521-3538a4ebe78a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2213348963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2213348963
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3799738565
Short name T749
Test name
Test status
Simulation time 14951661 ps
CPU time 1.49 seconds
Started Aug 04 05:35:15 PM PDT 24
Finished Aug 04 05:35:16 PM PDT 24
Peak memory 237716 kb
Host smart-3b43d20f-7859-4089-b36d-f018f306e7ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3799738565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3799738565
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1217287094
Short name T821
Test name
Test status
Simulation time 7863746 ps
CPU time 1.5 seconds
Started Aug 04 05:35:25 PM PDT 24
Finished Aug 04 05:35:27 PM PDT 24
Peak memory 235968 kb
Host smart-684ab103-07c7-42c9-b03b-52494802faf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1217287094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1217287094
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1134270300
Short name T733
Test name
Test status
Simulation time 11150728 ps
CPU time 1.44 seconds
Started Aug 04 05:35:15 PM PDT 24
Finished Aug 04 05:35:17 PM PDT 24
Peak memory 236788 kb
Host smart-31b07ef9-e7f0-4cbd-b3cd-972fde63e05b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1134270300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1134270300
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2032504306
Short name T813
Test name
Test status
Simulation time 38245523 ps
CPU time 2.45 seconds
Started Aug 04 05:35:23 PM PDT 24
Finished Aug 04 05:35:25 PM PDT 24
Peak memory 237732 kb
Host smart-64fbafe9-d381-4048-b6af-40cfd0f2de5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2032504306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2032504306
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.427801180
Short name T787
Test name
Test status
Simulation time 10176828 ps
CPU time 1.67 seconds
Started Aug 04 05:35:19 PM PDT 24
Finished Aug 04 05:35:21 PM PDT 24
Peak memory 237732 kb
Host smart-f535da69-9452-4845-af32-7def80ac1801
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=427801180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.427801180
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3924038517
Short name T166
Test name
Test status
Simulation time 10377536 ps
CPU time 1.28 seconds
Started Aug 04 05:35:17 PM PDT 24
Finished Aug 04 05:35:19 PM PDT 24
Peak memory 237704 kb
Host smart-26921ede-d96f-4210-916c-8437eb897000
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3924038517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3924038517
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.4170374751
Short name T763
Test name
Test status
Simulation time 18372355 ps
CPU time 1.66 seconds
Started Aug 04 05:35:20 PM PDT 24
Finished Aug 04 05:35:21 PM PDT 24
Peak memory 237632 kb
Host smart-b45795eb-5eac-428d-9f74-eb89e0dd4768
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4170374751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.4170374751
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.166208012
Short name T751
Test name
Test status
Simulation time 207484684 ps
CPU time 4.54 seconds
Started Aug 04 05:34:59 PM PDT 24
Finished Aug 04 05:35:04 PM PDT 24
Peak memory 237876 kb
Host smart-6d4f44d1-18ed-4822-9764-7b36c9a4082b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166208012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.166208012
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2430693685
Short name T199
Test name
Test status
Simulation time 142060856 ps
CPU time 5.31 seconds
Started Aug 04 05:34:55 PM PDT 24
Finished Aug 04 05:35:01 PM PDT 24
Peak memory 240628 kb
Host smart-06ddb4b0-32ab-4ccb-88f8-3487ac8f2e50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2430693685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2430693685
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3884275887
Short name T783
Test name
Test status
Simulation time 8396408 ps
CPU time 1.37 seconds
Started Aug 04 05:34:55 PM PDT 24
Finished Aug 04 05:34:57 PM PDT 24
Peak memory 236728 kb
Host smart-a21ed9bd-50b9-47bd-8a87-63356e179f5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3884275887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3884275887
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.646133627
Short name T785
Test name
Test status
Simulation time 168946659 ps
CPU time 24.7 seconds
Started Aug 04 05:34:55 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 245028 kb
Host smart-c47626e8-c717-488a-bdb8-f384dcac8b29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=646133627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.646133627
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.557090193
Short name T807
Test name
Test status
Simulation time 259956849 ps
CPU time 8.26 seconds
Started Aug 04 05:34:54 PM PDT 24
Finished Aug 04 05:35:02 PM PDT 24
Peak memory 248140 kb
Host smart-04cb0a87-cfb2-419d-abc7-cd10f4219f66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=557090193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.557090193
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.4070212372
Short name T739
Test name
Test status
Simulation time 266676066 ps
CPU time 12.05 seconds
Started Aug 04 05:35:00 PM PDT 24
Finished Aug 04 05:35:12 PM PDT 24
Peak memory 253192 kb
Host smart-bf7fd5b0-d33f-40c7-a197-593eb70eb68a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070212372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.4070212372
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3071869841
Short name T779
Test name
Test status
Simulation time 59029068 ps
CPU time 5.31 seconds
Started Aug 04 05:34:58 PM PDT 24
Finished Aug 04 05:35:03 PM PDT 24
Peak memory 240612 kb
Host smart-682aaf9e-1a1e-4339-8179-0d0a5e12a53c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3071869841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3071869841
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1253917248
Short name T758
Test name
Test status
Simulation time 12370698 ps
CPU time 1.55 seconds
Started Aug 04 05:35:03 PM PDT 24
Finished Aug 04 05:35:04 PM PDT 24
Peak memory 237640 kb
Host smart-5b6e6ab2-d3a9-43f4-b165-78955438c920
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1253917248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1253917248
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1445503171
Short name T788
Test name
Test status
Simulation time 2975630398 ps
CPU time 51.4 seconds
Started Aug 04 05:34:57 PM PDT 24
Finished Aug 04 05:35:49 PM PDT 24
Peak memory 248916 kb
Host smart-7a0bdbb1-015b-4c92-b1d6-4c1e6c03897d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1445503171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1445503171
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3829279416
Short name T131
Test name
Test status
Simulation time 16046422081 ps
CPU time 294.67 seconds
Started Aug 04 05:34:57 PM PDT 24
Finished Aug 04 05:39:52 PM PDT 24
Peak memory 271844 kb
Host smart-2da8dbd9-d817-4909-9fb0-7a59fb1d2952
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3829279416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3829279416
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2151397256
Short name T154
Test name
Test status
Simulation time 49978676427 ps
CPU time 996.94 seconds
Started Aug 04 05:35:00 PM PDT 24
Finished Aug 04 05:51:38 PM PDT 24
Peak memory 265692 kb
Host smart-186a4ada-76d9-4187-995a-320f5cc22a72
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151397256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2151397256
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.42312628
Short name T820
Test name
Test status
Simulation time 48741517 ps
CPU time 6.8 seconds
Started Aug 04 05:34:58 PM PDT 24
Finished Aug 04 05:35:05 PM PDT 24
Peak memory 252672 kb
Host smart-e2390eff-41c1-4344-8360-9cac1fcbd424
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=42312628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.42312628
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.338607206
Short name T262
Test name
Test status
Simulation time 122018527 ps
CPU time 9.1 seconds
Started Aug 04 05:35:03 PM PDT 24
Finished Aug 04 05:35:13 PM PDT 24
Peak memory 240712 kb
Host smart-3971f466-5826-4790-b15a-4347edb6bbf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338607206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.338607206
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2289452935
Short name T770
Test name
Test status
Simulation time 1120761431 ps
CPU time 7.87 seconds
Started Aug 04 05:35:02 PM PDT 24
Finished Aug 04 05:35:10 PM PDT 24
Peak memory 237664 kb
Host smart-d8a1b2db-a35e-4dce-b8af-8a001c7eac9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2289452935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2289452935
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.714492868
Short name T806
Test name
Test status
Simulation time 17213369 ps
CPU time 1.29 seconds
Started Aug 04 05:34:57 PM PDT 24
Finished Aug 04 05:34:58 PM PDT 24
Peak memory 236852 kb
Host smart-efd8fea5-6dcd-4440-9e10-e89cfdc0f286
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=714492868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.714492868
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.716197384
Short name T810
Test name
Test status
Simulation time 315755519 ps
CPU time 20.04 seconds
Started Aug 04 05:35:01 PM PDT 24
Finished Aug 04 05:35:22 PM PDT 24
Peak memory 244892 kb
Host smart-c2341b5e-3181-43d9-acf5-4e95d96325ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=716197384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.716197384
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3731542762
Short name T777
Test name
Test status
Simulation time 11457918116 ps
CPU time 169.76 seconds
Started Aug 04 05:34:59 PM PDT 24
Finished Aug 04 05:37:48 PM PDT 24
Peak memory 265648 kb
Host smart-32d263b2-4ff9-4bd3-82ce-df096581a88e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3731542762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3731542762
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1340127301
Short name T152
Test name
Test status
Simulation time 12369938987 ps
CPU time 484.79 seconds
Started Aug 04 05:34:58 PM PDT 24
Finished Aug 04 05:43:03 PM PDT 24
Peak memory 265800 kb
Host smart-12fe6144-e2fa-4502-9293-d06ede0b0d38
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340127301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1340127301
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1075863689
Short name T791
Test name
Test status
Simulation time 290061636 ps
CPU time 18.16 seconds
Started Aug 04 05:35:02 PM PDT 24
Finished Aug 04 05:35:21 PM PDT 24
Peak memory 253372 kb
Host smart-fd41122d-abb5-4e47-ad9d-572327741e3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1075863689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1075863689
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3701301797
Short name T772
Test name
Test status
Simulation time 562301902 ps
CPU time 12.33 seconds
Started Aug 04 05:35:07 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 251948 kb
Host smart-c23608b2-b209-4ee5-82c8-ead200d05a53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701301797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3701301797
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.743248806
Short name T373
Test name
Test status
Simulation time 8292889 ps
CPU time 1.4 seconds
Started Aug 04 05:35:08 PM PDT 24
Finished Aug 04 05:35:09 PM PDT 24
Peak memory 236784 kb
Host smart-226391bc-835f-4a88-9441-1929d05b6858
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=743248806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.743248806
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1869277005
Short name T729
Test name
Test status
Simulation time 553595939 ps
CPU time 37.07 seconds
Started Aug 04 05:35:01 PM PDT 24
Finished Aug 04 05:35:39 PM PDT 24
Peak memory 245024 kb
Host smart-dc9c915f-983e-4cd0-bbf4-e4fb0ea4c115
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1869277005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1869277005
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.58545456
Short name T140
Test name
Test status
Simulation time 3850604076 ps
CPU time 147.61 seconds
Started Aug 04 05:35:04 PM PDT 24
Finished Aug 04 05:37:31 PM PDT 24
Peak memory 265576 kb
Host smart-12b1350a-5510-4971-8f05-d9fb15327b77
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=58545456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors
.58545456
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1120774634
Short name T156
Test name
Test status
Simulation time 13948718452 ps
CPU time 978.97 seconds
Started Aug 04 05:35:07 PM PDT 24
Finished Aug 04 05:51:26 PM PDT 24
Peak memory 265604 kb
Host smart-5f5ea505-2762-42d9-8d25-ab4d00d38ca7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120774634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1120774634
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3835797408
Short name T720
Test name
Test status
Simulation time 369233206 ps
CPU time 12.75 seconds
Started Aug 04 05:35:02 PM PDT 24
Finished Aug 04 05:35:15 PM PDT 24
Peak memory 249900 kb
Host smart-ac1d88ab-46f8-4290-9db1-40f11ae69ad2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3835797408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3835797408
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2287685963
Short name T754
Test name
Test status
Simulation time 343034419 ps
CPU time 8.17 seconds
Started Aug 04 05:35:04 PM PDT 24
Finished Aug 04 05:35:12 PM PDT 24
Peak memory 238764 kb
Host smart-e7da85a6-4bda-4b2a-995a-9169a1bb1831
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287685963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2287685963
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2037870109
Short name T742
Test name
Test status
Simulation time 181306289 ps
CPU time 4.64 seconds
Started Aug 04 05:35:02 PM PDT 24
Finished Aug 04 05:35:07 PM PDT 24
Peak memory 237700 kb
Host smart-19dac9ed-8b7c-4af7-9104-237390c1bcb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2037870109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2037870109
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2488167752
Short name T762
Test name
Test status
Simulation time 8779913 ps
CPU time 1.54 seconds
Started Aug 04 05:35:03 PM PDT 24
Finished Aug 04 05:35:04 PM PDT 24
Peak memory 236728 kb
Host smart-e56b8c01-2fb5-4479-886d-86d787c0fae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2488167752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2488167752
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1855085400
Short name T825
Test name
Test status
Simulation time 782158064 ps
CPU time 20.9 seconds
Started Aug 04 05:35:03 PM PDT 24
Finished Aug 04 05:35:24 PM PDT 24
Peak memory 245792 kb
Host smart-72c328bd-22df-4181-8e52-2ad70ee1130c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1855085400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1855085400
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1290380145
Short name T759
Test name
Test status
Simulation time 77294840 ps
CPU time 6.02 seconds
Started Aug 04 05:35:02 PM PDT 24
Finished Aug 04 05:35:09 PM PDT 24
Peak memory 248888 kb
Host smart-7f6b7259-0155-443e-a0b1-a348f7ad6a83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1290380145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1290380145
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3629284367
Short name T173
Test name
Test status
Simulation time 606743335 ps
CPU time 22.38 seconds
Started Aug 04 05:35:00 PM PDT 24
Finished Aug 04 05:35:23 PM PDT 24
Peak memory 240636 kb
Host smart-0d972b8c-dfc9-4ba7-9b83-4d1942353242
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3629284367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3629284367
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3962242969
Short name T497
Test name
Test status
Simulation time 1420151596 ps
CPU time 7.6 seconds
Started Aug 04 04:42:31 PM PDT 24
Finished Aug 04 04:42:39 PM PDT 24
Peak memory 248208 kb
Host smart-9396a4a0-208e-449c-8a7a-51880d655333
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3962242969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3962242969
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2156622839
Short name T270
Test name
Test status
Simulation time 4301611273 ps
CPU time 229.78 seconds
Started Aug 04 04:42:30 PM PDT 24
Finished Aug 04 04:46:20 PM PDT 24
Peak memory 255640 kb
Host smart-a66550c6-9e67-483d-9a11-760d560a8c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21566
22839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2156622839
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1272671209
Short name T87
Test name
Test status
Simulation time 1126318784 ps
CPU time 35.06 seconds
Started Aug 04 04:42:32 PM PDT 24
Finished Aug 04 04:43:07 PM PDT 24
Peak memory 248192 kb
Host smart-b894469a-5078-465c-9330-7cc91d88df55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12726
71209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1272671209
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2877136253
Short name T367
Test name
Test status
Simulation time 27694310497 ps
CPU time 1657.99 seconds
Started Aug 04 04:42:33 PM PDT 24
Finished Aug 04 05:10:11 PM PDT 24
Peak memory 282472 kb
Host smart-846d21b3-9814-42b8-9303-7e17a226a2ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877136253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2877136253
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3252173489
Short name T505
Test name
Test status
Simulation time 22888714898 ps
CPU time 1446.46 seconds
Started Aug 04 04:42:34 PM PDT 24
Finished Aug 04 05:06:41 PM PDT 24
Peak memory 269740 kb
Host smart-76eae1f1-02bc-4e6d-a7dc-4d17b4f6f5b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252173489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3252173489
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.4072235336
Short name T713
Test name
Test status
Simulation time 397780906 ps
CPU time 37.27 seconds
Started Aug 04 04:42:31 PM PDT 24
Finished Aug 04 04:43:09 PM PDT 24
Peak memory 248284 kb
Host smart-c1ba2aad-a113-49b9-9655-0ffba492673e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40722
35336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.4072235336
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3022853295
Short name T45
Test name
Test status
Simulation time 6381326382 ps
CPU time 70.26 seconds
Started Aug 04 04:42:32 PM PDT 24
Finished Aug 04 04:43:43 PM PDT 24
Peak memory 248352 kb
Host smart-91f9a37c-2e2a-49a1-a31a-26ed8f0488da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30228
53295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3022853295
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2185859412
Short name T38
Test name
Test status
Simulation time 457321554 ps
CPU time 13.67 seconds
Started Aug 04 04:42:35 PM PDT 24
Finished Aug 04 04:42:48 PM PDT 24
Peak memory 273740 kb
Host smart-5b97e716-c43d-4941-b8aa-b9a98dbfc583
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2185859412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2185859412
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.312886270
Short name T661
Test name
Test status
Simulation time 36109105 ps
CPU time 4.87 seconds
Started Aug 04 04:42:30 PM PDT 24
Finished Aug 04 04:42:35 PM PDT 24
Peak memory 240032 kb
Host smart-0feac413-d94a-4d1b-b024-bed0606ce349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31288
6270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.312886270
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2787746789
Short name T658
Test name
Test status
Simulation time 122296501 ps
CPU time 7.42 seconds
Started Aug 04 04:42:29 PM PDT 24
Finished Aug 04 04:42:36 PM PDT 24
Peak memory 253440 kb
Host smart-d2664595-a14a-4d7c-81bd-9b366d9dbb72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27877
46789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2787746789
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.767495076
Short name T536
Test name
Test status
Simulation time 10935270091 ps
CPU time 985.5 seconds
Started Aug 04 04:42:34 PM PDT 24
Finished Aug 04 04:59:00 PM PDT 24
Peak memory 285864 kb
Host smart-3fb94bf5-df92-4b3b-8e17-0604ebcafc2d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767495076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.767495076
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.3868576406
Short name T56
Test name
Test status
Simulation time 338701303145 ps
CPU time 7097.52 seconds
Started Aug 04 04:42:39 PM PDT 24
Finished Aug 04 06:40:58 PM PDT 24
Peak memory 393608 kb
Host smart-0aeced7f-bf69-4338-988e-395ded201ec5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868576406 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.3868576406
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.709927323
Short name T559
Test name
Test status
Simulation time 15016583012 ps
CPU time 1398.85 seconds
Started Aug 04 04:42:38 PM PDT 24
Finished Aug 04 05:05:57 PM PDT 24
Peak memory 288920 kb
Host smart-62e73dd5-2cab-47a6-a727-cf65920b7c3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709927323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.709927323
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2467417849
Short name T44
Test name
Test status
Simulation time 6223912186 ps
CPU time 36.41 seconds
Started Aug 04 04:42:42 PM PDT 24
Finished Aug 04 04:43:18 PM PDT 24
Peak memory 248272 kb
Host smart-eeb10d64-5819-4b80-8cb9-67b1f0fc0343
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2467417849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2467417849
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1985072231
Short name T442
Test name
Test status
Simulation time 1915168405 ps
CPU time 134.91 seconds
Started Aug 04 04:42:34 PM PDT 24
Finished Aug 04 04:44:49 PM PDT 24
Peak memory 251652 kb
Host smart-a9deb186-3e35-4da2-9e66-6d9911d2faf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19850
72231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1985072231
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1491137646
Short name T238
Test name
Test status
Simulation time 317784634 ps
CPU time 5.62 seconds
Started Aug 04 04:42:38 PM PDT 24
Finished Aug 04 04:42:44 PM PDT 24
Peak memory 253732 kb
Host smart-7d210902-7692-4a9c-8e82-094faa9299c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14911
37646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1491137646
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3534576970
Short name T500
Test name
Test status
Simulation time 12303409336 ps
CPU time 1270.76 seconds
Started Aug 04 04:42:37 PM PDT 24
Finished Aug 04 05:03:48 PM PDT 24
Peak memory 285144 kb
Host smart-b0625f6e-54d5-464a-a546-f11a64e2069c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534576970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3534576970
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1972285804
Short name T324
Test name
Test status
Simulation time 20469511640 ps
CPU time 425.34 seconds
Started Aug 04 04:42:39 PM PDT 24
Finished Aug 04 04:49:44 PM PDT 24
Peak memory 256416 kb
Host smart-d412e5a3-3c85-4e7e-8e4a-56cf77a5310d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972285804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1972285804
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2116316826
Short name T489
Test name
Test status
Simulation time 96431011 ps
CPU time 10.18 seconds
Started Aug 04 04:42:39 PM PDT 24
Finished Aug 04 04:42:49 PM PDT 24
Peak memory 248208 kb
Host smart-c4c9a940-648f-4972-96f5-645ea871d257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21163
16826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2116316826
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.765633674
Short name T260
Test name
Test status
Simulation time 458270965 ps
CPU time 37.27 seconds
Started Aug 04 04:42:39 PM PDT 24
Finished Aug 04 04:43:16 PM PDT 24
Peak memory 248224 kb
Host smart-ab0c0259-4c04-49a8-bfc7-fddaa691470c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76563
3674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.765633674
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1695347852
Short name T11
Test name
Test status
Simulation time 663993699 ps
CPU time 11.42 seconds
Started Aug 04 04:42:41 PM PDT 24
Finished Aug 04 04:42:52 PM PDT 24
Peak memory 271548 kb
Host smart-a315b3a6-1654-42b6-bf60-cb99833b64d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1695347852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1695347852
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3275153586
Short name T437
Test name
Test status
Simulation time 241118395 ps
CPU time 13.12 seconds
Started Aug 04 04:42:35 PM PDT 24
Finished Aug 04 04:42:48 PM PDT 24
Peak memory 248692 kb
Host smart-ff9f8658-a0c1-4f33-ac35-a8b94763cfa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32751
53586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3275153586
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.1703557355
Short name T112
Test name
Test status
Simulation time 57857396205 ps
CPU time 2761.03 seconds
Started Aug 04 04:42:41 PM PDT 24
Finished Aug 04 05:28:42 PM PDT 24
Peak memory 305072 kb
Host smart-695760d5-a062-4935-a804-dd47453e0aca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703557355 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.1703557355
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1918764021
Short name T573
Test name
Test status
Simulation time 25132667634 ps
CPU time 1634.47 seconds
Started Aug 04 04:43:42 PM PDT 24
Finished Aug 04 05:10:57 PM PDT 24
Peak memory 281112 kb
Host smart-e78035de-5610-434e-b9f1-19c87067bf23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918764021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1918764021
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3424958117
Short name T124
Test name
Test status
Simulation time 227027104 ps
CPU time 13.03 seconds
Started Aug 04 04:43:40 PM PDT 24
Finished Aug 04 04:43:53 PM PDT 24
Peak memory 248156 kb
Host smart-c848e493-7a7f-47de-93a1-00f244559b4d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3424958117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3424958117
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2633889
Short name T79
Test name
Test status
Simulation time 2188458701 ps
CPU time 120.87 seconds
Started Aug 04 04:43:36 PM PDT 24
Finished Aug 04 04:45:37 PM PDT 24
Peak memory 256464 kb
Host smart-e8167c40-7d6a-4246-a93c-173f05ce1494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26338
89 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2633889
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1717831267
Short name T643
Test name
Test status
Simulation time 4545391192 ps
CPU time 65.84 seconds
Started Aug 04 04:43:44 PM PDT 24
Finished Aug 04 04:44:50 PM PDT 24
Peak memory 256472 kb
Host smart-cea7d8e5-fc12-4489-800c-9ae45a90ddba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17178
31267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1717831267
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.4099990085
Short name T697
Test name
Test status
Simulation time 63858581127 ps
CPU time 1768.45 seconds
Started Aug 04 04:43:46 PM PDT 24
Finished Aug 04 05:13:15 PM PDT 24
Peak memory 271552 kb
Host smart-a6cd0851-ebe5-4351-8c1a-2521298bbbfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099990085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.4099990085
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.192546060
Short name T530
Test name
Test status
Simulation time 32862631788 ps
CPU time 841.8 seconds
Started Aug 04 04:43:37 PM PDT 24
Finished Aug 04 04:57:39 PM PDT 24
Peak memory 282752 kb
Host smart-6b46d4ce-6045-4b3c-8f59-12f28f409a3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192546060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.192546060
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.156195999
Short name T345
Test name
Test status
Simulation time 19632046334 ps
CPU time 220.14 seconds
Started Aug 04 04:43:36 PM PDT 24
Finished Aug 04 04:47:16 PM PDT 24
Peak memory 255544 kb
Host smart-c20587b5-b027-4986-93dd-32331ab914ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156195999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.156195999
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2078155921
Short name T480
Test name
Test status
Simulation time 423838915 ps
CPU time 8.08 seconds
Started Aug 04 04:43:36 PM PDT 24
Finished Aug 04 04:43:44 PM PDT 24
Peak memory 254072 kb
Host smart-d8d8b784-45aa-4f2c-9bd1-2f43593022af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20781
55921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2078155921
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.700434520
Short name T49
Test name
Test status
Simulation time 731870066 ps
CPU time 50.96 seconds
Started Aug 04 04:43:43 PM PDT 24
Finished Aug 04 04:44:34 PM PDT 24
Peak memory 255540 kb
Host smart-88a0f677-7947-443c-9a24-f4c87299a80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70043
4520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.700434520
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.133041734
Short name T305
Test name
Test status
Simulation time 684875056 ps
CPU time 45.63 seconds
Started Aug 04 04:43:42 PM PDT 24
Finished Aug 04 04:44:28 PM PDT 24
Peak memory 255744 kb
Host smart-90972b14-094a-4bd2-bb2e-836121cd28f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13304
1734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.133041734
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2945173728
Short name T237
Test name
Test status
Simulation time 331077095 ps
CPU time 8.75 seconds
Started Aug 04 04:43:34 PM PDT 24
Finished Aug 04 04:43:42 PM PDT 24
Peak memory 248264 kb
Host smart-10aa6f07-0a8f-498e-b97d-05a7f2bfa024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29451
73728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2945173728
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.2164883551
Short name T257
Test name
Test status
Simulation time 24899418363 ps
CPU time 399.35 seconds
Started Aug 04 04:43:39 PM PDT 24
Finished Aug 04 04:50:18 PM PDT 24
Peak memory 256488 kb
Host smart-a5fa765f-a269-4be9-815f-8efac0edb259
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164883551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.2164883551
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3375083746
Short name T618
Test name
Test status
Simulation time 28913954509 ps
CPU time 1369.77 seconds
Started Aug 04 04:43:42 PM PDT 24
Finished Aug 04 05:06:32 PM PDT 24
Peak memory 289476 kb
Host smart-ba3fd73b-03ea-42e3-9e3a-2b3bea46c0e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375083746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3375083746
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2027517675
Short name T417
Test name
Test status
Simulation time 512425265 ps
CPU time 24.05 seconds
Started Aug 04 04:43:45 PM PDT 24
Finished Aug 04 04:44:09 PM PDT 24
Peak memory 248276 kb
Host smart-2b562218-df9e-4cfa-95f1-053b56a527d8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2027517675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2027517675
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.4118475767
Short name T561
Test name
Test status
Simulation time 988614762 ps
CPU time 59.44 seconds
Started Aug 04 04:43:46 PM PDT 24
Finished Aug 04 04:44:46 PM PDT 24
Peak memory 255600 kb
Host smart-920cc03c-a801-4cc4-b371-234f5db3936a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41184
75767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.4118475767
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.4012244765
Short name T581
Test name
Test status
Simulation time 14542664706 ps
CPU time 48.58 seconds
Started Aug 04 04:43:43 PM PDT 24
Finished Aug 04 04:44:32 PM PDT 24
Peak memory 255788 kb
Host smart-49a11932-1592-4d4b-8f4a-c013eade8960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40122
44765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.4012244765
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3634839255
Short name T316
Test name
Test status
Simulation time 12791181153 ps
CPU time 1267.42 seconds
Started Aug 04 04:43:44 PM PDT 24
Finished Aug 04 05:04:51 PM PDT 24
Peak memory 287648 kb
Host smart-e6306f01-3991-4162-b0c1-3b6a2cd15359
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634839255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3634839255
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.806817842
Short name T448
Test name
Test status
Simulation time 171869110547 ps
CPU time 1811.55 seconds
Started Aug 04 04:43:44 PM PDT 24
Finished Aug 04 05:13:56 PM PDT 24
Peak memory 272820 kb
Host smart-b38a248e-18a5-42b6-97aa-f746d191baad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806817842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.806817842
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.910485544
Short name T115
Test name
Test status
Simulation time 8868405162 ps
CPU time 97.05 seconds
Started Aug 04 04:43:42 PM PDT 24
Finished Aug 04 04:45:19 PM PDT 24
Peak memory 248256 kb
Host smart-15b3ecfc-7f99-44dd-8145-52a969d8ffc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910485544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.910485544
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2158227382
Short name T641
Test name
Test status
Simulation time 978261719 ps
CPU time 59.25 seconds
Started Aug 04 04:43:45 PM PDT 24
Finished Aug 04 04:44:44 PM PDT 24
Peak memory 256336 kb
Host smart-225a2f7e-1bb6-4e7d-b1fa-fa057f30e8ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21582
27382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2158227382
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.1228220827
Short name T435
Test name
Test status
Simulation time 2063355326 ps
CPU time 25.06 seconds
Started Aug 04 04:43:44 PM PDT 24
Finished Aug 04 04:44:10 PM PDT 24
Peak memory 247824 kb
Host smart-50961ef6-d94c-4b9f-8a69-564949318cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12282
20827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1228220827
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.172056460
Short name T258
Test name
Test status
Simulation time 797521209 ps
CPU time 21.18 seconds
Started Aug 04 04:43:41 PM PDT 24
Finished Aug 04 04:44:03 PM PDT 24
Peak memory 247692 kb
Host smart-2fa54917-06cd-499a-9ccd-5d4b7acf53f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17205
6460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.172056460
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.972116497
Short name T445
Test name
Test status
Simulation time 213344563961 ps
CPU time 1488.36 seconds
Started Aug 04 04:43:47 PM PDT 24
Finished Aug 04 05:08:36 PM PDT 24
Peak memory 288792 kb
Host smart-baebd716-f5d1-48ea-a324-40a30e164be5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972116497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.972116497
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1571637533
Short name T227
Test name
Test status
Simulation time 40186057 ps
CPU time 3.3 seconds
Started Aug 04 04:43:52 PM PDT 24
Finished Aug 04 04:43:56 PM PDT 24
Peak memory 248440 kb
Host smart-89adfb42-6054-45ed-a9b5-310f3d208a68
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1571637533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1571637533
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2640266694
Short name T577
Test name
Test status
Simulation time 144840602723 ps
CPU time 2082.9 seconds
Started Aug 04 04:43:47 PM PDT 24
Finished Aug 04 05:18:30 PM PDT 24
Peak memory 272612 kb
Host smart-95dee407-f6df-42d7-a51d-52aefede58b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640266694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2640266694
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2026627201
Short name T649
Test name
Test status
Simulation time 281102940 ps
CPU time 13.46 seconds
Started Aug 04 04:43:50 PM PDT 24
Finished Aug 04 04:44:03 PM PDT 24
Peak memory 248264 kb
Host smart-1cbb556c-cc3b-4900-ad80-4e795e354796
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2026627201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2026627201
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.886287186
Short name T578
Test name
Test status
Simulation time 3945493640 ps
CPU time 92.52 seconds
Started Aug 04 04:43:46 PM PDT 24
Finished Aug 04 04:45:19 PM PDT 24
Peak memory 255968 kb
Host smart-00fa0d6e-49fe-4054-8d30-027c031dfd9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88628
7186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.886287186
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2856291867
Short name T479
Test name
Test status
Simulation time 4348906697 ps
CPU time 58.6 seconds
Started Aug 04 04:43:50 PM PDT 24
Finished Aug 04 04:44:48 PM PDT 24
Peak memory 256456 kb
Host smart-2f98a4f2-0e21-4097-97de-9fbef33a3e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28562
91867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2856291867
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2069201861
Short name T684
Test name
Test status
Simulation time 561238748847 ps
CPU time 1435.54 seconds
Started Aug 04 04:43:50 PM PDT 24
Finished Aug 04 05:07:46 PM PDT 24
Peak memory 272812 kb
Host smart-370b3713-8664-499e-9617-82f111d6d367
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069201861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2069201861
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1344805530
Short name T443
Test name
Test status
Simulation time 32662714293 ps
CPU time 668.13 seconds
Started Aug 04 04:43:49 PM PDT 24
Finished Aug 04 04:54:57 PM PDT 24
Peak memory 272208 kb
Host smart-c950c82a-ec89-49dc-94e9-61e7585994e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344805530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1344805530
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1823252922
Short name T341
Test name
Test status
Simulation time 21720013631 ps
CPU time 355.07 seconds
Started Aug 04 04:43:46 PM PDT 24
Finished Aug 04 04:49:42 PM PDT 24
Peak memory 248356 kb
Host smart-8e0b5e5f-c5c8-494d-88f9-63cce6ec88f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823252922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1823252922
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3188503079
Short name T460
Test name
Test status
Simulation time 721235860 ps
CPU time 17.3 seconds
Started Aug 04 04:43:47 PM PDT 24
Finished Aug 04 04:44:04 PM PDT 24
Peak memory 255664 kb
Host smart-78743667-f8df-43a9-8c16-bd082c06185e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31885
03079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3188503079
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2173199334
Short name T438
Test name
Test status
Simulation time 213115105 ps
CPU time 15.87 seconds
Started Aug 04 04:43:46 PM PDT 24
Finished Aug 04 04:44:02 PM PDT 24
Peak memory 255956 kb
Host smart-6f6a48bb-563f-4a61-8402-5db2344764ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21731
99334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2173199334
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3072808033
Short name T285
Test name
Test status
Simulation time 416230008 ps
CPU time 15.21 seconds
Started Aug 04 04:43:47 PM PDT 24
Finished Aug 04 04:44:02 PM PDT 24
Peak memory 255088 kb
Host smart-0a12018d-82a9-404c-954c-f6f8ef9a735a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30728
08033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3072808033
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.968702475
Short name T712
Test name
Test status
Simulation time 1252520395 ps
CPU time 21.93 seconds
Started Aug 04 04:43:50 PM PDT 24
Finished Aug 04 04:44:12 PM PDT 24
Peak memory 255280 kb
Host smart-eb9c8534-0a52-4cb7-aa42-0ee16ad7c37a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96870
2475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.968702475
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3914558410
Short name T284
Test name
Test status
Simulation time 4048506042 ps
CPU time 353.59 seconds
Started Aug 04 04:43:48 PM PDT 24
Finished Aug 04 04:49:42 PM PDT 24
Peak memory 264632 kb
Host smart-6267e8c8-d360-40fc-9b9d-9c0c196f012f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914558410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3914558410
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.4082189297
Short name T217
Test name
Test status
Simulation time 111890616 ps
CPU time 3.44 seconds
Started Aug 04 04:43:56 PM PDT 24
Finished Aug 04 04:43:59 PM PDT 24
Peak memory 248452 kb
Host smart-3ba66c10-df28-45a6-a5c9-21ee93dd4fef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4082189297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.4082189297
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.167304174
Short name T420
Test name
Test status
Simulation time 28047443189 ps
CPU time 1218.53 seconds
Started Aug 04 04:43:50 PM PDT 24
Finished Aug 04 05:04:09 PM PDT 24
Peak memory 272080 kb
Host smart-ceec626c-af11-4fa2-a693-216b448bad44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167304174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.167304174
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.645556822
Short name T576
Test name
Test status
Simulation time 4808074226 ps
CPU time 281.58 seconds
Started Aug 04 04:43:52 PM PDT 24
Finished Aug 04 04:48:34 PM PDT 24
Peak memory 256012 kb
Host smart-7c2c6b2a-70d3-4981-9da3-b06e9c00ce31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64555
6822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.645556822
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2364888534
Short name T14
Test name
Test status
Simulation time 512070238 ps
CPU time 18.14 seconds
Started Aug 04 04:43:48 PM PDT 24
Finished Aug 04 04:44:06 PM PDT 24
Peak memory 247700 kb
Host smart-6e0f180b-ac41-418a-b987-f22e44a0a9d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23648
88534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2364888534
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.817535717
Short name T488
Test name
Test status
Simulation time 30534044779 ps
CPU time 1897.11 seconds
Started Aug 04 04:43:57 PM PDT 24
Finished Aug 04 05:15:34 PM PDT 24
Peak memory 284920 kb
Host smart-ce6adf97-3b5e-4f1c-9f23-a87b063c99fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817535717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.817535717
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2796930767
Short name T346
Test name
Test status
Simulation time 6826325091 ps
CPU time 267.73 seconds
Started Aug 04 04:43:52 PM PDT 24
Finished Aug 04 04:48:20 PM PDT 24
Peak memory 247368 kb
Host smart-bffa7826-3a9a-4c0d-bd27-11fe16253b5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796930767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2796930767
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2120447588
Short name T546
Test name
Test status
Simulation time 1694832956 ps
CPU time 25.61 seconds
Started Aug 04 04:43:49 PM PDT 24
Finished Aug 04 04:44:15 PM PDT 24
Peak memory 248236 kb
Host smart-6f38e168-e63b-45a6-ac67-f9f5706bf673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21204
47588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2120447588
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3286430111
Short name T302
Test name
Test status
Simulation time 746086127 ps
CPU time 14.26 seconds
Started Aug 04 04:43:49 PM PDT 24
Finished Aug 04 04:44:04 PM PDT 24
Peak memory 247788 kb
Host smart-d116a1dd-7f57-455e-aef5-d5cad801a35a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32864
30111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3286430111
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2463494750
Short name T205
Test name
Test status
Simulation time 256851244 ps
CPU time 17.87 seconds
Started Aug 04 04:43:52 PM PDT 24
Finished Aug 04 04:44:10 PM PDT 24
Peak memory 255480 kb
Host smart-ab798492-07bd-47c9-a1cc-93192b41a45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24634
94750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2463494750
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1635752437
Short name T485
Test name
Test status
Simulation time 117284246 ps
CPU time 8.67 seconds
Started Aug 04 04:43:51 PM PDT 24
Finished Aug 04 04:44:00 PM PDT 24
Peak memory 248204 kb
Host smart-49ff78bb-205c-4d39-b67a-8851211df1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16357
52437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1635752437
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2885097030
Short name T228
Test name
Test status
Simulation time 22073289 ps
CPU time 2.3 seconds
Started Aug 04 04:44:02 PM PDT 24
Finished Aug 04 04:44:05 PM PDT 24
Peak memory 248580 kb
Host smart-39b51042-6e74-43eb-bde2-fa8fa4e223e8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2885097030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2885097030
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.329132628
Short name T711
Test name
Test status
Simulation time 30198669813 ps
CPU time 671.46 seconds
Started Aug 04 04:43:59 PM PDT 24
Finished Aug 04 04:55:10 PM PDT 24
Peak memory 264740 kb
Host smart-3765f8a4-6fc2-44bb-b98b-7d76c7ee59a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329132628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.329132628
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1885064333
Short name T503
Test name
Test status
Simulation time 1227414110 ps
CPU time 16.72 seconds
Started Aug 04 04:43:59 PM PDT 24
Finished Aug 04 04:44:16 PM PDT 24
Peak memory 248072 kb
Host smart-17da9589-6ef4-400a-bc15-a35bd9ddaa73
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1885064333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1885064333
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3720207184
Short name T441
Test name
Test status
Simulation time 367444398 ps
CPU time 7.46 seconds
Started Aug 04 04:44:00 PM PDT 24
Finished Aug 04 04:44:07 PM PDT 24
Peak memory 248188 kb
Host smart-9272d193-349a-4c9e-90c6-0b239a41740f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37202
07184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3720207184
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1521021478
Short name T406
Test name
Test status
Simulation time 402960539 ps
CPU time 29.5 seconds
Started Aug 04 04:43:57 PM PDT 24
Finished Aug 04 04:44:27 PM PDT 24
Peak memory 248320 kb
Host smart-9c109ff4-0ce9-43bf-a2c6-d8f444759122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15210
21478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1521021478
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2191642418
Short name T564
Test name
Test status
Simulation time 30102380474 ps
CPU time 1929.09 seconds
Started Aug 04 04:43:58 PM PDT 24
Finished Aug 04 05:16:07 PM PDT 24
Peak memory 282288 kb
Host smart-6ea19eca-3e52-4b87-b59f-3432e88890f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191642418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2191642418
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3477363856
Short name T517
Test name
Test status
Simulation time 2262703411 ps
CPU time 35.27 seconds
Started Aug 04 04:43:56 PM PDT 24
Finished Aug 04 04:44:31 PM PDT 24
Peak memory 255760 kb
Host smart-7cce2496-1186-4330-b8fb-084b0979c06f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34773
63856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3477363856
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2064608485
Short name T67
Test name
Test status
Simulation time 825397286 ps
CPU time 48.03 seconds
Started Aug 04 04:43:58 PM PDT 24
Finished Aug 04 04:44:47 PM PDT 24
Peak memory 248264 kb
Host smart-8287714a-dc58-44dc-a83f-67969b0ae340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20646
08485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2064608485
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3583827995
Short name T593
Test name
Test status
Simulation time 315708415 ps
CPU time 19.41 seconds
Started Aug 04 04:44:05 PM PDT 24
Finished Aug 04 04:44:24 PM PDT 24
Peak memory 248216 kb
Host smart-7a1a61e6-4ce1-423d-8b11-ad127e319be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35838
27995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3583827995
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3259096179
Short name T393
Test name
Test status
Simulation time 159573195 ps
CPU time 14.58 seconds
Started Aug 04 04:43:55 PM PDT 24
Finished Aug 04 04:44:10 PM PDT 24
Peak memory 248408 kb
Host smart-7d1e22fd-94e1-48a2-b147-b8aa072b1b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32590
96179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3259096179
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3149885740
Short name T123
Test name
Test status
Simulation time 3001825136 ps
CPU time 235.12 seconds
Started Aug 04 04:44:01 PM PDT 24
Finished Aug 04 04:47:56 PM PDT 24
Peak memory 255104 kb
Host smart-bb21c33a-09de-4214-94e5-9e965cf6687b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149885740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3149885740
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.3750648851
Short name T107
Test name
Test status
Simulation time 38205539443 ps
CPU time 3428.59 seconds
Started Aug 04 04:44:01 PM PDT 24
Finished Aug 04 05:41:10 PM PDT 24
Peak memory 332428 kb
Host smart-5e71d34a-6fcf-4786-9229-70bb34af2d3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750648851 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.3750648851
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2584268243
Short name T226
Test name
Test status
Simulation time 17413428 ps
CPU time 2.5 seconds
Started Aug 04 04:44:08 PM PDT 24
Finished Aug 04 04:44:11 PM PDT 24
Peak memory 248480 kb
Host smart-9ef6f2d9-c03e-44ae-b991-85b676bc4d3b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2584268243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2584268243
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3770354084
Short name T106
Test name
Test status
Simulation time 35118581311 ps
CPU time 1421.62 seconds
Started Aug 04 04:44:05 PM PDT 24
Finished Aug 04 05:07:47 PM PDT 24
Peak memory 287912 kb
Host smart-22a2303a-3ed6-4eb3-ae08-6b7de89b456c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770354084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3770354084
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1131823521
Short name T477
Test name
Test status
Simulation time 169155005 ps
CPU time 9.27 seconds
Started Aug 04 04:44:07 PM PDT 24
Finished Aug 04 04:44:17 PM PDT 24
Peak memory 248228 kb
Host smart-afecd17d-0dfd-420e-ba87-0d1da0fcbe74
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1131823521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1131823521
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3226955705
Short name T422
Test name
Test status
Simulation time 13690369459 ps
CPU time 120.19 seconds
Started Aug 04 04:44:04 PM PDT 24
Finished Aug 04 04:46:04 PM PDT 24
Peak memory 255648 kb
Host smart-61a79660-8536-40c2-b3bc-1a408f2b626b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32269
55705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3226955705
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1224106656
Short name T675
Test name
Test status
Simulation time 32906983036 ps
CPU time 1849.31 seconds
Started Aug 04 04:44:07 PM PDT 24
Finished Aug 04 05:14:57 PM PDT 24
Peak memory 289028 kb
Host smart-32e9aace-89ea-4f0c-8fd2-46febf783725
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224106656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1224106656
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.4184443732
Short name T359
Test name
Test status
Simulation time 271982800013 ps
CPU time 2646.54 seconds
Started Aug 04 04:44:10 PM PDT 24
Finished Aug 04 05:28:17 PM PDT 24
Peak memory 288628 kb
Host smart-6f1ec621-76fe-4972-bb20-66f65bf7d5e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184443732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.4184443732
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3545268190
Short name T331
Test name
Test status
Simulation time 97414085535 ps
CPU time 210.39 seconds
Started Aug 04 04:44:05 PM PDT 24
Finished Aug 04 04:47:36 PM PDT 24
Peak memory 254776 kb
Host smart-82482d51-dcd4-44b6-9cdb-e0a92f1a20d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545268190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3545268190
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1512449686
Short name T469
Test name
Test status
Simulation time 1034559221 ps
CPU time 21.97 seconds
Started Aug 04 04:44:02 PM PDT 24
Finished Aug 04 04:44:24 PM PDT 24
Peak memory 248148 kb
Host smart-22ec4c16-43c3-489a-99fe-775cef943570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15124
49686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1512449686
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1587359634
Short name T194
Test name
Test status
Simulation time 532382932 ps
CPU time 10.87 seconds
Started Aug 04 04:44:05 PM PDT 24
Finished Aug 04 04:44:16 PM PDT 24
Peak memory 247708 kb
Host smart-8c85ba18-1303-4d8d-ba26-7d6e370d926b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15873
59634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1587359634
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.333686407
Short name T672
Test name
Test status
Simulation time 1287709363 ps
CPU time 31.16 seconds
Started Aug 04 04:44:03 PM PDT 24
Finished Aug 04 04:44:34 PM PDT 24
Peak memory 248236 kb
Host smart-a7ffe222-f220-464e-90e5-a23aead5ba1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33368
6407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.333686407
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.504528896
Short name T492
Test name
Test status
Simulation time 5421641622 ps
CPU time 69.81 seconds
Started Aug 04 04:44:11 PM PDT 24
Finished Aug 04 04:45:21 PM PDT 24
Peak memory 249792 kb
Host smart-0ab49f79-38b1-487b-9fe7-abbb11b6aea7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504528896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.504528896
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2503852407
Short name T230
Test name
Test status
Simulation time 37324844 ps
CPU time 3.69 seconds
Started Aug 04 04:44:10 PM PDT 24
Finished Aug 04 04:44:14 PM PDT 24
Peak memory 248484 kb
Host smart-7ba0457b-1a11-4b0f-aa01-87bd30ce952c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2503852407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2503852407
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3551959530
Short name T102
Test name
Test status
Simulation time 34470304621 ps
CPU time 1934.81 seconds
Started Aug 04 04:44:10 PM PDT 24
Finished Aug 04 05:16:25 PM PDT 24
Peak memory 272616 kb
Host smart-4372ced4-6a14-4207-8bc3-8268283cbfd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551959530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3551959530
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2246544871
Short name T390
Test name
Test status
Simulation time 1016778027 ps
CPU time 41.52 seconds
Started Aug 04 04:44:10 PM PDT 24
Finished Aug 04 04:44:52 PM PDT 24
Peak memory 248120 kb
Host smart-269b5ad3-e555-40dd-bb4c-a7de608658aa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2246544871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2246544871
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.158263540
Short name T602
Test name
Test status
Simulation time 4296028475 ps
CPU time 119.76 seconds
Started Aug 04 04:44:11 PM PDT 24
Finished Aug 04 04:46:10 PM PDT 24
Peak memory 256012 kb
Host smart-b874eaa6-9320-4dcd-a654-78453971455d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15826
3540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.158263540
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1335764758
Short name T616
Test name
Test status
Simulation time 210035415 ps
CPU time 14.06 seconds
Started Aug 04 04:44:11 PM PDT 24
Finished Aug 04 04:44:25 PM PDT 24
Peak memory 256020 kb
Host smart-c74ed4ce-896d-4044-8cc3-89f9fb0f19e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13357
64758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1335764758
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3687885883
Short name T240
Test name
Test status
Simulation time 39614304515 ps
CPU time 2294.02 seconds
Started Aug 04 04:44:11 PM PDT 24
Finished Aug 04 05:22:25 PM PDT 24
Peak memory 284480 kb
Host smart-c046b980-c038-4f65-bd0d-b9f1f3bab918
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687885883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3687885883
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.4271577582
Short name T261
Test name
Test status
Simulation time 2352681242 ps
CPU time 86.75 seconds
Started Aug 04 04:44:11 PM PDT 24
Finished Aug 04 04:45:38 PM PDT 24
Peak memory 248336 kb
Host smart-4e0e5962-05a7-4b57-8c5f-120c02822fc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271577582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.4271577582
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3013969008
Short name T470
Test name
Test status
Simulation time 236412890 ps
CPU time 17.69 seconds
Started Aug 04 04:44:08 PM PDT 24
Finished Aug 04 04:44:26 PM PDT 24
Peak memory 255448 kb
Host smart-211346ea-16f9-4931-8c27-e97a59d84be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30139
69008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3013969008
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.4176834296
Short name T31
Test name
Test status
Simulation time 445901835 ps
CPU time 10.14 seconds
Started Aug 04 04:44:07 PM PDT 24
Finished Aug 04 04:44:17 PM PDT 24
Peak memory 247596 kb
Host smart-e7f92ebf-af4a-4466-bb99-50d3989b1f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41768
34296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.4176834296
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2716748195
Short name T91
Test name
Test status
Simulation time 267538606 ps
CPU time 27.49 seconds
Started Aug 04 04:44:11 PM PDT 24
Finished Aug 04 04:44:38 PM PDT 24
Peak memory 255832 kb
Host smart-551a8128-1921-47ac-a0ba-7d1bb23af284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27167
48195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2716748195
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1137853663
Short name T538
Test name
Test status
Simulation time 512581058 ps
CPU time 39.43 seconds
Started Aug 04 04:44:10 PM PDT 24
Finished Aug 04 04:44:49 PM PDT 24
Peak memory 256364 kb
Host smart-efb7fe36-095e-413f-9f38-48ec21cde61e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11378
53663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1137853663
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3003498743
Short name T666
Test name
Test status
Simulation time 62028344331 ps
CPU time 3633.04 seconds
Started Aug 04 04:44:11 PM PDT 24
Finished Aug 04 05:44:45 PM PDT 24
Peak memory 288832 kb
Host smart-20157e2c-c952-4ceb-905f-66cc8d3b2aad
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003498743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3003498743
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.699026497
Short name T233
Test name
Test status
Simulation time 39943527 ps
CPU time 3.45 seconds
Started Aug 04 04:44:19 PM PDT 24
Finished Aug 04 04:44:22 PM PDT 24
Peak memory 248564 kb
Host smart-19f3b319-cce8-4f38-a57b-cdc31ae88520
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=699026497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.699026497
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2521902640
Short name T532
Test name
Test status
Simulation time 56342248863 ps
CPU time 1244.56 seconds
Started Aug 04 04:44:21 PM PDT 24
Finished Aug 04 05:05:06 PM PDT 24
Peak memory 288948 kb
Host smart-f70d8c66-ad72-45c2-87aa-c10b8f61774c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521902640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2521902640
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1162052910
Short name T691
Test name
Test status
Simulation time 582093695 ps
CPU time 15.42 seconds
Started Aug 04 04:44:19 PM PDT 24
Finished Aug 04 04:44:35 PM PDT 24
Peak memory 248228 kb
Host smart-2a461fae-be2a-4ec5-a0f9-96d854d58f69
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1162052910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1162052910
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.4095560723
Short name T433
Test name
Test status
Simulation time 15098733602 ps
CPU time 191.06 seconds
Started Aug 04 04:44:17 PM PDT 24
Finished Aug 04 04:47:29 PM PDT 24
Peak memory 255632 kb
Host smart-d531e311-e6b2-46eb-8675-9012ac66c772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40955
60723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.4095560723
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3707251694
Short name T495
Test name
Test status
Simulation time 4289707579 ps
CPU time 71.2 seconds
Started Aug 04 04:44:18 PM PDT 24
Finished Aug 04 04:45:29 PM PDT 24
Peak memory 256012 kb
Host smart-71060b9d-b8fe-433e-9b77-b447addec463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37072
51694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3707251694
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2840435720
Short name T308
Test name
Test status
Simulation time 39704445335 ps
CPU time 1683.18 seconds
Started Aug 04 04:44:20 PM PDT 24
Finished Aug 04 05:12:24 PM PDT 24
Peak memory 289192 kb
Host smart-7d7c1dbf-7adb-472b-a96f-0ef034748803
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840435720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2840435720
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3754352401
Short name T429
Test name
Test status
Simulation time 9584521989 ps
CPU time 1212.06 seconds
Started Aug 04 04:44:15 PM PDT 24
Finished Aug 04 05:04:28 PM PDT 24
Peak memory 288332 kb
Host smart-b3edab22-c40f-4461-be57-b34385c0af84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754352401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3754352401
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3642531239
Short name T196
Test name
Test status
Simulation time 85785027915 ps
CPU time 408.51 seconds
Started Aug 04 04:44:18 PM PDT 24
Finished Aug 04 04:51:07 PM PDT 24
Peak memory 248244 kb
Host smart-be5a76de-9f7b-46eb-825d-d59cabe4b8c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642531239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3642531239
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1527554652
Short name T636
Test name
Test status
Simulation time 121111391 ps
CPU time 8.58 seconds
Started Aug 04 04:44:17 PM PDT 24
Finished Aug 04 04:44:26 PM PDT 24
Peak memory 253176 kb
Host smart-0adb6df7-73db-4ab8-ba9c-2d5facc89baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15275
54652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1527554652
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2847745209
Short name T542
Test name
Test status
Simulation time 148730788 ps
CPU time 15.19 seconds
Started Aug 04 04:44:13 PM PDT 24
Finished Aug 04 04:44:29 PM PDT 24
Peak memory 248136 kb
Host smart-63dfab99-9f95-4fe8-bc60-be308b2f38b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28477
45209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2847745209
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1317675637
Short name T607
Test name
Test status
Simulation time 593968567 ps
CPU time 16.86 seconds
Started Aug 04 04:44:19 PM PDT 24
Finished Aug 04 04:44:36 PM PDT 24
Peak memory 252644 kb
Host smart-9f375550-d1be-4a57-8fc0-275ec3c41737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13176
75637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1317675637
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3682505666
Short name T391
Test name
Test status
Simulation time 472763161 ps
CPU time 28.19 seconds
Started Aug 04 04:44:12 PM PDT 24
Finished Aug 04 04:44:41 PM PDT 24
Peak memory 255440 kb
Host smart-b908460d-94ed-435b-b498-b0c3192e9805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36825
05666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3682505666
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.325951023
Short name T582
Test name
Test status
Simulation time 294726142687 ps
CPU time 1618.97 seconds
Started Aug 04 04:44:18 PM PDT 24
Finished Aug 04 05:11:17 PM PDT 24
Peak memory 281056 kb
Host smart-8c417c7b-7beb-44b0-9feb-f60e93666762
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325951023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.325951023
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.4203287235
Short name T218
Test name
Test status
Simulation time 146576008 ps
CPU time 3.74 seconds
Started Aug 04 04:44:21 PM PDT 24
Finished Aug 04 04:44:25 PM PDT 24
Peak memory 248456 kb
Host smart-0077b144-a2a6-4479-959f-ecca6c3e0598
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4203287235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.4203287235
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.660000715
Short name T545
Test name
Test status
Simulation time 232515458872 ps
CPU time 986.35 seconds
Started Aug 04 04:44:23 PM PDT 24
Finished Aug 04 05:00:49 PM PDT 24
Peak memory 272472 kb
Host smart-0553a958-c6c3-43bc-ba47-93a911b1348f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660000715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.660000715
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3546647359
Short name T639
Test name
Test status
Simulation time 1106987185 ps
CPU time 16.31 seconds
Started Aug 04 04:44:21 PM PDT 24
Finished Aug 04 04:44:38 PM PDT 24
Peak memory 248284 kb
Host smart-aeb9b185-d32a-4d5d-971f-e60f0a49bd7c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3546647359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3546647359
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3513654106
Short name T47
Test name
Test status
Simulation time 7980598673 ps
CPU time 237.57 seconds
Started Aug 04 04:44:19 PM PDT 24
Finished Aug 04 04:48:16 PM PDT 24
Peak memory 250824 kb
Host smart-53ead91b-d33e-4a4a-8a10-a6a6c1060207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35136
54106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3513654106
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.882036416
Short name T567
Test name
Test status
Simulation time 2518636676 ps
CPU time 69.09 seconds
Started Aug 04 04:44:18 PM PDT 24
Finished Aug 04 04:45:27 PM PDT 24
Peak memory 256380 kb
Host smart-d197fd68-cfb5-4a3a-982b-e37b688f69e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88203
6416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.882036416
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.161978198
Short name T327
Test name
Test status
Simulation time 193861115827 ps
CPU time 1766.79 seconds
Started Aug 04 04:44:21 PM PDT 24
Finished Aug 04 05:13:48 PM PDT 24
Peak memory 288156 kb
Host smart-6f702e61-946b-47d1-818d-7cc35eb8ff20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161978198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.161978198
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1516776284
Short name T93
Test name
Test status
Simulation time 913631709179 ps
CPU time 3429.97 seconds
Started Aug 04 04:44:20 PM PDT 24
Finished Aug 04 05:41:31 PM PDT 24
Peak memory 288940 kb
Host smart-87aa59b1-03e8-4bc2-9db9-cb567ff6b900
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516776284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1516776284
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.249544185
Short name T349
Test name
Test status
Simulation time 9299132846 ps
CPU time 382.28 seconds
Started Aug 04 04:44:21 PM PDT 24
Finished Aug 04 04:50:43 PM PDT 24
Peak memory 248344 kb
Host smart-04cf8e19-1e7d-4435-9ca2-093715654dd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249544185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.249544185
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.876287753
Short name T48
Test name
Test status
Simulation time 439862572 ps
CPU time 17.16 seconds
Started Aug 04 04:44:17 PM PDT 24
Finished Aug 04 04:44:34 PM PDT 24
Peak memory 255764 kb
Host smart-992d170e-62c5-49da-a56c-eb6481f1571f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87628
7753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.876287753
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1181499015
Short name T76
Test name
Test status
Simulation time 985004079 ps
CPU time 30.18 seconds
Started Aug 04 04:44:16 PM PDT 24
Finished Aug 04 04:44:47 PM PDT 24
Peak memory 255672 kb
Host smart-08652dbd-bf55-4082-b388-04173bd828bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11814
99015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1181499015
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1308226714
Short name T556
Test name
Test status
Simulation time 4094675581 ps
CPU time 33.3 seconds
Started Aug 04 04:44:21 PM PDT 24
Finished Aug 04 04:44:55 PM PDT 24
Peak memory 255808 kb
Host smart-da2f362b-b238-4eae-983b-342a9e62a6e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13082
26714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1308226714
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2753328469
Short name T627
Test name
Test status
Simulation time 3868449388 ps
CPU time 21.99 seconds
Started Aug 04 04:44:18 PM PDT 24
Finished Aug 04 04:44:40 PM PDT 24
Peak memory 248616 kb
Host smart-91748255-9864-4787-a7b1-f3fc04e4cf50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27533
28469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2753328469
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2463544272
Short name T431
Test name
Test status
Simulation time 649968402 ps
CPU time 32.75 seconds
Started Aug 04 04:44:21 PM PDT 24
Finished Aug 04 04:44:54 PM PDT 24
Peak memory 255412 kb
Host smart-31aa2a02-1f2d-4409-abac-10f72249d862
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463544272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2463544272
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2054944172
Short name T281
Test name
Test status
Simulation time 99153827154 ps
CPU time 2704.99 seconds
Started Aug 04 04:44:22 PM PDT 24
Finished Aug 04 05:29:28 PM PDT 24
Peak memory 322136 kb
Host smart-622a6195-772c-4e44-8f79-ace907018b1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054944172 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2054944172
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3759234232
Short name T223
Test name
Test status
Simulation time 32240443 ps
CPU time 3.52 seconds
Started Aug 04 04:44:28 PM PDT 24
Finished Aug 04 04:44:31 PM PDT 24
Peak memory 248544 kb
Host smart-6e1bfc11-6b1f-4dfa-a372-4dc304df4162
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3759234232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3759234232
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3398912586
Short name T544
Test name
Test status
Simulation time 36704617704 ps
CPU time 1200.33 seconds
Started Aug 04 04:44:24 PM PDT 24
Finished Aug 04 05:04:25 PM PDT 24
Peak memory 272316 kb
Host smart-93434227-b719-44f8-b167-5ae911237f81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398912586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3398912586
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1140724642
Short name T486
Test name
Test status
Simulation time 342354104 ps
CPU time 15.61 seconds
Started Aug 04 04:44:24 PM PDT 24
Finished Aug 04 04:44:40 PM PDT 24
Peak memory 248172 kb
Host smart-4ecbb552-362d-48f3-a02a-1db654e2581a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1140724642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1140724642
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.3039671719
Short name T600
Test name
Test status
Simulation time 1331328707 ps
CPU time 99.5 seconds
Started Aug 04 04:44:24 PM PDT 24
Finished Aug 04 04:46:04 PM PDT 24
Peak memory 255924 kb
Host smart-c48c3bc1-f9ce-4f85-9a47-7d7c23fccae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30396
71719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.3039671719
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1735313326
Short name T640
Test name
Test status
Simulation time 473906654 ps
CPU time 15.03 seconds
Started Aug 04 04:44:37 PM PDT 24
Finished Aug 04 04:44:52 PM PDT 24
Peak memory 252840 kb
Host smart-bf91f597-a2e0-4c2d-a82c-203cafd751ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17353
13326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1735313326
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3656657318
Short name T357
Test name
Test status
Simulation time 122286430343 ps
CPU time 3359.17 seconds
Started Aug 04 04:44:24 PM PDT 24
Finished Aug 04 05:40:24 PM PDT 24
Peak memory 288984 kb
Host smart-066210d9-4ea5-4bd4-b9f0-4c840fba8022
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656657318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3656657318
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.759233293
Short name T98
Test name
Test status
Simulation time 60070849863 ps
CPU time 1480.58 seconds
Started Aug 04 04:44:25 PM PDT 24
Finished Aug 04 05:09:06 PM PDT 24
Peak memory 289088 kb
Host smart-16ed376d-42e7-4f70-95c3-2e7c66e8512a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759233293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.759233293
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2920534274
Short name T524
Test name
Test status
Simulation time 147145981 ps
CPU time 16.18 seconds
Started Aug 04 04:44:24 PM PDT 24
Finished Aug 04 04:44:41 PM PDT 24
Peak memory 255780 kb
Host smart-f4d4d3b6-fd16-4c9f-821d-946e59308e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29205
34274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2920534274
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2577140614
Short name T398
Test name
Test status
Simulation time 119212045 ps
CPU time 13.68 seconds
Started Aug 04 04:44:25 PM PDT 24
Finished Aug 04 04:44:39 PM PDT 24
Peak memory 255552 kb
Host smart-4f5154b3-c700-4994-a95a-fbc67b4e1681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25771
40614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2577140614
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1227921640
Short name T213
Test name
Test status
Simulation time 288725455150 ps
CPU time 5184.2 seconds
Started Aug 04 04:44:27 PM PDT 24
Finished Aug 04 06:10:51 PM PDT 24
Peak memory 366588 kb
Host smart-7c9897bf-5e2c-4c52-9ffa-88ecfee4a387
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227921640 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1227921640
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.798871118
Short name T86
Test name
Test status
Simulation time 37753061 ps
CPU time 2.57 seconds
Started Aug 04 04:42:48 PM PDT 24
Finished Aug 04 04:42:50 PM PDT 24
Peak memory 248440 kb
Host smart-cb7d2e91-ba70-40e6-87f7-dcabea25674f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=798871118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.798871118
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.473260060
Short name T110
Test name
Test status
Simulation time 67226073488 ps
CPU time 1886.43 seconds
Started Aug 04 04:42:46 PM PDT 24
Finished Aug 04 05:14:12 PM PDT 24
Peak memory 288548 kb
Host smart-7163c3dd-c39b-4e66-8de6-e172993b5f44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473260060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.473260060
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2992130542
Short name T386
Test name
Test status
Simulation time 2685600735 ps
CPU time 28.68 seconds
Started Aug 04 04:42:44 PM PDT 24
Finished Aug 04 04:43:13 PM PDT 24
Peak memory 248224 kb
Host smart-f0fb5015-8799-4a8f-9bc2-4aeb20ab765c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2992130542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2992130542
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2699481421
Short name T405
Test name
Test status
Simulation time 1893089628 ps
CPU time 139.38 seconds
Started Aug 04 04:42:45 PM PDT 24
Finished Aug 04 04:45:04 PM PDT 24
Peak memory 255900 kb
Host smart-6646bd97-f805-4e6a-957d-7ead3ee8f625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26994
81421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2699481421
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.904230863
Short name T404
Test name
Test status
Simulation time 621368524 ps
CPU time 16.29 seconds
Started Aug 04 04:42:41 PM PDT 24
Finished Aug 04 04:42:57 PM PDT 24
Peak memory 247924 kb
Host smart-11b7901c-e6ae-49a8-a44f-307e9d3a8ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90423
0863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.904230863
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.567660592
Short name T484
Test name
Test status
Simulation time 56001429766 ps
CPU time 1391.1 seconds
Started Aug 04 04:42:45 PM PDT 24
Finished Aug 04 05:05:56 PM PDT 24
Peak memory 288276 kb
Host smart-65392508-5d1e-41e1-b6a2-556e3e849d93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567660592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.567660592
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2431221054
Short name T595
Test name
Test status
Simulation time 28900474436 ps
CPU time 1672.98 seconds
Started Aug 04 04:42:45 PM PDT 24
Finished Aug 04 05:10:38 PM PDT 24
Peak memory 283768 kb
Host smart-04ab2de7-9483-4576-abee-728e2fa5226e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431221054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2431221054
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3241667473
Short name T662
Test name
Test status
Simulation time 117723822176 ps
CPU time 498.22 seconds
Started Aug 04 04:42:43 PM PDT 24
Finished Aug 04 04:51:01 PM PDT 24
Peak memory 255372 kb
Host smart-b9ae4416-ce67-40d0-90a0-b5a3c481ffd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241667473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3241667473
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1349502646
Short name T704
Test name
Test status
Simulation time 331547267 ps
CPU time 7.99 seconds
Started Aug 04 04:42:44 PM PDT 24
Finished Aug 04 04:42:52 PM PDT 24
Peak memory 248272 kb
Host smart-89b3da92-30a7-40e5-ba41-b2d105d1d397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13495
02646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1349502646
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1635266350
Short name T518
Test name
Test status
Simulation time 451906858 ps
CPU time 27.35 seconds
Started Aug 04 04:42:43 PM PDT 24
Finished Aug 04 04:43:11 PM PDT 24
Peak memory 255848 kb
Host smart-0f71b917-84db-4b09-954d-c8e6ad305700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16352
66350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1635266350
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3131671958
Short name T10
Test name
Test status
Simulation time 436647091 ps
CPU time 24.8 seconds
Started Aug 04 04:42:47 PM PDT 24
Finished Aug 04 04:43:12 PM PDT 24
Peak memory 269788 kb
Host smart-97aa78f2-ff4e-4a53-ba24-ac42b88fdb06
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3131671958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3131671958
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2464293462
Short name T624
Test name
Test status
Simulation time 1868483596 ps
CPU time 31.11 seconds
Started Aug 04 04:42:41 PM PDT 24
Finished Aug 04 04:43:12 PM PDT 24
Peak memory 256380 kb
Host smart-47e7a110-d165-40a1-b0f2-830165a79913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24642
93462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2464293462
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3605661704
Short name T701
Test name
Test status
Simulation time 16893603316 ps
CPU time 828.13 seconds
Started Aug 04 04:44:31 PM PDT 24
Finished Aug 04 04:58:19 PM PDT 24
Peak memory 272844 kb
Host smart-69b7603b-ffc1-46da-aa31-cc08ca700d60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605661704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3605661704
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2738743254
Short name T388
Test name
Test status
Simulation time 1635213361 ps
CPU time 32.51 seconds
Started Aug 04 04:44:31 PM PDT 24
Finished Aug 04 04:45:03 PM PDT 24
Peak memory 256264 kb
Host smart-938f79b5-982f-4a06-9ce6-e4773eefafce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27387
43254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2738743254
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.622953696
Short name T458
Test name
Test status
Simulation time 606027886 ps
CPU time 24.12 seconds
Started Aug 04 04:44:31 PM PDT 24
Finished Aug 04 04:44:55 PM PDT 24
Peak memory 247808 kb
Host smart-15a7a763-a7f9-4907-b373-836b8ea6d315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62295
3696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.622953696
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.807659713
Short name T452
Test name
Test status
Simulation time 23523790000 ps
CPU time 696.58 seconds
Started Aug 04 04:44:35 PM PDT 24
Finished Aug 04 04:56:11 PM PDT 24
Peak memory 272300 kb
Host smart-708e85bb-3a0b-48c9-8966-5434c421bc7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807659713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.807659713
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3255150253
Short name T245
Test name
Test status
Simulation time 447181834 ps
CPU time 18.26 seconds
Started Aug 04 04:44:27 PM PDT 24
Finished Aug 04 04:44:46 PM PDT 24
Peak memory 248276 kb
Host smart-a9fb0f7f-acb4-408f-a75c-9dc6e1256a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32551
50253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3255150253
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3183608357
Short name T543
Test name
Test status
Simulation time 279614553 ps
CPU time 27.73 seconds
Started Aug 04 04:44:29 PM PDT 24
Finished Aug 04 04:44:57 PM PDT 24
Peak memory 248244 kb
Host smart-aa4783d2-5d94-4714-a235-5f12b3ea50d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31836
08357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3183608357
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1478880541
Short name T699
Test name
Test status
Simulation time 280203729 ps
CPU time 10.58 seconds
Started Aug 04 04:44:33 PM PDT 24
Finished Aug 04 04:44:43 PM PDT 24
Peak memory 248200 kb
Host smart-6539aead-4743-42d1-af22-3dbfe0a02165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14788
80541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1478880541
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2479853282
Short name T688
Test name
Test status
Simulation time 7962668298 ps
CPU time 51.06 seconds
Started Aug 04 04:44:30 PM PDT 24
Finished Aug 04 04:45:21 PM PDT 24
Peak memory 256524 kb
Host smart-b91a919b-05d3-4402-9d00-32182d73cddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24798
53282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2479853282
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1241865749
Short name T447
Test name
Test status
Simulation time 17250485092 ps
CPU time 1325.15 seconds
Started Aug 04 04:44:36 PM PDT 24
Finished Aug 04 05:06:41 PM PDT 24
Peak memory 288508 kb
Host smart-d5e8e78a-d8bd-4196-a57e-9bff7b1081f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241865749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1241865749
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.93259325
Short name T475
Test name
Test status
Simulation time 1842580769 ps
CPU time 76.21 seconds
Started Aug 04 04:44:34 PM PDT 24
Finished Aug 04 04:45:50 PM PDT 24
Peak memory 256220 kb
Host smart-dbdada59-0509-47d8-9b58-e671009e9849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93259
325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.93259325
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.263011777
Short name T660
Test name
Test status
Simulation time 3089146719 ps
CPU time 46.32 seconds
Started Aug 04 04:44:35 PM PDT 24
Finished Aug 04 04:45:21 PM PDT 24
Peak memory 256460 kb
Host smart-d08f9961-35b3-43e2-9f2a-8d67b157cba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26301
1777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.263011777
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3121074245
Short name T513
Test name
Test status
Simulation time 272364589938 ps
CPU time 1586.33 seconds
Started Aug 04 04:44:38 PM PDT 24
Finished Aug 04 05:11:05 PM PDT 24
Peak memory 288988 kb
Host smart-19934978-be28-4e03-837c-f095c45d5273
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121074245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3121074245
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2852482011
Short name T629
Test name
Test status
Simulation time 248006887 ps
CPU time 6.15 seconds
Started Aug 04 04:44:33 PM PDT 24
Finished Aug 04 04:44:40 PM PDT 24
Peak memory 248148 kb
Host smart-4f9b7469-be67-4a6e-a9ed-c0772d2aff3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28524
82011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2852482011
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1480271904
Short name T466
Test name
Test status
Simulation time 164005975 ps
CPU time 12.31 seconds
Started Aug 04 04:44:34 PM PDT 24
Finished Aug 04 04:44:46 PM PDT 24
Peak memory 255944 kb
Host smart-763f10df-16cc-4ff1-8cf6-e0d69aa6ee67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14802
71904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1480271904
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.4249091453
Short name T13
Test name
Test status
Simulation time 21394101 ps
CPU time 3 seconds
Started Aug 04 04:44:35 PM PDT 24
Finished Aug 04 04:44:38 PM PDT 24
Peak memory 239188 kb
Host smart-79398b07-1bbc-4932-b37e-87db4c188c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42490
91453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.4249091453
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.725227763
Short name T209
Test name
Test status
Simulation time 6255365957 ps
CPU time 50.87 seconds
Started Aug 04 04:44:35 PM PDT 24
Finished Aug 04 04:45:26 PM PDT 24
Peak memory 256060 kb
Host smart-d027c80e-a05d-4f78-9928-838796d627d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72522
7763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.725227763
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3874002823
Short name T411
Test name
Test status
Simulation time 77269819944 ps
CPU time 2469.27 seconds
Started Aug 04 04:44:40 PM PDT 24
Finished Aug 04 05:25:50 PM PDT 24
Peak memory 286404 kb
Host smart-fa6d6db2-38e8-48e0-a6c1-66f8691d7593
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874002823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3874002823
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.212188012
Short name T687
Test name
Test status
Simulation time 259038773 ps
CPU time 15.37 seconds
Started Aug 04 04:44:41 PM PDT 24
Finished Aug 04 04:44:56 PM PDT 24
Peak memory 253452 kb
Host smart-0be2cb65-9dfe-4a9d-a6ae-5ee5e8c1c65e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21218
8012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.212188012
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.704897420
Short name T344
Test name
Test status
Simulation time 13647322731 ps
CPU time 1255.74 seconds
Started Aug 04 04:44:44 PM PDT 24
Finished Aug 04 05:05:40 PM PDT 24
Peak memory 287832 kb
Host smart-cb9d18f0-d537-4e18-9a49-a6e9b2918d94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704897420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.704897420
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3931029449
Short name T365
Test name
Test status
Simulation time 19604686398 ps
CPU time 1346.46 seconds
Started Aug 04 04:44:43 PM PDT 24
Finished Aug 04 05:07:10 PM PDT 24
Peak memory 272784 kb
Host smart-e169701d-0726-4ce8-85f3-8126960e7857
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931029449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3931029449
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2127619583
Short name T472
Test name
Test status
Simulation time 2666613049 ps
CPU time 98.17 seconds
Started Aug 04 04:44:41 PM PDT 24
Finished Aug 04 04:46:19 PM PDT 24
Peak memory 247136 kb
Host smart-22e5a032-c76b-4fea-bcab-98437cd780df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127619583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2127619583
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1634421680
Short name T668
Test name
Test status
Simulation time 370096157 ps
CPU time 11.71 seconds
Started Aug 04 04:44:44 PM PDT 24
Finished Aug 04 04:44:55 PM PDT 24
Peak memory 255768 kb
Host smart-5682f86c-0ee7-4f62-9e79-dced2aaefdc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16344
21680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1634421680
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2789263636
Short name T623
Test name
Test status
Simulation time 49640958 ps
CPU time 6.37 seconds
Started Aug 04 04:44:41 PM PDT 24
Finished Aug 04 04:44:47 PM PDT 24
Peak memory 248216 kb
Host smart-9f1ebc36-088f-4d94-8594-1a5aa73607ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27892
63636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2789263636
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1242644273
Short name T117
Test name
Test status
Simulation time 299949049 ps
CPU time 29.4 seconds
Started Aug 04 04:44:41 PM PDT 24
Finished Aug 04 04:45:10 PM PDT 24
Peak memory 255508 kb
Host smart-28b44f68-9e7e-4f08-ac8e-6324163d5324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12426
44273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1242644273
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2096515731
Short name T499
Test name
Test status
Simulation time 4214527859 ps
CPU time 22 seconds
Started Aug 04 04:44:42 PM PDT 24
Finished Aug 04 04:45:04 PM PDT 24
Peak memory 256244 kb
Host smart-ff90d4eb-152b-4db0-9465-ef78ee302475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20965
15731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2096515731
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3273197008
Short name T101
Test name
Test status
Simulation time 34872868635 ps
CPU time 2177.78 seconds
Started Aug 04 04:44:41 PM PDT 24
Finished Aug 04 05:20:59 PM PDT 24
Peak memory 288148 kb
Host smart-cd0fad50-8f94-497f-83bc-23704400c294
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273197008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3273197008
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2032302347
Short name T459
Test name
Test status
Simulation time 110192648537 ps
CPU time 1688.36 seconds
Started Aug 04 04:44:45 PM PDT 24
Finished Aug 04 05:12:53 PM PDT 24
Peak memory 272292 kb
Host smart-27af8942-8a3d-4b56-b22e-9187593a37e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032302347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2032302347
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2590914120
Short name T197
Test name
Test status
Simulation time 621034269 ps
CPU time 35.26 seconds
Started Aug 04 04:44:43 PM PDT 24
Finished Aug 04 04:45:19 PM PDT 24
Peak memory 255744 kb
Host smart-b6e64f24-570e-4776-8577-a2850ae01da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25909
14120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2590914120
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1093236295
Short name T428
Test name
Test status
Simulation time 3836926078 ps
CPU time 53.52 seconds
Started Aug 04 04:44:45 PM PDT 24
Finished Aug 04 04:45:38 PM PDT 24
Peak memory 248280 kb
Host smart-47b0acc6-119f-48f8-a64b-708e553e433b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10932
36295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1093236295
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3915680791
Short name T352
Test name
Test status
Simulation time 25206136251 ps
CPU time 1686.24 seconds
Started Aug 04 04:44:44 PM PDT 24
Finished Aug 04 05:12:51 PM PDT 24
Peak memory 272820 kb
Host smart-ff05dc3a-9974-4e4a-a8f7-ff372cea3953
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915680791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3915680791
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3710387779
Short name T528
Test name
Test status
Simulation time 65148674510 ps
CPU time 1965.99 seconds
Started Aug 04 04:44:48 PM PDT 24
Finished Aug 04 05:17:34 PM PDT 24
Peak memory 283904 kb
Host smart-42e64622-de81-4c6b-97d0-2238f0b3d137
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710387779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3710387779
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1033361895
Short name T702
Test name
Test status
Simulation time 8552026970 ps
CPU time 244.91 seconds
Started Aug 04 04:44:48 PM PDT 24
Finished Aug 04 04:48:53 PM PDT 24
Peak memory 256076 kb
Host smart-d5b42d63-817c-4ba1-9321-9b223f6fa234
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033361895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1033361895
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.392396630
Short name T52
Test name
Test status
Simulation time 1029471177 ps
CPU time 34.18 seconds
Started Aug 04 04:44:48 PM PDT 24
Finished Aug 04 04:45:22 PM PDT 24
Peak memory 256076 kb
Host smart-43d7d211-f3e0-4030-999c-22b4fd44d837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39239
6630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.392396630
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1226354095
Short name T84
Test name
Test status
Simulation time 429075944 ps
CPU time 29.3 seconds
Started Aug 04 04:44:45 PM PDT 24
Finished Aug 04 04:45:14 PM PDT 24
Peak memory 248228 kb
Host smart-2c0e8359-af48-40b0-ae16-9b9857456833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12263
54095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1226354095
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3097941288
Short name T509
Test name
Test status
Simulation time 1056386647 ps
CPU time 27.12 seconds
Started Aug 04 04:44:48 PM PDT 24
Finished Aug 04 04:45:15 PM PDT 24
Peak memory 249220 kb
Host smart-27b159c7-36f6-4c4e-82ab-5951054c1de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30979
41288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3097941288
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2700016356
Short name T568
Test name
Test status
Simulation time 37832152 ps
CPU time 4.69 seconds
Started Aug 04 04:44:44 PM PDT 24
Finished Aug 04 04:44:49 PM PDT 24
Peak memory 251152 kb
Host smart-82bc8d68-16a3-494c-9635-665a801492ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27000
16356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2700016356
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3173841566
Short name T663
Test name
Test status
Simulation time 20027268761 ps
CPU time 1126.86 seconds
Started Aug 04 04:44:52 PM PDT 24
Finished Aug 04 05:03:39 PM PDT 24
Peak memory 288960 kb
Host smart-ea1fa996-f68e-4bc3-9673-000605af1efb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173841566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3173841566
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.604570018
Short name T416
Test name
Test status
Simulation time 989435314 ps
CPU time 25.28 seconds
Started Aug 04 04:44:50 PM PDT 24
Finished Aug 04 04:45:15 PM PDT 24
Peak memory 247856 kb
Host smart-13df8b19-67ba-42c4-8271-123f2f9452ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60457
0018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.604570018
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2623746383
Short name T300
Test name
Test status
Simulation time 43006238904 ps
CPU time 2844.88 seconds
Started Aug 04 04:44:53 PM PDT 24
Finished Aug 04 05:32:18 PM PDT 24
Peak memory 288380 kb
Host smart-ec83bd1b-ecf6-4f02-9857-88d1b105d973
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623746383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2623746383
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2516714040
Short name T421
Test name
Test status
Simulation time 78557363149 ps
CPU time 1127.34 seconds
Started Aug 04 04:44:52 PM PDT 24
Finished Aug 04 05:03:40 PM PDT 24
Peak memory 272712 kb
Host smart-b0504331-f03f-45e6-abff-9fe5865dc9f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516714040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2516714040
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1756222202
Short name T211
Test name
Test status
Simulation time 3089877234 ps
CPU time 120.97 seconds
Started Aug 04 04:44:52 PM PDT 24
Finished Aug 04 04:46:53 PM PDT 24
Peak memory 248324 kb
Host smart-b728fb4a-0601-4ced-a9b5-bc9786fa7609
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756222202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1756222202
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2422965406
Short name T236
Test name
Test status
Simulation time 803251290 ps
CPU time 17.36 seconds
Started Aug 04 04:44:49 PM PDT 24
Finished Aug 04 04:45:06 PM PDT 24
Peak memory 248184 kb
Host smart-040edd03-9685-4cd6-a095-987d0462161d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24229
65406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2422965406
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.591941709
Short name T601
Test name
Test status
Simulation time 2533629301 ps
CPU time 33.41 seconds
Started Aug 04 04:44:48 PM PDT 24
Finished Aug 04 04:45:21 PM PDT 24
Peak memory 256796 kb
Host smart-c4caebb2-65e3-4a50-bfef-91d99d28ece5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59194
1709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.591941709
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2804503821
Short name T446
Test name
Test status
Simulation time 504616010 ps
CPU time 34.08 seconds
Started Aug 04 04:44:47 PM PDT 24
Finished Aug 04 04:45:21 PM PDT 24
Peak memory 255492 kb
Host smart-19b77fc9-7a33-4aa5-b869-45908582df67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28045
03821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2804503821
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.4002581762
Short name T243
Test name
Test status
Simulation time 184815744 ps
CPU time 12.7 seconds
Started Aug 04 04:44:48 PM PDT 24
Finished Aug 04 04:45:01 PM PDT 24
Peak memory 254336 kb
Host smart-804bc9d9-1f31-4d60-ad00-822371b21259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40025
81762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.4002581762
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1540801914
Short name T62
Test name
Test status
Simulation time 246905915061 ps
CPU time 1727.11 seconds
Started Aug 04 04:44:56 PM PDT 24
Finished Aug 04 05:13:44 PM PDT 24
Peak memory 297412 kb
Host smart-befda8e8-abc2-4e2f-b505-d28c04f8c167
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540801914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1540801914
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.228286904
Short name T188
Test name
Test status
Simulation time 191653598357 ps
CPU time 3381.29 seconds
Started Aug 04 04:44:58 PM PDT 24
Finished Aug 04 05:41:19 PM PDT 24
Peak memory 322124 kb
Host smart-e5260c5a-69b3-490e-a364-9ffb7f6a0454
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228286904 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.228286904
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.723061951
Short name T303
Test name
Test status
Simulation time 40595314337 ps
CPU time 1169.03 seconds
Started Aug 04 04:45:02 PM PDT 24
Finished Aug 04 05:04:31 PM PDT 24
Peak memory 272780 kb
Host smart-84a1a521-daad-43e8-9219-5ba4574c672d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723061951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.723061951
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2664206959
Short name T655
Test name
Test status
Simulation time 7610659835 ps
CPU time 50.13 seconds
Started Aug 04 04:44:57 PM PDT 24
Finished Aug 04 04:45:47 PM PDT 24
Peak memory 256556 kb
Host smart-55ea7bb7-7b5b-4936-bc59-291763fb6d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26642
06959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2664206959
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.98650780
Short name T634
Test name
Test status
Simulation time 71737955 ps
CPU time 10.4 seconds
Started Aug 04 04:44:57 PM PDT 24
Finished Aug 04 04:45:08 PM PDT 24
Peak memory 247700 kb
Host smart-66bc6b8a-0076-464d-8197-c408b1d1e63c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98650
780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.98650780
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3838540194
Short name T317
Test name
Test status
Simulation time 161921040961 ps
CPU time 1117.53 seconds
Started Aug 04 04:45:02 PM PDT 24
Finished Aug 04 05:03:40 PM PDT 24
Peak memory 288792 kb
Host smart-315c5a65-288e-4087-bddd-654056213e50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838540194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3838540194
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1726062534
Short name T603
Test name
Test status
Simulation time 98140138009 ps
CPU time 1504.27 seconds
Started Aug 04 04:45:01 PM PDT 24
Finished Aug 04 05:10:06 PM PDT 24
Peak memory 264580 kb
Host smart-934f704e-3e29-4cd9-8bd1-75e7157538ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726062534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1726062534
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1152185641
Short name T630
Test name
Test status
Simulation time 6033376515 ps
CPU time 233.32 seconds
Started Aug 04 04:45:01 PM PDT 24
Finished Aug 04 04:48:54 PM PDT 24
Peak memory 248312 kb
Host smart-5e01bfeb-86e5-442b-a0bc-1d4e90260d52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152185641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1152185641
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.604680640
Short name T468
Test name
Test status
Simulation time 58089262 ps
CPU time 4.74 seconds
Started Aug 04 04:44:57 PM PDT 24
Finished Aug 04 04:45:02 PM PDT 24
Peak memory 248160 kb
Host smart-ff5075b4-6621-4b26-9e42-ab2065c41f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60468
0640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.604680640
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1234582025
Short name T599
Test name
Test status
Simulation time 3413227980 ps
CPU time 57.82 seconds
Started Aug 04 04:44:56 PM PDT 24
Finished Aug 04 04:45:54 PM PDT 24
Peak memory 248064 kb
Host smart-21ca7ea0-54f0-451b-9d5b-47d4411a8449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12345
82025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1234582025
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.347517024
Short name T277
Test name
Test status
Simulation time 159252592 ps
CPU time 25.65 seconds
Started Aug 04 04:44:56 PM PDT 24
Finished Aug 04 04:45:22 PM PDT 24
Peak memory 248312 kb
Host smart-5f874b31-fbf6-4601-b88a-bf026305e1b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34751
7024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.347517024
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2650573516
Short name T394
Test name
Test status
Simulation time 1355205161 ps
CPU time 35.3 seconds
Started Aug 04 04:44:56 PM PDT 24
Finished Aug 04 04:45:31 PM PDT 24
Peak memory 256400 kb
Host smart-e43b52e1-ac6c-4d3b-b22a-bfbb9fd2c145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26505
73516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2650573516
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2853214910
Short name T566
Test name
Test status
Simulation time 13145870562 ps
CPU time 307.53 seconds
Started Aug 04 04:45:00 PM PDT 24
Finished Aug 04 04:50:08 PM PDT 24
Peak memory 272928 kb
Host smart-50650f36-35ee-4a1d-8407-97d6fef42b96
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853214910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2853214910
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.199336185
Short name T454
Test name
Test status
Simulation time 53468691052 ps
CPU time 849.06 seconds
Started Aug 04 04:45:00 PM PDT 24
Finished Aug 04 04:59:09 PM PDT 24
Peak memory 272364 kb
Host smart-e5d77482-3d3e-4c0a-9d9a-b954fcb1873d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199336185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.199336185
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3843719253
Short name T584
Test name
Test status
Simulation time 12429447422 ps
CPU time 171.05 seconds
Started Aug 04 04:45:02 PM PDT 24
Finished Aug 04 04:47:53 PM PDT 24
Peak memory 256544 kb
Host smart-46f0229c-e375-4a50-9713-7ed80b89c9d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38437
19253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3843719253
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.2962093683
Short name T207
Test name
Test status
Simulation time 1815420887 ps
CPU time 35.17 seconds
Started Aug 04 04:45:00 PM PDT 24
Finished Aug 04 04:45:36 PM PDT 24
Peak memory 248240 kb
Host smart-9bf344ff-0d4f-43e6-a7d9-f88b3430b6eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29620
93683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2962093683
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2063883812
Short name T360
Test name
Test status
Simulation time 41538394178 ps
CPU time 1332.87 seconds
Started Aug 04 04:45:02 PM PDT 24
Finished Aug 04 05:07:15 PM PDT 24
Peak memory 283528 kb
Host smart-9d6cc6d8-bf21-43e6-92d9-1ba52941c4d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063883812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2063883812
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2066031485
Short name T425
Test name
Test status
Simulation time 64066831999 ps
CPU time 1032.58 seconds
Started Aug 04 04:45:01 PM PDT 24
Finished Aug 04 05:02:14 PM PDT 24
Peak memory 272320 kb
Host smart-07d8a4eb-2c4c-4556-8dc9-b59b6f520683
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066031485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2066031485
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2628259444
Short name T190
Test name
Test status
Simulation time 24643513449 ps
CPU time 494.19 seconds
Started Aug 04 04:45:00 PM PDT 24
Finished Aug 04 04:53:14 PM PDT 24
Peak memory 248280 kb
Host smart-3bb89f89-de3e-4535-a02a-73d543b4337d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628259444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2628259444
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3991568575
Short name T706
Test name
Test status
Simulation time 1760330841 ps
CPU time 32.73 seconds
Started Aug 04 04:45:01 PM PDT 24
Finished Aug 04 04:45:33 PM PDT 24
Peak memory 248200 kb
Host smart-01a95af5-9ca9-4361-a591-9337eb08251e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39915
68575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3991568575
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.464350878
Short name T259
Test name
Test status
Simulation time 318924316 ps
CPU time 35.22 seconds
Started Aug 04 04:45:01 PM PDT 24
Finished Aug 04 04:45:36 PM PDT 24
Peak memory 247896 kb
Host smart-c073b758-ba11-4574-b02e-e598a4e607f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46435
0878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.464350878
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.746809202
Short name T75
Test name
Test status
Simulation time 324469662 ps
CPU time 34.28 seconds
Started Aug 04 04:45:02 PM PDT 24
Finished Aug 04 04:45:36 PM PDT 24
Peak memory 256376 kb
Host smart-36e14d50-2e69-4ec4-8307-04ef28532f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74680
9202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.746809202
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.173917450
Short name T392
Test name
Test status
Simulation time 12594678353 ps
CPU time 35.71 seconds
Started Aug 04 04:45:01 PM PDT 24
Finished Aug 04 04:45:37 PM PDT 24
Peak memory 255752 kb
Host smart-38daf6ad-e3cb-4512-a1e5-43f692fd79fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17391
7450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.173917450
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.4022608208
Short name T69
Test name
Test status
Simulation time 36172769182 ps
CPU time 951.45 seconds
Started Aug 04 04:45:01 PM PDT 24
Finished Aug 04 05:00:53 PM PDT 24
Peak memory 272548 kb
Host smart-03c3565e-8c39-4101-acef-7aea39fb3c6a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022608208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.4022608208
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3253858957
Short name T462
Test name
Test status
Simulation time 13307374786 ps
CPU time 1048.98 seconds
Started Aug 04 04:45:10 PM PDT 24
Finished Aug 04 05:02:39 PM PDT 24
Peak memory 285908 kb
Host smart-813eab81-43bf-4756-95ae-b0fc8b3cb77b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253858957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3253858957
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.369163063
Short name T482
Test name
Test status
Simulation time 4488099707 ps
CPU time 268.92 seconds
Started Aug 04 04:45:06 PM PDT 24
Finished Aug 04 04:49:35 PM PDT 24
Peak memory 256016 kb
Host smart-c3db7d7c-257d-471f-b869-69b0baa46d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36916
3063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.369163063
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2265045416
Short name T632
Test name
Test status
Simulation time 380585110 ps
CPU time 23.2 seconds
Started Aug 04 04:45:05 PM PDT 24
Finished Aug 04 04:45:28 PM PDT 24
Peak memory 247852 kb
Host smart-18f3b061-b720-4777-9794-d75e63c443e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22650
45416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2265045416
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3026116758
Short name T366
Test name
Test status
Simulation time 21691374848 ps
CPU time 1455.46 seconds
Started Aug 04 04:45:10 PM PDT 24
Finished Aug 04 05:09:26 PM PDT 24
Peak memory 288628 kb
Host smart-e29db8cd-aecd-44d4-bf8e-631d5ac7fee8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026116758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3026116758
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3592656183
Short name T464
Test name
Test status
Simulation time 64636129481 ps
CPU time 2604.13 seconds
Started Aug 04 04:45:11 PM PDT 24
Finished Aug 04 05:28:35 PM PDT 24
Peak memory 288616 kb
Host smart-a7ada566-78fa-489e-9b67-3c88b3bf33eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592656183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3592656183
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1708637950
Short name T212
Test name
Test status
Simulation time 9111749529 ps
CPU time 394.91 seconds
Started Aug 04 04:45:11 PM PDT 24
Finished Aug 04 04:51:46 PM PDT 24
Peak memory 256360 kb
Host smart-0a6e7135-e1c8-459f-a853-6a3ea9882b4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708637950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1708637950
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2167818240
Short name T596
Test name
Test status
Simulation time 561970011 ps
CPU time 15.9 seconds
Started Aug 04 04:45:06 PM PDT 24
Finished Aug 04 04:45:23 PM PDT 24
Peak memory 248320 kb
Host smart-ce04a4a4-a3c7-444b-9ec0-1dad70a4a035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21678
18240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2167818240
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.760934172
Short name T42
Test name
Test status
Simulation time 2044290427 ps
CPU time 35.25 seconds
Started Aug 04 04:45:05 PM PDT 24
Finished Aug 04 04:45:41 PM PDT 24
Peak memory 255892 kb
Host smart-49778b4a-d496-4644-ab32-53994506f384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76093
4172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.760934172
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.4220367665
Short name T625
Test name
Test status
Simulation time 498415162 ps
CPU time 27.49 seconds
Started Aug 04 04:45:07 PM PDT 24
Finished Aug 04 04:45:35 PM PDT 24
Peak memory 248292 kb
Host smart-f2e4ef95-defe-46d6-be92-cdd0d8045f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42203
67665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.4220367665
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3513551511
Short name T680
Test name
Test status
Simulation time 100114736405 ps
CPU time 3157.59 seconds
Started Aug 04 04:45:11 PM PDT 24
Finished Aug 04 05:37:49 PM PDT 24
Peak memory 289116 kb
Host smart-3849d16a-41f1-4877-9d3f-8dc822686633
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513551511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3513551511
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1506087847
Short name T609
Test name
Test status
Simulation time 47535252142 ps
CPU time 1136.9 seconds
Started Aug 04 04:45:15 PM PDT 24
Finished Aug 04 05:04:12 PM PDT 24
Peak memory 289120 kb
Host smart-510819e3-73c1-4f9d-afb7-e3a833291567
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506087847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1506087847
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1489931261
Short name T579
Test name
Test status
Simulation time 7636061639 ps
CPU time 118.95 seconds
Started Aug 04 04:45:16 PM PDT 24
Finished Aug 04 04:47:15 PM PDT 24
Peak memory 256256 kb
Host smart-c99940f7-5ad3-4cbd-8b72-b86b7764fd4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14899
31261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1489931261
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1126697425
Short name T715
Test name
Test status
Simulation time 304635314 ps
CPU time 19.57 seconds
Started Aug 04 04:45:10 PM PDT 24
Finished Aug 04 04:45:29 PM PDT 24
Peak memory 248188 kb
Host smart-b2a5b042-1b34-4ee4-9686-a5b4d8ed8cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11266
97425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1126697425
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3660210831
Short name T364
Test name
Test status
Simulation time 50367146153 ps
CPU time 1073.7 seconds
Started Aug 04 04:45:14 PM PDT 24
Finished Aug 04 05:03:08 PM PDT 24
Peak memory 287324 kb
Host smart-d7c95806-022c-4b3d-86a9-15d532f9abe2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660210831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3660210831
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1489679657
Short name T534
Test name
Test status
Simulation time 2385486319 ps
CPU time 35.96 seconds
Started Aug 04 04:45:11 PM PDT 24
Finished Aug 04 04:45:47 PM PDT 24
Peak memory 256252 kb
Host smart-749ec48c-e459-469d-bd04-f06f3d3462d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14896
79657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1489679657
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.4110942061
Short name T399
Test name
Test status
Simulation time 858117463 ps
CPU time 47.86 seconds
Started Aug 04 04:45:12 PM PDT 24
Finished Aug 04 04:46:00 PM PDT 24
Peak memory 248244 kb
Host smart-cb465064-7c76-45b8-9bdc-c889544cbfe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41109
42061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.4110942061
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2310908296
Short name T247
Test name
Test status
Simulation time 1155070928 ps
CPU time 6.46 seconds
Started Aug 04 04:45:16 PM PDT 24
Finished Aug 04 04:45:22 PM PDT 24
Peak memory 251512 kb
Host smart-0c6d3ad1-124a-4385-a831-0ef8b16dc3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23109
08296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2310908296
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.542758841
Short name T72
Test name
Test status
Simulation time 410434051 ps
CPU time 26.07 seconds
Started Aug 04 04:45:12 PM PDT 24
Finished Aug 04 04:45:38 PM PDT 24
Peak memory 255660 kb
Host smart-4bfb7ebf-e777-434b-942e-fb5b2064c2f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54275
8841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.542758841
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.782533914
Short name T54
Test name
Test status
Simulation time 46937464950 ps
CPU time 1188.06 seconds
Started Aug 04 04:45:15 PM PDT 24
Finished Aug 04 05:05:03 PM PDT 24
Peak memory 289140 kb
Host smart-e4889e0a-cbec-474a-9d75-0f1801cbb17f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782533914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.782533914
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.2834773337
Short name T99
Test name
Test status
Simulation time 94828304963 ps
CPU time 4252.27 seconds
Started Aug 04 04:45:15 PM PDT 24
Finished Aug 04 05:56:08 PM PDT 24
Peak memory 321788 kb
Host smart-c2ebee7f-6ff0-44b9-a771-4a5dc6502fe2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834773337 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.2834773337
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.1587420389
Short name T114
Test name
Test status
Simulation time 30203328218 ps
CPU time 1751.6 seconds
Started Aug 04 04:45:20 PM PDT 24
Finished Aug 04 05:14:32 PM PDT 24
Peak memory 273156 kb
Host smart-e01ebe72-c329-48ca-91b3-b77e4759b061
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587420389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1587420389
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1526701090
Short name T73
Test name
Test status
Simulation time 3728443211 ps
CPU time 198.32 seconds
Started Aug 04 04:45:22 PM PDT 24
Finished Aug 04 04:48:41 PM PDT 24
Peak memory 256128 kb
Host smart-e954ea66-3e7d-4179-985f-7ea7595ae292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15267
01090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1526701090
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3062584247
Short name T511
Test name
Test status
Simulation time 2022884632 ps
CPU time 35.98 seconds
Started Aug 04 04:45:19 PM PDT 24
Finished Aug 04 04:45:55 PM PDT 24
Peak memory 255708 kb
Host smart-a32d03e2-027d-42fc-a11e-5a0bb75209aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30625
84247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3062584247
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1381884476
Short name T342
Test name
Test status
Simulation time 133046627261 ps
CPU time 1874.68 seconds
Started Aug 04 04:45:22 PM PDT 24
Finished Aug 04 05:16:37 PM PDT 24
Peak memory 281440 kb
Host smart-ecb428b3-5688-49bf-abf4-e0d1727a0648
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381884476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1381884476
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1879943806
Short name T621
Test name
Test status
Simulation time 107354498493 ps
CPU time 1908.68 seconds
Started Aug 04 04:45:20 PM PDT 24
Finished Aug 04 05:17:09 PM PDT 24
Peak memory 280984 kb
Host smart-0e58c97f-cf56-4919-8424-d9067346ea35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879943806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1879943806
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3370235617
Short name T348
Test name
Test status
Simulation time 13367627443 ps
CPU time 133.48 seconds
Started Aug 04 04:45:22 PM PDT 24
Finished Aug 04 04:47:35 PM PDT 24
Peak memory 254072 kb
Host smart-1fa2c433-58f5-4df8-8984-4683c9dd56da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370235617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3370235617
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.804145795
Short name T244
Test name
Test status
Simulation time 1285298831 ps
CPU time 35.02 seconds
Started Aug 04 04:45:21 PM PDT 24
Finished Aug 04 04:45:56 PM PDT 24
Peak memory 248252 kb
Host smart-332942d5-9c77-4424-8426-e8b0ed4b7291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80414
5795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.804145795
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3350060727
Short name T563
Test name
Test status
Simulation time 3031457528 ps
CPU time 42.5 seconds
Started Aug 04 04:45:21 PM PDT 24
Finished Aug 04 04:46:03 PM PDT 24
Peak memory 247976 kb
Host smart-12c5dae8-87ce-449e-b373-88e84949eb1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33500
60727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3350060727
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3704496618
Short name T290
Test name
Test status
Simulation time 286541081 ps
CPU time 18.15 seconds
Started Aug 04 04:45:20 PM PDT 24
Finished Aug 04 04:45:39 PM PDT 24
Peak memory 247544 kb
Host smart-45ec9815-2364-4d2d-acd5-7b7410c3dd25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37044
96618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3704496618
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2124929746
Short name T502
Test name
Test status
Simulation time 3343023224 ps
CPU time 25.87 seconds
Started Aug 04 04:45:21 PM PDT 24
Finished Aug 04 04:45:47 PM PDT 24
Peak memory 256424 kb
Host smart-e28537ba-616f-42a7-a7e9-bd9b99a7e6c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21249
29746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2124929746
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3872599929
Short name T286
Test name
Test status
Simulation time 117684905376 ps
CPU time 1797.29 seconds
Started Aug 04 04:45:22 PM PDT 24
Finished Aug 04 05:15:19 PM PDT 24
Peak memory 288500 kb
Host smart-6cdd2e1e-6061-4ea2-bcb7-2de62019e65c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872599929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3872599929
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2953390789
Short name T585
Test name
Test status
Simulation time 77706724343 ps
CPU time 2258.7 seconds
Started Aug 04 04:45:22 PM PDT 24
Finished Aug 04 05:23:01 PM PDT 24
Peak memory 299544 kb
Host smart-0d2512ac-fff6-4625-913a-eaecd85d1ffd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953390789 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2953390789
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.622028613
Short name T221
Test name
Test status
Simulation time 154238280 ps
CPU time 3.56 seconds
Started Aug 04 04:42:55 PM PDT 24
Finished Aug 04 04:42:58 PM PDT 24
Peak memory 248532 kb
Host smart-0e519162-fc7b-4363-b933-ca2cfcf85d7d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=622028613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.622028613
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.964210931
Short name T606
Test name
Test status
Simulation time 37551328759 ps
CPU time 2415.83 seconds
Started Aug 04 04:42:50 PM PDT 24
Finished Aug 04 05:23:06 PM PDT 24
Peak memory 288884 kb
Host smart-ce5a7b6a-326b-422a-9811-52da97990503
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964210931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.964210931
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1859069946
Short name T396
Test name
Test status
Simulation time 1252865729 ps
CPU time 51.92 seconds
Started Aug 04 04:42:56 PM PDT 24
Finished Aug 04 04:43:48 PM PDT 24
Peak memory 248220 kb
Host smart-604def12-0b67-492b-8b90-2ccd71be58dc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1859069946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1859069946
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2681379285
Short name T620
Test name
Test status
Simulation time 6947251628 ps
CPU time 79.08 seconds
Started Aug 04 04:42:51 PM PDT 24
Finished Aug 04 04:44:10 PM PDT 24
Peak memory 255812 kb
Host smart-cd56703b-7faa-4477-beae-11ac017fec01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26813
79285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2681379285
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3359339271
Short name T514
Test name
Test status
Simulation time 72346208 ps
CPU time 5.21 seconds
Started Aug 04 04:42:50 PM PDT 24
Finished Aug 04 04:42:55 PM PDT 24
Peak memory 247864 kb
Host smart-02a87542-b0ce-43e5-9346-a7614660a147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33593
39271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3359339271
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2918758275
Short name T255
Test name
Test status
Simulation time 17313917949 ps
CPU time 1327.62 seconds
Started Aug 04 04:42:56 PM PDT 24
Finished Aug 04 05:05:04 PM PDT 24
Peak memory 289120 kb
Host smart-9463ceb5-3d41-4f0b-99ec-793ed725c825
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918758275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2918758275
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1879942815
Short name T192
Test name
Test status
Simulation time 27888425507 ps
CPU time 665.45 seconds
Started Aug 04 04:42:54 PM PDT 24
Finished Aug 04 04:53:59 PM PDT 24
Peak memory 272784 kb
Host smart-1501e95f-17c2-4463-92d7-c59672ef8a82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879942815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1879942815
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3452452687
Short name T501
Test name
Test status
Simulation time 25194723691 ps
CPU time 552.1 seconds
Started Aug 04 04:42:54 PM PDT 24
Finished Aug 04 04:52:06 PM PDT 24
Peak memory 248176 kb
Host smart-f9cc1a0b-6ea3-4f44-b33d-e5a97d7683ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452452687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3452452687
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.4076939651
Short name T539
Test name
Test status
Simulation time 5191770915 ps
CPU time 46.49 seconds
Started Aug 04 04:42:47 PM PDT 24
Finished Aug 04 04:43:34 PM PDT 24
Peak memory 255600 kb
Host smart-5fba2606-4c78-4f1b-b20d-82290b6c4527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40769
39651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.4076939651
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.4153070134
Short name T57
Test name
Test status
Simulation time 1145699319 ps
CPU time 63.65 seconds
Started Aug 04 04:42:51 PM PDT 24
Finished Aug 04 04:43:55 PM PDT 24
Peak memory 247840 kb
Host smart-59dafff1-4bfd-463a-a907-4e17ae3ba91a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41530
70134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.4153070134
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.4050234092
Short name T37
Test name
Test status
Simulation time 1250115892 ps
CPU time 19.52 seconds
Started Aug 04 04:42:57 PM PDT 24
Finished Aug 04 04:43:16 PM PDT 24
Peak memory 278120 kb
Host smart-92f328a4-892c-4fed-a5db-281341da90e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4050234092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.4050234092
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3705075096
Short name T311
Test name
Test status
Simulation time 1036122557 ps
CPU time 32.47 seconds
Started Aug 04 04:42:50 PM PDT 24
Finished Aug 04 04:43:23 PM PDT 24
Peak memory 248156 kb
Host smart-b28ed7e4-0cea-4e64-a7a5-529a67a6c3f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37050
75096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3705075096
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3723885505
Short name T648
Test name
Test status
Simulation time 1362726309 ps
CPU time 34.25 seconds
Started Aug 04 04:42:48 PM PDT 24
Finished Aug 04 04:43:23 PM PDT 24
Peak memory 248264 kb
Host smart-a4608587-708f-4f85-9e9d-0e13085e246f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37238
85505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3723885505
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1090025743
Short name T427
Test name
Test status
Simulation time 586238577 ps
CPU time 32.69 seconds
Started Aug 04 04:42:54 PM PDT 24
Finished Aug 04 04:43:27 PM PDT 24
Peak memory 256220 kb
Host smart-f8fed028-7430-4f87-a4d2-3f2f4dd4c91e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090025743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1090025743
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2194557010
Short name T314
Test name
Test status
Simulation time 143085322298 ps
CPU time 2076.84 seconds
Started Aug 04 04:45:24 PM PDT 24
Finished Aug 04 05:20:01 PM PDT 24
Peak memory 285776 kb
Host smart-042c88e5-8c9e-41d3-90dd-a6850e9a8e4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194557010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2194557010
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1553111
Short name T555
Test name
Test status
Simulation time 2486076700 ps
CPU time 149.65 seconds
Started Aug 04 04:45:21 PM PDT 24
Finished Aug 04 04:47:51 PM PDT 24
Peak memory 256032 kb
Host smart-9d2a99b1-e309-405d-9a95-12f2f4e1ae10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15531
11 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1553111
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2421652077
Short name T89
Test name
Test status
Simulation time 333884336 ps
CPU time 15.01 seconds
Started Aug 04 04:45:20 PM PDT 24
Finished Aug 04 04:45:35 PM PDT 24
Peak memory 247784 kb
Host smart-d76cf94c-d833-43b7-b7cb-03b8ae6f6457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24216
52077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2421652077
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2329127290
Short name T368
Test name
Test status
Simulation time 20431731256 ps
CPU time 1559.28 seconds
Started Aug 04 04:45:24 PM PDT 24
Finished Aug 04 05:11:23 PM PDT 24
Peak memory 287952 kb
Host smart-a8043185-5876-4045-be02-e9ce35ac67f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329127290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2329127290
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3899298852
Short name T519
Test name
Test status
Simulation time 17350055736 ps
CPU time 1189.96 seconds
Started Aug 04 04:45:25 PM PDT 24
Finished Aug 04 05:05:15 PM PDT 24
Peak memory 272584 kb
Host smart-fb072813-d4a3-4271-84ed-7ed05ad1c471
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899298852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3899298852
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2015360528
Short name T322
Test name
Test status
Simulation time 142406270528 ps
CPU time 499.23 seconds
Started Aug 04 04:45:24 PM PDT 24
Finished Aug 04 04:53:44 PM PDT 24
Peak memory 254764 kb
Host smart-86e4ec8f-2eec-45a9-b2c9-e258676d133e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015360528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2015360528
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.624438124
Short name T412
Test name
Test status
Simulation time 585323635 ps
CPU time 11.83 seconds
Started Aug 04 04:45:22 PM PDT 24
Finished Aug 04 04:45:33 PM PDT 24
Peak memory 248140 kb
Host smart-d398f0eb-30f0-47a7-afc8-cfbfeb901545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62443
8124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.624438124
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2928532606
Short name T657
Test name
Test status
Simulation time 359838661 ps
CPU time 22.93 seconds
Started Aug 04 04:45:21 PM PDT 24
Finished Aug 04 04:45:44 PM PDT 24
Peak memory 248212 kb
Host smart-770c7b2e-fccd-4743-82d7-01347c9a3a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29285
32606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2928532606
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.2780655115
Short name T698
Test name
Test status
Simulation time 1325424452 ps
CPU time 51.3 seconds
Started Aug 04 04:45:22 PM PDT 24
Finished Aug 04 04:46:13 PM PDT 24
Peak memory 248316 kb
Host smart-752d4ef2-7124-40ea-967e-aad7bf4c6f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27806
55115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2780655115
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.4146121749
Short name T12
Test name
Test status
Simulation time 1525800808 ps
CPU time 27.43 seconds
Started Aug 04 04:45:22 PM PDT 24
Finished Aug 04 04:45:50 PM PDT 24
Peak memory 256360 kb
Host smart-8a0e8d21-cdcc-40e7-8b98-4aaa849a159a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41461
21749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.4146121749
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3381096864
Short name T588
Test name
Test status
Simulation time 55745904118 ps
CPU time 1190.54 seconds
Started Aug 04 04:45:25 PM PDT 24
Finished Aug 04 05:05:15 PM PDT 24
Peak memory 288748 kb
Host smart-7f4975be-eeca-4b34-9786-af3c14563ab8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381096864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3381096864
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.290981861
Short name T51
Test name
Test status
Simulation time 38593987597 ps
CPU time 3744.1 seconds
Started Aug 04 04:45:23 PM PDT 24
Finished Aug 04 05:47:48 PM PDT 24
Peak memory 321572 kb
Host smart-01725525-a69a-437d-9419-5f50a2746bc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290981861 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.290981861
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.654857554
Short name T444
Test name
Test status
Simulation time 4519391698 ps
CPU time 498.65 seconds
Started Aug 04 04:45:30 PM PDT 24
Finished Aug 04 04:53:49 PM PDT 24
Peak memory 272568 kb
Host smart-180f42d3-473b-40f1-ba52-f4aed6ea238b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654857554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.654857554
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.912292840
Short name T389
Test name
Test status
Simulation time 17599530122 ps
CPU time 254.34 seconds
Started Aug 04 04:45:24 PM PDT 24
Finished Aug 04 04:49:38 PM PDT 24
Peak memory 256408 kb
Host smart-f9ade1de-37c9-4691-aacb-eca95819f974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91229
2840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.912292840
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3113707480
Short name T535
Test name
Test status
Simulation time 245617802 ps
CPU time 23.17 seconds
Started Aug 04 04:45:25 PM PDT 24
Finished Aug 04 04:45:48 PM PDT 24
Peak memory 255700 kb
Host smart-718501b0-2cf3-4a3b-bfd6-45770ac7961a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31137
07480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3113707480
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1597691877
Short name T354
Test name
Test status
Simulation time 200001902081 ps
CPU time 2911.47 seconds
Started Aug 04 04:45:28 PM PDT 24
Finished Aug 04 05:34:00 PM PDT 24
Peak memory 288656 kb
Host smart-dff39f77-948e-4b1a-8bb4-b39d1fc65cb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597691877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1597691877
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3873611008
Short name T633
Test name
Test status
Simulation time 100805275855 ps
CPU time 3023.52 seconds
Started Aug 04 04:45:29 PM PDT 24
Finished Aug 04 05:35:53 PM PDT 24
Peak memory 288488 kb
Host smart-ac32fa80-463c-4ce2-bf39-b9d61b85b283
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873611008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3873611008
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1064114132
Short name T330
Test name
Test status
Simulation time 30656324060 ps
CPU time 303.08 seconds
Started Aug 04 04:45:30 PM PDT 24
Finished Aug 04 04:50:33 PM PDT 24
Peak memory 248348 kb
Host smart-4acb1606-09ee-4f5f-af4d-d5d7120960e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064114132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1064114132
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3737243828
Short name T631
Test name
Test status
Simulation time 300488538 ps
CPU time 26.8 seconds
Started Aug 04 04:45:25 PM PDT 24
Finished Aug 04 04:45:51 PM PDT 24
Peak memory 255748 kb
Host smart-fd4e5fdd-c019-4e83-91ce-f691b431163f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37372
43828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3737243828
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.4139759212
Short name T553
Test name
Test status
Simulation time 454616112 ps
CPU time 38.21 seconds
Started Aug 04 04:45:23 PM PDT 24
Finished Aug 04 04:46:02 PM PDT 24
Peak memory 248260 kb
Host smart-b68cf0ea-7722-4ddb-9601-4e7f31f997e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41397
59212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.4139759212
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.414953825
Short name T78
Test name
Test status
Simulation time 649956060 ps
CPU time 39.41 seconds
Started Aug 04 04:45:24 PM PDT 24
Finished Aug 04 04:46:04 PM PDT 24
Peak memory 255772 kb
Host smart-8465e795-724b-4166-be02-fd92cbde15d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41495
3825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.414953825
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1157320083
Short name T241
Test name
Test status
Simulation time 606887320 ps
CPU time 29.51 seconds
Started Aug 04 04:45:24 PM PDT 24
Finished Aug 04 04:45:54 PM PDT 24
Peak memory 256344 kb
Host smart-e9e5bf5b-dc7f-4e6a-9813-8a79edcaecbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11573
20083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1157320083
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3907160654
Short name T562
Test name
Test status
Simulation time 40325876578 ps
CPU time 1515.5 seconds
Started Aug 04 04:45:29 PM PDT 24
Finished Aug 04 05:10:45 PM PDT 24
Peak memory 288500 kb
Host smart-2b5812c0-6998-486e-a1e8-b52be9bcb4e1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907160654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3907160654
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.4179600162
Short name T63
Test name
Test status
Simulation time 65321348506 ps
CPU time 1803.09 seconds
Started Aug 04 04:45:34 PM PDT 24
Finished Aug 04 05:15:37 PM PDT 24
Peak memory 272688 kb
Host smart-ebcbd035-2e8a-4853-9a2f-d0b5b7503565
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179600162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.4179600162
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.4280480791
Short name T664
Test name
Test status
Simulation time 324885235 ps
CPU time 21.97 seconds
Started Aug 04 04:45:32 PM PDT 24
Finished Aug 04 04:45:54 PM PDT 24
Peak memory 255720 kb
Host smart-1bdd5f40-4f1b-42ba-b72d-e9812d8f6a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42804
80791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.4280480791
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.4153249500
Short name T463
Test name
Test status
Simulation time 766886366 ps
CPU time 16.84 seconds
Started Aug 04 04:45:29 PM PDT 24
Finished Aug 04 04:45:45 PM PDT 24
Peak memory 248100 kb
Host smart-e347c073-2caf-4f1c-9594-8638d8b67e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41532
49500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.4153249500
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1109829435
Short name T41
Test name
Test status
Simulation time 30414791336 ps
CPU time 1794.08 seconds
Started Aug 04 04:45:32 PM PDT 24
Finished Aug 04 05:15:26 PM PDT 24
Peak memory 271844 kb
Host smart-aeae79f9-2830-4cd6-a8ce-ee7b4a4c0002
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109829435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1109829435
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.362750366
Short name T647
Test name
Test status
Simulation time 32020973661 ps
CPU time 2096.37 seconds
Started Aug 04 04:45:32 PM PDT 24
Finished Aug 04 05:20:29 PM PDT 24
Peak memory 285028 kb
Host smart-dfbea94f-c21a-4cc7-a631-71010ba5e2b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362750366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.362750366
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3620806203
Short name T70
Test name
Test status
Simulation time 240357607 ps
CPU time 23.63 seconds
Started Aug 04 04:45:30 PM PDT 24
Finished Aug 04 04:45:54 PM PDT 24
Peak memory 255928 kb
Host smart-2f725965-7ba8-466d-87a0-9ed57826cea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36208
06203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3620806203
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.808901422
Short name T707
Test name
Test status
Simulation time 560601318 ps
CPU time 32.65 seconds
Started Aug 04 04:45:33 PM PDT 24
Finished Aug 04 04:46:05 PM PDT 24
Peak memory 248264 kb
Host smart-e5c7772d-6514-4481-97cf-c9d0d88ac426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80890
1422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.808901422
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3074358856
Short name T708
Test name
Test status
Simulation time 9488778648 ps
CPU time 40.94 seconds
Started Aug 04 04:45:28 PM PDT 24
Finished Aug 04 04:46:09 PM PDT 24
Peak memory 248268 kb
Host smart-c223f03c-1b42-4c41-aeae-6b1a0ca03d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30743
58856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3074358856
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1803611891
Short name T450
Test name
Test status
Simulation time 497379181 ps
CPU time 30.09 seconds
Started Aug 04 04:45:39 PM PDT 24
Finished Aug 04 04:46:09 PM PDT 24
Peak memory 248136 kb
Host smart-45bd4b40-3f3f-4ef1-9ee0-3589ed321d41
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803611891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1803611891
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.2374474200
Short name T105
Test name
Test status
Simulation time 44720939949 ps
CPU time 2659.77 seconds
Started Aug 04 04:45:36 PM PDT 24
Finished Aug 04 05:29:57 PM PDT 24
Peak memory 321300 kb
Host smart-35a41e52-71c3-4f73-b345-d7df9d914d3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374474200 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.2374474200
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.989061567
Short name T119
Test name
Test status
Simulation time 43110380952 ps
CPU time 2647.73 seconds
Started Aug 04 04:45:40 PM PDT 24
Finished Aug 04 05:29:49 PM PDT 24
Peak memory 289200 kb
Host smart-6cdbe919-3289-42dd-b11d-240684f902f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989061567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.989061567
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3597006403
Short name T387
Test name
Test status
Simulation time 3120604736 ps
CPU time 72.01 seconds
Started Aug 04 04:45:39 PM PDT 24
Finished Aug 04 04:46:52 PM PDT 24
Peak memory 255976 kb
Host smart-abc63e4e-88a0-45c9-8cfa-28d7cff4aa14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35970
06403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3597006403
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.878408092
Short name T426
Test name
Test status
Simulation time 322964606 ps
CPU time 26.91 seconds
Started Aug 04 04:45:37 PM PDT 24
Finished Aug 04 04:46:04 PM PDT 24
Peak memory 248176 kb
Host smart-17c7cf32-8386-4fce-b752-52db8b6e7bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87840
8092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.878408092
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1134643560
Short name T451
Test name
Test status
Simulation time 13295223623 ps
CPU time 1247.29 seconds
Started Aug 04 04:45:41 PM PDT 24
Finished Aug 04 05:06:28 PM PDT 24
Peak memory 288588 kb
Host smart-c8f7b5ee-d793-4158-9565-4e6c2a20ed94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134643560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1134643560
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2037472513
Short name T557
Test name
Test status
Simulation time 39809029318 ps
CPU time 122.33 seconds
Started Aug 04 04:45:40 PM PDT 24
Finished Aug 04 04:47:43 PM PDT 24
Peak memory 248352 kb
Host smart-8800a8e5-c051-4aa6-9b0d-91e7d61730b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037472513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2037472513
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.805185257
Short name T242
Test name
Test status
Simulation time 186264616 ps
CPU time 4.98 seconds
Started Aug 04 04:45:37 PM PDT 24
Finished Aug 04 04:45:42 PM PDT 24
Peak memory 248288 kb
Host smart-09b01db7-4915-4be8-b1fd-8f47912d234d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80518
5257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.805185257
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2499708620
Short name T695
Test name
Test status
Simulation time 3627151863 ps
CPU time 57.87 seconds
Started Aug 04 04:45:37 PM PDT 24
Finished Aug 04 04:46:35 PM PDT 24
Peak memory 248444 kb
Host smart-76f63969-9476-4ff9-adc5-712bf2a18f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24997
08620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2499708620
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.318228681
Short name T642
Test name
Test status
Simulation time 64976342 ps
CPU time 8.53 seconds
Started Aug 04 04:46:05 PM PDT 24
Finished Aug 04 04:46:13 PM PDT 24
Peak memory 254396 kb
Host smart-e64fffe7-8b59-4277-97b1-88bd779d5533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31822
8681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.318228681
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2043782428
Short name T580
Test name
Test status
Simulation time 4186232898 ps
CPU time 70.59 seconds
Started Aug 04 04:45:40 PM PDT 24
Finished Aug 04 04:46:50 PM PDT 24
Peak memory 255488 kb
Host smart-a0b4b503-9413-414e-88d4-0a62d451a31f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20437
82428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2043782428
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3671918783
Short name T191
Test name
Test status
Simulation time 97008392228 ps
CPU time 1508.49 seconds
Started Aug 04 04:45:48 PM PDT 24
Finished Aug 04 05:10:57 PM PDT 24
Peak memory 289176 kb
Host smart-db3cd6cc-47e5-4866-8568-e505dbc2c393
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671918783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3671918783
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.778099888
Short name T652
Test name
Test status
Simulation time 189275082 ps
CPU time 13.06 seconds
Started Aug 04 04:45:52 PM PDT 24
Finished Aug 04 04:46:05 PM PDT 24
Peak memory 254352 kb
Host smart-f4ec9a66-c621-4b38-a962-3fa84b3f17f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77809
9888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.778099888
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1162275418
Short name T400
Test name
Test status
Simulation time 945070770 ps
CPU time 30.86 seconds
Started Aug 04 04:45:49 PM PDT 24
Finished Aug 04 04:46:20 PM PDT 24
Peak memory 247648 kb
Host smart-64960c38-f47a-4f01-906a-1dd183c4e220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11622
75418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1162275418
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.774703581
Short name T80
Test name
Test status
Simulation time 52274286515 ps
CPU time 2019.95 seconds
Started Aug 04 04:45:51 PM PDT 24
Finished Aug 04 05:19:31 PM PDT 24
Peak memory 283664 kb
Host smart-df766c4e-985f-47c8-a9f0-12f4db203f36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774703581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.774703581
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.45363792
Short name T350
Test name
Test status
Simulation time 38752742296 ps
CPU time 402.55 seconds
Started Aug 04 04:45:48 PM PDT 24
Finished Aug 04 04:52:31 PM PDT 24
Peak memory 248088 kb
Host smart-f0ace1c5-b1ef-4cf0-b5a2-3ef556eb15e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45363792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.45363792
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3939210319
Short name T656
Test name
Test status
Simulation time 1606482833 ps
CPU time 14.41 seconds
Started Aug 04 04:45:45 PM PDT 24
Finished Aug 04 04:46:00 PM PDT 24
Peak memory 255472 kb
Host smart-e02cd0f3-7de0-424f-9c2e-2049926db114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39392
10319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3939210319
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1836888405
Short name T521
Test name
Test status
Simulation time 125016472 ps
CPU time 10.29 seconds
Started Aug 04 04:45:43 PM PDT 24
Finished Aug 04 04:45:54 PM PDT 24
Peak memory 248316 kb
Host smart-97891bb3-857e-4007-8c06-1ce8c6e28b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18368
88405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1836888405
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3620048631
Short name T615
Test name
Test status
Simulation time 193330596 ps
CPU time 21.4 seconds
Started Aug 04 04:45:49 PM PDT 24
Finished Aug 04 04:46:10 PM PDT 24
Peak memory 255640 kb
Host smart-75cab8bf-e86b-49c5-b479-a66f1b2eba84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36200
48631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3620048631
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.793115768
Short name T407
Test name
Test status
Simulation time 376839338 ps
CPU time 20.69 seconds
Started Aug 04 04:45:43 PM PDT 24
Finished Aug 04 04:46:04 PM PDT 24
Peak memory 256396 kb
Host smart-93c14c43-1212-407d-bd72-799b9c0216c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79311
5768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.793115768
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.4172756027
Short name T55
Test name
Test status
Simulation time 53489681922 ps
CPU time 1485.36 seconds
Started Aug 04 04:45:52 PM PDT 24
Finished Aug 04 05:10:38 PM PDT 24
Peak memory 298280 kb
Host smart-4ae84a21-394c-4063-9cab-e94c00e5f29d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172756027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.4172756027
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2803052455
Short name T626
Test name
Test status
Simulation time 156714560488 ps
CPU time 2057.01 seconds
Started Aug 04 04:45:54 PM PDT 24
Finished Aug 04 05:20:11 PM PDT 24
Peak memory 272348 kb
Host smart-67f8fede-2e07-40f3-aaa2-43ac5575b61f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803052455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2803052455
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.601376101
Short name T268
Test name
Test status
Simulation time 2792529551 ps
CPU time 124.58 seconds
Started Aug 04 04:45:53 PM PDT 24
Finished Aug 04 04:47:57 PM PDT 24
Peak memory 256020 kb
Host smart-956ae534-af1e-4f0f-9059-c3ebbff49265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60137
6101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.601376101
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2343792621
Short name T88
Test name
Test status
Simulation time 97794680 ps
CPU time 8.07 seconds
Started Aug 04 04:46:00 PM PDT 24
Finished Aug 04 04:46:08 PM PDT 24
Peak memory 247756 kb
Host smart-25b1b20f-173d-4aeb-81ec-116d320ef9a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23437
92621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2343792621
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.346742557
Short name T547
Test name
Test status
Simulation time 614940305246 ps
CPU time 2135.85 seconds
Started Aug 04 04:46:00 PM PDT 24
Finished Aug 04 05:21:36 PM PDT 24
Peak memory 281752 kb
Host smart-d6ef3f1c-92a8-4e1d-94d9-7b14302684d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346742557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.346742557
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1896590823
Short name T418
Test name
Test status
Simulation time 118924413164 ps
CPU time 1789.13 seconds
Started Aug 04 04:46:00 PM PDT 24
Finished Aug 04 05:15:49 PM PDT 24
Peak memory 272468 kb
Host smart-385cb50a-aae4-4cf4-b010-fcd5f61ded9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896590823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1896590823
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3005500685
Short name T18
Test name
Test status
Simulation time 8433972880 ps
CPU time 335.56 seconds
Started Aug 04 04:45:54 PM PDT 24
Finished Aug 04 04:51:29 PM PDT 24
Peak memory 248320 kb
Host smart-89547c2f-c083-47b8-9161-2fd70d4e06a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005500685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3005500685
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3968217735
Short name T569
Test name
Test status
Simulation time 2183190584 ps
CPU time 34.98 seconds
Started Aug 04 04:45:53 PM PDT 24
Finished Aug 04 04:46:28 PM PDT 24
Peak memory 255668 kb
Host smart-65923e8c-a27b-448a-83fd-2c1156d8c497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39682
17735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3968217735
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.439682750
Short name T253
Test name
Test status
Simulation time 519997297 ps
CPU time 5.15 seconds
Started Aug 04 04:45:59 PM PDT 24
Finished Aug 04 04:46:04 PM PDT 24
Peak memory 239344 kb
Host smart-4ff6ab8f-e808-4e5a-94a2-9cfe222280ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43968
2750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.439682750
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3973649926
Short name T59
Test name
Test status
Simulation time 205490996 ps
CPU time 7.1 seconds
Started Aug 04 04:45:54 PM PDT 24
Finished Aug 04 04:46:01 PM PDT 24
Peak memory 247828 kb
Host smart-e6ec3788-0273-4923-b857-fa53ec0b9ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39736
49926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3973649926
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1366933042
Short name T541
Test name
Test status
Simulation time 1737529093 ps
CPU time 73.94 seconds
Started Aug 04 04:46:05 PM PDT 24
Finished Aug 04 04:47:19 PM PDT 24
Peak memory 256320 kb
Host smart-71f45b68-4fd4-41f5-9d51-34dacd1c6d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13669
33042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1366933042
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1747755097
Short name T239
Test name
Test status
Simulation time 9652690448 ps
CPU time 1093.5 seconds
Started Aug 04 04:46:00 PM PDT 24
Finished Aug 04 05:04:13 PM PDT 24
Peak memory 272484 kb
Host smart-ebb3709f-9353-4ba8-997e-628884026cbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747755097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1747755097
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2677303213
Short name T529
Test name
Test status
Simulation time 4534853623 ps
CPU time 84.59 seconds
Started Aug 04 04:46:00 PM PDT 24
Finished Aug 04 04:47:24 PM PDT 24
Peak memory 256084 kb
Host smart-ddd9b16f-4f64-4448-9f88-f2c64d8be4db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26773
03213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2677303213
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3900397173
Short name T432
Test name
Test status
Simulation time 662639110 ps
CPU time 31.37 seconds
Started Aug 04 04:45:56 PM PDT 24
Finished Aug 04 04:46:27 PM PDT 24
Peak memory 247784 kb
Host smart-a48d3b19-5320-4461-9ada-347846fef9b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39003
97173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3900397173
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2885930029
Short name T434
Test name
Test status
Simulation time 30286731283 ps
CPU time 825.73 seconds
Started Aug 04 04:46:01 PM PDT 24
Finished Aug 04 04:59:46 PM PDT 24
Peak memory 272888 kb
Host smart-07f4c5aa-1734-4736-83ee-c038582489a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885930029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2885930029
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.781588023
Short name T254
Test name
Test status
Simulation time 4771435014 ps
CPU time 199.02 seconds
Started Aug 04 04:46:01 PM PDT 24
Finished Aug 04 04:49:20 PM PDT 24
Peak memory 248344 kb
Host smart-54dbfc7d-549d-4c46-b374-718d926c84cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781588023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.781588023
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.887330051
Short name T397
Test name
Test status
Simulation time 388623810 ps
CPU time 35.18 seconds
Started Aug 04 04:45:58 PM PDT 24
Finished Aug 04 04:46:33 PM PDT 24
Peak memory 255844 kb
Host smart-c1ad69d9-6980-4200-bb9d-b778c45587eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88733
0051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.887330051
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.455907267
Short name T645
Test name
Test status
Simulation time 4451828705 ps
CPU time 62.31 seconds
Started Aug 04 04:45:57 PM PDT 24
Finished Aug 04 04:46:59 PM PDT 24
Peak memory 247876 kb
Host smart-d0056ac7-5979-4eb1-a343-9a698e6161ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45590
7267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.455907267
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.284423087
Short name T677
Test name
Test status
Simulation time 11241774515 ps
CPU time 48.95 seconds
Started Aug 04 04:46:00 PM PDT 24
Finished Aug 04 04:46:49 PM PDT 24
Peak memory 248236 kb
Host smart-950f597a-1588-42dd-b16d-f1bee6b7b367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28442
3087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.284423087
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.14249004
Short name T554
Test name
Test status
Simulation time 1685222470 ps
CPU time 12.15 seconds
Started Aug 04 04:45:55 PM PDT 24
Finished Aug 04 04:46:07 PM PDT 24
Peak memory 248280 kb
Host smart-dc71b6cc-563b-4ad8-bb5e-895cd1e85db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14249
004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.14249004
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3423505808
Short name T608
Test name
Test status
Simulation time 1194971079 ps
CPU time 21.04 seconds
Started Aug 04 04:46:07 PM PDT 24
Finished Aug 04 04:46:28 PM PDT 24
Peak memory 255056 kb
Host smart-aad4de50-b79f-427e-b8a5-5832a3f8e8ab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423505808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3423505808
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1864578428
Short name T58
Test name
Test status
Simulation time 39835299851 ps
CPU time 3550.5 seconds
Started Aug 04 04:46:05 PM PDT 24
Finished Aug 04 05:45:16 PM PDT 24
Peak memory 322108 kb
Host smart-d9433cef-8daf-49ab-a5bf-55b76ea3a02f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864578428 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1864578428
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.499123213
Short name T310
Test name
Test status
Simulation time 33044060639 ps
CPU time 2006.48 seconds
Started Aug 04 04:46:06 PM PDT 24
Finished Aug 04 05:19:33 PM PDT 24
Peak memory 284084 kb
Host smart-89d3b46b-9737-468f-b60d-455216bffcb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499123213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.499123213
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3176040552
Short name T692
Test name
Test status
Simulation time 156300136 ps
CPU time 6.13 seconds
Started Aug 04 04:46:06 PM PDT 24
Finished Aug 04 04:46:12 PM PDT 24
Peak memory 239576 kb
Host smart-be5ba9e3-22b7-4472-8cd1-b3cb767ff455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31760
40552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3176040552
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3516749834
Short name T269
Test name
Test status
Simulation time 1279958313 ps
CPU time 71 seconds
Started Aug 04 04:46:07 PM PDT 24
Finished Aug 04 04:47:18 PM PDT 24
Peak memory 248312 kb
Host smart-0089aba0-5082-40a4-b145-ab8dfff5e1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35167
49834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3516749834
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.4172572043
Short name T362
Test name
Test status
Simulation time 223740627068 ps
CPU time 3144.43 seconds
Started Aug 04 04:46:13 PM PDT 24
Finished Aug 04 05:38:38 PM PDT 24
Peak memory 288928 kb
Host smart-64fca481-5781-4efe-a60f-d9eeab127fdf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172572043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.4172572043
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.556598117
Short name T293
Test name
Test status
Simulation time 80494321919 ps
CPU time 2056.71 seconds
Started Aug 04 04:46:10 PM PDT 24
Finished Aug 04 05:20:27 PM PDT 24
Peak memory 272700 kb
Host smart-f525eaf9-e6ae-4b1c-ae7c-bd6c4c78c59f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556598117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.556598117
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2001367685
Short name T328
Test name
Test status
Simulation time 15379255386 ps
CPU time 165.68 seconds
Started Aug 04 04:46:07 PM PDT 24
Finished Aug 04 04:48:53 PM PDT 24
Peak memory 254732 kb
Host smart-003d6be4-0e9a-4bd3-bb78-410415add39d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001367685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2001367685
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.4046051142
Short name T94
Test name
Test status
Simulation time 1586135295 ps
CPU time 30.01 seconds
Started Aug 04 04:46:02 PM PDT 24
Finished Aug 04 04:46:32 PM PDT 24
Peak memory 255616 kb
Host smart-61d636aa-6218-458b-8b1d-8174063049d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40460
51142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.4046051142
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1619985531
Short name T24
Test name
Test status
Simulation time 117645153 ps
CPU time 15.48 seconds
Started Aug 04 04:46:07 PM PDT 24
Finished Aug 04 04:46:23 PM PDT 24
Peak memory 247912 kb
Host smart-fcd290d7-d6d2-4c65-a4dd-90532ff87f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16199
85531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1619985531
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3291878769
Short name T487
Test name
Test status
Simulation time 1395242287 ps
CPU time 38.73 seconds
Started Aug 04 04:46:11 PM PDT 24
Finished Aug 04 04:46:50 PM PDT 24
Peak memory 247464 kb
Host smart-61c32a08-a96c-4329-8231-c06fa3bbb94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32918
78769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3291878769
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2780864711
Short name T646
Test name
Test status
Simulation time 8389964802 ps
CPU time 57.25 seconds
Started Aug 04 04:46:04 PM PDT 24
Finished Aug 04 04:47:01 PM PDT 24
Peak memory 248372 kb
Host smart-4b258b06-02d5-4e6a-8dde-072e59adf94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27808
64711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2780864711
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1913877393
Short name T690
Test name
Test status
Simulation time 83208618238 ps
CPU time 1361.14 seconds
Started Aug 04 04:46:13 PM PDT 24
Finished Aug 04 05:08:55 PM PDT 24
Peak memory 288504 kb
Host smart-dd65ab43-66e0-415e-864e-1f7699218816
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913877393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1913877393
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.4166219932
Short name T671
Test name
Test status
Simulation time 54863318947 ps
CPU time 4948.86 seconds
Started Aug 04 04:46:10 PM PDT 24
Finished Aug 04 06:08:39 PM PDT 24
Peak memory 320984 kb
Host smart-f34cb46b-118c-4149-85a9-a60769305a55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166219932 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.4166219932
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3508416428
Short name T64
Test name
Test status
Simulation time 25272267534 ps
CPU time 1334.6 seconds
Started Aug 04 04:46:13 PM PDT 24
Finished Aug 04 05:08:28 PM PDT 24
Peak memory 272640 kb
Host smart-72ae53cb-76e9-458d-bded-6c3f5c5255dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508416428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3508416428
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.876037266
Short name T65
Test name
Test status
Simulation time 3132505506 ps
CPU time 232 seconds
Started Aug 04 04:46:14 PM PDT 24
Finished Aug 04 04:50:06 PM PDT 24
Peak memory 256500 kb
Host smart-17d038fa-9943-4250-92e3-da7f87f7b36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87603
7266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.876037266
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.123606258
Short name T589
Test name
Test status
Simulation time 1709906671 ps
CPU time 26.25 seconds
Started Aug 04 04:46:14 PM PDT 24
Finished Aug 04 04:46:40 PM PDT 24
Peak memory 248148 kb
Host smart-b7384474-91ab-46d0-910c-2062c3eb552a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12360
6258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.123606258
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1912668780
Short name T457
Test name
Test status
Simulation time 207120319091 ps
CPU time 2824.25 seconds
Started Aug 04 04:46:16 PM PDT 24
Finished Aug 04 05:33:21 PM PDT 24
Peak memory 288568 kb
Host smart-8abf4651-ce93-472a-9767-19f97a998fb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912668780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1912668780
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2237961047
Short name T705
Test name
Test status
Simulation time 8147395427 ps
CPU time 353.24 seconds
Started Aug 04 04:46:13 PM PDT 24
Finished Aug 04 04:52:07 PM PDT 24
Peak memory 248212 kb
Host smart-3e16c639-800f-4137-b1f9-8c6b7ddf02a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237961047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2237961047
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.785019479
Short name T395
Test name
Test status
Simulation time 263357179 ps
CPU time 16.52 seconds
Started Aug 04 04:46:11 PM PDT 24
Finished Aug 04 04:46:28 PM PDT 24
Peak memory 248208 kb
Host smart-dfbb56de-018b-4318-8c43-b5be5f796d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78501
9479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.785019479
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3416205241
Short name T478
Test name
Test status
Simulation time 166518223 ps
CPU time 16.57 seconds
Started Aug 04 04:46:14 PM PDT 24
Finished Aug 04 04:46:31 PM PDT 24
Peak memory 255436 kb
Host smart-3d9e62d0-9dd5-488b-b11a-f57a3b54db0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34162
05241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3416205241
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2405575258
Short name T613
Test name
Test status
Simulation time 12855079380 ps
CPU time 37.43 seconds
Started Aug 04 04:46:14 PM PDT 24
Finished Aug 04 04:46:52 PM PDT 24
Peak memory 255564 kb
Host smart-714e3129-1ba2-4ea2-b6fe-045ee0ffc218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24055
75258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2405575258
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3149833525
Short name T669
Test name
Test status
Simulation time 14311281994 ps
CPU time 1241.73 seconds
Started Aug 04 04:46:16 PM PDT 24
Finished Aug 04 05:06:58 PM PDT 24
Peak memory 281080 kb
Host smart-f8275bc7-87ed-4b9f-860e-32f4db84da0c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149833525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3149833525
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.856131148
Short name T714
Test name
Test status
Simulation time 27366901817 ps
CPU time 1426.31 seconds
Started Aug 04 04:46:17 PM PDT 24
Finished Aug 04 05:10:03 PM PDT 24
Peak memory 272724 kb
Host smart-714116e9-2d05-4cfb-b553-08f1dd49f480
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856131148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.856131148
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3875393133
Short name T685
Test name
Test status
Simulation time 4890186141 ps
CPU time 136.78 seconds
Started Aug 04 04:46:15 PM PDT 24
Finished Aug 04 04:48:32 PM PDT 24
Peak memory 256488 kb
Host smart-4a5d5bb5-c65a-4ad9-9679-8da6bce01a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38753
93133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3875393133
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1244070235
Short name T92
Test name
Test status
Simulation time 959478625 ps
CPU time 25.66 seconds
Started Aug 04 04:46:16 PM PDT 24
Finished Aug 04 04:46:42 PM PDT 24
Peak memory 247872 kb
Host smart-21146b5e-7df9-4bd6-98bd-af642533b7d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12440
70235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1244070235
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2620549728
Short name T703
Test name
Test status
Simulation time 83398288734 ps
CPU time 2276.04 seconds
Started Aug 04 04:46:19 PM PDT 24
Finished Aug 04 05:24:15 PM PDT 24
Peak memory 289204 kb
Host smart-ca15b92f-5d3b-480a-bb95-38aca75083f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620549728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2620549728
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1794063509
Short name T522
Test name
Test status
Simulation time 43735462906 ps
CPU time 2691.05 seconds
Started Aug 04 04:46:17 PM PDT 24
Finished Aug 04 05:31:09 PM PDT 24
Peak memory 288684 kb
Host smart-6e0941fe-6cdd-4bc6-8789-a3876e04a424
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794063509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1794063509
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1432507600
Short name T326
Test name
Test status
Simulation time 17053391161 ps
CPU time 222.83 seconds
Started Aug 04 04:46:16 PM PDT 24
Finished Aug 04 04:49:59 PM PDT 24
Peak memory 247196 kb
Host smart-2c6223f8-e764-4d5c-9a43-25df43571249
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432507600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1432507600
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.4266222206
Short name T717
Test name
Test status
Simulation time 1138354364 ps
CPU time 33.9 seconds
Started Aug 04 04:46:13 PM PDT 24
Finished Aug 04 04:46:47 PM PDT 24
Peak memory 248148 kb
Host smart-25f3a3a6-3372-46a3-83cd-45fcaff68f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42662
22206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.4266222206
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2296033030
Short name T307
Test name
Test status
Simulation time 2090780799 ps
CPU time 48.33 seconds
Started Aug 04 04:46:15 PM PDT 24
Finished Aug 04 04:47:03 PM PDT 24
Peak memory 248172 kb
Host smart-6d55d805-e4de-442a-b935-394f9d0ecd7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22960
33030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2296033030
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2711809173
Short name T507
Test name
Test status
Simulation time 1562246927 ps
CPU time 20.82 seconds
Started Aug 04 04:46:17 PM PDT 24
Finished Aug 04 04:46:38 PM PDT 24
Peak memory 255008 kb
Host smart-3809dbd9-4a0b-4344-be86-afc0160f8c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27118
09173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2711809173
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2337819570
Short name T525
Test name
Test status
Simulation time 547354475 ps
CPU time 30.44 seconds
Started Aug 04 04:46:16 PM PDT 24
Finished Aug 04 04:46:47 PM PDT 24
Peak memory 248256 kb
Host smart-9d94c11d-b976-4718-83ca-32eb2a0f11bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23378
19570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2337819570
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1226552303
Short name T5
Test name
Test status
Simulation time 14141159223 ps
CPU time 443.56 seconds
Started Aug 04 04:46:16 PM PDT 24
Finished Aug 04 04:53:40 PM PDT 24
Peak memory 264736 kb
Host smart-1320461e-7b4e-41d6-9644-46c243f2b2e8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226552303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1226552303
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3233910597
Short name T234
Test name
Test status
Simulation time 49469029 ps
CPU time 3.79 seconds
Started Aug 04 04:43:05 PM PDT 24
Finished Aug 04 04:43:09 PM PDT 24
Peak memory 248384 kb
Host smart-d464feed-4d03-4965-af03-cfe673898ff1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3233910597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3233910597
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3874481500
Short name T592
Test name
Test status
Simulation time 72842501145 ps
CPU time 1647.45 seconds
Started Aug 04 04:43:00 PM PDT 24
Finished Aug 04 05:10:28 PM PDT 24
Peak memory 288016 kb
Host smart-3fcb2cee-f3cc-42b7-a31c-5c763fe1c551
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874481500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3874481500
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3518145638
Short name T414
Test name
Test status
Simulation time 850084647 ps
CPU time 21.46 seconds
Started Aug 04 04:43:05 PM PDT 24
Finished Aug 04 04:43:26 PM PDT 24
Peak memory 248236 kb
Host smart-cf18ad17-d1a3-47a3-9dbc-cc4610f8af51
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3518145638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3518145638
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3447913199
Short name T604
Test name
Test status
Simulation time 8877483489 ps
CPU time 271.47 seconds
Started Aug 04 04:42:58 PM PDT 24
Finished Aug 04 04:47:30 PM PDT 24
Peak memory 256460 kb
Host smart-1c917d3a-9ae9-4a9c-b350-c2d95b0a28f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34479
13199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3447913199
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3507521846
Short name T510
Test name
Test status
Simulation time 526287981 ps
CPU time 36.95 seconds
Started Aug 04 04:42:57 PM PDT 24
Finished Aug 04 04:43:34 PM PDT 24
Peak memory 248060 kb
Host smart-866d0173-a033-4cc9-a316-680eca279da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35075
21846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3507521846
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1751320097
Short name T195
Test name
Test status
Simulation time 89496540085 ps
CPU time 1343.54 seconds
Started Aug 04 04:43:02 PM PDT 24
Finished Aug 04 05:05:26 PM PDT 24
Peak memory 272240 kb
Host smart-1e03432a-5a42-42fc-bb09-69f788df664f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751320097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1751320097
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.4074534318
Short name T301
Test name
Test status
Simulation time 105180951186 ps
CPU time 2940.39 seconds
Started Aug 04 04:43:02 PM PDT 24
Finished Aug 04 05:32:03 PM PDT 24
Peak memory 287528 kb
Host smart-89ee0187-5500-4e59-a048-da4b3f2ca3b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074534318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.4074534318
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.37173145
Short name T336
Test name
Test status
Simulation time 34979505375 ps
CPU time 246.71 seconds
Started Aug 04 04:43:00 PM PDT 24
Finished Aug 04 04:47:07 PM PDT 24
Peak memory 248288 kb
Host smart-e6bdac02-dcf6-4550-acd1-d672b4b17afc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37173145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.37173145
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.517914017
Short name T456
Test name
Test status
Simulation time 307197902 ps
CPU time 25.88 seconds
Started Aug 04 04:42:59 PM PDT 24
Finished Aug 04 04:43:25 PM PDT 24
Peak memory 248320 kb
Host smart-5322fc7a-a3dd-4364-ab5b-56f06a37526b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51791
4017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.517914017
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1924851633
Short name T120
Test name
Test status
Simulation time 555430809 ps
CPU time 8.51 seconds
Started Aug 04 04:42:57 PM PDT 24
Finished Aug 04 04:43:06 PM PDT 24
Peak memory 251452 kb
Host smart-d0e688c9-a94b-421d-8c2a-a72ecc45eda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19248
51633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1924851633
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1861294743
Short name T583
Test name
Test status
Simulation time 487643929 ps
CPU time 21.13 seconds
Started Aug 04 04:42:58 PM PDT 24
Finished Aug 04 04:43:20 PM PDT 24
Peak memory 256288 kb
Host smart-47a97e39-8af5-43d5-8f21-4c3ff254a47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18612
94743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1861294743
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2555943080
Short name T82
Test name
Test status
Simulation time 1483760124 ps
CPU time 43.12 seconds
Started Aug 04 04:43:06 PM PDT 24
Finished Aug 04 04:43:49 PM PDT 24
Peak memory 255640 kb
Host smart-355dc782-7c82-46e8-a535-bad29571a21d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555943080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2555943080
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.782257877
Short name T103
Test name
Test status
Simulation time 29397375544 ps
CPU time 1581.76 seconds
Started Aug 04 04:43:05 PM PDT 24
Finished Aug 04 05:09:27 PM PDT 24
Peak memory 297596 kb
Host smart-1745d6e3-6485-442f-8f60-7c6c313e52c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782257877 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.782257877
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1358089224
Short name T491
Test name
Test status
Simulation time 30357153475 ps
CPU time 1468.12 seconds
Started Aug 04 04:46:20 PM PDT 24
Finished Aug 04 05:10:49 PM PDT 24
Peak memory 287892 kb
Host smart-fb5f87a9-e9c4-4514-9761-5be3b671b050
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358089224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1358089224
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.632442488
Short name T476
Test name
Test status
Simulation time 3868194535 ps
CPU time 168.53 seconds
Started Aug 04 04:46:21 PM PDT 24
Finished Aug 04 04:49:09 PM PDT 24
Peak memory 256472 kb
Host smart-08a7931c-6a2a-4255-bf75-8fa6edc88258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63244
2488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.632442488
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3321062311
Short name T709
Test name
Test status
Simulation time 1163220962 ps
CPU time 19.43 seconds
Started Aug 04 04:46:20 PM PDT 24
Finished Aug 04 04:46:40 PM PDT 24
Peak memory 248324 kb
Host smart-8d9bf997-47d7-4fec-b1d5-699e7d2d8c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33210
62311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3321062311
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1600337292
Short name T693
Test name
Test status
Simulation time 233693010526 ps
CPU time 1635.69 seconds
Started Aug 04 04:46:21 PM PDT 24
Finished Aug 04 05:13:37 PM PDT 24
Peak memory 281388 kb
Host smart-5e58dbc6-3d6f-4610-94a9-707a39354362
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600337292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1600337292
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.4217216175
Short name T347
Test name
Test status
Simulation time 3044893304 ps
CPU time 115.67 seconds
Started Aug 04 04:46:22 PM PDT 24
Finished Aug 04 04:48:17 PM PDT 24
Peak memory 247136 kb
Host smart-635ef4c5-f49a-4d67-b4c2-ed545f89a0ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217216175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.4217216175
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3942283907
Short name T256
Test name
Test status
Simulation time 1321036558 ps
CPU time 51.37 seconds
Started Aug 04 04:46:17 PM PDT 24
Finished Aug 04 04:47:09 PM PDT 24
Peak memory 255004 kb
Host smart-9a8f667c-8b1b-41fb-b005-b96f6e1116b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39422
83907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3942283907
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3007113968
Short name T401
Test name
Test status
Simulation time 727885351 ps
CPU time 8.68 seconds
Started Aug 04 04:46:22 PM PDT 24
Finished Aug 04 04:46:31 PM PDT 24
Peak memory 247728 kb
Host smart-ef4398e0-daa5-42a7-a17f-836569eace6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30071
13968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3007113968
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2872420502
Short name T83
Test name
Test status
Simulation time 1244682656 ps
CPU time 29.3 seconds
Started Aug 04 04:46:21 PM PDT 24
Finished Aug 04 04:46:51 PM PDT 24
Peak memory 248228 kb
Host smart-00d09ccf-80c6-4bcd-bfa5-827a6dcdf5f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28724
20502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2872420502
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3653141257
Short name T410
Test name
Test status
Simulation time 3762142885 ps
CPU time 57.86 seconds
Started Aug 04 04:46:16 PM PDT 24
Finished Aug 04 04:47:14 PM PDT 24
Peak memory 248320 kb
Host smart-8d3c02c3-7905-4949-8fcd-11d02f652d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36531
41257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3653141257
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1176219771
Short name T294
Test name
Test status
Simulation time 736528982649 ps
CPU time 2310.54 seconds
Started Aug 04 04:46:25 PM PDT 24
Finished Aug 04 05:24:56 PM PDT 24
Peak memory 288800 kb
Host smart-0b55877a-ff86-4ec2-8b33-1dd44e63168d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176219771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1176219771
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.692662242
Short name T628
Test name
Test status
Simulation time 25529768310 ps
CPU time 667.85 seconds
Started Aug 04 04:46:31 PM PDT 24
Finished Aug 04 04:57:39 PM PDT 24
Peak memory 272816 kb
Host smart-db00db25-bfc1-49b4-a05c-5453a37338c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692662242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.692662242
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2339594769
Short name T498
Test name
Test status
Simulation time 6424610162 ps
CPU time 88.44 seconds
Started Aug 04 04:46:30 PM PDT 24
Finished Aug 04 04:47:59 PM PDT 24
Peak memory 255664 kb
Host smart-9b2e0fd1-a3db-4632-a2dc-77d28149d7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23395
94769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2339594769
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.234872321
Short name T474
Test name
Test status
Simulation time 418015183 ps
CPU time 27.96 seconds
Started Aug 04 04:46:30 PM PDT 24
Finished Aug 04 04:46:58 PM PDT 24
Peak memory 255716 kb
Host smart-6130ad21-817b-4698-a9fb-9b82b75965f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23487
2321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.234872321
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2704454266
Short name T325
Test name
Test status
Simulation time 48160626360 ps
CPU time 2616.5 seconds
Started Aug 04 04:46:31 PM PDT 24
Finished Aug 04 05:30:08 PM PDT 24
Peak memory 289060 kb
Host smart-c7178375-004a-433d-8899-4853ce523abb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704454266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2704454266
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2379805465
Short name T565
Test name
Test status
Simulation time 175444434655 ps
CPU time 1382.32 seconds
Started Aug 04 04:46:31 PM PDT 24
Finished Aug 04 05:09:33 PM PDT 24
Peak memory 272924 kb
Host smart-441e51f4-09e8-41f3-b3ed-6dc5aceb398e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379805465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2379805465
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.193195779
Short name T337
Test name
Test status
Simulation time 16811930569 ps
CPU time 171.08 seconds
Started Aug 04 04:46:29 PM PDT 24
Finished Aug 04 04:49:21 PM PDT 24
Peak memory 248324 kb
Host smart-29b7813b-d0c1-4d7c-907b-1441e95cb6c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193195779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.193195779
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1883250916
Short name T516
Test name
Test status
Simulation time 2600100768 ps
CPU time 34.9 seconds
Started Aug 04 04:46:26 PM PDT 24
Finished Aug 04 04:47:00 PM PDT 24
Peak memory 255856 kb
Host smart-fe8bd47e-47a2-4bef-a712-8d83ad821d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18832
50916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1883250916
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1419483602
Short name T552
Test name
Test status
Simulation time 97556621 ps
CPU time 7.1 seconds
Started Aug 04 04:46:30 PM PDT 24
Finished Aug 04 04:46:37 PM PDT 24
Peak memory 250328 kb
Host smart-f0558deb-7f91-43a3-86b6-9f0cf41dc295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14194
83602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1419483602
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.4029692222
Short name T23
Test name
Test status
Simulation time 902312406 ps
CPU time 27.19 seconds
Started Aug 04 04:46:30 PM PDT 24
Finished Aug 04 04:46:57 PM PDT 24
Peak memory 248312 kb
Host smart-f18ff60a-acac-4d47-8b16-743be5be70b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40296
92222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.4029692222
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.4126355973
Short name T591
Test name
Test status
Simulation time 481139558 ps
CPU time 19.27 seconds
Started Aug 04 04:46:23 PM PDT 24
Finished Aug 04 04:46:42 PM PDT 24
Peak memory 255340 kb
Host smart-d0a007d2-fdb4-49c9-bafd-37c6d81feb04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41263
55973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.4126355973
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1924137182
Short name T43
Test name
Test status
Simulation time 66005998061 ps
CPU time 2151.82 seconds
Started Aug 04 04:46:30 PM PDT 24
Finished Aug 04 05:22:23 PM PDT 24
Peak memory 281156 kb
Host smart-213efab5-4c83-4171-82be-b5c2b1de3b8c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924137182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1924137182
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.157108235
Short name T467
Test name
Test status
Simulation time 41703349385 ps
CPU time 819.34 seconds
Started Aug 04 04:46:34 PM PDT 24
Finished Aug 04 05:00:13 PM PDT 24
Peak memory 272920 kb
Host smart-f7244a10-9e2c-4e3c-8db9-948f3e58240b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157108235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.157108235
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1965817527
Short name T246
Test name
Test status
Simulation time 396442745 ps
CPU time 40.42 seconds
Started Aug 04 04:46:31 PM PDT 24
Finished Aug 04 04:47:11 PM PDT 24
Peak memory 256400 kb
Host smart-b155794c-b583-4b7b-acf3-475851d0bac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19658
17527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1965817527
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3673279998
Short name T122
Test name
Test status
Simulation time 1547052039 ps
CPU time 27.86 seconds
Started Aug 04 04:46:31 PM PDT 24
Finished Aug 04 04:46:59 PM PDT 24
Peak memory 254796 kb
Host smart-3cd9757c-b90a-412a-9e3c-28fc6336d3ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36732
79998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3673279998
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1620160893
Short name T700
Test name
Test status
Simulation time 181142996838 ps
CPU time 2328.3 seconds
Started Aug 04 04:46:38 PM PDT 24
Finished Aug 04 05:25:26 PM PDT 24
Peak memory 283496 kb
Host smart-1700a250-99a0-456a-8b2b-e260c3c29464
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620160893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1620160893
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2823189692
Short name T575
Test name
Test status
Simulation time 31471904312 ps
CPU time 2098.66 seconds
Started Aug 04 04:46:35 PM PDT 24
Finished Aug 04 05:21:34 PM PDT 24
Peak memory 286672 kb
Host smart-0cd5a8bd-f601-4bc8-9d4a-80b5bab0f2d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823189692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2823189692
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2402543011
Short name T68
Test name
Test status
Simulation time 837463834 ps
CPU time 46.75 seconds
Started Aug 04 04:46:30 PM PDT 24
Finished Aug 04 04:47:17 PM PDT 24
Peak memory 255564 kb
Host smart-43052b2a-5abb-465d-a41e-7c56323a52e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24025
43011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2402543011
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.4266493435
Short name T111
Test name
Test status
Simulation time 1975686580 ps
CPU time 43.58 seconds
Started Aug 04 04:46:30 PM PDT 24
Finished Aug 04 04:47:14 PM PDT 24
Peak memory 255944 kb
Host smart-888a0850-2ef4-41a4-a818-f5854884faa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42664
93435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.4266493435
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.738964310
Short name T424
Test name
Test status
Simulation time 105988497 ps
CPU time 12.02 seconds
Started Aug 04 04:46:34 PM PDT 24
Finished Aug 04 04:46:46 PM PDT 24
Peak memory 255852 kb
Host smart-f6cb7381-f690-43d5-b9c3-36a251013402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73896
4310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.738964310
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3456293421
Short name T678
Test name
Test status
Simulation time 1149616183 ps
CPU time 19.21 seconds
Started Aug 04 04:46:31 PM PDT 24
Finished Aug 04 04:46:50 PM PDT 24
Peak memory 255392 kb
Host smart-04d9a2d5-259b-46b0-876b-56acd27c6db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34562
93421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3456293421
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3271822773
Short name T61
Test name
Test status
Simulation time 49973583952 ps
CPU time 2932.66 seconds
Started Aug 04 04:46:33 PM PDT 24
Finished Aug 04 05:35:26 PM PDT 24
Peak memory 305020 kb
Host smart-054bfb6f-7c1e-4527-806e-c342cb730caa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271822773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3271822773
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.3366260672
Short name T100
Test name
Test status
Simulation time 330475311181 ps
CPU time 4192.26 seconds
Started Aug 04 04:46:37 PM PDT 24
Finished Aug 04 05:56:30 PM PDT 24
Peak memory 321968 kb
Host smart-f454a869-5d9e-4f15-b0e3-0fc3696725db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366260672 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3366260672
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.151289615
Short name T686
Test name
Test status
Simulation time 10832510811 ps
CPU time 1092.95 seconds
Started Aug 04 04:46:39 PM PDT 24
Finished Aug 04 05:04:53 PM PDT 24
Peak memory 288316 kb
Host smart-65b9bd55-373b-4ef6-8130-e8448dd2a78a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151289615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.151289615
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1255438795
Short name T572
Test name
Test status
Simulation time 2847205381 ps
CPU time 144.54 seconds
Started Aug 04 04:46:39 PM PDT 24
Finished Aug 04 04:49:04 PM PDT 24
Peak memory 256436 kb
Host smart-5fdcff90-3be0-4ec2-974f-b237c0d34611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12554
38795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1255438795
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1653294667
Short name T26
Test name
Test status
Simulation time 811254157 ps
CPU time 25.97 seconds
Started Aug 04 04:46:37 PM PDT 24
Finished Aug 04 04:47:03 PM PDT 24
Peak memory 256360 kb
Host smart-ba12646b-2c1b-4223-a237-3e0fd8898a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16532
94667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1653294667
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1417954683
Short name T586
Test name
Test status
Simulation time 62251144434 ps
CPU time 1593.6 seconds
Started Aug 04 04:46:40 PM PDT 24
Finished Aug 04 05:13:14 PM PDT 24
Peak memory 272076 kb
Host smart-6902ce87-d875-4505-b57b-8208b6247c2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417954683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1417954683
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3076976390
Short name T121
Test name
Test status
Simulation time 39434934105 ps
CPU time 1272.17 seconds
Started Aug 04 04:46:41 PM PDT 24
Finished Aug 04 05:07:53 PM PDT 24
Peak memory 271620 kb
Host smart-eb46d35e-000d-475e-97a2-8eebcd4174ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076976390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3076976390
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1009365567
Short name T40
Test name
Test status
Simulation time 4649968761 ps
CPU time 100.15 seconds
Started Aug 04 04:46:41 PM PDT 24
Finished Aug 04 04:48:21 PM PDT 24
Peak memory 248192 kb
Host smart-63d4406b-2eb1-4dfc-b438-3dd44771b778
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009365567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1009365567
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3347145293
Short name T33
Test name
Test status
Simulation time 1179945075 ps
CPU time 30.8 seconds
Started Aug 04 04:46:39 PM PDT 24
Finished Aug 04 04:47:10 PM PDT 24
Peak memory 256312 kb
Host smart-24776a57-032f-4212-94cb-20bd344ca050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33471
45293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3347145293
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2170805025
Short name T46
Test name
Test status
Simulation time 7437686346 ps
CPU time 40.13 seconds
Started Aug 04 04:46:36 PM PDT 24
Finished Aug 04 04:47:16 PM PDT 24
Peak memory 248216 kb
Host smart-b332d92a-e02b-4510-ab50-2a9af90d2c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21708
05025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2170805025
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3952551268
Short name T402
Test name
Test status
Simulation time 1540776982 ps
CPU time 23.94 seconds
Started Aug 04 04:46:37 PM PDT 24
Finished Aug 04 04:47:01 PM PDT 24
Peak memory 248664 kb
Host smart-6956f9a2-2430-4739-bac4-f08b6c1e2221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39525
51268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3952551268
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.21146301
Short name T644
Test name
Test status
Simulation time 1045746282 ps
CPU time 22.06 seconds
Started Aug 04 04:46:39 PM PDT 24
Finished Aug 04 04:47:01 PM PDT 24
Peak memory 256376 kb
Host smart-fe97c970-b215-45be-bd35-8cd860050610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21146
301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.21146301
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2773982555
Short name T619
Test name
Test status
Simulation time 105693972388 ps
CPU time 1794.34 seconds
Started Aug 04 04:46:45 PM PDT 24
Finished Aug 04 05:16:40 PM PDT 24
Peak memory 272884 kb
Host smart-8edf18f6-0fc4-4436-9007-5093863d4ec2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773982555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2773982555
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2352540508
Short name T415
Test name
Test status
Simulation time 2046202518 ps
CPU time 32.92 seconds
Started Aug 04 04:46:44 PM PDT 24
Finished Aug 04 04:47:17 PM PDT 24
Peak memory 256140 kb
Host smart-791314cf-47ce-437b-be7a-d8eddc513349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23525
40508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2352540508
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2417241476
Short name T570
Test name
Test status
Simulation time 1809955137 ps
CPU time 59.92 seconds
Started Aug 04 04:46:44 PM PDT 24
Finished Aug 04 04:47:44 PM PDT 24
Peak memory 248260 kb
Host smart-7ab17f1b-59f4-44eb-a9b6-de432d8b4ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24172
41476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2417241476
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2488520972
Short name T651
Test name
Test status
Simulation time 170818022608 ps
CPU time 1334.63 seconds
Started Aug 04 04:46:46 PM PDT 24
Finished Aug 04 05:09:01 PM PDT 24
Peak memory 288660 kb
Host smart-6e4702dd-d781-4dfe-ab7b-9590e5a0aa5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488520972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2488520972
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1570237177
Short name T409
Test name
Test status
Simulation time 202328187695 ps
CPU time 2468.08 seconds
Started Aug 04 04:46:49 PM PDT 24
Finished Aug 04 05:27:57 PM PDT 24
Peak memory 288484 kb
Host smart-13823979-3a7f-4502-a412-a44227d6838b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570237177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1570237177
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.931571421
Short name T323
Test name
Test status
Simulation time 22045637045 ps
CPU time 596.6 seconds
Started Aug 04 04:46:46 PM PDT 24
Finished Aug 04 04:56:43 PM PDT 24
Peak memory 256300 kb
Host smart-c057ea25-46a0-48ac-b1e4-a38c89b227be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931571421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.931571421
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.367827510
Short name T637
Test name
Test status
Simulation time 164141873 ps
CPU time 15.43 seconds
Started Aug 04 04:46:44 PM PDT 24
Finished Aug 04 04:46:59 PM PDT 24
Peak memory 255812 kb
Host smart-8e5a2340-8dbc-4b6f-8667-fc2ae0d67af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36782
7510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.367827510
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1758176791
Short name T531
Test name
Test status
Simulation time 865430320 ps
CPU time 49.78 seconds
Started Aug 04 04:46:45 PM PDT 24
Finished Aug 04 04:47:35 PM PDT 24
Peak memory 255756 kb
Host smart-8d365d1e-6100-43cb-a487-8b0b01d5ad4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17581
76791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1758176791
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3089758123
Short name T3
Test name
Test status
Simulation time 158577479 ps
CPU time 19.23 seconds
Started Aug 04 04:46:43 PM PDT 24
Finished Aug 04 04:47:03 PM PDT 24
Peak memory 255696 kb
Host smart-48889766-f58e-4c49-922c-605208d9581f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30897
58123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3089758123
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2811231714
Short name T512
Test name
Test status
Simulation time 1315923071 ps
CPU time 32 seconds
Started Aug 04 04:46:41 PM PDT 24
Finished Aug 04 04:47:13 PM PDT 24
Peak memory 256428 kb
Host smart-47a72229-3b80-43b2-bbd8-62126545a19e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28112
31714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2811231714
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3992363779
Short name T252
Test name
Test status
Simulation time 532995189933 ps
CPU time 6296.53 seconds
Started Aug 04 04:46:52 PM PDT 24
Finished Aug 04 06:31:51 PM PDT 24
Peak memory 321272 kb
Host smart-37ab5ec9-4283-4065-b468-2abeaca9c04a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992363779 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3992363779
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2813377013
Short name T483
Test name
Test status
Simulation time 884488864 ps
CPU time 50.49 seconds
Started Aug 04 04:46:56 PM PDT 24
Finished Aug 04 04:47:47 PM PDT 24
Peak memory 256328 kb
Host smart-dde44669-74cd-4ff8-aa8c-4fc0e924be2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28133
77013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2813377013
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.4173261239
Short name T605
Test name
Test status
Simulation time 318581345 ps
CPU time 29.63 seconds
Started Aug 04 04:46:57 PM PDT 24
Finished Aug 04 04:47:27 PM PDT 24
Peak memory 256036 kb
Host smart-fb0e0463-b7b6-4fb3-9897-cbad1bf83b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41732
61239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.4173261239
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2501830436
Short name T15
Test name
Test status
Simulation time 12656885075 ps
CPU time 1116.81 seconds
Started Aug 04 04:47:04 PM PDT 24
Finished Aug 04 05:05:41 PM PDT 24
Peak memory 287488 kb
Host smart-57fff36e-aaa2-4ed3-afd9-e802f33c774e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501830436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2501830436
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2616926121
Short name T465
Test name
Test status
Simulation time 15590695803 ps
CPU time 1473.58 seconds
Started Aug 04 04:47:00 PM PDT 24
Finished Aug 04 05:11:34 PM PDT 24
Peak memory 288744 kb
Host smart-80a1d3e4-1fe3-4da3-8646-38c0e7906a46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616926121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2616926121
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1496812853
Short name T436
Test name
Test status
Simulation time 362326885 ps
CPU time 34.13 seconds
Started Aug 04 04:46:54 PM PDT 24
Finished Aug 04 04:47:28 PM PDT 24
Peak memory 248252 kb
Host smart-2211978c-ae22-463e-b35a-828d78f28637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14968
12853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1496812853
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2764121418
Short name T455
Test name
Test status
Simulation time 421058142 ps
CPU time 48.46 seconds
Started Aug 04 04:46:53 PM PDT 24
Finished Aug 04 04:47:41 PM PDT 24
Peak memory 248560 kb
Host smart-bcc9b153-5534-4b7c-b23b-ab77387dee42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27641
21418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2764121418
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2745866695
Short name T116
Test name
Test status
Simulation time 370915763 ps
CPU time 23.84 seconds
Started Aug 04 04:46:58 PM PDT 24
Finished Aug 04 04:47:22 PM PDT 24
Peak memory 247780 kb
Host smart-b3557174-281c-4a19-9b92-03cd394896bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27458
66695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2745866695
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1364172003
Short name T413
Test name
Test status
Simulation time 692492627 ps
CPU time 14.55 seconds
Started Aug 04 04:46:54 PM PDT 24
Finished Aug 04 04:47:09 PM PDT 24
Peak memory 254004 kb
Host smart-4c424dea-8e9b-485f-8efd-b13617c1b6e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13641
72003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1364172003
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1723414491
Short name T250
Test name
Test status
Simulation time 50981893477 ps
CPU time 1489.12 seconds
Started Aug 04 04:47:02 PM PDT 24
Finished Aug 04 05:11:51 PM PDT 24
Peak memory 281940 kb
Host smart-ed36b636-26df-4325-890f-afefb4920292
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723414491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1723414491
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2355600915
Short name T665
Test name
Test status
Simulation time 26075363107 ps
CPU time 1217.05 seconds
Started Aug 04 04:47:11 PM PDT 24
Finished Aug 04 05:07:29 PM PDT 24
Peak memory 280964 kb
Host smart-12dd484f-78f2-458d-a9a2-f730018c8772
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355600915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2355600915
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1905001665
Short name T206
Test name
Test status
Simulation time 1606344858 ps
CPU time 152.39 seconds
Started Aug 04 04:47:04 PM PDT 24
Finished Aug 04 04:49:37 PM PDT 24
Peak memory 251372 kb
Host smart-5c7a80e9-3ce6-41a0-ab75-7ba8541e7941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19050
01665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1905001665
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3175772973
Short name T635
Test name
Test status
Simulation time 12089453021 ps
CPU time 48.43 seconds
Started Aug 04 04:47:05 PM PDT 24
Finished Aug 04 04:47:53 PM PDT 24
Peak memory 247924 kb
Host smart-cdf225de-6f88-44a8-9a97-48f43aa94baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31757
72973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3175772973
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3477200048
Short name T653
Test name
Test status
Simulation time 29923954908 ps
CPU time 746.28 seconds
Started Aug 04 04:47:11 PM PDT 24
Finished Aug 04 04:59:38 PM PDT 24
Peak memory 272248 kb
Host smart-9d327cbb-2ea2-4f20-8483-7608f02e7259
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477200048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3477200048
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3534817164
Short name T423
Test name
Test status
Simulation time 80718667670 ps
CPU time 1934.49 seconds
Started Aug 04 04:47:08 PM PDT 24
Finished Aug 04 05:19:22 PM PDT 24
Peak memory 280956 kb
Host smart-0ceece1c-28c1-4820-a43d-3c2832e6c478
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534817164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3534817164
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2882235654
Short name T674
Test name
Test status
Simulation time 14846507668 ps
CPU time 166.17 seconds
Started Aug 04 04:47:11 PM PDT 24
Finished Aug 04 04:49:58 PM PDT 24
Peak memory 247048 kb
Host smart-3aaec742-bbfc-40bd-9a6e-809475b0b955
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882235654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2882235654
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.644328423
Short name T537
Test name
Test status
Simulation time 54997903 ps
CPU time 5.37 seconds
Started Aug 04 04:47:05 PM PDT 24
Finished Aug 04 04:47:10 PM PDT 24
Peak memory 248224 kb
Host smart-3e3c53a0-5d25-47cd-b737-eb0abd9711c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64432
8423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.644328423
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3083168829
Short name T549
Test name
Test status
Simulation time 400152405 ps
CPU time 18.01 seconds
Started Aug 04 04:47:02 PM PDT 24
Finished Aug 04 04:47:20 PM PDT 24
Peak memory 256192 kb
Host smart-ce7885dd-9ca1-4c57-9d82-e0e6efe273ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30831
68829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3083168829
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.4159496807
Short name T473
Test name
Test status
Simulation time 1358662133 ps
CPU time 23.72 seconds
Started Aug 04 04:47:08 PM PDT 24
Finished Aug 04 04:47:32 PM PDT 24
Peak memory 247764 kb
Host smart-110e7a41-b0cb-4444-ba6a-0917e6bc9ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41594
96807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.4159496807
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2409697832
Short name T718
Test name
Test status
Simulation time 154501037 ps
CPU time 12.7 seconds
Started Aug 04 04:47:04 PM PDT 24
Finished Aug 04 04:47:16 PM PDT 24
Peak memory 254420 kb
Host smart-30c71ede-d0fa-4483-9c30-052659c96874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24096
97832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2409697832
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.310551638
Short name T638
Test name
Test status
Simulation time 83312565524 ps
CPU time 1916.37 seconds
Started Aug 04 04:47:09 PM PDT 24
Finished Aug 04 05:19:06 PM PDT 24
Peak memory 297440 kb
Host smart-45d41067-54ce-4674-9ab8-9a7dfcc1d7bf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310551638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_han
dler_stress_all.310551638
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2391386427
Short name T696
Test name
Test status
Simulation time 40639092906 ps
CPU time 1338.78 seconds
Started Aug 04 04:47:18 PM PDT 24
Finished Aug 04 05:09:37 PM PDT 24
Peak memory 266712 kb
Host smart-0bd8d2d9-2b2e-472b-bbe6-f12290cfeeff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391386427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2391386427
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.4064348299
Short name T650
Test name
Test status
Simulation time 13299336576 ps
CPU time 163.3 seconds
Started Aug 04 04:47:15 PM PDT 24
Finished Aug 04 04:49:58 PM PDT 24
Peak memory 255728 kb
Host smart-6020790d-a944-4940-acb7-157d0ebd1c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40643
48299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.4064348299
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2743366451
Short name T408
Test name
Test status
Simulation time 941264436 ps
CPU time 59.24 seconds
Started Aug 04 04:47:18 PM PDT 24
Finished Aug 04 04:48:17 PM PDT 24
Peak memory 248076 kb
Host smart-6e68a6b2-832e-4fed-861a-6c62dc8d24d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27433
66451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2743366451
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2156819069
Short name T315
Test name
Test status
Simulation time 86999705727 ps
CPU time 1477.71 seconds
Started Aug 04 04:47:17 PM PDT 24
Finished Aug 04 05:11:55 PM PDT 24
Peak memory 264624 kb
Host smart-64b094a6-0c86-45a9-a250-3f0508652498
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156819069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2156819069
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.446904989
Short name T560
Test name
Test status
Simulation time 22580885499 ps
CPU time 1468.45 seconds
Started Aug 04 04:47:22 PM PDT 24
Finished Aug 04 05:11:51 PM PDT 24
Peak memory 272756 kb
Host smart-4b6c027a-a86e-4824-ae12-2e2c78320673
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446904989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.446904989
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.167474974
Short name T681
Test name
Test status
Simulation time 42483088533 ps
CPU time 434.1 seconds
Started Aug 04 04:47:17 PM PDT 24
Finished Aug 04 04:54:31 PM PDT 24
Peak memory 247128 kb
Host smart-228d498d-3d8a-424a-887a-dc21c46509e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167474974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.167474974
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.4281290345
Short name T403
Test name
Test status
Simulation time 1512490520 ps
CPU time 37.04 seconds
Started Aug 04 04:47:15 PM PDT 24
Finished Aug 04 04:47:52 PM PDT 24
Peak memory 255732 kb
Host smart-5eee93a0-c261-4778-8199-e47a37eb02db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42812
90345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.4281290345
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1071012927
Short name T670
Test name
Test status
Simulation time 90734242 ps
CPU time 7.69 seconds
Started Aug 04 04:47:11 PM PDT 24
Finished Aug 04 04:47:19 PM PDT 24
Peak memory 239932 kb
Host smart-5f24ac59-0187-42ae-9df3-e6bf84a9261e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10710
12927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1071012927
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3386675774
Short name T504
Test name
Test status
Simulation time 3038232164 ps
CPU time 34.95 seconds
Started Aug 04 04:47:16 PM PDT 24
Finished Aug 04 04:47:51 PM PDT 24
Peak memory 256160 kb
Host smart-2ffd8706-228f-4c53-8a72-c0c6bc892018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33866
75774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3386675774
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.297150332
Short name T526
Test name
Test status
Simulation time 896655033 ps
CPU time 18.05 seconds
Started Aug 04 04:47:11 PM PDT 24
Finished Aug 04 04:47:29 PM PDT 24
Peak memory 248628 kb
Host smart-9255593e-f6f7-4001-9721-ded958385b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29715
0332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.297150332
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.51231939
Short name T271
Test name
Test status
Simulation time 92940292055 ps
CPU time 1634.02 seconds
Started Aug 04 04:47:19 PM PDT 24
Finished Aug 04 05:14:33 PM PDT 24
Peak memory 272484 kb
Host smart-4ec7c3e3-0064-4ab6-9f6c-8af407dd4bdc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51231939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_hand
ler_stress_all.51231939
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1257610549
Short name T298
Test name
Test status
Simulation time 6183223114 ps
CPU time 114.54 seconds
Started Aug 04 04:47:24 PM PDT 24
Finished Aug 04 04:49:19 PM PDT 24
Peak memory 256040 kb
Host smart-689e4674-f381-4950-974c-dd8d87edde62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12576
10549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1257610549
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1817983203
Short name T523
Test name
Test status
Simulation time 716688520 ps
CPU time 20.61 seconds
Started Aug 04 04:47:22 PM PDT 24
Finished Aug 04 04:47:43 PM PDT 24
Peak memory 256192 kb
Host smart-ad1962e1-1abb-454f-9f2d-963f49b8d990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18179
83203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1817983203
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.528715544
Short name T356
Test name
Test status
Simulation time 20566483848 ps
CPU time 1578.53 seconds
Started Aug 04 04:47:24 PM PDT 24
Finished Aug 04 05:13:43 PM PDT 24
Peak memory 288012 kb
Host smart-5f7f1bb0-f6ad-401c-ab54-0daa53e1372a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528715544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.528715544
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1384366128
Short name T77
Test name
Test status
Simulation time 139654102261 ps
CPU time 2193.63 seconds
Started Aug 04 04:47:24 PM PDT 24
Finished Aug 04 05:23:58 PM PDT 24
Peak memory 286428 kb
Host smart-71f38cfd-c067-48bd-82bb-a98105bcdc3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384366128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1384366128
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2406328186
Short name T332
Test name
Test status
Simulation time 39375210167 ps
CPU time 121.01 seconds
Started Aug 04 04:47:25 PM PDT 24
Finished Aug 04 04:49:26 PM PDT 24
Peak memory 253868 kb
Host smart-671b32f0-56e0-47cf-8641-efa8939f0be4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406328186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2406328186
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.891356494
Short name T508
Test name
Test status
Simulation time 768988387 ps
CPU time 52.98 seconds
Started Aug 04 04:47:22 PM PDT 24
Finished Aug 04 04:48:15 PM PDT 24
Peak memory 255844 kb
Host smart-f3b736c0-98be-41e1-b49d-24d943d6e8d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89135
6494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.891356494
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2548057700
Short name T587
Test name
Test status
Simulation time 20881761 ps
CPU time 4.22 seconds
Started Aug 04 04:47:18 PM PDT 24
Finished Aug 04 04:47:22 PM PDT 24
Peak memory 239528 kb
Host smart-1b39d431-9127-4a9a-8648-8c994830933c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25480
57700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2548057700
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.145350608
Short name T682
Test name
Test status
Simulation time 274586203 ps
CPU time 33.49 seconds
Started Aug 04 04:47:24 PM PDT 24
Finished Aug 04 04:47:57 PM PDT 24
Peak memory 255684 kb
Host smart-38d63830-67b9-4d37-a84f-4a5294bfd573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14535
0608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.145350608
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.471368460
Short name T654
Test name
Test status
Simulation time 2534532283 ps
CPU time 29.96 seconds
Started Aug 04 04:47:18 PM PDT 24
Finished Aug 04 04:47:48 PM PDT 24
Peak memory 248308 kb
Host smart-81ced2cf-ed36-4c80-8416-f7ecf95af6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47136
8460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.471368460
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1928348484
Short name T34
Test name
Test status
Simulation time 39501467226 ps
CPU time 2625.15 seconds
Started Aug 04 04:47:25 PM PDT 24
Finished Aug 04 05:31:10 PM PDT 24
Peak memory 289180 kb
Host smart-5ddf81de-c414-4dba-84aa-9faa6a03cdac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928348484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1928348484
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2015566398
Short name T272
Test name
Test status
Simulation time 104346816723 ps
CPU time 2459.32 seconds
Started Aug 04 04:47:25 PM PDT 24
Finished Aug 04 05:28:24 PM PDT 24
Peak memory 305828 kb
Host smart-39045f03-5c53-4c57-8ad3-664628272160
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015566398 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2015566398
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.4020990474
Short name T481
Test name
Test status
Simulation time 107580890994 ps
CPU time 1624.74 seconds
Started Aug 04 04:47:26 PM PDT 24
Finished Aug 04 05:14:31 PM PDT 24
Peak memory 272800 kb
Host smart-88995420-fedc-4b7b-9ec7-18dccc3dfd29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020990474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.4020990474
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3668571294
Short name T496
Test name
Test status
Simulation time 522407816 ps
CPU time 31.56 seconds
Started Aug 04 04:47:26 PM PDT 24
Finished Aug 04 04:47:58 PM PDT 24
Peak memory 255980 kb
Host smart-0370ddc0-a1e4-4dc4-9237-2492148eeda3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36685
71294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3668571294
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3005749934
Short name T2
Test name
Test status
Simulation time 601739367 ps
CPU time 27.07 seconds
Started Aug 04 04:47:27 PM PDT 24
Finished Aug 04 04:47:54 PM PDT 24
Peak memory 256040 kb
Host smart-fddd9194-5621-4375-a990-5776684b742a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30057
49934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3005749934
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.456269108
Short name T363
Test name
Test status
Simulation time 26299726439 ps
CPU time 1446.26 seconds
Started Aug 04 04:47:27 PM PDT 24
Finished Aug 04 05:11:34 PM PDT 24
Peak memory 271072 kb
Host smart-54aa1b28-aa60-4ae2-a2c3-faaf04291e9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456269108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.456269108
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1857589513
Short name T597
Test name
Test status
Simulation time 261103640559 ps
CPU time 1942.51 seconds
Started Aug 04 04:47:29 PM PDT 24
Finished Aug 04 05:19:52 PM PDT 24
Peak memory 281000 kb
Host smart-c790bce2-8b46-4421-a531-ab522548f9df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857589513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1857589513
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.4030411412
Short name T659
Test name
Test status
Simulation time 73295722003 ps
CPU time 413.92 seconds
Started Aug 04 04:47:26 PM PDT 24
Finished Aug 04 04:54:21 PM PDT 24
Peak memory 248248 kb
Host smart-63da2fd9-b021-494d-bf09-0919117a2401
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030411412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.4030411412
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2337956266
Short name T520
Test name
Test status
Simulation time 236715795 ps
CPU time 24.96 seconds
Started Aug 04 04:47:26 PM PDT 24
Finished Aug 04 04:47:51 PM PDT 24
Peak memory 256228 kb
Host smart-a43a673d-dcf8-4c4c-88d7-b016d6487591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23379
56266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2337956266
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.488361980
Short name T490
Test name
Test status
Simulation time 62849445 ps
CPU time 5.42 seconds
Started Aug 04 04:47:28 PM PDT 24
Finished Aug 04 04:47:33 PM PDT 24
Peak memory 239312 kb
Host smart-50e325cb-d364-4777-8cb5-9136d28a2303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48836
1980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.488361980
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3043577747
Short name T279
Test name
Test status
Simulation time 1039795663 ps
CPU time 56.82 seconds
Started Aug 04 04:47:27 PM PDT 24
Finished Aug 04 04:48:24 PM PDT 24
Peak memory 255668 kb
Host smart-0023acb0-9273-4de4-8db5-3a2b481156e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30435
77747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3043577747
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.451417941
Short name T533
Test name
Test status
Simulation time 1231508131 ps
CPU time 44.71 seconds
Started Aug 04 04:47:25 PM PDT 24
Finished Aug 04 04:48:10 PM PDT 24
Peak memory 255396 kb
Host smart-e220c443-b3a1-47ed-a9c1-fb2f1651a54a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45141
7941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.451417941
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1387415539
Short name T306
Test name
Test status
Simulation time 31326945599 ps
CPU time 1797.25 seconds
Started Aug 04 04:47:28 PM PDT 24
Finished Aug 04 05:17:25 PM PDT 24
Peak memory 280524 kb
Host smart-7a6542f4-3183-41db-99a2-b27e1fbf8f81
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387415539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1387415539
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.764949924
Short name T251
Test name
Test status
Simulation time 45137672722 ps
CPU time 2469.02 seconds
Started Aug 04 04:47:34 PM PDT 24
Finished Aug 04 05:28:43 PM PDT 24
Peak memory 289260 kb
Host smart-4dbf2b9e-46da-436c-8112-78cab34fc32a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764949924 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.764949924
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1359101319
Short name T219
Test name
Test status
Simulation time 21789738 ps
CPU time 2.72 seconds
Started Aug 04 04:43:12 PM PDT 24
Finished Aug 04 04:43:15 PM PDT 24
Peak memory 248432 kb
Host smart-1f2f8618-cf79-4a96-a260-821a31be8dc8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1359101319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1359101319
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1060785602
Short name T617
Test name
Test status
Simulation time 67654458583 ps
CPU time 2108.03 seconds
Started Aug 04 04:43:08 PM PDT 24
Finished Aug 04 05:18:17 PM PDT 24
Peak memory 272172 kb
Host smart-3543bcf1-2706-495e-9c41-9fa4dbe2d569
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060785602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1060785602
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.851967798
Short name T548
Test name
Test status
Simulation time 429052966 ps
CPU time 7.2 seconds
Started Aug 04 04:43:11 PM PDT 24
Finished Aug 04 04:43:18 PM PDT 24
Peak memory 248144 kb
Host smart-e2140334-7e6e-40eb-926e-40a80946e6bc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=851967798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.851967798
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1238742594
Short name T716
Test name
Test status
Simulation time 1704512596 ps
CPU time 32.87 seconds
Started Aug 04 04:43:08 PM PDT 24
Finished Aug 04 04:43:41 PM PDT 24
Peak memory 247932 kb
Host smart-2a845e27-d088-4b61-9634-7c9b7cc33f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12387
42594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1238742594
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3968620540
Short name T689
Test name
Test status
Simulation time 93195351 ps
CPU time 4.57 seconds
Started Aug 04 04:43:11 PM PDT 24
Finished Aug 04 04:43:16 PM PDT 24
Peak memory 239592 kb
Host smart-2acaa0ea-2513-4a16-88b7-f979bc46353e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39686
20540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3968620540
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1071146240
Short name T335
Test name
Test status
Simulation time 22644848412 ps
CPU time 1439.21 seconds
Started Aug 04 04:43:11 PM PDT 24
Finished Aug 04 05:07:10 PM PDT 24
Peak memory 272044 kb
Host smart-313364dc-aa08-4a28-b817-21578b51a413
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071146240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1071146240
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.899895241
Short name T622
Test name
Test status
Simulation time 47473061410 ps
CPU time 1231.93 seconds
Started Aug 04 04:43:08 PM PDT 24
Finished Aug 04 05:03:40 PM PDT 24
Peak memory 288944 kb
Host smart-aa468e06-1179-49cc-b7e1-19d8fa8797fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899895241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.899895241
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3439286790
Short name T20
Test name
Test status
Simulation time 48981294172 ps
CPU time 467.38 seconds
Started Aug 04 04:43:08 PM PDT 24
Finished Aug 04 04:50:56 PM PDT 24
Peak memory 248272 kb
Host smart-a7ca3ee0-9bcc-4b6e-a681-5a648c20cc7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439286790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3439286790
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2491028062
Short name T594
Test name
Test status
Simulation time 242148265 ps
CPU time 25.13 seconds
Started Aug 04 04:43:08 PM PDT 24
Finished Aug 04 04:43:33 PM PDT 24
Peak memory 248256 kb
Host smart-f6589463-080d-47fb-bfe8-8b640675bf01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24910
28062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2491028062
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3443154936
Short name T611
Test name
Test status
Simulation time 1591048706 ps
CPU time 27.74 seconds
Started Aug 04 04:43:11 PM PDT 24
Finished Aug 04 04:43:38 PM PDT 24
Peak memory 247768 kb
Host smart-5b7ce100-2451-4f61-94ce-9a2be14e79f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34431
54936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3443154936
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.4188682440
Short name T506
Test name
Test status
Simulation time 2060235970 ps
CPU time 34.9 seconds
Started Aug 04 04:43:11 PM PDT 24
Finished Aug 04 04:43:46 PM PDT 24
Peak memory 255952 kb
Host smart-115664ef-48a0-4cc6-9f7b-a6a5d9e5b7a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41886
82440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.4188682440
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2806525771
Short name T299
Test name
Test status
Simulation time 667192665 ps
CPU time 40.58 seconds
Started Aug 04 04:43:12 PM PDT 24
Finished Aug 04 04:43:53 PM PDT 24
Peak memory 255472 kb
Host smart-afe2bab6-dffb-427f-9baf-4645d3b7e889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28065
25771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2806525771
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1620372421
Short name T283
Test name
Test status
Simulation time 67217379254 ps
CPU time 3391.75 seconds
Started Aug 04 04:43:12 PM PDT 24
Finished Aug 04 05:39:44 PM PDT 24
Peak memory 297960 kb
Host smart-294b9ce0-2fbb-4a4e-8a84-b853b8668574
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620372421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1620372421
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1052971457
Short name T222
Test name
Test status
Simulation time 36304833 ps
CPU time 2.2 seconds
Started Aug 04 04:43:16 PM PDT 24
Finished Aug 04 04:43:18 PM PDT 24
Peak memory 247868 kb
Host smart-ed985a5d-bee4-4213-bfc6-d116403a16f8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1052971457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1052971457
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3418281874
Short name T610
Test name
Test status
Simulation time 22408967415 ps
CPU time 1224.34 seconds
Started Aug 04 04:43:16 PM PDT 24
Finished Aug 04 05:03:41 PM PDT 24
Peak memory 272656 kb
Host smart-9ce1066a-6c0d-44c7-9d40-113b1f8eaf05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418281874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3418281874
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2612843381
Short name T189
Test name
Test status
Simulation time 425484318 ps
CPU time 8.65 seconds
Started Aug 04 04:43:16 PM PDT 24
Finished Aug 04 04:43:25 PM PDT 24
Peak memory 247568 kb
Host smart-26813b93-fb62-4c5f-9928-0c6b0b08ce16
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2612843381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2612843381
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3618504258
Short name T598
Test name
Test status
Simulation time 1479334354 ps
CPU time 40.03 seconds
Started Aug 04 04:43:11 PM PDT 24
Finished Aug 04 04:43:51 PM PDT 24
Peak memory 256044 kb
Host smart-aa2b99cd-47af-420d-a26c-1a1103ac8985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36185
04258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3618504258
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3628611760
Short name T667
Test name
Test status
Simulation time 49454531 ps
CPU time 4.13 seconds
Started Aug 04 04:43:11 PM PDT 24
Finished Aug 04 04:43:15 PM PDT 24
Peak memory 239628 kb
Host smart-eedfd6e1-8ffb-4f79-be8c-be9c49bf3dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36286
11760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3628611760
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.834885535
Short name T694
Test name
Test status
Simulation time 25294249620 ps
CPU time 1331.64 seconds
Started Aug 04 04:43:14 PM PDT 24
Finished Aug 04 05:05:26 PM PDT 24
Peak memory 272880 kb
Host smart-e48ade3e-2f60-4463-88c7-90776cd8aa6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834885535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.834885535
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1036905472
Short name T590
Test name
Test status
Simulation time 9911228115 ps
CPU time 946.05 seconds
Started Aug 04 04:43:14 PM PDT 24
Finished Aug 04 04:59:01 PM PDT 24
Peak memory 272360 kb
Host smart-d73576fe-7176-45ee-bc70-f00136d0d9c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036905472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1036905472
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1485823229
Short name T612
Test name
Test status
Simulation time 1284468020 ps
CPU time 58.66 seconds
Started Aug 04 04:43:17 PM PDT 24
Finished Aug 04 04:44:16 PM PDT 24
Peak memory 253256 kb
Host smart-e87a5229-a3b3-4154-a212-0c336bcd24b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485823229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1485823229
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.436970240
Short name T419
Test name
Test status
Simulation time 1116795518 ps
CPU time 21.68 seconds
Started Aug 04 04:43:13 PM PDT 24
Finished Aug 04 04:43:35 PM PDT 24
Peak memory 255780 kb
Host smart-ab445b5f-4a4c-4424-97d3-45b2e5ffa055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43697
0240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.436970240
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3506423870
Short name T109
Test name
Test status
Simulation time 420797052 ps
CPU time 37.86 seconds
Started Aug 04 04:43:11 PM PDT 24
Finished Aug 04 04:43:49 PM PDT 24
Peak memory 248212 kb
Host smart-ae460076-8926-448d-a097-930a3d465170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35064
23870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3506423870
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2526209984
Short name T288
Test name
Test status
Simulation time 426350541 ps
CPU time 24.12 seconds
Started Aug 04 04:43:14 PM PDT 24
Finished Aug 04 04:43:39 PM PDT 24
Peak memory 255940 kb
Host smart-0b3207ff-d690-447e-a59a-2fb507c723c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25262
09984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2526209984
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.150217040
Short name T453
Test name
Test status
Simulation time 281301423 ps
CPU time 22.41 seconds
Started Aug 04 04:43:13 PM PDT 24
Finished Aug 04 04:43:35 PM PDT 24
Peak memory 255944 kb
Host smart-5b7f5931-f5c4-4e44-86cb-d9ecace2fa4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15021
7040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.150217040
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1345497741
Short name T449
Test name
Test status
Simulation time 167807812515 ps
CPU time 1753.79 seconds
Started Aug 04 04:43:17 PM PDT 24
Finished Aug 04 05:12:31 PM PDT 24
Peak memory 272932 kb
Host smart-27c66c92-0531-47c9-a0b1-8db30abf4aa6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345497741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1345497741
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.1379510547
Short name T215
Test name
Test status
Simulation time 124191649348 ps
CPU time 8042.93 seconds
Started Aug 04 04:43:15 PM PDT 24
Finished Aug 04 06:57:19 PM PDT 24
Peak memory 321052 kb
Host smart-d2ea1566-2e9d-4006-ad3b-75b73e768222
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379510547 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.1379510547
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3921038467
Short name T235
Test name
Test status
Simulation time 15104006 ps
CPU time 2.63 seconds
Started Aug 04 04:43:20 PM PDT 24
Finished Aug 04 04:43:23 PM PDT 24
Peak memory 248600 kb
Host smart-68f132b8-bbeb-4129-988b-c90cace9003d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3921038467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3921038467
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3262235260
Short name T60
Test name
Test status
Simulation time 89159693315 ps
CPU time 1524.15 seconds
Started Aug 04 04:43:17 PM PDT 24
Finished Aug 04 05:08:42 PM PDT 24
Peak memory 272560 kb
Host smart-63c1fadd-20db-4d9d-ba7e-02dbca8d4a45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262235260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3262235260
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.757228639
Short name T471
Test name
Test status
Simulation time 3540680561 ps
CPU time 33.56 seconds
Started Aug 04 04:43:20 PM PDT 24
Finished Aug 04 04:43:54 PM PDT 24
Peak memory 248300 kb
Host smart-da70de53-2bf6-476e-8f81-2b219302beb7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=757228639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.757228639
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1642490205
Short name T309
Test name
Test status
Simulation time 11549221217 ps
CPU time 206.67 seconds
Started Aug 04 04:43:17 PM PDT 24
Finished Aug 04 04:46:44 PM PDT 24
Peak memory 255836 kb
Host smart-453bdd42-bd22-43de-8c12-e440660e95a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16424
90205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1642490205
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3926709914
Short name T340
Test name
Test status
Simulation time 40588604357 ps
CPU time 2379.09 seconds
Started Aug 04 04:43:24 PM PDT 24
Finished Aug 04 05:23:03 PM PDT 24
Peak memory 288676 kb
Host smart-3e6f4685-4853-49d5-889d-722aba5cfcfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926709914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3926709914
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1313058879
Short name T461
Test name
Test status
Simulation time 32786392006 ps
CPU time 1454.39 seconds
Started Aug 04 04:43:22 PM PDT 24
Finished Aug 04 05:07:37 PM PDT 24
Peak memory 272824 kb
Host smart-3973993d-336f-48d9-8243-4a6ffd88423d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313058879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1313058879
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2626349188
Short name T297
Test name
Test status
Simulation time 54204067219 ps
CPU time 565.81 seconds
Started Aug 04 04:43:20 PM PDT 24
Finished Aug 04 04:52:46 PM PDT 24
Peak memory 248280 kb
Host smart-6af91237-c949-484d-baf7-c61a2bd68678
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626349188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2626349188
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2443244326
Short name T558
Test name
Test status
Simulation time 1230983606 ps
CPU time 21.02 seconds
Started Aug 04 04:43:18 PM PDT 24
Finished Aug 04 04:43:39 PM PDT 24
Peak memory 255804 kb
Host smart-1c890645-df0f-4569-98cf-74c479e6615f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24432
44326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2443244326
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3683770917
Short name T85
Test name
Test status
Simulation time 370874482 ps
CPU time 13.11 seconds
Started Aug 04 04:43:18 PM PDT 24
Finished Aug 04 04:43:31 PM PDT 24
Peak memory 254452 kb
Host smart-acb09f13-61f1-4b82-a639-8be3c23de2a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36837
70917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3683770917
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2436516185
Short name T74
Test name
Test status
Simulation time 1417457028 ps
CPU time 42.47 seconds
Started Aug 04 04:43:17 PM PDT 24
Finished Aug 04 04:43:59 PM PDT 24
Peak memory 255820 kb
Host smart-90b9a3a6-b9cd-454c-91e3-80ae365feb2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24365
16185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2436516185
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3601322339
Short name T527
Test name
Test status
Simulation time 458907934 ps
CPU time 10.48 seconds
Started Aug 04 04:43:14 PM PDT 24
Finished Aug 04 04:43:25 PM PDT 24
Peak memory 255388 kb
Host smart-79453750-cf86-4cf1-83bb-4b9642bee0be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36013
22339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3601322339
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3026479337
Short name T676
Test name
Test status
Simulation time 1231636058 ps
CPU time 14.47 seconds
Started Aug 04 04:43:23 PM PDT 24
Finished Aug 04 04:43:38 PM PDT 24
Peak memory 246992 kb
Host smart-c221c86e-d75f-4879-9b71-494c532fecd6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026479337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3026479337
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3264556711
Short name T225
Test name
Test status
Simulation time 33062003 ps
CPU time 3.29 seconds
Started Aug 04 04:43:27 PM PDT 24
Finished Aug 04 04:43:30 PM PDT 24
Peak memory 248480 kb
Host smart-ee290f1a-85e4-45a2-9fc7-fef549dcb53d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3264556711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3264556711
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1394349720
Short name T515
Test name
Test status
Simulation time 263897867231 ps
CPU time 1501.22 seconds
Started Aug 04 04:43:24 PM PDT 24
Finished Aug 04 05:08:25 PM PDT 24
Peak memory 272820 kb
Host smart-5370ef69-3883-4918-8ec3-bf01f53219b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394349720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1394349720
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3000567180
Short name T71
Test name
Test status
Simulation time 241996909 ps
CPU time 12.77 seconds
Started Aug 04 04:43:27 PM PDT 24
Finished Aug 04 04:43:40 PM PDT 24
Peak memory 248112 kb
Host smart-ccfaf94f-a4dd-4d05-9f64-be51e895593d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3000567180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3000567180
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3447692458
Short name T208
Test name
Test status
Simulation time 3436824461 ps
CPU time 138.97 seconds
Started Aug 04 04:43:24 PM PDT 24
Finished Aug 04 04:45:43 PM PDT 24
Peak memory 256484 kb
Host smart-5b6b86dd-5b09-4db3-84f1-19f641e81f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34476
92458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3447692458
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3059223068
Short name T710
Test name
Test status
Simulation time 739313312 ps
CPU time 15.58 seconds
Started Aug 04 04:43:24 PM PDT 24
Finished Aug 04 04:43:40 PM PDT 24
Peak memory 255788 kb
Host smart-49dfdf33-8c57-4504-b075-9688ffa48130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30592
23068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3059223068
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3251650082
Short name T361
Test name
Test status
Simulation time 15443339347 ps
CPU time 1393.13 seconds
Started Aug 04 04:43:27 PM PDT 24
Finished Aug 04 05:06:41 PM PDT 24
Peak memory 288608 kb
Host smart-1b348b72-c4bf-47c0-82f1-974a75bc3251
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251650082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3251650082
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3900932444
Short name T679
Test name
Test status
Simulation time 10451421425 ps
CPU time 1356.23 seconds
Started Aug 04 04:43:26 PM PDT 24
Finished Aug 04 05:06:02 PM PDT 24
Peak memory 288676 kb
Host smart-85c31be3-997e-4d7b-a49c-3542f97e5fd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900932444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3900932444
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.4181080757
Short name T338
Test name
Test status
Simulation time 29433017973 ps
CPU time 297.43 seconds
Started Aug 04 04:43:23 PM PDT 24
Finished Aug 04 04:48:21 PM PDT 24
Peak memory 248240 kb
Host smart-6a55b917-a2cb-4244-9351-c46e34c72ac0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181080757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.4181080757
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1003257119
Short name T574
Test name
Test status
Simulation time 810000864 ps
CPU time 17.76 seconds
Started Aug 04 04:43:19 PM PDT 24
Finished Aug 04 04:43:37 PM PDT 24
Peak memory 248256 kb
Host smart-ffe198b0-220e-47e4-8c9e-e9070545a5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10032
57119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1003257119
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3854321284
Short name T430
Test name
Test status
Simulation time 328091497 ps
CPU time 31.36 seconds
Started Aug 04 04:43:22 PM PDT 24
Finished Aug 04 04:43:53 PM PDT 24
Peak memory 247536 kb
Host smart-d8827666-c137-4a1e-bbe7-81d33747fb3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38543
21284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3854321284
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3744134747
Short name T540
Test name
Test status
Simulation time 182911137 ps
CPU time 19.96 seconds
Started Aug 04 04:43:28 PM PDT 24
Finished Aug 04 04:43:48 PM PDT 24
Peak memory 247768 kb
Host smart-4184ffa1-8f88-452e-a324-1ef9fef5f2bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37441
34747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3744134747
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.17137322
Short name T673
Test name
Test status
Simulation time 758218721 ps
CPU time 20.1 seconds
Started Aug 04 04:43:22 PM PDT 24
Finished Aug 04 04:43:42 PM PDT 24
Peak memory 255876 kb
Host smart-4bbd2cba-092e-4f1d-a272-112343899518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17137
322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.17137322
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3915764436
Short name T550
Test name
Test status
Simulation time 253178707176 ps
CPU time 2968.11 seconds
Started Aug 04 04:43:26 PM PDT 24
Finished Aug 04 05:32:54 PM PDT 24
Peak memory 297076 kb
Host smart-feddc109-78b0-4779-83ef-c88bb2eaeca6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915764436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3915764436
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1095986938
Short name T231
Test name
Test status
Simulation time 36633010 ps
CPU time 2.08 seconds
Started Aug 04 04:43:31 PM PDT 24
Finished Aug 04 04:43:33 PM PDT 24
Peak memory 248440 kb
Host smart-65f5a626-a272-48e9-9f43-6fedfe552531
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1095986938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1095986938
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2626756503
Short name T19
Test name
Test status
Simulation time 22431388559 ps
CPU time 658.86 seconds
Started Aug 04 04:43:27 PM PDT 24
Finished Aug 04 04:54:26 PM PDT 24
Peak memory 272404 kb
Host smart-db7b1896-ca04-4bae-9582-8f3670e9d298
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626756503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2626756503
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2659060068
Short name T614
Test name
Test status
Simulation time 205180090 ps
CPU time 11.58 seconds
Started Aug 04 04:43:30 PM PDT 24
Finished Aug 04 04:43:42 PM PDT 24
Peak memory 248284 kb
Host smart-dc342beb-958c-4b1b-9035-a4598d92080b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2659060068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2659060068
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3419201640
Short name T439
Test name
Test status
Simulation time 16664055810 ps
CPU time 212.67 seconds
Started Aug 04 04:43:28 PM PDT 24
Finished Aug 04 04:47:01 PM PDT 24
Peak memory 255956 kb
Host smart-4cfc0b21-56c8-4772-8896-819b4aeb9a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34192
01640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3419201640
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.4288039374
Short name T571
Test name
Test status
Simulation time 3553016503 ps
CPU time 45.25 seconds
Started Aug 04 04:43:28 PM PDT 24
Finished Aug 04 04:44:13 PM PDT 24
Peak memory 248184 kb
Host smart-09017be4-6041-4aae-b931-417012ccfc66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42880
39374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.4288039374
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3219316858
Short name T210
Test name
Test status
Simulation time 71180584668 ps
CPU time 1129.82 seconds
Started Aug 04 04:43:32 PM PDT 24
Finished Aug 04 05:02:22 PM PDT 24
Peak memory 270964 kb
Host smart-6829dc12-09d9-4d68-a278-c24dbef6c3c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219316858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3219316858
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2414556444
Short name T312
Test name
Test status
Simulation time 8953412293 ps
CPU time 639 seconds
Started Aug 04 04:43:29 PM PDT 24
Finished Aug 04 04:54:08 PM PDT 24
Peak memory 267020 kb
Host smart-d1fb0055-f729-494f-bc56-cb8b4197d06f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414556444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2414556444
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3150330426
Short name T333
Test name
Test status
Simulation time 14900876797 ps
CPU time 134.59 seconds
Started Aug 04 04:43:31 PM PDT 24
Finished Aug 04 04:45:46 PM PDT 24
Peak memory 248092 kb
Host smart-1312890d-81cb-41d1-bc12-a25efbe85624
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150330426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3150330426
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1328967982
Short name T494
Test name
Test status
Simulation time 777204169 ps
CPU time 16.76 seconds
Started Aug 04 04:43:29 PM PDT 24
Finished Aug 04 04:43:46 PM PDT 24
Peak memory 248308 kb
Host smart-c5794885-8af9-48a0-976d-be278626f93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13289
67982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1328967982
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3313536319
Short name T440
Test name
Test status
Simulation time 113143896 ps
CPU time 8.18 seconds
Started Aug 04 04:43:27 PM PDT 24
Finished Aug 04 04:43:35 PM PDT 24
Peak memory 251196 kb
Host smart-c352f24d-99e9-4d38-b5cf-5d3f1a412ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33135
36319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3313536319
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3693799659
Short name T36
Test name
Test status
Simulation time 272541252 ps
CPU time 32.3 seconds
Started Aug 04 04:43:27 PM PDT 24
Finished Aug 04 04:43:59 PM PDT 24
Peak memory 256020 kb
Host smart-d2d678fe-b379-41d5-aaf2-75de14249621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36937
99659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3693799659
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3437867567
Short name T493
Test name
Test status
Simulation time 312850197 ps
CPU time 32.05 seconds
Started Aug 04 04:43:27 PM PDT 24
Finished Aug 04 04:43:59 PM PDT 24
Peak memory 255592 kb
Host smart-8999f31b-9c8f-427c-8cda-14817729f232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34378
67567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3437867567
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.533754592
Short name T551
Test name
Test status
Simulation time 3475948195 ps
CPU time 104.64 seconds
Started Aug 04 04:43:30 PM PDT 24
Finished Aug 04 04:45:15 PM PDT 24
Peak memory 256468 kb
Host smart-23d268be-09a8-41ae-aff8-c1ff5c2797b1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533754592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.533754592
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.966195346
Short name T214
Test name
Test status
Simulation time 97886469173 ps
CPU time 2557.83 seconds
Started Aug 04 04:43:30 PM PDT 24
Finished Aug 04 05:26:08 PM PDT 24
Peak memory 316396 kb
Host smart-9f4a2b6f-a218-4ae1-868e-aa0d529acccb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966195346 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.966195346
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%