Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	70341	1			T1	60		T7	4		T16	6
class_i[0x1]	68473	1			T7	6		T15	2		T4	14
class_i[0x2]	42776	1			T1	61		T2	53		T15	9
class_i[0x3]	56004	1			T2	1545		T3	17		T11	1

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	56881	1			T1	8		T2	473		T3	7
alert[0x1]	60135	1			T1	25		T2	418		T3	2
alert[0x2]	59711	1			T1	72		T2	482		T3	7
alert[0x3]	60867	1			T1	16		T2	225		T3	1

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

237326

1

T1

121

T2

1598

T3

17

esc_ping_fail

268

1

T7

6

T15

9

T16

6

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	56798	1			T1	8		T2	473		T3	7
esc_integrity_fail	alert[0x1]	60075	1			T1	25		T2	418		T3	2
esc_integrity_fail	alert[0x2]	59638	1			T1	72		T2	482		T3	7
esc_integrity_fail	alert[0x3]	60815	1			T1	16		T2	225		T3	1
esc_ping_fail	alert[0x0]	83	1			T7	1		T15	4		T17	2
esc_ping_fail	alert[0x1]	60	1			T15	1		T16	2		T17	1
esc_ping_fail	alert[0x2]	73	1			T7	3		T15	2		T16	2
esc_ping_fail	alert[0x3]	52	1			T7	2		T15	2		T16	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	70287	1			T1	60		T7	4		T31	1426
esc_integrity_fail	class_i[0x1]	68404	1			T15	2		T4	14		T17	3
esc_integrity_fail	class_i[0x2]	42696	1			T1	61		T2	53		T4	3
esc_integrity_fail	class_i[0x3]	55939	1			T2	1545		T3	17		T11	1
esc_ping_fail	class_i[0x0]	54	1			T16	6		T70	2		T173	3
esc_ping_fail	class_i[0x1]	69	1			T7	6		T17	4		T308	4
esc_ping_fail	class_i[0x2]	80	1			T15	9		T207	1		T173	1
esc_ping_fail	class_i[0x3]	65	1			T70	3		T207	7		T310	6