Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	727712217	0	0	629
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	727712217	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	727712217	727567330	0	0
tb.dut.CheckAccuCntDw	0	0	629	629	0	0
tb.dut.CheckEscCntDw	0	0	629	629	0	0
tb.dut.CheckNAlerts	0	0	629	629	0	0
tb.dut.CheckNClasses	0	0	629	629	0	0
tb.dut.CheckNEscSev	0	0	629	629	0	0
tb.dut.CrashdumpKnownO_A	0	0	727712217	727567330	0	0
tb.dut.EdnKnownO_A	0	0	727712217	727567330	0	0
tb.dut.EscPKnownO_A	0	0	727712217	727567330	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	727712217	60	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	727712217	60	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	727712217	60	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	727712217	60	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	727712217	60	0	0
tb.dut.IrqAKnownO_A	0	0	727712217	727567330	0	0
tb.dut.IrqBKnownO_A	0	0	727712217	727567330	0	0
tb.dut.IrqCKnownO_A	0	0	727712217	727567330	0	0
tb.dut.IrqDKnownO_A	0	0	727712217	727567330	0	0
tb.dut.TlAReadyKnownO_A	0	0	727712217	727567330	0	0
tb.dut.TlDValidKnownO_A	0	0	727712217	727567330	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	750626207	2981152	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	750626207	10906	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	750626207	10772	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	750626207	10680	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	750626207	10603	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	750626207	11034	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	750626207	10533	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	750626207	10470	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	750626207	10772	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	750626207	10860	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	750626207	10850	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	750626207	10591	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	750626207	10575	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	750626207	10624	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	750626207	10817	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	750626207	11064	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	750626207	10397	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	750626207	10760	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	750626207	10751	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	750626207	10921	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	750626207	10489	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	750626207	10999	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	750626207	10723	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	750626207	10662	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	750626207	10854	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	750626207	10626	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	750626207	10821	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	750626207	10137	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	750626207	10627	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	750626207	10531	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	750626207	10829	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	750626207	10821	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	750626207	10712	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	750626207	10683	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	750626207	11013	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	750626207	10385	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	750626207	10554	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	750626207	10855	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	750626207	10700	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	750626207	10745	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	750626207	10900	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	750626207	10504	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	750626207	10705	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	750626207	10768	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	750626207	10991	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	750626207	10619	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	750626207	10858	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	750626207	10707	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	750626207	10645	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	750626207	10567	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	750626207	10463	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	750626207	10743	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	750626207	10586	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	750626207	10413	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	750626207	10684	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	750626207	10831	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	750626207	10589	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	750626207	10961	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	750626207	10596	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	750626207	10744	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	750626207	10497	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	750626207	10799	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	750626207	10934	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	750626207	10582	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	750626207	10826	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	750626207	10629	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	750626207	10557	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	750626207	10647	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	750626207	10404	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	750626207	10587	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	750626207	19996	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	750626207	10684	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	750626207	10478	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	750626207	10834	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	750626207	10800	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	750626207	10744	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	750626207	10671	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	750626207	10736	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	750626207	10353	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	727712217	60	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	727712217	60	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	727712217	60	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	727712217	3405	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	727712217	216524	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	727712217	390514016	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	727712217	208	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	727712217	875	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	727712217	42	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	727712217	423	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	727596159	284307814	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	727712217	966	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	727712217	943	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	727712217	923	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	727712217	902	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	727712217	581	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	727712217	76944	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	727712217	474	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	727712217	63	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	727712217	989	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	727712217	809	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	727595321	727526509	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	629	629	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	727712217	727567330	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	727712217	60	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	727712217	60	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	727712217	60	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	727712217	3942	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	727712217	258130	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	727712217	385978691	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	727712217	155	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	727712217	530	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	727712217	26	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	727712217	235	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	727596159	307490740	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	727712217	592	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	727712217	575	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	727712217	566	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	727712217	552	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	727712217	891	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	727712217	112601	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	727712217	817	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	727712217	46	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	727712217	980	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	727712217	800	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	727595321	727526509	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	629	629	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	727712217	727567330	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	727712217	60	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	727712217	60	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	727712217	60	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	727712217	1318	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	727712217	171053	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	727712217	407139591	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	727712217	176	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	727712217	474	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	727712217	22	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	727712217	211	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	727596159	312621072	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	727712217	567	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	727712217	559	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	727712217	546	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	727712217	534	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	727712217	1035	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	727712217	105168	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	727712217	936	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	727712217	76	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	727712217	941	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	727712217	761	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	727595321	727526509	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	629	629	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	727712217	727567330	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	727712217	60	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	727712217	60	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	727712217	60	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	727712217	5737	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	727712217	184374	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	727712217	430595305	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	727712217	192	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	727712217	525	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	727712217	25	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	727712217	254	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	727596159	324646369	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	727712217	598	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	727712217	590	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	727712217	577	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	727712217	558	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	727712217	690	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	727712217	81801	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	727712217	606	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	727712217	58	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	727712217	1012	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	727712217	832	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	727595321	727526509	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	629	629	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	727712217	727567330	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	750626207	130897557	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	750626207	749950249	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	750626207	749950249	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	750626207	203118542	0	0
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