Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	63	1			T1	1		T2	1		T75	1
class_index[0x1]	46	1			T1	2		T2	1		T66	2
class_index[0x2]	76	1			T1	1		T2	1		T25	1
class_index[0x3]	58	1			T25	1		T66	1		T29	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	89	1			T25	2		T66	3		T76	1
intr_timeout_cnt[1]	51	1			T1	1		T75	1		T66	1
intr_timeout_cnt[2]	30	1			T2	1		T54	1		T91	4
intr_timeout_cnt[3]	15	1			T1	3		T2	1		T29	1
intr_timeout_cnt[4]	9	1			T66	1		T79	1		T249	1
intr_timeout_cnt[5]	14	1			T29	1		T91	1		T250	1
intr_timeout_cnt[6]	6	1			T73	1		T83	1		T251	1
intr_timeout_cnt[7]	18	1			T83	1		T98	1		T62	2
intr_timeout_cnt[8]	6	1			T2	1		T66	1		T51	1
intr_timeout_cnt[9]	5	1			T91	1		T58	1		T251	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	28	1			T66	1		T76	1		T73	1
class_index[0x0]	intr_timeout_cnt[1]	13	1			T1	1		T75	1		T80	1
class_index[0x0]	intr_timeout_cnt[2]	6	1			T2	1		T91	1		T41	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T23	1		T252	1		T253	1
class_index[0x0]	intr_timeout_cnt[4]	1	1			T79	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[5]	2	1			T250	1		T249	1		-	-
class_index[0x0]	intr_timeout_cnt[6]	1	1			T254	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	5	1			T62	2		T251	1		T255	1
class_index[0x0]	intr_timeout_cnt[8]	2	1			T66	1		T51	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T91	1		T58	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	15	1			T66	1		T36	2		T82	1
class_index[0x1]	intr_timeout_cnt[1]	8	1			T91	1		T92	1		T86	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T54	1		T91	1		T86	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T1	2		T29	1		T256	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T66	1		T257	1		T258	1
class_index[0x1]	intr_timeout_cnt[5]	3	1			T259	1		T252	2		-	-
class_index[0x1]	intr_timeout_cnt[6]	3	1			T73	1		T260	1		T261	1
class_index[0x1]	intr_timeout_cnt[7]	2	1			T83	1		T262	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T2	1		T263	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	28	1			T25	1		T66	1		T50	1
class_index[0x2]	intr_timeout_cnt[1]	17	1			T30	1		T81	1		T54	1
class_index[0x2]	intr_timeout_cnt[2]	14	1			T91	2		T92	2		T171	1
class_index[0x2]	intr_timeout_cnt[3]	3	1			T1	1		T2	1		T41	1
class_index[0x2]	intr_timeout_cnt[4]	2	1			T264	1		T265	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	4	1			T259	1		T266	1		T267	1
class_index[0x2]	intr_timeout_cnt[7]	5	1			T268	1		T269	2		T254	1
class_index[0x2]	intr_timeout_cnt[9]	3	1			T251	1		T254	1		T270	1
class_index[0x3]	intr_timeout_cnt[0]	18	1			T25	1		T30	1		T83	1
class_index[0x3]	intr_timeout_cnt[1]	13	1			T66	1		T96	1		T86	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T268	1		T257	1		T230	1
class_index[0x3]	intr_timeout_cnt[3]	5	1			T79	1		T53	1		T86	1
class_index[0x3]	intr_timeout_cnt[4]	3	1			T249	1		T269	1		T260	1
class_index[0x3]	intr_timeout_cnt[5]	5	1			T29	1		T91	1		T98	1
class_index[0x3]	intr_timeout_cnt[6]	2	1			T83	1		T251	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	6	1			T98	1		T271	1		T272	1
class_index[0x3]	intr_timeout_cnt[8]	2	1			T249	1		T273	1		-	-