Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	355297	1			T1	14		T2	715		T3	1405
all_values[1]	355297	1			T1	14		T2	715		T3	1405
all_values[2]	355297	1			T1	14		T2	715		T3	1405
all_values[3]	355297	1			T1	14		T2	715		T3	1405

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

707333

1

T1

26

T2

1456

T3

2825

auto[1]

713855

1

T1

30

T2

1404

T3

2795

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

835784

1

T1

9

T2

2034

T3

2852

auto[1]

585404

1

T1

47

T2

826

T3

2768

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	100473	1			T2	262		T3	356		T6	438
all_values[0]	auto[0]	auto[1]	76175	1			T1	3		T2	105		T3	350
all_values[0]	auto[1]	auto[0]	101907	1			T1	1		T2	257		T3	350
all_values[0]	auto[1]	auto[1]	76742	1			T1	10		T2	91		T3	349
all_values[1]	auto[0]	auto[0]	105143	1			T1	4		T2	261		T3	362
all_values[1]	auto[0]	auto[1]	71765	1			T1	1		T2	89		T3	359
all_values[1]	auto[1]	auto[0]	106453	1			T1	1		T2	258		T3	347
all_values[1]	auto[1]	auto[1]	71936	1			T1	8		T2	107		T3	337
all_values[2]	auto[0]	auto[0]	105031	1			T1	1		T2	250		T3	359
all_values[2]	auto[0]	auto[1]	71793	1			T1	8		T2	114		T3	334
all_values[2]	auto[1]	auto[0]	106585	1			T2	250		T3	371		T11	1
all_values[2]	auto[1]	auto[1]	71888	1			T1	5		T2	101		T3	341
all_values[3]	auto[0]	auto[0]	104455	1			T1	2		T2	262		T3	355
all_values[3]	auto[0]	auto[1]	72498	1			T1	7		T2	113		T3	350
all_values[3]	auto[1]	auto[0]	105737	1			T2	234		T3	352		T11	1
all_values[3]	auto[1]	auto[1]	72607	1			T1	5		T2	106		T3	348