Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	355297	1			T1	14		T2	715		T3	1405
all_pins[1]	355297	1			T1	14		T2	715		T3	1405
all_pins[2]	355297	1			T1	14		T2	715		T3	1405
all_pins[3]	355297	1			T1	14		T2	715		T3	1405

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1128015	1			T1	28		T2	2455		T3	4245
values[0x1]	293173	1			T1	28		T2	405		T3	1375
transitions[0x0=>0x1]	194639	1			T1	13		T2	273		T3	870
transitions[0x1=>0x0]	194892	1			T1	14		T2	273		T3	871

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	278555	1			T1	4		T2	624		T3	1056
all_pins[0]	values[0x1]	76742	1			T1	10		T2	91		T3	349
all_pins[0]	transitions[0x0=>0x1]	76018	1			T1	6		T2	90		T3	348
all_pins[0]	transitions[0x1=>0x0]	72136	1			T1	2		T2	105		T3	348
all_pins[1]	values[0x0]	283361	1			T1	6		T2	608		T3	1068
all_pins[1]	values[0x1]	71936	1			T1	8		T2	107		T3	337
all_pins[1]	transitions[0x0=>0x1]	38935	1			T1	3		T2	67		T3	170
all_pins[1]	transitions[0x1=>0x0]	43741	1			T1	5		T2	51		T3	182
all_pins[2]	values[0x0]	283409	1			T1	9		T2	614		T3	1064
all_pins[2]	values[0x1]	71888	1			T1	5		T2	101		T3	341
all_pins[2]	transitions[0x0=>0x1]	39633	1			T1	2		T2	58		T3	169
all_pins[2]	transitions[0x1=>0x0]	39681	1			T1	5		T2	64		T3	165
all_pins[3]	values[0x0]	282690	1			T1	9		T2	609		T3	1057
all_pins[3]	values[0x1]	72607	1			T1	5		T2	106		T3	348
all_pins[3]	transitions[0x0=>0x1]	40053	1			T1	2		T2	58		T3	183
all_pins[3]	transitions[0x1=>0x0]	39334	1			T1	2		T2	53		T3	176