Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1			T147	4		T149	7		T224	4
all_values[1]	278	1			T147	4		T149	7		T224	4
all_values[2]	278	1			T147	4		T149	7		T224	4
all_values[3]	278	1			T147	4		T149	7		T224	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

638

1

T147

7

T149

16

T224

7

auto[1]

474

1

T147

9

T149

12

T224

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

412

1

T147

5

T149

13

T224

2

auto[1]

700

1

T147

11

T149

15

T224

14

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

619

1

T147

10

T149

18

T224

10

auto[1]

493

1

T147

6

T149

10

T224

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

62

1

T147

3

T337

2

T338

3

all_values[0]

auto[0]

auto[0]

auto[1]

26

1

T149

1

T337

1

T338

1

all_values[0]

auto[0]

auto[1]

auto[0]

43

1

T149

1

T337

1

T338

2

all_values[0]

auto[0]

auto[1]

auto[1]

18

1

T149

1

T224

1

T339

1

all_values[0]

auto[1]

auto[0]

auto[1]

78

1

T149

3

T224

2

T337

1

all_values[0]

auto[1]

auto[1]

auto[1]

51

1

T147

1

T149

1

T224

1

all_values[1]

auto[0]

auto[0]

auto[0]

57

1

T149

3

T337

2

T338

2

all_values[1]

auto[0]

auto[0]

auto[1]

34

1

T149

1

T337

1

T338

1

all_values[1]

auto[0]

auto[1]

auto[0]

37

1

T147

1

T337

1

T244

1

all_values[1]

auto[0]

auto[1]

auto[1]

26

1

T149

1

T224

3

T245

1

all_values[1]

auto[1]

auto[0]

auto[1]

75

1

T147

2

T149

1

T224

1

all_values[1]

auto[1]

auto[1]

auto[1]

49

1

T147

1

T149

1

T337

1

all_values[2]

auto[0]

auto[0]

auto[0]

59

1

T149

3

T224

1

T337

1

all_values[2]

auto[0]

auto[0]

auto[1]

25

1

T149

1

T224

1

T340

1

all_values[2]

auto[0]

auto[1]

auto[0]

45

1

T147

1

T338

1

T244

2

all_values[2]

auto[0]

auto[1]

auto[1]

25

1

T147

2

T224

1

T337

2

all_values[2]

auto[1]

auto[0]

auto[1]

69

1

T149

1

T337

2

T338

2

all_values[2]

auto[1]

auto[1]

auto[1]

55

1

T147

1

T149

2

T224

1

all_values[3]

auto[0]

auto[0]

auto[0]

53

1

T149

2

T337

2

T338

1

all_values[3]

auto[0]

auto[0]

auto[1]

32

1

T147

2

T224

1

T338

1

all_values[3]

auto[0]

auto[1]

auto[0]

56

1

T149

4

T224

1

T337

1

all_values[3]

auto[0]

auto[1]

auto[1]

21

1

T147

1

T224

1

T245

1

all_values[3]

auto[1]

auto[0]

auto[1]

68

1

T224

1

T337

3

T338

3

all_values[3]

auto[1]

auto[1]

auto[1]

48

1

T147

1

T149

1

T337

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal