Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	90268	1			T3	1388		T6	1756		T13	13
accum_cnt_1000	236010	1			T2	335		T3	1521		T6	1558
accum_cnt_100	26706	1			T1	15		T2	137		T3	86
accum_cnt_50	66793	1			T1	39		T2	314		T3	70
accum_cnt_10	215695	1			T1	29		T2	964		T3	26
accum_cnt_0	371495	1			T1	1		T2	506		T3	1063

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	262314	1			T1	21		T2	564		T3	1057
class_index[0x1]	262314	1			T1	21		T2	564		T3	1057
class_index[0x2]	262314	1			T1	21		T2	564		T3	1057
class_index[0x3]	262314	1			T1	21		T2	564		T3	1057

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	23690	1			T3	495		T6	609		T4	496
class_index[0x0]	accum_cnt_1000	61664	1			T3	492		T6	528		T22	21
class_index[0x0]	accum_cnt_100	7891	1			T1	15		T3	27		T6	24
class_index[0x0]	accum_cnt_50	15139	1			T1	4		T3	20		T6	21
class_index[0x0]	accum_cnt_10	60791	1			T1	2		T2	447		T3	15
class_index[0x0]	accum_cnt_0	84085	1			T2	117		T3	3		T11	13
class_index[0x1]	accum_cnt_2000	24834	1			T6	533		T49	371		T31	299
class_index[0x1]	accum_cnt_1000	61388	1			T2	108		T6	489		T13	662
class_index[0x1]	accum_cnt_100	6366	1			T2	82		T6	21		T13	158
class_index[0x1]	accum_cnt_50	14295	1			T1	13		T2	43		T11	8
class_index[0x1]	accum_cnt_10	49783	1			T1	7		T2	298		T11	5
class_index[0x1]	accum_cnt_0	90081	1			T1	1		T2	33		T3	1057
class_index[0x2]	accum_cnt_2000	23365	1			T3	400		T6	614		T4	514
class_index[0x2]	accum_cnt_1000	60523	1			T2	226		T3	591		T6	541
class_index[0x2]	accum_cnt_100	6649	1			T2	55		T3	35		T6	29
class_index[0x2]	accum_cnt_50	15399	1			T1	9		T2	36		T3	27
class_index[0x2]	accum_cnt_10	50950	1			T1	12		T2	16		T3	3
class_index[0x2]	accum_cnt_0	97186	1			T2	231		T3	1		T6	1
class_index[0x3]	accum_cnt_2000	18379	1			T3	493		T13	13		T49	561
class_index[0x3]	accum_cnt_1000	52435	1			T2	1		T3	438		T13	856
class_index[0x3]	accum_cnt_100	5800	1			T3	24		T13	46		T49	26
class_index[0x3]	accum_cnt_50	21960	1			T1	13		T2	235		T3	23
class_index[0x3]	accum_cnt_10	54171	1			T1	8		T2	203		T3	8
class_index[0x3]	accum_cnt_0	100143	1			T2	125		T3	2		T11	13