Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	9020	1			T15	1		T4	1197		T31	493
alert[0x1]	8347	1			T16	1		T4	994		T87	31
alert[0x2]	11070	1			T16	1		T31	49		T32	57
alert[0x3]	6981	1			T4	77		T66	466		T87	47
alert[0x4]	6702	1			T1	8		T15	2		T4	330
alert[0x5]	9094	1			T15	2		T4	170		T31	1612
alert[0x6]	8537	1			T2	3		T7	1		T31	61
alert[0x7]	9133	1			T15	1		T4	441		T32	866
alert[0x8]	7487	1			T7	1		T4	270		T17	1
alert[0x9]	4512	1			T4	82		T17	1		T35	11
alert[0xa]	10056	1			T7	1		T4	33		T66	8
alert[0xb]	2887	1			T15	1		T31	280		T32	37
alert[0xc]	5988	1			T15	1		T4	636		T31	48
alert[0xd]	12897	1			T32	8		T76	9		T35	23
alert[0xe]	8313	1			T16	1		T4	760		T87	1273
alert[0xf]	3687	1			T2	29		T70	2		T35	5
alert[0x10]	18248	1			T16	1		T31	4		T35	8
alert[0x11]	3865	1			T31	646		T66	3		T87	376
alert[0x12]	5734	1			T1	1		T15	1		T4	26
alert[0x13]	14117	1			T16	1		T70	3		T76	14
alert[0x14]	10326	1			T16	1		T4	68		T65	1
alert[0x15]	7765	1			T66	18		T70	1		T35	4
alert[0x16]	12177	1			T31	90		T87	21		T76	1
alert[0x17]	8535	1			T11	3		T7	2		T87	6
alert[0x18]	10184	1			T15	1		T31	59		T32	6
alert[0x19]	10010	1			T31	1589		T66	7		T70	1
alert[0x1a]	10551	1			T7	1		T15	1		T16	1
alert[0x1b]	8513	1			T16	1		T32	1		T300	128
alert[0x1c]	5433	1			T7	2		T16	2		T4	41
alert[0x1d]	11752	1			T2	40		T29	1112		T207	1
alert[0x1e]	10766	1			T15	1		T16	1		T4	201
alert[0x1f]	5167	1			T16	1		T31	11		T87	16
alert[0x20]	5284	1			T4	1		T64	1		T66	72
alert[0x21]	5379	1			T4	119		T31	104		T87	17
alert[0x22]	10284	1			T16	1		T17	1		T32	357
alert[0x23]	8704	1			T16	1		T4	1		T32	68
alert[0x24]	11111	1			T31	325		T64	1		T70	2
alert[0x25]	5833	1			T16	1		T4	3		T32	89
alert[0x26]	8115	1			T11	4		T66	88		T87	1
alert[0x27]	6334	1			T4	31		T31	35		T228	2
alert[0x28]	9862	1			T2	3		T15	1		T31	133
alert[0x29]	16563	1			T7	1		T15	1		T4	34
alert[0x2a]	4587	1			T7	1		T4	138		T17	1
alert[0x2b]	6047	1			T4	2		T31	664		T66	161
alert[0x2c]	5091	1			T2	6		T16	1		T32	16
alert[0x2d]	8963	1			T66	7		T87	140		T29	326
alert[0x2e]	13051	1			T7	1		T32	10		T301	1
alert[0x2f]	3352	1			T15	1		T31	8		T32	10
alert[0x30]	9742	1			T16	1		T66	640		T87	483
alert[0x31]	7492	1			T2	30		T7	1		T32	26
alert[0x32]	5527	1			T15	1		T4	12		T35	71
alert[0x33]	6802	1			T7	1		T15	1		T4	516
alert[0x34]	17303	1			T7	1		T16	1		T64	4
alert[0x35]	9358	1			T1	9		T4	610		T32	201
alert[0x36]	5048	1			T15	1		T31	24		T32	65
alert[0x37]	3675	1			T76	3		T35	3		T29	16
alert[0x38]	8405	1			T4	29		T32	21		T66	242
alert[0x39]	10957	1			T4	21		T32	31		T64	3
alert[0x3a]	6727	1			T4	32		T31	25		T32	1
alert[0x3b]	4216	1			T31	1		T76	1		T29	202
alert[0x3c]	14998	1			T7	1		T16	1		T4	29
alert[0x3d]	7886	1			T4	25		T87	6		T35	6
alert[0x3e]	19847	1			T1	2		T3	3		T11	2
alert[0x3f]	3737	1			T11	9		T36	3		T30	4
alert[0x40]	7578	1			T15	1		T4	96		T32	4154

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	141712	1			T7	2		T15	1		T66	44
class_i[0x1]	136845	1			T1	8		T3	3		T11	4
class_i[0x2]	82654	1			T11	5		T7	1		T15	18
class_i[0x3]	194501	1			T1	12		T2	111		T11	9

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

555028

1

T1

20

T2

111

T3

3

alert_ping_fail

684

1

T7

15

T15

19

T16

19

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	9014	1			T4	1197		T31	493		T66	1
alert_integrity_fail	alert[0x1]	8331	1			T4	994		T87	31		T30	1
alert_integrity_fail	alert[0x2]	11064	1			T31	49		T32	57		T66	13
alert_integrity_fail	alert[0x3]	6975	1			T4	77		T66	466		T87	47
alert_integrity_fail	alert[0x4]	6692	1			T1	8		T4	330		T31	125
alert_integrity_fail	alert[0x5]	9083	1			T4	170		T31	1612		T32	204
alert_integrity_fail	alert[0x6]	8527	1			T2	3		T31	61		T32	65
alert_integrity_fail	alert[0x7]	9113	1			T4	441		T32	866		T66	18
alert_integrity_fail	alert[0x8]	7469	1			T4	270		T32	19		T87	125
alert_integrity_fail	alert[0x9]	4499	1			T4	82		T35	11		T29	1907
alert_integrity_fail	alert[0xa]	10044	1			T4	33		T66	8		T36	2
alert_integrity_fail	alert[0xb]	2881	1			T31	280		T32	37		T76	5
alert_integrity_fail	alert[0xc]	5977	1			T4	636		T31	48		T32	37
alert_integrity_fail	alert[0xd]	12891	1			T32	8		T76	9		T35	23
alert_integrity_fail	alert[0xe]	8304	1			T4	760		T87	1273		T29	2
alert_integrity_fail	alert[0xf]	3678	1			T2	29		T35	5		T81	105
alert_integrity_fail	alert[0x10]	18240	1			T31	4		T35	8		T29	1685
alert_integrity_fail	alert[0x11]	3860	1			T31	646		T66	3		T87	376
alert_integrity_fail	alert[0x12]	5723	1			T1	1		T4	26		T31	13
alert_integrity_fail	alert[0x13]	14102	1			T76	14		T53	42		T101	84
alert_integrity_fail	alert[0x14]	10315	1			T4	68		T76	1		T300	101
alert_integrity_fail	alert[0x15]	7759	1			T66	18		T35	4		T300	63
alert_integrity_fail	alert[0x16]	12169	1			T31	90		T87	21		T76	1
alert_integrity_fail	alert[0x17]	8522	1			T11	3		T87	6		T29	77
alert_integrity_fail	alert[0x18]	10175	1			T31	59		T32	6		T29	67
alert_integrity_fail	alert[0x19]	10002	1			T31	1589		T66	7		T87	10
alert_integrity_fail	alert[0x1a]	10537	1			T31	583		T66	120		T87	44
alert_integrity_fail	alert[0x1b]	8508	1			T32	1		T300	128		T81	131
alert_integrity_fail	alert[0x1c]	5419	1			T4	41		T32	161		T64	6
alert_integrity_fail	alert[0x1d]	11742	1			T2	40		T29	1112		T53	3
alert_integrity_fail	alert[0x1e]	10754	1			T4	201		T31	153		T87	121
alert_integrity_fail	alert[0x1f]	5150	1			T31	11		T87	16		T35	7
alert_integrity_fail	alert[0x20]	5271	1			T4	1		T64	1		T66	72
alert_integrity_fail	alert[0x21]	5367	1			T4	119		T31	104		T87	17
alert_integrity_fail	alert[0x22]	10270	1			T32	357		T29	94		T36	3
alert_integrity_fail	alert[0x23]	8696	1			T4	1		T32	68		T87	49
alert_integrity_fail	alert[0x24]	11097	1			T31	325		T64	1		T76	13
alert_integrity_fail	alert[0x25]	5825	1			T4	3		T32	89		T35	1
alert_integrity_fail	alert[0x26]	8106	1			T11	4		T66	88		T87	1
alert_integrity_fail	alert[0x27]	6321	1			T4	31		T31	35		T228	2
alert_integrity_fail	alert[0x28]	9851	1			T2	3		T31	133		T32	265
alert_integrity_fail	alert[0x29]	16552	1			T4	34		T31	229		T66	5
alert_integrity_fail	alert[0x2a]	4572	1			T4	138		T32	5		T66	14
alert_integrity_fail	alert[0x2b]	6036	1			T4	2		T31	664		T66	161
alert_integrity_fail	alert[0x2c]	5081	1			T2	6		T32	16		T87	72
alert_integrity_fail	alert[0x2d]	8957	1			T66	7		T87	140		T29	326
alert_integrity_fail	alert[0x2e]	13039	1			T32	10		T300	1020		T81	133
alert_integrity_fail	alert[0x2f]	3344	1			T31	8		T32	10		T53	110
alert_integrity_fail	alert[0x30]	9734	1			T66	640		T87	483		T300	115
alert_integrity_fail	alert[0x31]	7477	1			T2	30		T32	26		T87	70
alert_integrity_fail	alert[0x32]	5518	1			T4	12		T35	71		T29	261
alert_integrity_fail	alert[0x33]	6782	1			T4	516		T76	1		T35	2
alert_integrity_fail	alert[0x34]	17290	1			T64	4		T87	77		T76	70
alert_integrity_fail	alert[0x35]	9349	1			T1	9		T4	610		T32	201
alert_integrity_fail	alert[0x36]	5038	1			T31	24		T32	65		T87	1487
alert_integrity_fail	alert[0x37]	3668	1			T76	3		T35	3		T29	16
alert_integrity_fail	alert[0x38]	8394	1			T4	29		T32	21		T66	242
alert_integrity_fail	alert[0x39]	10946	1			T4	21		T32	31		T64	3
alert_integrity_fail	alert[0x3a]	6720	1			T4	32		T31	25		T32	1
alert_integrity_fail	alert[0x3b]	4207	1			T31	1		T76	1		T29	202
alert_integrity_fail	alert[0x3c]	14986	1			T4	29		T76	10		T29	20
alert_integrity_fail	alert[0x3d]	7874	1			T4	25		T87	6		T35	6
alert_integrity_fail	alert[0x3e]	19838	1			T1	2		T3	3		T11	2
alert_integrity_fail	alert[0x3f]	3732	1			T11	9		T36	3		T30	4
alert_integrity_fail	alert[0x40]	7571	1			T4	96		T32	4154		T66	7
alert_ping_fail	alert[0x0]	6	1			T15	1		T302	1		T303	2
alert_ping_fail	alert[0x1]	16	1			T16	1		T207	1		T216	1
alert_ping_fail	alert[0x2]	6	1			T16	1		T304	1		T305	1
alert_ping_fail	alert[0x3]	6	1			T302	1		T306	1		T307	1
alert_ping_fail	alert[0x4]	10	1			T15	2		T308	1		T173	1
alert_ping_fail	alert[0x5]	11	1			T15	2		T207	2		T234	1
alert_ping_fail	alert[0x6]	10	1			T7	1		T70	1		T308	1
alert_ping_fail	alert[0x7]	20	1			T15	1		T216	1		T173	1
alert_ping_fail	alert[0x8]	18	1			T7	1		T17	1		T207	1
alert_ping_fail	alert[0x9]	13	1			T17	1		T308	1		T302	1
alert_ping_fail	alert[0xa]	12	1			T7	1		T213	1		T301	1
alert_ping_fail	alert[0xb]	6	1			T15	1		T173	1		T309	1
alert_ping_fail	alert[0xc]	11	1			T15	1		T310	1		T173	1
alert_ping_fail	alert[0xd]	6	1			T311	1		T303	1		T45	1
alert_ping_fail	alert[0xe]	9	1			T16	1		T312	2		T309	2
alert_ping_fail	alert[0xf]	9	1			T70	2		T313	1		T314	1
alert_ping_fail	alert[0x10]	8	1			T16	1		T173	1		T311	1
alert_ping_fail	alert[0x11]	5	1			T310	1		T45	1		T315	1
alert_ping_fail	alert[0x12]	11	1			T15	1		T70	1		T207	1
alert_ping_fail	alert[0x13]	15	1			T16	1		T70	3		T207	1
alert_ping_fail	alert[0x14]	11	1			T16	1		T65	1		T70	1
alert_ping_fail	alert[0x15]	6	1			T70	1		T316	1		T317	1
alert_ping_fail	alert[0x16]	8	1			T207	1		T318	1		T45	1
alert_ping_fail	alert[0x17]	13	1			T7	2		T313	1		T305	2
alert_ping_fail	alert[0x18]	9	1			T15	1		T216	1		T173	2
alert_ping_fail	alert[0x19]	8	1			T70	1		T310	1		T45	1
alert_ping_fail	alert[0x1a]	14	1			T7	1		T15	1		T16	1
alert_ping_fail	alert[0x1b]	5	1			T16	1		T39	1		T319	1
alert_ping_fail	alert[0x1c]	14	1			T7	2		T16	2		T302	1
alert_ping_fail	alert[0x1d]	10	1			T207	1		T320	1		T303	1
alert_ping_fail	alert[0x1e]	12	1			T15	1		T16	1		T70	1
alert_ping_fail	alert[0x1f]	17	1			T16	1		T321	1		T173	1
alert_ping_fail	alert[0x20]	13	1			T308	1		T318	1		T302	1
alert_ping_fail	alert[0x21]	12	1			T308	1		T311	1		T315	1
alert_ping_fail	alert[0x22]	14	1			T16	1		T17	1		T74	2
alert_ping_fail	alert[0x23]	8	1			T16	1		T207	1		T302	1
alert_ping_fail	alert[0x24]	14	1			T70	2		T312	1		T45	1
alert_ping_fail	alert[0x25]	8	1			T16	1		T318	1		T304	1
alert_ping_fail	alert[0x26]	9	1			T207	1		T173	1		T315	2
alert_ping_fail	alert[0x27]	13	1			T45	1		T313	1		T315	1
alert_ping_fail	alert[0x28]	11	1			T15	1		T320	1		T322	1
alert_ping_fail	alert[0x29]	11	1			T7	1		T15	1		T17	1
alert_ping_fail	alert[0x2a]	15	1			T7	1		T17	1		T207	1
alert_ping_fail	alert[0x2b]	11	1			T303	2		T309	2		T323	1
alert_ping_fail	alert[0x2c]	10	1			T16	1		T207	1		T173	1
alert_ping_fail	alert[0x2d]	6	1			T310	1		T216	1		T312	1
alert_ping_fail	alert[0x2e]	12	1			T7	1		T301	1		T277	1
alert_ping_fail	alert[0x2f]	8	1			T15	1		T310	2		T173	1
alert_ping_fail	alert[0x30]	8	1			T16	1		T207	1		T309	1
alert_ping_fail	alert[0x31]	15	1			T7	1		T207	1		T173	1
alert_ping_fail	alert[0x32]	9	1			T15	1		T302	1		T311	1
alert_ping_fail	alert[0x33]	20	1			T7	1		T15	1		T308	1
alert_ping_fail	alert[0x34]	13	1			T7	1		T16	1		T313	2
alert_ping_fail	alert[0x35]	9	1			T173	1		T318	1		T312	1
alert_ping_fail	alert[0x36]	10	1			T15	1		T70	1		T308	1
alert_ping_fail	alert[0x37]	7	1			T318	1		T311	1		T45	1
alert_ping_fail	alert[0x38]	11	1			T310	1		T312	1		T45	1
alert_ping_fail	alert[0x39]	11	1			T308	1		T207	1		T324	1
alert_ping_fail	alert[0x3a]	7	1			T311	1		T325	1		T305	1
alert_ping_fail	alert[0x3b]	9	1			T303	1		T309	1		T313	1
alert_ping_fail	alert[0x3c]	12	1			T7	1		T16	1		T207	1
alert_ping_fail	alert[0x3d]	12	1			T318	1		T303	1		T312	1
alert_ping_fail	alert[0x3e]	9	1			T70	1		T207	1		T313	1
alert_ping_fail	alert[0x3f]	5	1			T317	1		T304	1		T326	1
alert_ping_fail	alert[0x40]	7	1			T15	1		T207	1		T303	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	141534	1			T66	44		T87	5366		T76	98
alert_integrity_fail	class_i[0x1]	136685	1			T1	8		T3	3		T11	4
alert_integrity_fail	class_i[0x2]	82447	1			T11	5		T4	1		T32	6779
alert_integrity_fail	class_i[0x3]	194362	1			T1	12		T2	111		T11	9
alert_ping_fail	class_i[0x0]	178	1			T7	2		T15	1		T70	6
alert_ping_fail	class_i[0x1]	160	1			T7	3		T16	18		T70	4
alert_ping_fail	class_i[0x2]	207	1			T7	1		T15	18		T17	4
alert_ping_fail	class_i[0x3]	139	1			T7	9		T16	1		T17	1