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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.25 99.99 98.72 97.09 100.00 100.00 99.38 99.56


Total test records in report: 834
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T134 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2075709477 Aug 05 06:01:32 PM PDT 24 Aug 05 06:20:08 PM PDT 24 47285681492 ps
T775 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.4165974884 Aug 05 06:01:12 PM PDT 24 Aug 05 06:01:14 PM PDT 24 26806207 ps
T776 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3770881541 Aug 05 06:01:20 PM PDT 24 Aug 05 06:09:53 PM PDT 24 16472018437 ps
T777 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2341191972 Aug 05 06:01:38 PM PDT 24 Aug 05 06:01:45 PM PDT 24 49179583 ps
T778 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2353064841 Aug 05 06:01:58 PM PDT 24 Aug 05 06:01:59 PM PDT 24 10335041 ps
T111 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.877248234 Aug 05 06:01:36 PM PDT 24 Aug 05 06:19:20 PM PDT 24 58332223876 ps
T779 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2972496447 Aug 05 06:01:41 PM PDT 24 Aug 05 06:01:55 PM PDT 24 87588216 ps
T131 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.705668181 Aug 05 06:01:21 PM PDT 24 Aug 05 06:12:05 PM PDT 24 4372132143 ps
T780 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3410082919 Aug 05 06:01:18 PM PDT 24 Aug 05 06:01:30 PM PDT 24 359540283 ps
T781 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2925910967 Aug 05 06:01:32 PM PDT 24 Aug 05 06:01:42 PM PDT 24 265838397 ps
T782 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3577495015 Aug 05 06:01:44 PM PDT 24 Aug 05 06:01:50 PM PDT 24 59781074 ps
T783 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1773912972 Aug 05 06:01:43 PM PDT 24 Aug 05 06:02:00 PM PDT 24 244046924 ps
T784 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1454642731 Aug 05 06:01:32 PM PDT 24 Aug 05 06:01:55 PM PDT 24 469472897 ps
T785 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3376214858 Aug 05 06:01:24 PM PDT 24 Aug 05 06:01:38 PM PDT 24 101639276 ps
T786 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3684952595 Aug 05 06:01:47 PM PDT 24 Aug 05 06:01:53 PM PDT 24 47980854 ps
T787 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2721091899 Aug 05 06:01:50 PM PDT 24 Aug 05 06:01:53 PM PDT 24 42735448 ps
T788 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3861123406 Aug 05 06:01:59 PM PDT 24 Aug 05 06:02:00 PM PDT 24 17422074 ps
T789 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.4220885742 Aug 05 06:01:36 PM PDT 24 Aug 05 06:02:13 PM PDT 24 629763992 ps
T790 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.4180151614 Aug 05 06:01:52 PM PDT 24 Aug 05 06:01:54 PM PDT 24 11439906 ps
T791 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.36151534 Aug 05 06:01:22 PM PDT 24 Aug 05 06:01:49 PM PDT 24 1545288071 ps
T792 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3810920965 Aug 05 06:01:55 PM PDT 24 Aug 05 06:01:57 PM PDT 24 6190052 ps
T793 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1842130898 Aug 05 06:01:51 PM PDT 24 Aug 05 06:01:52 PM PDT 24 7597184 ps
T158 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3759723414 Aug 05 06:01:44 PM PDT 24 Aug 05 06:01:47 PM PDT 24 50997323 ps
T794 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2927315110 Aug 05 06:01:24 PM PDT 24 Aug 05 06:01:33 PM PDT 24 191983032 ps
T137 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2049462603 Aug 05 06:01:19 PM PDT 24 Aug 05 06:04:04 PM PDT 24 2174679007 ps
T795 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1650063788 Aug 05 06:01:50 PM PDT 24 Aug 05 06:01:55 PM PDT 24 72328284 ps
T112 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1889975565 Aug 05 06:01:35 PM PDT 24 Aug 05 06:12:05 PM PDT 24 18636953246 ps
T796 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.547998071 Aug 05 06:02:03 PM PDT 24 Aug 05 06:02:05 PM PDT 24 8165283 ps
T136 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3799122478 Aug 05 06:01:32 PM PDT 24 Aug 05 06:06:57 PM PDT 24 8298925649 ps
T797 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.4097876649 Aug 05 06:01:23 PM PDT 24 Aug 05 06:01:25 PM PDT 24 10063135 ps
T127 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.791423109 Aug 05 06:01:50 PM PDT 24 Aug 05 06:05:28 PM PDT 24 1756858306 ps
T798 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1045167685 Aug 05 06:01:18 PM PDT 24 Aug 05 06:01:24 PM PDT 24 429749731 ps
T135 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3015991440 Aug 05 06:01:23 PM PDT 24 Aug 05 06:06:13 PM PDT 24 7756153923 ps
T132 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2073798827 Aug 05 06:01:50 PM PDT 24 Aug 05 06:12:14 PM PDT 24 14916454808 ps
T799 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3442944767 Aug 05 06:01:44 PM PDT 24 Aug 05 06:01:53 PM PDT 24 478988818 ps
T142 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.559189371 Aug 05 06:01:18 PM PDT 24 Aug 05 06:03:48 PM PDT 24 3748744292 ps
T800 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1164295913 Aug 05 06:01:58 PM PDT 24 Aug 05 06:02:00 PM PDT 24 16388301 ps
T801 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.799063033 Aug 05 06:01:16 PM PDT 24 Aug 05 06:01:53 PM PDT 24 1261211784 ps
T802 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.99794704 Aug 05 06:01:36 PM PDT 24 Aug 05 06:01:53 PM PDT 24 2819530400 ps
T803 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.341895320 Aug 05 06:01:19 PM PDT 24 Aug 05 06:01:24 PM PDT 24 55030001 ps
T804 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3286987349 Aug 05 06:01:23 PM PDT 24 Aug 05 06:01:24 PM PDT 24 15182670 ps
T805 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1629383238 Aug 05 06:01:29 PM PDT 24 Aug 05 06:01:34 PM PDT 24 43943072 ps
T133 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1912592549 Aug 05 06:01:43 PM PDT 24 Aug 05 06:12:05 PM PDT 24 5098579930 ps
T806 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.4282720184 Aug 05 06:01:22 PM PDT 24 Aug 05 06:01:31 PM PDT 24 232471649 ps
T807 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3449667162 Aug 05 06:02:00 PM PDT 24 Aug 05 06:02:01 PM PDT 24 21496506 ps
T345 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2195318988 Aug 05 06:01:51 PM PDT 24 Aug 05 06:07:38 PM PDT 24 2442308678 ps
T808 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3538384709 Aug 05 06:01:19 PM PDT 24 Aug 05 06:03:23 PM PDT 24 1740542421 ps
T156 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1559830079 Aug 05 06:01:31 PM PDT 24 Aug 05 06:02:41 PM PDT 24 10468336561 ps
T809 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3451647777 Aug 05 06:01:42 PM PDT 24 Aug 05 06:01:43 PM PDT 24 10757262 ps
T810 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3106479107 Aug 05 06:01:27 PM PDT 24 Aug 05 06:01:32 PM PDT 24 75648519 ps
T811 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2645597700 Aug 05 06:01:57 PM PDT 24 Aug 05 06:01:59 PM PDT 24 10015051 ps
T812 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.783306576 Aug 05 06:01:32 PM PDT 24 Aug 05 06:01:38 PM PDT 24 37650875 ps
T813 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2241083745 Aug 05 06:01:56 PM PDT 24 Aug 05 06:01:58 PM PDT 24 18133715 ps
T814 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2686372546 Aug 05 06:01:36 PM PDT 24 Aug 05 06:02:29 PM PDT 24 2776480470 ps
T815 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1635154010 Aug 05 06:01:24 PM PDT 24 Aug 05 06:01:29 PM PDT 24 62350061 ps
T816 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.300269849 Aug 05 06:01:56 PM PDT 24 Aug 05 06:01:58 PM PDT 24 8491949 ps
T817 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2039552637 Aug 05 06:01:33 PM PDT 24 Aug 05 06:01:39 PM PDT 24 117342892 ps
T346 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2879515348 Aug 05 06:01:23 PM PDT 24 Aug 05 06:10:16 PM PDT 24 7689312447 ps
T818 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3895340268 Aug 05 06:01:50 PM PDT 24 Aug 05 06:01:52 PM PDT 24 22976482 ps
T819 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3822978337 Aug 05 06:01:45 PM PDT 24 Aug 05 06:02:05 PM PDT 24 1111038550 ps
T820 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.402829871 Aug 05 06:01:49 PM PDT 24 Aug 05 06:01:51 PM PDT 24 12306572 ps
T821 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3502302149 Aug 05 06:01:22 PM PDT 24 Aug 05 06:01:36 PM PDT 24 656413270 ps
T159 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.433103024 Aug 05 06:01:51 PM PDT 24 Aug 05 06:01:54 PM PDT 24 96625636 ps
T143 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1604113853 Aug 05 06:01:49 PM PDT 24 Aug 05 06:04:30 PM PDT 24 7660036795 ps
T822 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1085045935 Aug 05 06:01:31 PM PDT 24 Aug 05 06:01:33 PM PDT 24 25415842 ps
T823 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1613185568 Aug 05 06:01:16 PM PDT 24 Aug 05 06:01:21 PM PDT 24 199303528 ps
T824 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1803642855 Aug 05 06:01:35 PM PDT 24 Aug 05 06:02:26 PM PDT 24 2749889439 ps
T825 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2181608820 Aug 05 06:01:41 PM PDT 24 Aug 05 06:01:43 PM PDT 24 14318999 ps
T826 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2653398817 Aug 05 06:01:44 PM PDT 24 Aug 05 06:01:46 PM PDT 24 38162616 ps
T827 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2785026210 Aug 05 06:01:45 PM PDT 24 Aug 05 06:01:56 PM PDT 24 527351596 ps
T154 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.980429115 Aug 05 06:01:49 PM PDT 24 Aug 05 06:01:51 PM PDT 24 23584851 ps
T828 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2082954577 Aug 05 06:01:17 PM PDT 24 Aug 05 06:01:42 PM PDT 24 2333350714 ps
T829 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1251545783 Aug 05 06:01:55 PM PDT 24 Aug 05 06:01:57 PM PDT 24 8370659 ps
T830 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.416068576 Aug 05 06:02:03 PM PDT 24 Aug 05 06:02:05 PM PDT 24 11407416 ps
T163 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.805440340 Aug 05 06:01:43 PM PDT 24 Aug 05 06:02:10 PM PDT 24 193135023 ps
T139 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3619528591 Aug 05 06:01:26 PM PDT 24 Aug 05 06:06:57 PM PDT 24 4678485811 ps
T344 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.4279131647 Aug 05 06:01:37 PM PDT 24 Aug 05 06:09:22 PM PDT 24 6131405647 ps
T831 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2174433716 Aug 05 06:01:24 PM PDT 24 Aug 05 06:02:16 PM PDT 24 1357657728 ps
T832 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1818185166 Aug 05 06:02:03 PM PDT 24 Aug 05 06:02:04 PM PDT 24 11670978 ps
T833 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.482148063 Aug 05 06:01:20 PM PDT 24 Aug 05 06:03:16 PM PDT 24 2064565596 ps
T834 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3463677689 Aug 05 06:01:49 PM PDT 24 Aug 05 06:01:51 PM PDT 24 10228057 ps
T140 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3795624772 Aug 05 06:01:33 PM PDT 24 Aug 05 06:07:32 PM PDT 24 6111614205 ps
T161 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3767777040 Aug 05 06:01:25 PM PDT 24 Aug 05 06:01:28 PM PDT 24 104465923 ps
T141 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.851222067 Aug 05 06:01:29 PM PDT 24 Aug 05 06:18:06 PM PDT 24 134668242298 ps

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3334901600
Short name T2
Test name
Test status
Simulation time 47923884102 ps
CPU time 1828.36 seconds
Started Aug 05 05:09:01 PM PDT 24
Finished Aug 05 05:39:30 PM PDT 24
Peak memory 288076 kb
Host smart-cf8947ed-c0a2-4dbf-bcde-96efbdc7e5f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334901600 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3334901600
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2244077050
Short name T4
Test name
Test status
Simulation time 131778745633 ps
CPU time 2083.81 seconds
Started Aug 05 05:09:23 PM PDT 24
Finished Aug 05 05:44:07 PM PDT 24
Peak memory 289128 kb
Host smart-58e90d81-36e8-46d8-9a4d-e4ab1ecf9d00
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244077050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2244077050
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.225874770
Short name T38
Test name
Test status
Simulation time 2893128564 ps
CPU time 23.97 seconds
Started Aug 05 05:08:51 PM PDT 24
Finished Aug 05 05:09:15 PM PDT 24
Peak memory 271276 kb
Host smart-cd20b79f-2411-4ce7-b923-ffba502078d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=225874770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.225874770
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.413468852
Short name T145
Test name
Test status
Simulation time 572044452 ps
CPU time 39.97 seconds
Started Aug 05 06:01:34 PM PDT 24
Finished Aug 05 06:02:15 PM PDT 24
Peak memory 240616 kb
Host smart-c797cbce-4538-4d0c-b512-0fdd1c30fa77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=413468852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.413468852
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1897432004
Short name T29
Test name
Test status
Simulation time 36073804852 ps
CPU time 2104.99 seconds
Started Aug 05 05:08:50 PM PDT 24
Finished Aug 05 05:43:56 PM PDT 24
Peak memory 289056 kb
Host smart-26ede44e-323f-414b-8a2f-a9a4b0d96ca6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897432004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1897432004
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2905004284
Short name T31
Test name
Test status
Simulation time 149924170360 ps
CPU time 7695.22 seconds
Started Aug 05 05:10:03 PM PDT 24
Finished Aug 05 07:18:19 PM PDT 24
Peak memory 394204 kb
Host smart-01da49cd-7515-4932-ab00-d05e83082799
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905004284 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2905004284
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2441972431
Short name T13
Test name
Test status
Simulation time 32049391956 ps
CPU time 1946.1 seconds
Started Aug 05 05:09:27 PM PDT 24
Finished Aug 05 05:41:53 PM PDT 24
Peak memory 272884 kb
Host smart-67b987bb-1b39-4c3e-b3c2-ed7850a5b20c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441972431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2441972431
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1870713233
Short name T108
Test name
Test status
Simulation time 15955277912 ps
CPU time 285.99 seconds
Started Aug 05 06:01:23 PM PDT 24
Finished Aug 05 06:06:09 PM PDT 24
Peak memory 265676 kb
Host smart-781a389c-f87e-4374-af44-bc79c58e4de7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1870713233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1870713233
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3522340798
Short name T101
Test name
Test status
Simulation time 67535185182 ps
CPU time 3218.25 seconds
Started Aug 05 05:09:36 PM PDT 24
Finished Aug 05 06:03:14 PM PDT 24
Peak memory 337616 kb
Host smart-fac907c3-0781-485b-b4b5-99c6e1517b07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522340798 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3522340798
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.888192254
Short name T116
Test name
Test status
Simulation time 124939400604 ps
CPU time 1115.94 seconds
Started Aug 05 06:01:29 PM PDT 24
Finished Aug 05 06:20:05 PM PDT 24
Peak memory 271856 kb
Host smart-4b01e1e4-9100-45e0-87b5-777b3977423e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888192254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.888192254
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1354664300
Short name T53
Test name
Test status
Simulation time 36454806161 ps
CPU time 1774.07 seconds
Started Aug 05 05:09:56 PM PDT 24
Finished Aug 05 05:39:31 PM PDT 24
Peak memory 305736 kb
Host smart-26aeef95-883c-438d-925f-edf0a0f42c50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354664300 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1354664300
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.1408366128
Short name T62
Test name
Test status
Simulation time 67445235018 ps
CPU time 2431.36 seconds
Started Aug 05 05:10:38 PM PDT 24
Finished Aug 05 05:51:10 PM PDT 24
Peak memory 289504 kb
Host smart-75da855c-bda6-4fb4-b340-640735af6218
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408366128 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.1408366128
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2057587993
Short name T115
Test name
Test status
Simulation time 8692538327 ps
CPU time 299.28 seconds
Started Aug 05 06:01:28 PM PDT 24
Finished Aug 05 06:06:28 PM PDT 24
Peak memory 265748 kb
Host smart-1b2afd43-2eee-4422-b154-20b9d300dd72
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2057587993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2057587993
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2268730963
Short name T65
Test name
Test status
Simulation time 143431871911 ps
CPU time 2010.84 seconds
Started Aug 05 05:09:38 PM PDT 24
Finished Aug 05 05:43:09 PM PDT 24
Peak memory 285648 kb
Host smart-460d8c4b-acd2-40d6-8ab6-b3a0cb8bab11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268730963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2268730963
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2789137368
Short name T615
Test name
Test status
Simulation time 78509090982 ps
CPU time 534.19 seconds
Started Aug 05 05:09:44 PM PDT 24
Finished Aug 05 05:18:38 PM PDT 24
Peak memory 254780 kb
Host smart-974a5195-bcd6-4dff-9044-0d780b24e8b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789137368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2789137368
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2075709477
Short name T134
Test name
Test status
Simulation time 47285681492 ps
CPU time 1116.01 seconds
Started Aug 05 06:01:32 PM PDT 24
Finished Aug 05 06:20:08 PM PDT 24
Peak memory 265672 kb
Host smart-1c49aba7-bc4b-4e34-9c8c-c617a2a20e1a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075709477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2075709477
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1064782413
Short name T225
Test name
Test status
Simulation time 340605285 ps
CPU time 15.54 seconds
Started Aug 05 05:09:13 PM PDT 24
Finished Aug 05 05:09:28 PM PDT 24
Peak memory 248352 kb
Host smart-c4714f21-281e-4d02-92e4-8c1a23d2701b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1064782413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1064782413
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2160612977
Short name T337
Test name
Test status
Simulation time 7513241 ps
CPU time 1.45 seconds
Started Aug 05 06:01:32 PM PDT 24
Finished Aug 05 06:01:34 PM PDT 24
Peak memory 236828 kb
Host smart-ec306f92-4052-4a04-b6f3-9b94a523fd66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2160612977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2160612977
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.4210160553
Short name T207
Test name
Test status
Simulation time 53902323890 ps
CPU time 573.72 seconds
Started Aug 05 05:09:23 PM PDT 24
Finished Aug 05 05:18:57 PM PDT 24
Peak memory 247232 kb
Host smart-ba932ef7-4b18-408b-850f-76d3d8c72447
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210160553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.4210160553
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.310043842
Short name T126
Test name
Test status
Simulation time 25974686599 ps
CPU time 635.66 seconds
Started Aug 05 06:01:30 PM PDT 24
Finished Aug 05 06:12:06 PM PDT 24
Peak memory 265640 kb
Host smart-0268ba02-e622-4641-af15-91ea79fe891b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310043842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.310043842
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1620186413
Short name T301
Test name
Test status
Simulation time 312146019508 ps
CPU time 3421.27 seconds
Started Aug 05 05:09:12 PM PDT 24
Finished Aug 05 06:06:14 PM PDT 24
Peak memory 288596 kb
Host smart-190f536e-22f7-408b-91ed-e68165aedda7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620186413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1620186413
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2906412054
Short name T66
Test name
Test status
Simulation time 166552251250 ps
CPU time 2849.42 seconds
Started Aug 05 05:09:42 PM PDT 24
Finished Aug 05 05:57:12 PM PDT 24
Peak memory 288696 kb
Host smart-80c4f0f6-325e-4d58-9b3c-1e5463db6303
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906412054 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2906412054
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.877248234
Short name T111
Test name
Test status
Simulation time 58332223876 ps
CPU time 1063.89 seconds
Started Aug 05 06:01:36 PM PDT 24
Finished Aug 05 06:19:20 PM PDT 24
Peak memory 265736 kb
Host smart-f420aaef-1dff-4e48-af25-4d14940d924c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877248234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.877248234
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3252030827
Short name T210
Test name
Test status
Simulation time 111539655120 ps
CPU time 1739.38 seconds
Started Aug 05 05:09:30 PM PDT 24
Finished Aug 05 05:38:29 PM PDT 24
Peak memory 288732 kb
Host smart-314663c2-d286-457e-a429-75bb806422e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252030827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3252030827
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1232984115
Short name T91
Test name
Test status
Simulation time 361231024028 ps
CPU time 3634.63 seconds
Started Aug 05 05:08:53 PM PDT 24
Finished Aug 05 06:09:28 PM PDT 24
Peak memory 297488 kb
Host smart-aabd0d68-f73b-408a-9736-e871a474e355
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232984115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1232984115
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.259770206
Short name T542
Test name
Test status
Simulation time 15233930645 ps
CPU time 621.28 seconds
Started Aug 05 05:09:06 PM PDT 24
Finished Aug 05 05:19:27 PM PDT 24
Peak memory 248368 kb
Host smart-1242a1e6-7cd0-4956-9809-a179e2e1388e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259770206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.259770206
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3568814333
Short name T107
Test name
Test status
Simulation time 3017959644 ps
CPU time 187.62 seconds
Started Aug 05 06:01:20 PM PDT 24
Finished Aug 05 06:04:28 PM PDT 24
Peak memory 270260 kb
Host smart-4959c719-2569-4673-9861-102a8e51f449
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3568814333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3568814333
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3018497506
Short name T278
Test name
Test status
Simulation time 46762718678 ps
CPU time 2708.18 seconds
Started Aug 05 05:09:06 PM PDT 24
Finished Aug 05 05:54:15 PM PDT 24
Peak memory 288376 kb
Host smart-ae0c44e3-7a58-41ba-83b2-f26545fc9561
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018497506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3018497506
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.4158141931
Short name T3
Test name
Test status
Simulation time 11695389249 ps
CPU time 1039.14 seconds
Started Aug 05 05:10:54 PM PDT 24
Finished Aug 05 05:28:13 PM PDT 24
Peak memory 281116 kb
Host smart-22744110-f8ad-400a-96ff-d7f67cbc4036
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158141931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.4158141931
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2889409612
Short name T15
Test name
Test status
Simulation time 29939857474 ps
CPU time 428.11 seconds
Started Aug 05 05:09:17 PM PDT 24
Finished Aug 05 05:16:26 PM PDT 24
Peak memory 248408 kb
Host smart-2c216ca3-53ed-4a69-bda0-ae4e98a8ccd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889409612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2889409612
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3799122478
Short name T136
Test name
Test status
Simulation time 8298925649 ps
CPU time 324.5 seconds
Started Aug 05 06:01:32 PM PDT 24
Finished Aug 05 06:06:57 PM PDT 24
Peak memory 265656 kb
Host smart-bce44bd2-71d0-4e1a-9cc7-038b33b64c46
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3799122478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3799122478
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.4225959531
Short name T73
Test name
Test status
Simulation time 34379075233 ps
CPU time 2751.43 seconds
Started Aug 05 05:09:57 PM PDT 24
Finished Aug 05 05:55:48 PM PDT 24
Peak memory 287964 kb
Host smart-065413dc-8dbf-4252-8b8f-a5438fcb0053
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225959531 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.4225959531
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1346374374
Short name T321
Test name
Test status
Simulation time 201623125652 ps
CPU time 2778.04 seconds
Started Aug 05 05:09:12 PM PDT 24
Finished Aug 05 05:55:30 PM PDT 24
Peak memory 288568 kb
Host smart-71c6f075-f5ac-4845-bceb-fc7a3ca24e59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346374374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1346374374
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2645656434
Short name T146
Test name
Test status
Simulation time 1303011131 ps
CPU time 88.47 seconds
Started Aug 05 06:01:41 PM PDT 24
Finished Aug 05 06:03:10 PM PDT 24
Peak memory 240544 kb
Host smart-bdccf1f2-fd9e-43b7-b02f-9810124fd3aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2645656434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2645656434
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3765679165
Short name T23
Test name
Test status
Simulation time 220289146623 ps
CPU time 4600 seconds
Started Aug 05 05:09:16 PM PDT 24
Finished Aug 05 06:25:56 PM PDT 24
Peak memory 314036 kb
Host smart-8c499826-3d11-4338-a841-f0d05b8198cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765679165 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3765679165
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3038393401
Short name T676
Test name
Test status
Simulation time 12403512416 ps
CPU time 512.44 seconds
Started Aug 05 05:10:08 PM PDT 24
Finished Aug 05 05:18:40 PM PDT 24
Peak memory 248500 kb
Host smart-a8ef6820-d1d6-4509-93ac-40362e5c475d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038393401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3038393401
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2294547970
Short name T98
Test name
Test status
Simulation time 64732844798 ps
CPU time 2430.11 seconds
Started Aug 05 05:10:26 PM PDT 24
Finished Aug 05 05:50:56 PM PDT 24
Peak memory 288968 kb
Host smart-b5ecf067-2e26-4c3b-8c46-39a8ad9d47e9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294547970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2294547970
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.496925954
Short name T286
Test name
Test status
Simulation time 189042774329 ps
CPU time 2946.6 seconds
Started Aug 05 05:10:19 PM PDT 24
Finished Aug 05 05:59:25 PM PDT 24
Peak memory 288592 kb
Host smart-69eae1a4-7000-4aee-bf70-97950514f30f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496925954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.496925954
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1912592549
Short name T133
Test name
Test status
Simulation time 5098579930 ps
CPU time 621.71 seconds
Started Aug 05 06:01:43 PM PDT 24
Finished Aug 05 06:12:05 PM PDT 24
Peak memory 265584 kb
Host smart-0d81afef-a1da-4510-9c51-450ecf4d3b91
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912592549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1912592549
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2082831051
Short name T224
Test name
Test status
Simulation time 9804577 ps
CPU time 1.36 seconds
Started Aug 05 06:01:56 PM PDT 24
Finished Aug 05 06:01:58 PM PDT 24
Peak memory 237712 kb
Host smart-686c223a-d925-4500-8c6e-bf542ddc6098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2082831051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2082831051
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1629013289
Short name T30
Test name
Test status
Simulation time 70239583276 ps
CPU time 1526.4 seconds
Started Aug 05 05:10:37 PM PDT 24
Finished Aug 05 05:36:04 PM PDT 24
Peak memory 288516 kb
Host smart-51c433ad-a6a2-4e65-a595-fb73adf5f725
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629013289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1629013289
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.722003635
Short name T656
Test name
Test status
Simulation time 223112903843 ps
CPU time 2930.64 seconds
Started Aug 05 05:09:47 PM PDT 24
Finished Aug 05 05:58:38 PM PDT 24
Peak memory 281100 kb
Host smart-e0f25754-dba5-45e4-84dc-c53063533fca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722003635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.722003635
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3225377694
Short name T7
Test name
Test status
Simulation time 9983215581 ps
CPU time 419.58 seconds
Started Aug 05 05:10:13 PM PDT 24
Finished Aug 05 05:17:13 PM PDT 24
Peak memory 254768 kb
Host smart-245c0e2b-afe7-4920-8113-00cc60417073
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225377694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3225377694
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.875678173
Short name T249
Test name
Test status
Simulation time 691994455 ps
CPU time 40.09 seconds
Started Aug 05 05:10:19 PM PDT 24
Finished Aug 05 05:10:59 PM PDT 24
Peak memory 248248 kb
Host smart-e222284d-896f-472a-bf27-890cc844163d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87567
8173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.875678173
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3619528591
Short name T139
Test name
Test status
Simulation time 4678485811 ps
CPU time 330.42 seconds
Started Aug 05 06:01:26 PM PDT 24
Finished Aug 05 06:06:57 PM PDT 24
Peak memory 272908 kb
Host smart-1b74ddd5-ac29-4f51-af68-a3da09b4e614
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3619528591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3619528591
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.956389677
Short name T169
Test name
Test status
Simulation time 105237221562 ps
CPU time 2638.46 seconds
Started Aug 05 05:10:24 PM PDT 24
Finished Aug 05 05:54:23 PM PDT 24
Peak memory 316340 kb
Host smart-d7ab8f81-c3d6-474a-a188-d5ccc2e2bcc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956389677 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.956389677
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2235305294
Short name T259
Test name
Test status
Simulation time 33669172070 ps
CPU time 266.23 seconds
Started Aug 05 05:10:37 PM PDT 24
Finished Aug 05 05:15:04 PM PDT 24
Peak memory 253904 kb
Host smart-14e935b9-8d35-4ee5-9636-228ca51aa367
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235305294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2235305294
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1281368657
Short name T254
Test name
Test status
Simulation time 4121388972 ps
CPU time 66.54 seconds
Started Aug 05 05:10:40 PM PDT 24
Finished Aug 05 05:11:47 PM PDT 24
Peak memory 248172 kb
Host smart-4073f644-ba71-4601-9a4e-063bf05be69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12813
68657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1281368657
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1272151344
Short name T144
Test name
Test status
Simulation time 66291250 ps
CPU time 4.39 seconds
Started Aug 05 06:01:30 PM PDT 24
Finished Aug 05 06:01:35 PM PDT 24
Peak memory 237736 kb
Host smart-539f7a51-cdda-41a2-9232-1ec88ebfe84e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1272151344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1272151344
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3927786178
Short name T197
Test name
Test status
Simulation time 135312118 ps
CPU time 3.36 seconds
Started Aug 05 05:08:52 PM PDT 24
Finished Aug 05 05:08:55 PM PDT 24
Peak memory 248552 kb
Host smart-a4b9b5b0-3fd5-477b-876b-8484500a0ef1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3927786178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3927786178
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2652163368
Short name T200
Test name
Test status
Simulation time 305757708 ps
CPU time 4.26 seconds
Started Aug 05 05:09:13 PM PDT 24
Finished Aug 05 05:09:17 PM PDT 24
Peak memory 248652 kb
Host smart-21346f14-1d42-4859-ad6b-3d92ca897e55
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2652163368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2652163368
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1440468507
Short name T191
Test name
Test status
Simulation time 18010470 ps
CPU time 3.25 seconds
Started Aug 05 05:09:12 PM PDT 24
Finished Aug 05 05:09:16 PM PDT 24
Peak memory 248596 kb
Host smart-bb77459a-6f87-45fd-bad1-aef2e0704e42
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1440468507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1440468507
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.380340728
Short name T69
Test name
Test status
Simulation time 15932293 ps
CPU time 2.87 seconds
Started Aug 05 05:09:13 PM PDT 24
Finished Aug 05 05:09:16 PM PDT 24
Peak memory 248544 kb
Host smart-ee613d90-4420-4a0d-9673-4f1623254e15
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=380340728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.380340728
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.683258547
Short name T70
Test name
Test status
Simulation time 9733963469 ps
CPU time 358.29 seconds
Started Aug 05 05:08:44 PM PDT 24
Finished Aug 05 05:14:43 PM PDT 24
Peak memory 248280 kb
Host smart-36434346-38f5-4b81-8178-93c23d70b004
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683258547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.683258547
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.109399536
Short name T256
Test name
Test status
Simulation time 50876620121 ps
CPU time 2734.98 seconds
Started Aug 05 05:09:11 PM PDT 24
Finished Aug 05 05:54:46 PM PDT 24
Peak memory 288916 kb
Host smart-0b3e6d72-1f1a-4b5d-a9fb-6dd8faf48633
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109399536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.109399536
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1618261552
Short name T105
Test name
Test status
Simulation time 172516734446 ps
CPU time 2680.44 seconds
Started Aug 05 05:09:28 PM PDT 24
Finished Aug 05 05:54:09 PM PDT 24
Peak memory 289232 kb
Host smart-d129c227-eda0-4297-a214-aaf70497cf45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618261552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1618261552
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2783809583
Short name T312
Test name
Test status
Simulation time 7298919697 ps
CPU time 260.16 seconds
Started Aug 05 05:09:23 PM PDT 24
Finished Aug 05 05:13:43 PM PDT 24
Peak memory 248264 kb
Host smart-efa830b5-f2a2-4bb3-abfc-cef5f7286e6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783809583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2783809583
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.72386414
Short name T328
Test name
Test status
Simulation time 100364829758 ps
CPU time 2781.32 seconds
Started Aug 05 05:09:36 PM PDT 24
Finished Aug 05 05:55:57 PM PDT 24
Peak memory 286876 kb
Host smart-196fd7d3-afb8-4632-8861-f4753a4398f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72386414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.72386414
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3636498759
Short name T75
Test name
Test status
Simulation time 1072073655 ps
CPU time 18.38 seconds
Started Aug 05 05:09:50 PM PDT 24
Finished Aug 05 05:10:09 PM PDT 24
Peak memory 255688 kb
Host smart-84232a6d-bae8-43c3-9f2b-49829aa37c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36364
98759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3636498759
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1453348203
Short name T83
Test name
Test status
Simulation time 6503200416 ps
CPU time 151.6 seconds
Started Aug 05 05:09:45 PM PDT 24
Finished Aug 05 05:12:17 PM PDT 24
Peak memory 251800 kb
Host smart-bf2aeab2-acbf-4951-889a-baf17309740d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453348203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1453348203
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2073798827
Short name T132
Test name
Test status
Simulation time 14916454808 ps
CPU time 623.33 seconds
Started Aug 05 06:01:50 PM PDT 24
Finished Aug 05 06:12:14 PM PDT 24
Peak memory 265724 kb
Host smart-c7a118fa-a712-40b7-979b-776057782d68
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073798827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2073798827
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1795377700
Short name T166
Test name
Test status
Simulation time 185704191 ps
CPU time 7.21 seconds
Started Aug 05 06:01:23 PM PDT 24
Finished Aug 05 06:01:30 PM PDT 24
Peak memory 238284 kb
Host smart-7c91a281-fc14-4433-9ff6-4c597e8ee8bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795377700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1795377700
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2659240996
Short name T113
Test name
Test status
Simulation time 27425381817 ps
CPU time 477.76 seconds
Started Aug 05 06:01:18 PM PDT 24
Finished Aug 05 06:09:16 PM PDT 24
Peak memory 265660 kb
Host smart-e21853f0-b34c-4efd-b7b4-1f082ee40fd5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659240996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2659240996
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1853362775
Short name T725
Test name
Test status
Simulation time 16691205 ps
CPU time 1.35 seconds
Started Aug 05 06:01:18 PM PDT 24
Finished Aug 05 06:01:20 PM PDT 24
Peak memory 237716 kb
Host smart-36fd7162-876f-4bc7-83f2-3ea88fcef092
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1853362775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1853362775
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.629799931
Short name T291
Test name
Test status
Simulation time 2405503492 ps
CPU time 33.99 seconds
Started Aug 05 05:09:04 PM PDT 24
Finished Aug 05 05:09:39 PM PDT 24
Peak memory 256464 kb
Host smart-af9b3215-fb54-4104-b09e-90caf58c4643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62979
9931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.629799931
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3230757443
Short name T264
Test name
Test status
Simulation time 130440343472 ps
CPU time 2116.16 seconds
Started Aug 05 05:09:17 PM PDT 24
Finished Aug 05 05:44:33 PM PDT 24
Peak memory 288916 kb
Host smart-9fd98001-b0e1-4143-a51b-5d24d109a701
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230757443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3230757443
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2691109989
Short name T72
Test name
Test status
Simulation time 12192187289 ps
CPU time 1232.21 seconds
Started Aug 05 05:09:10 PM PDT 24
Finished Aug 05 05:29:42 PM PDT 24
Peak memory 284380 kb
Host smart-d70839fc-b64e-4ad8-b35d-1657c4aeddbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691109989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2691109989
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.1518470084
Short name T699
Test name
Test status
Simulation time 13402630746 ps
CPU time 524.72 seconds
Started Aug 05 05:09:31 PM PDT 24
Finished Aug 05 05:18:16 PM PDT 24
Peak memory 254792 kb
Host smart-de77dabd-5930-4ed0-b46b-8d5848bbd955
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518470084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1518470084
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.4177615692
Short name T257
Test name
Test status
Simulation time 272958575 ps
CPU time 15.3 seconds
Started Aug 05 05:09:38 PM PDT 24
Finished Aug 05 05:09:53 PM PDT 24
Peak memory 248792 kb
Host smart-211c68bd-8fa6-46c9-981f-705159a89321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41776
15692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.4177615692
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.2581216290
Short name T282
Test name
Test status
Simulation time 179131670604 ps
CPU time 2798.16 seconds
Started Aug 05 05:09:39 PM PDT 24
Finished Aug 05 05:56:17 PM PDT 24
Peak memory 297620 kb
Host smart-d7b2ae8a-a1f6-4ea7-9c18-da54362dbcbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581216290 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.2581216290
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2874783075
Short name T287
Test name
Test status
Simulation time 734648232 ps
CPU time 43.32 seconds
Started Aug 05 05:09:43 PM PDT 24
Finished Aug 05 05:10:27 PM PDT 24
Peak memory 248788 kb
Host smart-533b653d-dc52-40fd-b0c3-c1e2612c19ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28747
83075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2874783075
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.903583150
Short name T106
Test name
Test status
Simulation time 96225460288 ps
CPU time 1721.04 seconds
Started Aug 05 05:09:55 PM PDT 24
Finished Aug 05 05:38:37 PM PDT 24
Peak memory 272992 kb
Host smart-2a5a9841-6f78-4053-b082-ef2727d147b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903583150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.903583150
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.388714744
Short name T79
Test name
Test status
Simulation time 3283337899 ps
CPU time 27.59 seconds
Started Aug 05 05:09:03 PM PDT 24
Finished Aug 05 05:09:30 PM PDT 24
Peak memory 248976 kb
Host smart-8bf19b34-0042-483e-a270-f62b1bf9522b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38871
4744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.388714744
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.4162940514
Short name T277
Test name
Test status
Simulation time 80586816005 ps
CPU time 2536.78 seconds
Started Aug 05 05:10:39 PM PDT 24
Finished Aug 05 05:52:56 PM PDT 24
Peak memory 289360 kb
Host smart-9ae745fb-f5f4-497f-836d-65daf70a2177
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162940514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.4162940514
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3790225656
Short name T150
Test name
Test status
Simulation time 106001019 ps
CPU time 6.32 seconds
Started Aug 05 06:01:39 PM PDT 24
Finished Aug 05 06:01:46 PM PDT 24
Peak memory 237640 kb
Host smart-497453c3-5a3c-460d-9461-091055371cc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3790225656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3790225656
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1955157181
Short name T110
Test name
Test status
Simulation time 1601496558 ps
CPU time 205.17 seconds
Started Aug 05 06:01:40 PM PDT 24
Finished Aug 05 06:05:05 PM PDT 24
Peak memory 265548 kb
Host smart-1c603201-1b1b-4b44-bcc1-9662b4f9c612
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1955157181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1955157181
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1867848063
Short name T151
Test name
Test status
Simulation time 65325956 ps
CPU time 3.01 seconds
Started Aug 05 06:01:23 PM PDT 24
Finished Aug 05 06:01:26 PM PDT 24
Peak memory 237708 kb
Host smart-5bce172a-b6bb-4990-816d-4c9a1d8c7e8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1867848063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1867848063
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3759723414
Short name T158
Test name
Test status
Simulation time 50997323 ps
CPU time 2.69 seconds
Started Aug 05 06:01:44 PM PDT 24
Finished Aug 05 06:01:47 PM PDT 24
Peak memory 237964 kb
Host smart-583fb32b-6747-4826-addd-b62d740b7c20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3759723414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3759723414
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1719451305
Short name T121
Test name
Test status
Simulation time 1691307526 ps
CPU time 190.45 seconds
Started Aug 05 06:01:43 PM PDT 24
Finished Aug 05 06:04:54 PM PDT 24
Peak memory 265560 kb
Host smart-88c7e9c7-4a3f-4c17-ba95-cb65732994f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1719451305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1719451305
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.980429115
Short name T154
Test name
Test status
Simulation time 23584851 ps
CPU time 2.54 seconds
Started Aug 05 06:01:49 PM PDT 24
Finished Aug 05 06:01:51 PM PDT 24
Peak memory 237684 kb
Host smart-ed8d2bc1-8472-48b8-9cd8-75ff6798e82a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=980429115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.980429115
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1242377670
Short name T160
Test name
Test status
Simulation time 195636157 ps
CPU time 3.72 seconds
Started Aug 05 06:01:50 PM PDT 24
Finished Aug 05 06:01:54 PM PDT 24
Peak memory 236820 kb
Host smart-c87d1fe3-5f2f-4e08-950b-621199d9ca15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1242377670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1242377670
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.433103024
Short name T159
Test name
Test status
Simulation time 96625636 ps
CPU time 2.59 seconds
Started Aug 05 06:01:51 PM PDT 24
Finished Aug 05 06:01:54 PM PDT 24
Peak memory 237704 kb
Host smart-d58964d8-5dfb-4424-bbbd-cd6cedf265cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=433103024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.433103024
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1760888178
Short name T162
Test name
Test status
Simulation time 107208650 ps
CPU time 4.36 seconds
Started Aug 05 06:01:24 PM PDT 24
Finished Aug 05 06:01:28 PM PDT 24
Peak memory 237972 kb
Host smart-a47eac9f-68e4-4c03-af73-d126064f35fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1760888178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1760888178
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1669721603
Short name T164
Test name
Test status
Simulation time 1262707895 ps
CPU time 42.93 seconds
Started Aug 05 06:01:30 PM PDT 24
Finished Aug 05 06:02:13 PM PDT 24
Peak memory 238204 kb
Host smart-149a0c35-e10a-497e-8ffa-f096491c5206
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1669721603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1669721603
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.737606234
Short name T152
Test name
Test status
Simulation time 58334553 ps
CPU time 2.26 seconds
Started Aug 05 06:01:36 PM PDT 24
Finished Aug 05 06:01:38 PM PDT 24
Peak memory 236812 kb
Host smart-8451357b-0d23-46dd-89b2-05bc5877415f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=737606234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.737606234
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.22763622
Short name T155
Test name
Test status
Simulation time 216691635 ps
CPU time 17.99 seconds
Started Aug 05 06:01:37 PM PDT 24
Finished Aug 05 06:01:55 PM PDT 24
Peak memory 240584 kb
Host smart-2ea896f9-bbc1-40c9-9a1e-8b12e1669719
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=22763622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.22763622
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.805440340
Short name T163
Test name
Test status
Simulation time 193135023 ps
CPU time 27.09 seconds
Started Aug 05 06:01:43 PM PDT 24
Finished Aug 05 06:02:10 PM PDT 24
Peak memory 237756 kb
Host smart-3640ca1f-cb47-46fc-bec9-0bfd774406ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=805440340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.805440340
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1776998306
Short name T157
Test name
Test status
Simulation time 1013230581 ps
CPU time 22.78 seconds
Started Aug 05 06:01:18 PM PDT 24
Finished Aug 05 06:01:41 PM PDT 24
Peak memory 240624 kb
Host smart-27308f33-28c9-4d3d-b65f-538f9d1a06d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1776998306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1776998306
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3767777040
Short name T161
Test name
Test status
Simulation time 104465923 ps
CPU time 2.95 seconds
Started Aug 05 06:01:25 PM PDT 24
Finished Aug 05 06:01:28 PM PDT 24
Peak memory 238156 kb
Host smart-d6edc102-096f-4721-8f5f-2a46196778e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3767777040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3767777040
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.4228904312
Short name T153
Test name
Test status
Simulation time 59299463 ps
CPU time 2.31 seconds
Started Aug 05 06:01:23 PM PDT 24
Finished Aug 05 06:01:25 PM PDT 24
Peak memory 237716 kb
Host smart-9c7ce1ea-278b-4ccf-a288-3f7f1de28fb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4228904312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.4228904312
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2725816411
Short name T27
Test name
Test status
Simulation time 253750596 ps
CPU time 29.12 seconds
Started Aug 05 05:10:02 PM PDT 24
Finished Aug 05 05:10:31 PM PDT 24
Peak memory 248296 kb
Host smart-38e5e2aa-648c-46cf-b23f-58128618bb31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27258
16411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2725816411
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3313700329
Short name T24
Test name
Test status
Simulation time 157980075099 ps
CPU time 2613.37 seconds
Started Aug 05 05:10:05 PM PDT 24
Finished Aug 05 05:53:38 PM PDT 24
Peak memory 288504 kb
Host smart-8552b058-17e3-4833-b84d-149a3785320c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313700329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3313700329
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.135541844
Short name T741
Test name
Test status
Simulation time 607652197 ps
CPU time 65.72 seconds
Started Aug 05 06:01:14 PM PDT 24
Finished Aug 05 06:02:20 PM PDT 24
Peak memory 240676 kb
Host smart-7b819652-f6a5-476d-a6c2-5f2612443e63
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=135541844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.135541844
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2357885685
Short name T183
Test name
Test status
Simulation time 5447052212 ps
CPU time 106.93 seconds
Started Aug 05 06:01:14 PM PDT 24
Finished Aug 05 06:03:01 PM PDT 24
Peak memory 237836 kb
Host smart-0c741cb6-dc37-48b8-adba-e24032f62883
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2357885685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2357885685
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1613185568
Short name T823
Test name
Test status
Simulation time 199303528 ps
CPU time 5.29 seconds
Started Aug 05 06:01:16 PM PDT 24
Finished Aug 05 06:01:21 PM PDT 24
Peak memory 248860 kb
Host smart-c9b3ebdd-990a-40f6-8e5f-0ef601c0c79d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1613185568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1613185568
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2420801012
Short name T765
Test name
Test status
Simulation time 240853023 ps
CPU time 4.89 seconds
Started Aug 05 06:01:15 PM PDT 24
Finished Aug 05 06:01:20 PM PDT 24
Peak memory 236808 kb
Host smart-f7efc7b9-975c-4e8a-9946-fde7721bbe01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2420801012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2420801012
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.4165974884
Short name T775
Test name
Test status
Simulation time 26806207 ps
CPU time 1.46 seconds
Started Aug 05 06:01:12 PM PDT 24
Finished Aug 05 06:01:14 PM PDT 24
Peak memory 236744 kb
Host smart-a07a171d-50a1-4544-adf8-48bfb7c00eb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4165974884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.4165974884
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.379856884
Short name T181
Test name
Test status
Simulation time 688974478 ps
CPU time 23.03 seconds
Started Aug 05 06:01:19 PM PDT 24
Finished Aug 05 06:01:42 PM PDT 24
Peak memory 245012 kb
Host smart-bfb2a054-e014-4a91-8caf-ec0dfbadc362
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=379856884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.379856884
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1627646496
Short name T130
Test name
Test status
Simulation time 2781541520 ps
CPU time 89.17 seconds
Started Aug 05 06:01:16 PM PDT 24
Finished Aug 05 06:02:45 PM PDT 24
Peak memory 266712 kb
Host smart-4f12ac77-37da-417a-96ff-9b4373bc87b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1627646496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1627646496
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1421224506
Short name T128
Test name
Test status
Simulation time 12861400404 ps
CPU time 507.52 seconds
Started Aug 05 06:01:14 PM PDT 24
Finished Aug 05 06:09:42 PM PDT 24
Peak memory 265652 kb
Host smart-61eed15c-b840-41d3-879b-e8960a05df4a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421224506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1421224506
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3971789241
Short name T769
Test name
Test status
Simulation time 144809048 ps
CPU time 5.71 seconds
Started Aug 05 06:01:11 PM PDT 24
Finished Aug 05 06:01:17 PM PDT 24
Peak memory 254768 kb
Host smart-7f39bff7-a421-4055-8f26-afe103f5d6ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3971789241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3971789241
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.799063033
Short name T801
Test name
Test status
Simulation time 1261211784 ps
CPU time 37.2 seconds
Started Aug 05 06:01:16 PM PDT 24
Finished Aug 05 06:01:53 PM PDT 24
Peak memory 240636 kb
Host smart-1cb061d4-0f8f-4b3b-afa3-afbdbf83f7e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=799063033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.799063033
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3538384709
Short name T808
Test name
Test status
Simulation time 1740542421 ps
CPU time 123.42 seconds
Started Aug 05 06:01:19 PM PDT 24
Finished Aug 05 06:03:23 PM PDT 24
Peak memory 240664 kb
Host smart-ec4cf57e-b6ed-4dcc-b538-008751a51fa0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3538384709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3538384709
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1534114044
Short name T751
Test name
Test status
Simulation time 4283762433 ps
CPU time 265.7 seconds
Started Aug 05 06:01:20 PM PDT 24
Finished Aug 05 06:05:46 PM PDT 24
Peak memory 240620 kb
Host smart-1acb87f7-b58e-4dcc-b6b1-66540d9aac55
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1534114044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1534114044
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1045167685
Short name T798
Test name
Test status
Simulation time 429749731 ps
CPU time 5.71 seconds
Started Aug 05 06:01:18 PM PDT 24
Finished Aug 05 06:01:24 PM PDT 24
Peak memory 248828 kb
Host smart-36d1bd54-76f7-426b-9a12-91a3ca999001
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1045167685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1045167685
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.341895320
Short name T803
Test name
Test status
Simulation time 55030001 ps
CPU time 4.88 seconds
Started Aug 05 06:01:19 PM PDT 24
Finished Aug 05 06:01:24 PM PDT 24
Peak memory 238284 kb
Host smart-ac295a61-3eee-492c-b3c2-907485494af1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341895320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.341895320
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.34504549
Short name T178
Test name
Test status
Simulation time 171641306 ps
CPU time 5.39 seconds
Started Aug 05 06:01:18 PM PDT 24
Finished Aug 05 06:01:24 PM PDT 24
Peak memory 240644 kb
Host smart-dea5c898-eca9-4e36-a69e-ceb84a883ee7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=34504549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.34504549
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1140092844
Short name T750
Test name
Test status
Simulation time 1844356400 ps
CPU time 43.77 seconds
Started Aug 05 06:01:22 PM PDT 24
Finished Aug 05 06:02:05 PM PDT 24
Peak memory 245916 kb
Host smart-384dd43c-189f-43a3-8433-5571b9a2d221
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1140092844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1140092844
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3810119859
Short name T138
Test name
Test status
Simulation time 7222123025 ps
CPU time 471.16 seconds
Started Aug 05 06:01:21 PM PDT 24
Finished Aug 05 06:09:12 PM PDT 24
Peak memory 265848 kb
Host smart-53a96187-d45e-41f5-aa89-99277f405b8d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810119859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3810119859
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.104446666
Short name T243
Test name
Test status
Simulation time 61096913 ps
CPU time 5.04 seconds
Started Aug 05 06:01:18 PM PDT 24
Finished Aug 05 06:01:23 PM PDT 24
Peak memory 240720 kb
Host smart-9aeaf242-1981-4328-acbb-37dd59f95836
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=104446666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.104446666
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1337907149
Short name T747
Test name
Test status
Simulation time 204572601 ps
CPU time 9.2 seconds
Started Aug 05 06:01:29 PM PDT 24
Finished Aug 05 06:01:39 PM PDT 24
Peak memory 256304 kb
Host smart-65e192e3-2a4d-4b1c-b42e-b0ed84d2f1b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337907149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1337907149
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2981173625
Short name T752
Test name
Test status
Simulation time 195757975 ps
CPU time 8.76 seconds
Started Aug 05 06:01:32 PM PDT 24
Finished Aug 05 06:01:41 PM PDT 24
Peak memory 236832 kb
Host smart-37973f15-62c9-4ee4-8157-b15a848ca7f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2981173625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2981173625
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1860375243
Short name T728
Test name
Test status
Simulation time 18148678 ps
CPU time 1.79 seconds
Started Aug 05 06:01:33 PM PDT 24
Finished Aug 05 06:01:35 PM PDT 24
Peak memory 235756 kb
Host smart-641c0609-dceb-4852-9810-eb6b6c5b7f1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1860375243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1860375243
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2258917086
Short name T721
Test name
Test status
Simulation time 516229188 ps
CPU time 37.27 seconds
Started Aug 05 06:01:31 PM PDT 24
Finished Aug 05 06:02:09 PM PDT 24
Peak memory 245888 kb
Host smart-c603dfe5-fc7f-4139-a10f-b6aded5dbda1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2258917086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2258917086
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.360044768
Short name T114
Test name
Test status
Simulation time 9410190579 ps
CPU time 350.44 seconds
Started Aug 05 06:01:32 PM PDT 24
Finished Aug 05 06:07:23 PM PDT 24
Peak memory 272156 kb
Host smart-40c1ff49-86a8-46a7-93c9-7421522f222d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360044768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.360044768
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.731700351
Short name T242
Test name
Test status
Simulation time 339189132 ps
CPU time 24.66 seconds
Started Aug 05 06:01:32 PM PDT 24
Finished Aug 05 06:01:57 PM PDT 24
Peak memory 248096 kb
Host smart-4331ccde-3c96-47f3-becb-c5d8d62cca52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=731700351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.731700351
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2436802567
Short name T726
Test name
Test status
Simulation time 84553726 ps
CPU time 6.31 seconds
Started Aug 05 06:01:35 PM PDT 24
Finished Aug 05 06:01:41 PM PDT 24
Peak memory 240904 kb
Host smart-a4a16407-7dbc-4259-b0bc-42d5be2a246b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436802567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2436802567
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.783434157
Short name T341
Test name
Test status
Simulation time 627812418 ps
CPU time 4.62 seconds
Started Aug 05 06:01:37 PM PDT 24
Finished Aug 05 06:01:42 PM PDT 24
Peak memory 237688 kb
Host smart-7e589b40-1c6b-4d8c-899e-75649494301c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=783434157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.783434157
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2653398817
Short name T826
Test name
Test status
Simulation time 38162616 ps
CPU time 1.57 seconds
Started Aug 05 06:01:44 PM PDT 24
Finished Aug 05 06:01:46 PM PDT 24
Peak memory 237712 kb
Host smart-a9848827-01e2-4d87-9052-d48bf539fa47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2653398817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2653398817
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1803642855
Short name T824
Test name
Test status
Simulation time 2749889439 ps
CPU time 50.94 seconds
Started Aug 05 06:01:35 PM PDT 24
Finished Aug 05 06:02:26 PM PDT 24
Peak memory 248928 kb
Host smart-df0a5c00-8be5-4a4a-a704-f228988c917f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1803642855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1803642855
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.943670033
Short name T763
Test name
Test status
Simulation time 336597504 ps
CPU time 6.73 seconds
Started Aug 05 06:01:32 PM PDT 24
Finished Aug 05 06:01:39 PM PDT 24
Peak memory 250400 kb
Host smart-f4564964-4bea-4519-b83e-20f9931fe58d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=943670033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.943670033
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.331945870
Short name T766
Test name
Test status
Simulation time 142262105 ps
CPU time 7.46 seconds
Started Aug 05 06:01:35 PM PDT 24
Finished Aug 05 06:01:43 PM PDT 24
Peak memory 239936 kb
Host smart-37e5237e-a448-427a-8a8b-9d4128353c47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331945870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.331945870
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2341191972
Short name T777
Test name
Test status
Simulation time 49179583 ps
CPU time 6.47 seconds
Started Aug 05 06:01:38 PM PDT 24
Finished Aug 05 06:01:45 PM PDT 24
Peak memory 240652 kb
Host smart-f5893337-5529-4678-b43d-b48493f993b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2341191972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2341191972
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3642533430
Short name T731
Test name
Test status
Simulation time 10508446 ps
CPU time 1.62 seconds
Started Aug 05 06:01:36 PM PDT 24
Finished Aug 05 06:01:37 PM PDT 24
Peak memory 235752 kb
Host smart-e3014f86-1437-4a3b-883e-8390955743f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3642533430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3642533430
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2686372546
Short name T814
Test name
Test status
Simulation time 2776480470 ps
CPU time 52.45 seconds
Started Aug 05 06:01:36 PM PDT 24
Finished Aug 05 06:02:29 PM PDT 24
Peak memory 248908 kb
Host smart-f79af2d7-f277-4b23-b1d2-cbaf81a8985c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2686372546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2686372546
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.439397193
Short name T123
Test name
Test status
Simulation time 4181619242 ps
CPU time 304.39 seconds
Started Aug 05 06:01:35 PM PDT 24
Finished Aug 05 06:06:40 PM PDT 24
Peak memory 265576 kb
Host smart-2e4694b1-3af0-4e18-b953-be8c1fa191af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=439397193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.439397193
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3822978337
Short name T819
Test name
Test status
Simulation time 1111038550 ps
CPU time 20.14 seconds
Started Aug 05 06:01:45 PM PDT 24
Finished Aug 05 06:02:05 PM PDT 24
Peak memory 249956 kb
Host smart-ae5e47d7-5006-420c-813d-bb0f4c4ecea9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3822978337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3822978337
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1249319320
Short name T347
Test name
Test status
Simulation time 373427744 ps
CPU time 6.29 seconds
Started Aug 05 06:01:36 PM PDT 24
Finished Aug 05 06:01:42 PM PDT 24
Peak memory 239564 kb
Host smart-1376c899-417c-4bf9-801a-9864f765fc27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249319320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1249319320
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3442702192
Short name T177
Test name
Test status
Simulation time 297490233 ps
CPU time 4.47 seconds
Started Aug 05 06:01:37 PM PDT 24
Finished Aug 05 06:01:42 PM PDT 24
Peak memory 236816 kb
Host smart-bb112a23-902e-43f3-8b44-f99d91c357da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3442702192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3442702192
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.451463119
Short name T760
Test name
Test status
Simulation time 67624765 ps
CPU time 1.43 seconds
Started Aug 05 06:01:44 PM PDT 24
Finished Aug 05 06:01:46 PM PDT 24
Peak memory 236584 kb
Host smart-2aec5a4c-3ac3-4323-ae95-35bc5ec4e2d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=451463119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.451463119
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.4220885742
Short name T789
Test name
Test status
Simulation time 629763992 ps
CPU time 36.57 seconds
Started Aug 05 06:01:36 PM PDT 24
Finished Aug 05 06:02:13 PM PDT 24
Peak memory 245032 kb
Host smart-7d568343-19c0-4923-9cc5-3941c07e0798
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4220885742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.4220885742
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.145707250
Short name T119
Test name
Test status
Simulation time 7718693697 ps
CPU time 148.26 seconds
Started Aug 05 06:01:36 PM PDT 24
Finished Aug 05 06:04:04 PM PDT 24
Peak memory 265664 kb
Host smart-1d1f8137-34a2-4bf1-94f9-2d00455e668d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=145707250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.145707250
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.4279131647
Short name T344
Test name
Test status
Simulation time 6131405647 ps
CPU time 464.95 seconds
Started Aug 05 06:01:37 PM PDT 24
Finished Aug 05 06:09:22 PM PDT 24
Peak memory 265632 kb
Host smart-39dd79c9-b4d1-4be7-bd46-26c23bcc2621
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279131647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.4279131647
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.99794704
Short name T802
Test name
Test status
Simulation time 2819530400 ps
CPU time 16.08 seconds
Started Aug 05 06:01:36 PM PDT 24
Finished Aug 05 06:01:53 PM PDT 24
Peak memory 254108 kb
Host smart-bef8d8dd-35fd-4140-8594-c89489bce59f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=99794704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.99794704
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3442944767
Short name T799
Test name
Test status
Simulation time 478988818 ps
CPU time 9.22 seconds
Started Aug 05 06:01:44 PM PDT 24
Finished Aug 05 06:01:53 PM PDT 24
Peak memory 240676 kb
Host smart-85581712-c482-43ab-bd0d-0bfec3141fb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442944767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3442944767
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1363744381
Short name T734
Test name
Test status
Simulation time 120688550 ps
CPU time 3.22 seconds
Started Aug 05 06:01:45 PM PDT 24
Finished Aug 05 06:01:48 PM PDT 24
Peak memory 236788 kb
Host smart-c70e2e8e-2a93-4ab5-b99a-bba8528f9754
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1363744381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1363744381
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2181608820
Short name T825
Test name
Test status
Simulation time 14318999 ps
CPU time 1.32 seconds
Started Aug 05 06:01:41 PM PDT 24
Finished Aug 05 06:01:43 PM PDT 24
Peak memory 235796 kb
Host smart-1554be53-a6b7-4275-aa6c-34b169ed171a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2181608820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2181608820
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1364677082
Short name T762
Test name
Test status
Simulation time 337007216 ps
CPU time 23.11 seconds
Started Aug 05 06:01:43 PM PDT 24
Finished Aug 05 06:02:06 PM PDT 24
Peak memory 244980 kb
Host smart-92e45b3d-161e-44ac-a4a9-afd0d9ef311d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1364677082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1364677082
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1355769376
Short name T117
Test name
Test status
Simulation time 5040271692 ps
CPU time 97.54 seconds
Started Aug 05 06:01:38 PM PDT 24
Finished Aug 05 06:03:16 PM PDT 24
Peak memory 264912 kb
Host smart-c709cc7a-a12f-4665-befb-2759c930fc0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1355769376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1355769376
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1889975565
Short name T112
Test name
Test status
Simulation time 18636953246 ps
CPU time 630.42 seconds
Started Aug 05 06:01:35 PM PDT 24
Finished Aug 05 06:12:05 PM PDT 24
Peak memory 265632 kb
Host smart-7acd58ac-76c1-418a-9340-8b9f5f5c06e9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889975565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1889975565
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3684952595
Short name T786
Test name
Test status
Simulation time 47980854 ps
CPU time 5.67 seconds
Started Aug 05 06:01:47 PM PDT 24
Finished Aug 05 06:01:53 PM PDT 24
Peak memory 254388 kb
Host smart-04ea3b55-b56b-4d51-b341-11fedb09d7a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3684952595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3684952595
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2785026210
Short name T827
Test name
Test status
Simulation time 527351596 ps
CPU time 11.09 seconds
Started Aug 05 06:01:45 PM PDT 24
Finished Aug 05 06:01:56 PM PDT 24
Peak memory 251956 kb
Host smart-958c08ca-fed4-496a-bc4a-76d4c521e3db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785026210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2785026210
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3577495015
Short name T782
Test name
Test status
Simulation time 59781074 ps
CPU time 5.4 seconds
Started Aug 05 06:01:44 PM PDT 24
Finished Aug 05 06:01:50 PM PDT 24
Peak memory 237704 kb
Host smart-e6468ce7-0be4-4f6c-ac25-e0cf5fe6dc82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3577495015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3577495015
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1442382636
Short name T730
Test name
Test status
Simulation time 12136019 ps
CPU time 1.25 seconds
Started Aug 05 06:01:39 PM PDT 24
Finished Aug 05 06:01:41 PM PDT 24
Peak memory 237684 kb
Host smart-86af9723-3343-4cb9-b5ac-3834ebb0b124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1442382636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1442382636
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2972496447
Short name T779
Test name
Test status
Simulation time 87588216 ps
CPU time 13.95 seconds
Started Aug 05 06:01:41 PM PDT 24
Finished Aug 05 06:01:55 PM PDT 24
Peak memory 245908 kb
Host smart-ef4bdb79-3905-416f-bacb-7e38565a358b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2972496447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2972496447
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1415365321
Short name T122
Test name
Test status
Simulation time 2258046873 ps
CPU time 157.08 seconds
Started Aug 05 06:01:44 PM PDT 24
Finished Aug 05 06:04:21 PM PDT 24
Peak memory 265592 kb
Host smart-3cd052b9-044c-4e26-a387-8430dc8924bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1415365321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1415365321
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1773912972
Short name T783
Test name
Test status
Simulation time 244046924 ps
CPU time 17.11 seconds
Started Aug 05 06:01:43 PM PDT 24
Finished Aug 05 06:02:00 PM PDT 24
Peak memory 248904 kb
Host smart-4c20dd6c-8b7a-4f6b-81b4-ef1acd2eca9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1773912972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1773912972
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1060682730
Short name T767
Test name
Test status
Simulation time 58616772 ps
CPU time 7.65 seconds
Started Aug 05 06:01:41 PM PDT 24
Finished Aug 05 06:01:49 PM PDT 24
Peak memory 252904 kb
Host smart-e404281e-ff99-4255-8e3c-cab3587ea711
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060682730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1060682730
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2659087764
Short name T241
Test name
Test status
Simulation time 497272102 ps
CPU time 9.09 seconds
Started Aug 05 06:01:44 PM PDT 24
Finished Aug 05 06:01:53 PM PDT 24
Peak memory 237676 kb
Host smart-ef9ff566-93ff-4926-b2b6-22601d794b05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2659087764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2659087764
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3451647777
Short name T809
Test name
Test status
Simulation time 10757262 ps
CPU time 1.31 seconds
Started Aug 05 06:01:42 PM PDT 24
Finished Aug 05 06:01:43 PM PDT 24
Peak memory 237696 kb
Host smart-5b54cdec-1532-46a9-a28f-0bc60ac10ae6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3451647777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3451647777
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2482285294
Short name T743
Test name
Test status
Simulation time 88614648 ps
CPU time 12.44 seconds
Started Aug 05 06:01:42 PM PDT 24
Finished Aug 05 06:01:55 PM PDT 24
Peak memory 240660 kb
Host smart-c761b34c-2c5d-4cbd-9770-2a908569fe33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2482285294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2482285294
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2550062347
Short name T109
Test name
Test status
Simulation time 12661888057 ps
CPU time 467.06 seconds
Started Aug 05 06:01:41 PM PDT 24
Finished Aug 05 06:09:28 PM PDT 24
Peak memory 265676 kb
Host smart-597e997e-e706-4503-b3e4-a1ba135781a8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550062347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2550062347
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.267519074
Short name T231
Test name
Test status
Simulation time 1273891560 ps
CPU time 21.97 seconds
Started Aug 05 06:01:41 PM PDT 24
Finished Aug 05 06:02:03 PM PDT 24
Peak memory 254240 kb
Host smart-2a25dc1e-487f-400d-af3c-5350e1ead6ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=267519074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.267519074
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1396677125
Short name T773
Test name
Test status
Simulation time 348494022 ps
CPU time 7.25 seconds
Started Aug 05 06:01:48 PM PDT 24
Finished Aug 05 06:01:55 PM PDT 24
Peak memory 240464 kb
Host smart-fdbd1268-bd0d-47e5-87fe-6354564ab6fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396677125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1396677125
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1650063788
Short name T795
Test name
Test status
Simulation time 72328284 ps
CPU time 5.19 seconds
Started Aug 05 06:01:50 PM PDT 24
Finished Aug 05 06:01:55 PM PDT 24
Peak memory 240660 kb
Host smart-94a11a23-7012-4c36-a945-2095572b3b96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1650063788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1650063788
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1842130898
Short name T793
Test name
Test status
Simulation time 7597184 ps
CPU time 1.5 seconds
Started Aug 05 06:01:51 PM PDT 24
Finished Aug 05 06:01:52 PM PDT 24
Peak memory 236832 kb
Host smart-2c70643e-464c-41c1-be6a-fe91fa28b037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1842130898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1842130898
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.4093667741
Short name T724
Test name
Test status
Simulation time 1030278818 ps
CPU time 10.52 seconds
Started Aug 05 06:01:51 PM PDT 24
Finished Aug 05 06:02:02 PM PDT 24
Peak memory 248836 kb
Host smart-64bb9cde-48fb-4979-92f1-2927aefe3a26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4093667741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.4093667741
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2112143970
Short name T124
Test name
Test status
Simulation time 17962702889 ps
CPU time 313.93 seconds
Started Aug 05 06:01:42 PM PDT 24
Finished Aug 05 06:06:56 PM PDT 24
Peak memory 265600 kb
Host smart-8334661c-92c0-4457-83cb-f46c162fc75b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112143970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2112143970
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.4258230269
Short name T738
Test name
Test status
Simulation time 477390463 ps
CPU time 21.05 seconds
Started Aug 05 06:01:50 PM PDT 24
Finished Aug 05 06:02:11 PM PDT 24
Peak memory 248060 kb
Host smart-26da68d2-0fbf-4b8d-9f80-a08a7e4fa4a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4258230269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.4258230269
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3050908507
Short name T723
Test name
Test status
Simulation time 57727748 ps
CPU time 4.69 seconds
Started Aug 05 06:01:50 PM PDT 24
Finished Aug 05 06:01:55 PM PDT 24
Peak memory 240924 kb
Host smart-134af654-9454-47a9-8ce0-fb681b451448
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050908507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3050908507
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2351197578
Short name T772
Test name
Test status
Simulation time 20566513 ps
CPU time 3.3 seconds
Started Aug 05 06:01:50 PM PDT 24
Finished Aug 05 06:01:53 PM PDT 24
Peak memory 239600 kb
Host smart-17df7f13-6c0d-4b61-8a7f-13efc8173e00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2351197578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2351197578
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1409148547
Short name T149
Test name
Test status
Simulation time 13239264 ps
CPU time 1.34 seconds
Started Aug 05 06:01:49 PM PDT 24
Finished Aug 05 06:01:51 PM PDT 24
Peak memory 236692 kb
Host smart-d07e1c86-d874-4980-9862-9c13907eccd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1409148547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1409148547
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2284510412
Short name T740
Test name
Test status
Simulation time 623461301 ps
CPU time 20.13 seconds
Started Aug 05 06:01:52 PM PDT 24
Finished Aug 05 06:02:12 PM PDT 24
Peak memory 245016 kb
Host smart-1b887047-958e-49ce-9aa8-356089476af7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2284510412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2284510412
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.791423109
Short name T127
Test name
Test status
Simulation time 1756858306 ps
CPU time 218.11 seconds
Started Aug 05 06:01:50 PM PDT 24
Finished Aug 05 06:05:28 PM PDT 24
Peak memory 273000 kb
Host smart-03369077-21cc-4e5b-bba1-7e9abde2ab03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=791423109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.791423109
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2195318988
Short name T345
Test name
Test status
Simulation time 2442308678 ps
CPU time 347.22 seconds
Started Aug 05 06:01:51 PM PDT 24
Finished Aug 05 06:07:38 PM PDT 24
Peak memory 265672 kb
Host smart-8aba87b7-bacc-411e-a760-451d19604699
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195318988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2195318988
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2643724596
Short name T720
Test name
Test status
Simulation time 399087647 ps
CPU time 12.41 seconds
Started Aug 05 06:01:48 PM PDT 24
Finished Aug 05 06:02:01 PM PDT 24
Peak memory 248912 kb
Host smart-a6c7042c-f23d-4dba-80aa-8f83725ba561
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2643724596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2643724596
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1856104492
Short name T744
Test name
Test status
Simulation time 345516070 ps
CPU time 6.48 seconds
Started Aug 05 06:01:49 PM PDT 24
Finished Aug 05 06:01:56 PM PDT 24
Peak memory 240208 kb
Host smart-21ed0942-df53-4d18-bdd7-2a3bf3666d23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856104492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1856104492
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.4261873326
Short name T749
Test name
Test status
Simulation time 178845663 ps
CPU time 8.91 seconds
Started Aug 05 06:01:51 PM PDT 24
Finished Aug 05 06:02:00 PM PDT 24
Peak memory 237704 kb
Host smart-601c478c-cd6c-43db-90f8-a02741a6fb11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4261873326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.4261873326
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.402829871
Short name T820
Test name
Test status
Simulation time 12306572 ps
CPU time 1.46 seconds
Started Aug 05 06:01:49 PM PDT 24
Finished Aug 05 06:01:51 PM PDT 24
Peak memory 236760 kb
Host smart-9b483295-a2da-467b-90c4-e5365bcf7ef9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=402829871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.402829871
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3839847898
Short name T165
Test name
Test status
Simulation time 675657955 ps
CPU time 42.63 seconds
Started Aug 05 06:01:51 PM PDT 24
Finished Aug 05 06:02:34 PM PDT 24
Peak memory 245876 kb
Host smart-f57feacb-2451-43f9-bc0c-3848deed1139
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3839847898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3839847898
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1604113853
Short name T143
Test name
Test status
Simulation time 7660036795 ps
CPU time 160.86 seconds
Started Aug 05 06:01:49 PM PDT 24
Finished Aug 05 06:04:30 PM PDT 24
Peak memory 265800 kb
Host smart-a338285f-8240-4f16-ba37-a8e09736749c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1604113853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1604113853
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2740265295
Short name T718
Test name
Test status
Simulation time 215732247 ps
CPU time 6.6 seconds
Started Aug 05 06:01:49 PM PDT 24
Finished Aug 05 06:01:56 PM PDT 24
Peak memory 252104 kb
Host smart-3fcfa6ee-b723-4583-b681-e56ac81d230d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2740265295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2740265295
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2450352871
Short name T180
Test name
Test status
Simulation time 4704317884 ps
CPU time 150.64 seconds
Started Aug 05 06:01:19 PM PDT 24
Finished Aug 05 06:03:50 PM PDT 24
Peak memory 240776 kb
Host smart-5cbcc0c1-3fb9-49bb-a378-05bb60618667
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2450352871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2450352871
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3770881541
Short name T776
Test name
Test status
Simulation time 16472018437 ps
CPU time 513.15 seconds
Started Aug 05 06:01:20 PM PDT 24
Finished Aug 05 06:09:53 PM PDT 24
Peak memory 237864 kb
Host smart-7c9d078a-0948-4484-9cd2-acd1ef73e836
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3770881541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3770881541
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1238589505
Short name T148
Test name
Test status
Simulation time 192860496 ps
CPU time 6.38 seconds
Started Aug 05 06:01:18 PM PDT 24
Finished Aug 05 06:01:25 PM PDT 24
Peak memory 248848 kb
Host smart-f84ae212-1782-4bd1-bf4b-a077116d901c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1238589505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1238589505
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2657517283
Short name T733
Test name
Test status
Simulation time 247624702 ps
CPU time 8.51 seconds
Started Aug 05 06:01:20 PM PDT 24
Finished Aug 05 06:01:28 PM PDT 24
Peak memory 257052 kb
Host smart-ecb11bcd-e359-45b2-9b1f-020b86da433f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657517283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2657517283
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.536536890
Short name T729
Test name
Test status
Simulation time 43582146 ps
CPU time 3.48 seconds
Started Aug 05 06:01:17 PM PDT 24
Finished Aug 05 06:01:21 PM PDT 24
Peak memory 237700 kb
Host smart-0ba79f47-bae0-4642-87ef-0a4ba2995efa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=536536890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.536536890
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1016198460
Short name T147
Test name
Test status
Simulation time 7176435 ps
CPU time 1.57 seconds
Started Aug 05 06:01:28 PM PDT 24
Finished Aug 05 06:01:29 PM PDT 24
Peak memory 235704 kb
Host smart-ccd3ea3b-20a5-4a10-a88a-8be5d8e44d94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1016198460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1016198460
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3410082919
Short name T780
Test name
Test status
Simulation time 359540283 ps
CPU time 12.14 seconds
Started Aug 05 06:01:18 PM PDT 24
Finished Aug 05 06:01:30 PM PDT 24
Peak memory 240640 kb
Host smart-f73d032b-20ed-488f-bb2a-3c1bdcaea53f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3410082919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3410082919
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2049462603
Short name T137
Test name
Test status
Simulation time 2174679007 ps
CPU time 165.7 seconds
Started Aug 05 06:01:19 PM PDT 24
Finished Aug 05 06:04:04 PM PDT 24
Peak memory 265608 kb
Host smart-cbff8bf5-ee7f-4697-9550-f1920cba2047
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2049462603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2049462603
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.4023813313
Short name T118
Test name
Test status
Simulation time 4382572338 ps
CPU time 661.19 seconds
Started Aug 05 06:01:16 PM PDT 24
Finished Aug 05 06:12:18 PM PDT 24
Peak memory 265636 kb
Host smart-bd55d3f7-5839-47dc-bfb5-bea3aab95ff6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023813313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.4023813313
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3502302149
Short name T821
Test name
Test status
Simulation time 656413270 ps
CPU time 14.3 seconds
Started Aug 05 06:01:22 PM PDT 24
Finished Aug 05 06:01:36 PM PDT 24
Peak memory 254520 kb
Host smart-db4ba156-3310-4505-b449-e78cc84b8f68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3502302149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3502302149
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3895340268
Short name T818
Test name
Test status
Simulation time 22976482 ps
CPU time 1.39 seconds
Started Aug 05 06:01:50 PM PDT 24
Finished Aug 05 06:01:52 PM PDT 24
Peak memory 237696 kb
Host smart-3526054d-c9fa-420c-b201-51383c3d8959
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3895340268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3895340268
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2059884245
Short name T771
Test name
Test status
Simulation time 22067313 ps
CPU time 1.48 seconds
Started Aug 05 06:01:51 PM PDT 24
Finished Aug 05 06:01:53 PM PDT 24
Peak memory 236864 kb
Host smart-08103c36-8154-47e9-8b80-8fdf38a49895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2059884245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2059884245
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.222001119
Short name T739
Test name
Test status
Simulation time 10150250 ps
CPU time 1.42 seconds
Started Aug 05 06:01:52 PM PDT 24
Finished Aug 05 06:01:53 PM PDT 24
Peak memory 235744 kb
Host smart-e6aacffd-ccde-49b5-b8dd-be683adb22e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=222001119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.222001119
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2721091899
Short name T787
Test name
Test status
Simulation time 42735448 ps
CPU time 2.78 seconds
Started Aug 05 06:01:50 PM PDT 24
Finished Aug 05 06:01:53 PM PDT 24
Peak memory 235752 kb
Host smart-68e6cc3b-5ab4-4a8e-b0ef-515d085e6a0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2721091899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2721091899
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.4180151614
Short name T790
Test name
Test status
Simulation time 11439906 ps
CPU time 1.55 seconds
Started Aug 05 06:01:52 PM PDT 24
Finished Aug 05 06:01:54 PM PDT 24
Peak memory 236836 kb
Host smart-ee6a5c5f-d43f-4615-82eb-8351b0146981
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4180151614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.4180151614
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1376482877
Short name T753
Test name
Test status
Simulation time 10041743 ps
CPU time 1.3 seconds
Started Aug 05 06:01:52 PM PDT 24
Finished Aug 05 06:01:53 PM PDT 24
Peak memory 236836 kb
Host smart-e23fff87-537a-4e9f-8ff0-ce202c0b274f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1376482877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1376482877
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3463677689
Short name T834
Test name
Test status
Simulation time 10228057 ps
CPU time 1.62 seconds
Started Aug 05 06:01:49 PM PDT 24
Finished Aug 05 06:01:51 PM PDT 24
Peak memory 237680 kb
Host smart-254bfaa0-1f35-407e-ab19-8fa6e2e5186b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3463677689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3463677689
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.547998071
Short name T796
Test name
Test status
Simulation time 8165283 ps
CPU time 1.61 seconds
Started Aug 05 06:02:03 PM PDT 24
Finished Aug 05 06:02:05 PM PDT 24
Peak memory 237708 kb
Host smart-6367a805-9a2e-4045-a60c-96c9145ea08a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=547998071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.547998071
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3861123406
Short name T788
Test name
Test status
Simulation time 17422074 ps
CPU time 1.34 seconds
Started Aug 05 06:01:59 PM PDT 24
Finished Aug 05 06:02:00 PM PDT 24
Peak memory 237720 kb
Host smart-3365b18d-1e72-4408-bce9-9416d85eabf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3861123406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3861123406
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1597823629
Short name T742
Test name
Test status
Simulation time 8431899 ps
CPU time 1.43 seconds
Started Aug 05 06:01:57 PM PDT 24
Finished Aug 05 06:01:58 PM PDT 24
Peak memory 236836 kb
Host smart-5465cb51-f6a4-4f95-b8cd-c559faf2002a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1597823629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1597823629
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.482148063
Short name T833
Test name
Test status
Simulation time 2064565596 ps
CPU time 116.55 seconds
Started Aug 05 06:01:20 PM PDT 24
Finished Aug 05 06:03:16 PM PDT 24
Peak memory 237708 kb
Host smart-7884f49a-8d2a-47b2-b71b-a450d585fbea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=482148063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.482148063
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2233077907
Short name T737
Test name
Test status
Simulation time 1862159505 ps
CPU time 103.86 seconds
Started Aug 05 06:01:20 PM PDT 24
Finished Aug 05 06:03:04 PM PDT 24
Peak memory 240656 kb
Host smart-b2ec13af-be2e-49a5-a361-58081346df07
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2233077907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2233077907
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.954658963
Short name T757
Test name
Test status
Simulation time 77857571 ps
CPU time 4.24 seconds
Started Aug 05 06:01:20 PM PDT 24
Finished Aug 05 06:01:24 PM PDT 24
Peak memory 248828 kb
Host smart-7d18793f-5c61-4887-9529-9c77450f1022
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=954658963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.954658963
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2135861196
Short name T770
Test name
Test status
Simulation time 133449768 ps
CPU time 6.78 seconds
Started Aug 05 06:01:28 PM PDT 24
Finished Aug 05 06:01:35 PM PDT 24
Peak memory 249912 kb
Host smart-56848e68-911c-442d-be3e-18122cd9319b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135861196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2135861196
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2230750556
Short name T736
Test name
Test status
Simulation time 64224010 ps
CPU time 6.02 seconds
Started Aug 05 06:01:20 PM PDT 24
Finished Aug 05 06:01:27 PM PDT 24
Peak memory 240636 kb
Host smart-a402e6ef-1281-4b4d-bb33-6036bd9d07c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2230750556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2230750556
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.149612508
Short name T245
Test name
Test status
Simulation time 8325392 ps
CPU time 1.53 seconds
Started Aug 05 06:01:20 PM PDT 24
Finished Aug 05 06:01:21 PM PDT 24
Peak memory 235736 kb
Host smart-9d7d8309-b3c0-43f5-b93e-8214dbf9d546
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=149612508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.149612508
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2082954577
Short name T828
Test name
Test status
Simulation time 2333350714 ps
CPU time 24.64 seconds
Started Aug 05 06:01:17 PM PDT 24
Finished Aug 05 06:01:42 PM PDT 24
Peak memory 246012 kb
Host smart-53bd6534-ce81-49fc-b9da-d7d383b87e4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2082954577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2082954577
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.705668181
Short name T131
Test name
Test status
Simulation time 4372132143 ps
CPU time 643.81 seconds
Started Aug 05 06:01:21 PM PDT 24
Finished Aug 05 06:12:05 PM PDT 24
Peak memory 265732 kb
Host smart-dc12daef-4554-4ed6-a62b-2c26ea042abc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705668181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.705668181
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2454963715
Short name T774
Test name
Test status
Simulation time 77673538 ps
CPU time 6.29 seconds
Started Aug 05 06:01:20 PM PDT 24
Finished Aug 05 06:01:26 PM PDT 24
Peak memory 248880 kb
Host smart-3bd84f65-29fb-4c03-81f3-7defb192ae69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2454963715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2454963715
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2162532972
Short name T758
Test name
Test status
Simulation time 183786718 ps
CPU time 25.42 seconds
Started Aug 05 06:01:22 PM PDT 24
Finished Aug 05 06:01:48 PM PDT 24
Peak memory 240620 kb
Host smart-20f3aa9a-7e03-4563-8975-13495a8c6f63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2162532972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2162532972
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2645597700
Short name T811
Test name
Test status
Simulation time 10015051 ps
CPU time 1.65 seconds
Started Aug 05 06:01:57 PM PDT 24
Finished Aug 05 06:01:59 PM PDT 24
Peak memory 237716 kb
Host smart-f5431bc9-f94f-4fe9-9254-ec19dc535ea5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2645597700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2645597700
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.426290634
Short name T768
Test name
Test status
Simulation time 10658382 ps
CPU time 1.26 seconds
Started Aug 05 06:01:57 PM PDT 24
Finished Aug 05 06:01:58 PM PDT 24
Peak memory 237684 kb
Host smart-928e4e5b-5a9f-4c02-97e5-d06fb74dc17e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=426290634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.426290634
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2353064841
Short name T778
Test name
Test status
Simulation time 10335041 ps
CPU time 1.44 seconds
Started Aug 05 06:01:58 PM PDT 24
Finished Aug 05 06:01:59 PM PDT 24
Peak memory 237720 kb
Host smart-c11e5537-90cc-47de-8bb4-032ee085119b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2353064841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2353064841
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1102322409
Short name T748
Test name
Test status
Simulation time 37627341 ps
CPU time 1.35 seconds
Started Aug 05 06:01:56 PM PDT 24
Finished Aug 05 06:01:58 PM PDT 24
Peak memory 235788 kb
Host smart-d6d351f3-f3a2-4e2c-89ae-13db37f6c815
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1102322409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1102322409
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3449667162
Short name T807
Test name
Test status
Simulation time 21496506 ps
CPU time 1.55 seconds
Started Aug 05 06:02:00 PM PDT 24
Finished Aug 05 06:02:01 PM PDT 24
Peak memory 237732 kb
Host smart-4061f859-b428-47ef-9821-d655889ff3e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3449667162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3449667162
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1818185166
Short name T832
Test name
Test status
Simulation time 11670978 ps
CPU time 1.44 seconds
Started Aug 05 06:02:03 PM PDT 24
Finished Aug 05 06:02:04 PM PDT 24
Peak memory 237716 kb
Host smart-c389f716-9fa6-4d8e-8c52-5f9f489ee222
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1818185166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1818185166
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3810920965
Short name T792
Test name
Test status
Simulation time 6190052 ps
CPU time 1.44 seconds
Started Aug 05 06:01:55 PM PDT 24
Finished Aug 05 06:01:57 PM PDT 24
Peak memory 235740 kb
Host smart-f7fea7fa-df08-4730-851d-b35887087361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3810920965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3810920965
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2681326979
Short name T755
Test name
Test status
Simulation time 8708803 ps
CPU time 1.6 seconds
Started Aug 05 06:02:00 PM PDT 24
Finished Aug 05 06:02:01 PM PDT 24
Peak memory 236860 kb
Host smart-6dab6c40-b1f6-4b56-84b3-6a8155c47ec0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2681326979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2681326979
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1182978300
Short name T340
Test name
Test status
Simulation time 18865219 ps
CPU time 1.37 seconds
Started Aug 05 06:01:55 PM PDT 24
Finished Aug 05 06:01:57 PM PDT 24
Peak memory 237696 kb
Host smart-842d5182-37e1-402c-8dc2-07576ef81682
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1182978300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1182978300
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3013143386
Short name T727
Test name
Test status
Simulation time 21366569 ps
CPU time 2.17 seconds
Started Aug 05 06:01:57 PM PDT 24
Finished Aug 05 06:01:59 PM PDT 24
Peak memory 235708 kb
Host smart-4bfcd0d7-1266-4c5d-a505-e70f21f1f268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3013143386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3013143386
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3678479660
Short name T756
Test name
Test status
Simulation time 18114783774 ps
CPU time 158.33 seconds
Started Aug 05 06:01:24 PM PDT 24
Finished Aug 05 06:04:02 PM PDT 24
Peak memory 239624 kb
Host smart-192b8e68-48f4-4814-8989-4261b9edb559
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3678479660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3678479660
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2013725458
Short name T722
Test name
Test status
Simulation time 6531691915 ps
CPU time 209.46 seconds
Started Aug 05 06:01:25 PM PDT 24
Finished Aug 05 06:04:54 PM PDT 24
Peak memory 237828 kb
Host smart-7c7656af-6e5a-4cdf-8ef5-ae2fac49ba85
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2013725458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2013725458
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2927315110
Short name T794
Test name
Test status
Simulation time 191983032 ps
CPU time 9.08 seconds
Started Aug 05 06:01:24 PM PDT 24
Finished Aug 05 06:01:33 PM PDT 24
Peak memory 249304 kb
Host smart-9f25b684-e6ba-439e-a03c-3ecfca1e9dce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2927315110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2927315110
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3816566815
Short name T732
Test name
Test status
Simulation time 514927955 ps
CPU time 4.96 seconds
Started Aug 05 06:01:25 PM PDT 24
Finished Aug 05 06:01:30 PM PDT 24
Peak memory 239864 kb
Host smart-aad002b6-6c12-4e29-9a78-c29d14d69d07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816566815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3816566815
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3106479107
Short name T810
Test name
Test status
Simulation time 75648519 ps
CPU time 5.51 seconds
Started Aug 05 06:01:27 PM PDT 24
Finished Aug 05 06:01:32 PM PDT 24
Peak memory 237704 kb
Host smart-0ac81172-51be-4bc2-899a-e419f114a002
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3106479107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3106479107
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2672651565
Short name T338
Test name
Test status
Simulation time 10759864 ps
CPU time 1.29 seconds
Started Aug 05 06:01:25 PM PDT 24
Finished Aug 05 06:01:26 PM PDT 24
Peak memory 237612 kb
Host smart-1db5a640-bb0b-4d2f-93d5-43e099323f48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2672651565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2672651565
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.36151534
Short name T791
Test name
Test status
Simulation time 1545288071 ps
CPU time 26.83 seconds
Started Aug 05 06:01:22 PM PDT 24
Finished Aug 05 06:01:49 PM PDT 24
Peak memory 248844 kb
Host smart-5c816a5b-fc4f-4dce-b06a-00395bc4d3c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=36151534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outst
anding.36151534
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.559189371
Short name T142
Test name
Test status
Simulation time 3748744292 ps
CPU time 149.5 seconds
Started Aug 05 06:01:18 PM PDT 24
Finished Aug 05 06:03:48 PM PDT 24
Peak memory 265464 kb
Host smart-e4c8f8aa-8e8d-43d2-a449-e4d1ffb06983
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=559189371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.559189371
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1310736543
Short name T761
Test name
Test status
Simulation time 961446286 ps
CPU time 16 seconds
Started Aug 05 06:01:25 PM PDT 24
Finished Aug 05 06:01:41 PM PDT 24
Peak memory 248900 kb
Host smart-097871fa-e2e2-4a30-be8d-4b1a4f83e7da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1310736543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1310736543
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2241083745
Short name T813
Test name
Test status
Simulation time 18133715 ps
CPU time 1.45 seconds
Started Aug 05 06:01:56 PM PDT 24
Finished Aug 05 06:01:58 PM PDT 24
Peak memory 236832 kb
Host smart-fb76408e-06fa-4b9f-98aa-6fc07b40d6c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2241083745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2241083745
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2918510027
Short name T754
Test name
Test status
Simulation time 29454335 ps
CPU time 1.42 seconds
Started Aug 05 06:01:56 PM PDT 24
Finished Aug 05 06:01:58 PM PDT 24
Peak memory 237616 kb
Host smart-bb4cd809-661f-42ff-8496-f1eab6eeaeef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2918510027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2918510027
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1251545783
Short name T829
Test name
Test status
Simulation time 8370659 ps
CPU time 1.55 seconds
Started Aug 05 06:01:55 PM PDT 24
Finished Aug 05 06:01:57 PM PDT 24
Peak memory 237720 kb
Host smart-f228a09f-d512-4d30-af7d-77ddd4050bc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1251545783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1251545783
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1164295913
Short name T800
Test name
Test status
Simulation time 16388301 ps
CPU time 1.82 seconds
Started Aug 05 06:01:58 PM PDT 24
Finished Aug 05 06:02:00 PM PDT 24
Peak memory 237712 kb
Host smart-834339d9-af5b-4987-a3a4-8624a46cf030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1164295913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1164295913
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3709549331
Short name T339
Test name
Test status
Simulation time 10461402 ps
CPU time 1.67 seconds
Started Aug 05 06:01:56 PM PDT 24
Finished Aug 05 06:01:58 PM PDT 24
Peak memory 237728 kb
Host smart-ecc0fa38-0771-4ce8-b4c7-df4ea4fe09f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3709549331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3709549331
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.416068576
Short name T830
Test name
Test status
Simulation time 11407416 ps
CPU time 1.45 seconds
Started Aug 05 06:02:03 PM PDT 24
Finished Aug 05 06:02:05 PM PDT 24
Peak memory 236704 kb
Host smart-0276f822-a3df-4d2c-ac84-a8ce5fb03fe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=416068576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.416068576
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.300269849
Short name T816
Test name
Test status
Simulation time 8491949 ps
CPU time 1.42 seconds
Started Aug 05 06:01:56 PM PDT 24
Finished Aug 05 06:01:58 PM PDT 24
Peak memory 236772 kb
Host smart-82c1c910-6f37-4415-a47e-9d7ad66433f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=300269849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.300269849
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2884537339
Short name T764
Test name
Test status
Simulation time 11217934 ps
CPU time 1.59 seconds
Started Aug 05 06:01:55 PM PDT 24
Finished Aug 05 06:01:57 PM PDT 24
Peak memory 237712 kb
Host smart-33b14c4d-fd18-4b5b-bcf7-1ea635a9da67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2884537339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2884537339
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.905158701
Short name T244
Test name
Test status
Simulation time 24677974 ps
CPU time 1.48 seconds
Started Aug 05 06:01:56 PM PDT 24
Finished Aug 05 06:01:57 PM PDT 24
Peak memory 236820 kb
Host smart-6fef767d-09ec-4f28-a5f1-f0d29684f221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=905158701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.905158701
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2620709000
Short name T342
Test name
Test status
Simulation time 191866791 ps
CPU time 8.59 seconds
Started Aug 05 06:01:28 PM PDT 24
Finished Aug 05 06:01:37 PM PDT 24
Peak memory 243968 kb
Host smart-1fb69f9a-29f1-4928-8fa2-caf27d327f90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620709000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2620709000
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.4282720184
Short name T806
Test name
Test status
Simulation time 232471649 ps
CPU time 8.9 seconds
Started Aug 05 06:01:22 PM PDT 24
Finished Aug 05 06:01:31 PM PDT 24
Peak memory 236780 kb
Host smart-c8aa05a1-06b1-4754-b304-b627a54d0ca0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4282720184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.4282720184
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.27935894
Short name T759
Test name
Test status
Simulation time 8951811 ps
CPU time 1.53 seconds
Started Aug 05 06:01:26 PM PDT 24
Finished Aug 05 06:01:28 PM PDT 24
Peak memory 236832 kb
Host smart-922b831c-4cfa-4af6-a8ec-34438efd1eee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=27935894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.27935894
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2174433716
Short name T831
Test name
Test status
Simulation time 1357657728 ps
CPU time 52.58 seconds
Started Aug 05 06:01:24 PM PDT 24
Finished Aug 05 06:02:16 PM PDT 24
Peak memory 245916 kb
Host smart-07efbdf1-5972-4692-9658-5e5879358179
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2174433716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2174433716
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1629383238
Short name T805
Test name
Test status
Simulation time 43943072 ps
CPU time 5.52 seconds
Started Aug 05 06:01:29 PM PDT 24
Finished Aug 05 06:01:34 PM PDT 24
Peak memory 252020 kb
Host smart-1e480df9-0f9e-4b49-8899-11467dd8d1f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1629383238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1629383238
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2113245765
Short name T343
Test name
Test status
Simulation time 122464641 ps
CPU time 9.31 seconds
Started Aug 05 06:01:21 PM PDT 24
Finished Aug 05 06:01:31 PM PDT 24
Peak memory 243832 kb
Host smart-b2de45a7-be44-4063-bc24-efef5b2b05b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113245765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2113245765
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1635154010
Short name T815
Test name
Test status
Simulation time 62350061 ps
CPU time 5.03 seconds
Started Aug 05 06:01:24 PM PDT 24
Finished Aug 05 06:01:29 PM PDT 24
Peak memory 236800 kb
Host smart-69e54876-a28a-46a4-a5b9-2d7bf6960050
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1635154010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1635154010
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.4097876649
Short name T797
Test name
Test status
Simulation time 10063135 ps
CPU time 1.29 seconds
Started Aug 05 06:01:23 PM PDT 24
Finished Aug 05 06:01:25 PM PDT 24
Peak memory 235700 kb
Host smart-91ad0a7e-eb7b-4442-8fbb-ba068554393b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4097876649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.4097876649
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1191361101
Short name T176
Test name
Test status
Simulation time 257345751 ps
CPU time 19.82 seconds
Started Aug 05 06:01:29 PM PDT 24
Finished Aug 05 06:01:49 PM PDT 24
Peak memory 240644 kb
Host smart-dfd74c35-10f1-4e94-92d4-f7c0cb40cba9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1191361101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1191361101
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.940048388
Short name T120
Test name
Test status
Simulation time 1928525398 ps
CPU time 148.64 seconds
Started Aug 05 06:01:23 PM PDT 24
Finished Aug 05 06:03:52 PM PDT 24
Peak memory 266580 kb
Host smart-34a2ce27-77a8-4cff-8315-f845f4a557b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=940048388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.940048388
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2879515348
Short name T346
Test name
Test status
Simulation time 7689312447 ps
CPU time 532.8 seconds
Started Aug 05 06:01:23 PM PDT 24
Finished Aug 05 06:10:16 PM PDT 24
Peak memory 268068 kb
Host smart-5d9d1f60-cbdb-4431-af51-02273cd83e28
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879515348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2879515348
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3376214858
Short name T785
Test name
Test status
Simulation time 101639276 ps
CPU time 13.45 seconds
Started Aug 05 06:01:24 PM PDT 24
Finished Aug 05 06:01:38 PM PDT 24
Peak memory 248652 kb
Host smart-161a60bb-8da6-4a5e-9a9d-7ed037f0e990
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3376214858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3376214858
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.783306576
Short name T812
Test name
Test status
Simulation time 37650875 ps
CPU time 5.83 seconds
Started Aug 05 06:01:32 PM PDT 24
Finished Aug 05 06:01:38 PM PDT 24
Peak memory 243364 kb
Host smart-87b087b5-fd20-4b7e-ad1f-38c9239d0dcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783306576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.783306576
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1879456573
Short name T240
Test name
Test status
Simulation time 89498412 ps
CPU time 5.25 seconds
Started Aug 05 06:01:25 PM PDT 24
Finished Aug 05 06:01:30 PM PDT 24
Peak memory 237724 kb
Host smart-d2fcdfeb-6436-49c2-bc18-4caf804cf412
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1879456573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1879456573
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3286987349
Short name T804
Test name
Test status
Simulation time 15182670 ps
CPU time 1.6 seconds
Started Aug 05 06:01:23 PM PDT 24
Finished Aug 05 06:01:24 PM PDT 24
Peak memory 236788 kb
Host smart-50cbbfb9-0dff-4ecb-9865-c794e1c81200
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3286987349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3286987349
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1454642731
Short name T784
Test name
Test status
Simulation time 469472897 ps
CPU time 22.72 seconds
Started Aug 05 06:01:32 PM PDT 24
Finished Aug 05 06:01:55 PM PDT 24
Peak memory 240516 kb
Host smart-ae7170e9-26aa-48b1-8b2d-757f5424efe3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1454642731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1454642731
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3015991440
Short name T135
Test name
Test status
Simulation time 7756153923 ps
CPU time 290.23 seconds
Started Aug 05 06:01:23 PM PDT 24
Finished Aug 05 06:06:13 PM PDT 24
Peak memory 265668 kb
Host smart-76e15933-d325-4dbd-a36d-b6d284641a54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3015991440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3015991440
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.851222067
Short name T141
Test name
Test status
Simulation time 134668242298 ps
CPU time 996.02 seconds
Started Aug 05 06:01:29 PM PDT 24
Finished Aug 05 06:18:06 PM PDT 24
Peak memory 265808 kb
Host smart-a5ab6594-f2d9-41fe-94ee-d65a5c742816
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851222067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.851222067
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3810843362
Short name T719
Test name
Test status
Simulation time 49968947 ps
CPU time 6.44 seconds
Started Aug 05 06:01:25 PM PDT 24
Finished Aug 05 06:01:31 PM PDT 24
Peak memory 248408 kb
Host smart-c99d2c8c-3214-45a9-9b26-4921620bbc88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3810843362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3810843362
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3600431435
Short name T746
Test name
Test status
Simulation time 83950337 ps
CPU time 7.61 seconds
Started Aug 05 06:01:32 PM PDT 24
Finished Aug 05 06:01:40 PM PDT 24
Peak memory 240584 kb
Host smart-6d1bf55d-8341-4876-a155-c82bc3b34fe0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600431435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3600431435
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1262258603
Short name T735
Test name
Test status
Simulation time 34165180 ps
CPU time 7.24 seconds
Started Aug 05 06:01:31 PM PDT 24
Finished Aug 05 06:01:39 PM PDT 24
Peak memory 237696 kb
Host smart-dc5f5842-3f24-4260-bd14-239d4d42b415
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1262258603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1262258603
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3312353310
Short name T179
Test name
Test status
Simulation time 86805357 ps
CPU time 12.22 seconds
Started Aug 05 06:01:28 PM PDT 24
Finished Aug 05 06:01:40 PM PDT 24
Peak memory 245916 kb
Host smart-e0b98d02-ad65-4281-9258-21cf910a76ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3312353310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.3312353310
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1841426068
Short name T129
Test name
Test status
Simulation time 60568266797 ps
CPU time 383.65 seconds
Started Aug 05 06:01:30 PM PDT 24
Finished Aug 05 06:07:54 PM PDT 24
Peak memory 273456 kb
Host smart-ca675aba-b72c-4d3b-972c-c48648a1a7a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1841426068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1841426068
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2925910967
Short name T781
Test name
Test status
Simulation time 265838397 ps
CPU time 10.01 seconds
Started Aug 05 06:01:32 PM PDT 24
Finished Aug 05 06:01:42 PM PDT 24
Peak memory 248840 kb
Host smart-bd31696f-526a-4e22-8591-1622dab78465
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2925910967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2925910967
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2234181097
Short name T232
Test name
Test status
Simulation time 1494571057 ps
CPU time 12.16 seconds
Started Aug 05 06:01:29 PM PDT 24
Finished Aug 05 06:01:41 PM PDT 24
Peak memory 244420 kb
Host smart-887ac03e-9e13-42fe-9604-997ea42460a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234181097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2234181097
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2039552637
Short name T817
Test name
Test status
Simulation time 117342892 ps
CPU time 5.53 seconds
Started Aug 05 06:01:33 PM PDT 24
Finished Aug 05 06:01:39 PM PDT 24
Peak memory 240640 kb
Host smart-afc4201f-faa0-45ec-a74d-46852d1e269e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2039552637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2039552637
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1085045935
Short name T822
Test name
Test status
Simulation time 25415842 ps
CPU time 1.41 seconds
Started Aug 05 06:01:31 PM PDT 24
Finished Aug 05 06:01:33 PM PDT 24
Peak memory 235812 kb
Host smart-95cefc41-9366-49c5-9399-0c9aad9936f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1085045935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1085045935
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1216008093
Short name T745
Test name
Test status
Simulation time 362305684 ps
CPU time 23.37 seconds
Started Aug 05 06:01:29 PM PDT 24
Finished Aug 05 06:01:53 PM PDT 24
Peak memory 245048 kb
Host smart-fadf11b6-7d43-472b-9923-79d760470120
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1216008093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1216008093
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3795624772
Short name T140
Test name
Test status
Simulation time 6111614205 ps
CPU time 359.18 seconds
Started Aug 05 06:01:33 PM PDT 24
Finished Aug 05 06:07:32 PM PDT 24
Peak memory 265712 kb
Host smart-e937ffbd-9f04-418f-9e8e-441b8b20d957
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3795624772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3795624772
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.571400560
Short name T125
Test name
Test status
Simulation time 9048689717 ps
CPU time 655.77 seconds
Started Aug 05 06:01:32 PM PDT 24
Finished Aug 05 06:12:28 PM PDT 24
Peak memory 273812 kb
Host smart-61adfa87-43aa-4e72-a437-192d36c8e858
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571400560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.571400560
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3878614966
Short name T717
Test name
Test status
Simulation time 44942183 ps
CPU time 6.52 seconds
Started Aug 05 06:01:31 PM PDT 24
Finished Aug 05 06:01:38 PM PDT 24
Peak memory 255376 kb
Host smart-95fc0a09-710b-4d16-8b6a-4f5f0d50659f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3878614966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3878614966
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1559830079
Short name T156
Test name
Test status
Simulation time 10468336561 ps
CPU time 69.2 seconds
Started Aug 05 06:01:31 PM PDT 24
Finished Aug 05 06:02:41 PM PDT 24
Peak memory 240796 kb
Host smart-219a745d-88c7-4476-b96f-ab31d9609551
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1559830079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1559830079
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3224519900
Short name T298
Test name
Test status
Simulation time 44460500449 ps
CPU time 2532.71 seconds
Started Aug 05 05:08:46 PM PDT 24
Finished Aug 05 05:50:59 PM PDT 24
Peak memory 287176 kb
Host smart-41195192-fe76-456e-a67b-d3b98cb76748
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224519900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3224519900
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1434320308
Short name T5
Test name
Test status
Simulation time 2711257420 ps
CPU time 35.11 seconds
Started Aug 05 05:08:46 PM PDT 24
Finished Aug 05 05:09:22 PM PDT 24
Peak memory 248276 kb
Host smart-b5c4bc72-e716-4602-b12a-4e2ffaefd7d6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1434320308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1434320308
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3254718441
Short name T276
Test name
Test status
Simulation time 3119312823 ps
CPU time 66.31 seconds
Started Aug 05 05:08:47 PM PDT 24
Finished Aug 05 05:09:53 PM PDT 24
Peak memory 256524 kb
Host smart-8f168cfd-8e8b-46cb-9681-cfa744ebd0c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32547
18441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3254718441
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1957096214
Short name T77
Test name
Test status
Simulation time 237395640 ps
CPU time 4.75 seconds
Started Aug 05 05:08:59 PM PDT 24
Finished Aug 05 05:09:04 PM PDT 24
Peak memory 239724 kb
Host smart-2a9e2a1d-b52d-4e46-b7d2-fcfc542ca0c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19570
96214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1957096214
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1206823982
Short name T299
Test name
Test status
Simulation time 74099113584 ps
CPU time 1225.64 seconds
Started Aug 05 05:08:46 PM PDT 24
Finished Aug 05 05:29:12 PM PDT 24
Peak memory 272868 kb
Host smart-ddd08a47-581f-4ee2-81a2-73ed66a25acb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206823982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1206823982
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2668297957
Short name T491
Test name
Test status
Simulation time 7323920277 ps
CPU time 755.8 seconds
Started Aug 05 05:08:53 PM PDT 24
Finished Aug 05 05:21:29 PM PDT 24
Peak memory 267704 kb
Host smart-1c1b64a6-d23a-442c-9d24-5ce7357dcd91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668297957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2668297957
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3230388690
Short name T314
Test name
Test status
Simulation time 6769057478 ps
CPU time 288.62 seconds
Started Aug 05 05:08:45 PM PDT 24
Finished Aug 05 05:13:34 PM PDT 24
Peak memory 246932 kb
Host smart-ca3ad4a7-f378-4fef-9af7-a12b6e174a12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230388690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3230388690
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2355887449
Short name T223
Test name
Test status
Simulation time 801419264 ps
CPU time 25.72 seconds
Started Aug 05 05:08:48 PM PDT 24
Finished Aug 05 05:09:14 PM PDT 24
Peak memory 255704 kb
Host smart-6f92af36-b399-4145-bd10-73258e10a30d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23558
87449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2355887449
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2561798996
Short name T589
Test name
Test status
Simulation time 4009495799 ps
CPU time 26.38 seconds
Started Aug 05 05:08:47 PM PDT 24
Finished Aug 05 05:09:13 PM PDT 24
Peak memory 256028 kb
Host smart-133ea0ec-d313-417f-ac1f-4fa69c7e008c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25617
98996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2561798996
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3878275430
Short name T9
Test name
Test status
Simulation time 1942765653 ps
CPU time 13.05 seconds
Started Aug 05 05:08:49 PM PDT 24
Finished Aug 05 05:09:02 PM PDT 24
Peak memory 273528 kb
Host smart-95fd15f4-3a7e-4f18-b5d4-a59abf3e8610
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3878275430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3878275430
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.49887043
Short name T391
Test name
Test status
Simulation time 268631656 ps
CPU time 27.78 seconds
Started Aug 05 05:08:47 PM PDT 24
Finished Aug 05 05:09:14 PM PDT 24
Peak memory 256448 kb
Host smart-58c28083-c6a8-48c2-82eb-660725b59c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49887
043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.49887043
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.3801973146
Short name T487
Test name
Test status
Simulation time 117807890380 ps
CPU time 2288.62 seconds
Started Aug 05 05:08:44 PM PDT 24
Finished Aug 05 05:46:53 PM PDT 24
Peak memory 305860 kb
Host smart-1c9a4e05-c6de-44b1-9160-2cec7bb777e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801973146 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.3801973146
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1219398103
Short name T195
Test name
Test status
Simulation time 30789050 ps
CPU time 2.43 seconds
Started Aug 05 05:08:46 PM PDT 24
Finished Aug 05 05:08:48 PM PDT 24
Peak memory 248656 kb
Host smart-dccedf83-53ec-4fad-bb18-ea9ed0e46b4d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1219398103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1219398103
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2769452646
Short name T697
Test name
Test status
Simulation time 110861907067 ps
CPU time 1416.75 seconds
Started Aug 05 05:08:43 PM PDT 24
Finished Aug 05 05:32:20 PM PDT 24
Peak memory 272304 kb
Host smart-2791c1f0-9ceb-4188-b492-8e6da1396900
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769452646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2769452646
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.126304604
Short name T703
Test name
Test status
Simulation time 8496616852 ps
CPU time 24.19 seconds
Started Aug 05 05:09:03 PM PDT 24
Finished Aug 05 05:09:28 PM PDT 24
Peak memory 248376 kb
Host smart-1c197746-e805-40aa-8896-c741d2ae896b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=126304604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.126304604
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1746866771
Short name T709
Test name
Test status
Simulation time 772575277 ps
CPU time 75.09 seconds
Started Aug 05 05:08:46 PM PDT 24
Finished Aug 05 05:10:02 PM PDT 24
Peak memory 256476 kb
Host smart-f99a2cc1-4953-4cdc-9b01-098c10db1686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17468
66771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1746866771
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2864689596
Short name T390
Test name
Test status
Simulation time 612588680 ps
CPU time 14.51 seconds
Started Aug 05 05:09:05 PM PDT 24
Finished Aug 05 05:09:19 PM PDT 24
Peak memory 247856 kb
Host smart-4e2b5135-ecac-4857-9afb-ad731362f270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28646
89596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2864689596
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2049096868
Short name T331
Test name
Test status
Simulation time 28765120382 ps
CPU time 1518.7 seconds
Started Aug 05 05:08:52 PM PDT 24
Finished Aug 05 05:34:11 PM PDT 24
Peak memory 272364 kb
Host smart-14392632-760f-455c-bf90-f488d0c929a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049096868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2049096868
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3411653840
Short name T43
Test name
Test status
Simulation time 13221308469 ps
CPU time 1237.83 seconds
Started Aug 05 05:08:45 PM PDT 24
Finished Aug 05 05:29:23 PM PDT 24
Peak memory 289156 kb
Host smart-9850943b-cfa8-430a-983c-a9218280fbba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411653840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3411653840
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2514586427
Short name T398
Test name
Test status
Simulation time 6210458644 ps
CPU time 36.89 seconds
Started Aug 05 05:09:03 PM PDT 24
Finished Aug 05 05:09:40 PM PDT 24
Peak memory 256576 kb
Host smart-98e94d72-bf9e-4d8f-a126-10e3413adfcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25145
86427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2514586427
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.34731233
Short name T550
Test name
Test status
Simulation time 72177872 ps
CPU time 8.59 seconds
Started Aug 05 05:08:43 PM PDT 24
Finished Aug 05 05:08:52 PM PDT 24
Peak memory 247804 kb
Host smart-3dac1e87-fa94-40c5-b041-42c0cb3fcd61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34731
233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.34731233
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.740147865
Short name T37
Test name
Test status
Simulation time 2566234553 ps
CPU time 11.17 seconds
Started Aug 05 05:09:04 PM PDT 24
Finished Aug 05 05:09:15 PM PDT 24
Peak memory 274176 kb
Host smart-38eb0c88-fe0c-482e-91c3-2ca09d6b8e3f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=740147865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.740147865
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3281921187
Short name T634
Test name
Test status
Simulation time 766484136 ps
CPU time 25.37 seconds
Started Aug 05 05:08:46 PM PDT 24
Finished Aug 05 05:09:12 PM PDT 24
Peak memory 256540 kb
Host smart-c444ce96-70c8-43fd-8b7c-d55d17a3b21d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32819
21187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3281921187
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.401253751
Short name T372
Test name
Test status
Simulation time 1126260758 ps
CPU time 62 seconds
Started Aug 05 05:08:55 PM PDT 24
Finished Aug 05 05:09:57 PM PDT 24
Peak memory 256500 kb
Host smart-2bbf3cfd-e05f-47de-86da-459f27ef55ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40125
3751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.401253751
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3321547534
Short name T514
Test name
Test status
Simulation time 67415259203 ps
CPU time 2161.15 seconds
Started Aug 05 05:08:46 PM PDT 24
Finished Aug 05 05:44:48 PM PDT 24
Peak memory 288268 kb
Host smart-8a7a6155-6065-492e-aca3-760bc5161dd5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321547534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3321547534
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.3437889877
Short name T680
Test name
Test status
Simulation time 96936221681 ps
CPU time 2668.14 seconds
Started Aug 05 05:08:46 PM PDT 24
Finished Aug 05 05:53:15 PM PDT 24
Peak memory 321496 kb
Host smart-ef8e57b1-6b1e-48e6-83ef-5a9c6a053268
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437889877 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.3437889877
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2354400872
Short name T87
Test name
Test status
Simulation time 25472451284 ps
CPU time 1497.42 seconds
Started Aug 05 05:09:06 PM PDT 24
Finished Aug 05 05:34:04 PM PDT 24
Peak memory 272612 kb
Host smart-80f07ed2-bb5a-40eb-a29a-49f096453f1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354400872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2354400872
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2307393091
Short name T235
Test name
Test status
Simulation time 4160781482 ps
CPU time 225.62 seconds
Started Aug 05 05:09:06 PM PDT 24
Finished Aug 05 05:12:52 PM PDT 24
Peak memory 250644 kb
Host smart-e64c2f89-9218-4f16-aa4b-505d1b0ce46c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23073
93091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2307393091
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.30545388
Short name T376
Test name
Test status
Simulation time 727274468 ps
CPU time 31.3 seconds
Started Aug 05 05:09:11 PM PDT 24
Finished Aug 05 05:09:42 PM PDT 24
Peak memory 256488 kb
Host smart-30e52ad3-391b-4f25-a4aa-38256a1fb0eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30545
388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.30545388
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.724899655
Short name T535
Test name
Test status
Simulation time 73633735173 ps
CPU time 1372.77 seconds
Started Aug 05 05:09:38 PM PDT 24
Finished Aug 05 05:32:31 PM PDT 24
Peak memory 288592 kb
Host smart-60e8473a-9c7a-445b-91e8-1b6aa42878c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724899655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.724899655
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2496923207
Short name T285
Test name
Test status
Simulation time 8260869917 ps
CPU time 838.76 seconds
Started Aug 05 05:09:04 PM PDT 24
Finished Aug 05 05:23:03 PM PDT 24
Peak memory 265800 kb
Host smart-a97c4fe8-06e8-4370-9a84-563a64382a1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496923207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2496923207
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.623495585
Short name T595
Test name
Test status
Simulation time 49649862657 ps
CPU time 510.38 seconds
Started Aug 05 05:09:07 PM PDT 24
Finished Aug 05 05:17:37 PM PDT 24
Peak memory 248224 kb
Host smart-238a9582-9c71-4a9a-bd05-ae80a416158a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623495585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.623495585
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1316369246
Short name T59
Test name
Test status
Simulation time 904467378 ps
CPU time 48.91 seconds
Started Aug 05 05:09:05 PM PDT 24
Finished Aug 05 05:09:54 PM PDT 24
Peak memory 248364 kb
Host smart-10486f12-9b04-4fef-ac0f-b4c2fe1fa645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13163
69246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1316369246
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3328533579
Short name T530
Test name
Test status
Simulation time 496365240 ps
CPU time 32.38 seconds
Started Aug 05 05:09:19 PM PDT 24
Finished Aug 05 05:09:52 PM PDT 24
Peak memory 255864 kb
Host smart-cca9d6e3-fb66-4530-a214-1079cb90a99b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33285
33579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3328533579
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2827837129
Short name T11
Test name
Test status
Simulation time 640232679 ps
CPU time 19.7 seconds
Started Aug 05 05:09:12 PM PDT 24
Finished Aug 05 05:09:32 PM PDT 24
Peak memory 248836 kb
Host smart-b9d31288-e682-4a0f-99cd-333d492de394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28278
37129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2827837129
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.278834783
Short name T356
Test name
Test status
Simulation time 812232698 ps
CPU time 45.21 seconds
Started Aug 05 05:09:01 PM PDT 24
Finished Aug 05 05:09:46 PM PDT 24
Peak memory 256504 kb
Host smart-64d7a9fb-1efe-40f3-bf55-831044b6579c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27883
4783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.278834783
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3334021721
Short name T466
Test name
Test status
Simulation time 28696139180 ps
CPU time 774.53 seconds
Started Aug 05 05:09:17 PM PDT 24
Finished Aug 05 05:22:11 PM PDT 24
Peak memory 272884 kb
Host smart-41ccb45c-1e79-41e3-8bb5-7320ceb51160
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334021721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3334021721
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.62990150
Short name T679
Test name
Test status
Simulation time 805177582 ps
CPU time 19.26 seconds
Started Aug 05 05:09:38 PM PDT 24
Finished Aug 05 05:09:57 PM PDT 24
Peak memory 248348 kb
Host smart-17ebe8f0-4d5f-4aa3-ac65-6c4e33d42b52
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=62990150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.62990150
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1496124592
Short name T215
Test name
Test status
Simulation time 2101787972 ps
CPU time 84.75 seconds
Started Aug 05 05:09:13 PM PDT 24
Finished Aug 05 05:10:38 PM PDT 24
Peak memory 250424 kb
Host smart-cd1a799b-aa74-4de3-8f01-eaf551507d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14961
24592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1496124592
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3703508854
Short name T674
Test name
Test status
Simulation time 292956524 ps
CPU time 3.66 seconds
Started Aug 05 05:09:13 PM PDT 24
Finished Aug 05 05:09:17 PM PDT 24
Peak memory 239816 kb
Host smart-b1a15f50-2f75-40a6-bfe4-b6475c06cd23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37035
08854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3703508854
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.477656639
Short name T577
Test name
Test status
Simulation time 1084667147 ps
CPU time 27.73 seconds
Started Aug 05 05:09:05 PM PDT 24
Finished Aug 05 05:09:33 PM PDT 24
Peak memory 248308 kb
Host smart-0620f6f1-0059-43ec-9f4d-60db8b9818d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47765
6639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.477656639
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.1042471807
Short name T392
Test name
Test status
Simulation time 231572370 ps
CPU time 4.65 seconds
Started Aug 05 05:09:17 PM PDT 24
Finished Aug 05 05:09:22 PM PDT 24
Peak memory 239592 kb
Host smart-598887f3-d0b3-4383-a999-7a083a53378f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10424
71807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1042471807
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3237493033
Short name T261
Test name
Test status
Simulation time 177685848 ps
CPU time 12.28 seconds
Started Aug 05 05:09:15 PM PDT 24
Finished Aug 05 05:09:27 PM PDT 24
Peak memory 254824 kb
Host smart-f4014630-8faa-4a5a-b29a-16af4c33820f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32374
93033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3237493033
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2574103283
Short name T211
Test name
Test status
Simulation time 42101795 ps
CPU time 4.33 seconds
Started Aug 05 05:09:12 PM PDT 24
Finished Aug 05 05:09:16 PM PDT 24
Peak memory 250112 kb
Host smart-dfc9ce76-4af9-4422-8c61-05496cd07a0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25741
03283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2574103283
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.2088049598
Short name T270
Test name
Test status
Simulation time 99113317623 ps
CPU time 3739.57 seconds
Started Aug 05 05:09:11 PM PDT 24
Finished Aug 05 06:11:31 PM PDT 24
Peak memory 305840 kb
Host smart-dbbdd95a-4d0f-49ad-bf21-014002965626
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088049598 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.2088049598
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2298026656
Short name T186
Test name
Test status
Simulation time 151470262 ps
CPU time 3.41 seconds
Started Aug 05 05:09:22 PM PDT 24
Finished Aug 05 05:09:25 PM PDT 24
Peak memory 248652 kb
Host smart-2993e634-23ef-4fbf-b7cb-5b51e5a7cbd7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2298026656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2298026656
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.4178103760
Short name T620
Test name
Test status
Simulation time 19303712888 ps
CPU time 1362.43 seconds
Started Aug 05 05:09:16 PM PDT 24
Finished Aug 05 05:31:59 PM PDT 24
Peak memory 272628 kb
Host smart-4ebd32bc-b4de-4569-8058-784b49b7a47c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178103760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.4178103760
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.4068413568
Short name T518
Test name
Test status
Simulation time 827868261 ps
CPU time 35.27 seconds
Started Aug 05 05:09:10 PM PDT 24
Finished Aug 05 05:09:46 PM PDT 24
Peak memory 248156 kb
Host smart-b74badf3-22f7-4e53-b4de-cd34f0607f16
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4068413568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.4068413568
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3445292383
Short name T559
Test name
Test status
Simulation time 3988828096 ps
CPU time 217.34 seconds
Started Aug 05 05:09:11 PM PDT 24
Finished Aug 05 05:12:49 PM PDT 24
Peak memory 256140 kb
Host smart-3383403d-845f-4bca-aa36-e45a91461ae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34452
92383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3445292383
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1471329215
Short name T499
Test name
Test status
Simulation time 408832235 ps
CPU time 24.13 seconds
Started Aug 05 05:09:14 PM PDT 24
Finished Aug 05 05:09:38 PM PDT 24
Peak memory 248232 kb
Host smart-8330fe88-bc3a-419d-81dc-77b3f2c482c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14713
29215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1471329215
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.4181459170
Short name T695
Test name
Test status
Simulation time 112612645018 ps
CPU time 1620.01 seconds
Started Aug 05 05:09:11 PM PDT 24
Finished Aug 05 05:36:11 PM PDT 24
Peak memory 271068 kb
Host smart-75026afb-1847-44d2-817e-979e9fea843b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181459170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.4181459170
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2946598652
Short name T631
Test name
Test status
Simulation time 7020887586 ps
CPU time 735.51 seconds
Started Aug 05 05:09:14 PM PDT 24
Finished Aug 05 05:21:29 PM PDT 24
Peak memory 289264 kb
Host smart-5ae52e5c-bd99-441c-9f95-aa39cec3675e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946598652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2946598652
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1504586303
Short name T558
Test name
Test status
Simulation time 5179000984 ps
CPU time 206.05 seconds
Started Aug 05 05:09:11 PM PDT 24
Finished Aug 05 05:12:37 PM PDT 24
Peak memory 248088 kb
Host smart-c7ce1d99-8233-4a11-abb8-2a9f261a9893
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504586303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1504586303
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1198597400
Short name T68
Test name
Test status
Simulation time 499313791 ps
CPU time 10.64 seconds
Started Aug 05 05:09:25 PM PDT 24
Finished Aug 05 05:09:35 PM PDT 24
Peak memory 248352 kb
Host smart-8eec7ec0-42ae-4477-a418-de3465c8e2ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11985
97400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1198597400
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3800772476
Short name T172
Test name
Test status
Simulation time 7529269266 ps
CPU time 52.25 seconds
Started Aug 05 05:09:35 PM PDT 24
Finished Aug 05 05:10:27 PM PDT 24
Peak memory 248052 kb
Host smart-05168fbf-199c-4022-a7f0-321ca822f546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38007
72476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3800772476
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.504637388
Short name T80
Test name
Test status
Simulation time 234346384 ps
CPU time 18.38 seconds
Started Aug 05 05:09:18 PM PDT 24
Finished Aug 05 05:09:37 PM PDT 24
Peak memory 255780 kb
Host smart-ae8e4dc0-0759-4fac-9342-d6878807ede4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50463
7388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.504637388
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2219994501
Short name T283
Test name
Test status
Simulation time 1020065228 ps
CPU time 60.37 seconds
Started Aug 05 05:09:10 PM PDT 24
Finished Aug 05 05:10:10 PM PDT 24
Peak memory 256472 kb
Host smart-b8c7e6e3-9935-444d-9e76-b1a4797a20d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22199
94501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2219994501
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.166432069
Short name T716
Test name
Test status
Simulation time 12887980250 ps
CPU time 1027.36 seconds
Started Aug 05 05:09:17 PM PDT 24
Finished Aug 05 05:26:25 PM PDT 24
Peak memory 285212 kb
Host smart-de4e49b3-74c0-4dfa-ba87-f48356105d7c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166432069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.166432069
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2693238107
Short name T184
Test name
Test status
Simulation time 115669495 ps
CPU time 3.14 seconds
Started Aug 05 05:09:12 PM PDT 24
Finished Aug 05 05:09:15 PM PDT 24
Peak memory 248648 kb
Host smart-b648a7dc-5893-4689-886f-f53387fa617b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2693238107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2693238107
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1726006336
Short name T170
Test name
Test status
Simulation time 351586041 ps
CPU time 16.21 seconds
Started Aug 05 05:09:29 PM PDT 24
Finished Aug 05 05:09:45 PM PDT 24
Peak memory 248428 kb
Host smart-321e7f81-415f-4c9e-b171-2af83724fe09
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1726006336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1726006336
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.776743229
Short name T691
Test name
Test status
Simulation time 5420857904 ps
CPU time 265.05 seconds
Started Aug 05 05:09:28 PM PDT 24
Finished Aug 05 05:13:53 PM PDT 24
Peak memory 256176 kb
Host smart-49cfcfc2-231e-4f9c-afa4-3caef722bb3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77674
3229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.776743229
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.4294027141
Short name T418
Test name
Test status
Simulation time 1571013136 ps
CPU time 55.24 seconds
Started Aug 05 05:09:11 PM PDT 24
Finished Aug 05 05:10:07 PM PDT 24
Peak memory 248376 kb
Host smart-828d7517-6f8e-49ef-acae-f0caa0331712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42940
27141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.4294027141
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2641204067
Short name T329
Test name
Test status
Simulation time 10647431318 ps
CPU time 1104.08 seconds
Started Aug 05 05:09:10 PM PDT 24
Finished Aug 05 05:27:34 PM PDT 24
Peak memory 281164 kb
Host smart-676755c8-af61-4793-903b-ea95b07c7b9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641204067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2641204067
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2039300698
Short name T644
Test name
Test status
Simulation time 143229584222 ps
CPU time 2283.63 seconds
Started Aug 05 05:09:14 PM PDT 24
Finished Aug 05 05:47:18 PM PDT 24
Peak memory 288832 kb
Host smart-9e821268-9d3f-4fed-8770-68328dec3daa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039300698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2039300698
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1488691070
Short name T655
Test name
Test status
Simulation time 1415801210 ps
CPU time 65 seconds
Started Aug 05 05:09:10 PM PDT 24
Finished Aug 05 05:10:15 PM PDT 24
Peak memory 248220 kb
Host smart-149b0fb0-127a-43e1-a616-2309c03fcb03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488691070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1488691070
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2249779211
Short name T212
Test name
Test status
Simulation time 241349906 ps
CPU time 18.95 seconds
Started Aug 05 05:09:11 PM PDT 24
Finished Aug 05 05:09:30 PM PDT 24
Peak memory 256148 kb
Host smart-47c3f0b3-f933-4cb1-aa25-6ed7942432ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22497
79211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2249779211
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2192999064
Short name T436
Test name
Test status
Simulation time 47269277 ps
CPU time 3.75 seconds
Started Aug 05 05:09:28 PM PDT 24
Finished Aug 05 05:09:32 PM PDT 24
Peak memory 239720 kb
Host smart-54083133-fd1b-42f6-8321-0f994cc7964b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21929
99064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2192999064
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.724822452
Short name T611
Test name
Test status
Simulation time 590124613 ps
CPU time 36.12 seconds
Started Aug 05 05:09:12 PM PDT 24
Finished Aug 05 05:09:49 PM PDT 24
Peak memory 248392 kb
Host smart-45e61416-22fe-40eb-a3a8-569bcc1f5145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72482
2452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.724822452
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.483709844
Short name T571
Test name
Test status
Simulation time 2753565239 ps
CPU time 41.44 seconds
Started Aug 05 05:09:23 PM PDT 24
Finished Aug 05 05:10:05 PM PDT 24
Peak memory 255636 kb
Host smart-e0f11775-78c2-4fe5-82c0-ab0cc1d22bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48370
9844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.483709844
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3187748053
Short name T182
Test name
Test status
Simulation time 71797538902 ps
CPU time 2013.23 seconds
Started Aug 05 05:09:11 PM PDT 24
Finished Aug 05 05:42:44 PM PDT 24
Peak memory 305828 kb
Host smart-692a142c-b6b2-4496-be47-706d2776aac2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187748053 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3187748053
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2453525348
Short name T190
Test name
Test status
Simulation time 21287373 ps
CPU time 2.18 seconds
Started Aug 05 05:09:17 PM PDT 24
Finished Aug 05 05:09:19 PM PDT 24
Peak memory 248684 kb
Host smart-40734908-7b54-47c8-a050-47aa654d3049
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2453525348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2453525348
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3251509047
Short name T685
Test name
Test status
Simulation time 158560284173 ps
CPU time 1725.58 seconds
Started Aug 05 05:09:13 PM PDT 24
Finished Aug 05 05:37:59 PM PDT 24
Peak memory 272980 kb
Host smart-29635949-9f88-4645-907f-bb98f466b512
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251509047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3251509047
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2944791506
Short name T509
Test name
Test status
Simulation time 135378233 ps
CPU time 8.73 seconds
Started Aug 05 05:09:10 PM PDT 24
Finished Aug 05 05:09:19 PM PDT 24
Peak memory 248368 kb
Host smart-40cd45c6-cc78-48e6-93e7-948336d04181
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2944791506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2944791506
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3742841992
Short name T524
Test name
Test status
Simulation time 259130297 ps
CPU time 22 seconds
Started Aug 05 05:09:14 PM PDT 24
Finished Aug 05 05:09:36 PM PDT 24
Peak memory 256028 kb
Host smart-e43aa119-aefc-443c-967f-792a2c0c12e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37428
41992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3742841992
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3274979336
Short name T96
Test name
Test status
Simulation time 782996413 ps
CPU time 20.22 seconds
Started Aug 05 05:09:14 PM PDT 24
Finished Aug 05 05:09:34 PM PDT 24
Peak memory 248280 kb
Host smart-d97d7e3e-b952-440d-b340-f744a43b436c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32749
79336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3274979336
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3518697728
Short name T49
Test name
Test status
Simulation time 59952225439 ps
CPU time 1335.94 seconds
Started Aug 05 05:09:25 PM PDT 24
Finished Aug 05 05:31:41 PM PDT 24
Peak memory 289200 kb
Host smart-a546297b-f3a9-43b5-9e02-60660f6a02da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518697728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3518697728
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3753881965
Short name T700
Test name
Test status
Simulation time 22669884713 ps
CPU time 451.67 seconds
Started Aug 05 05:09:14 PM PDT 24
Finished Aug 05 05:16:46 PM PDT 24
Peak memory 248132 kb
Host smart-bee2ece6-d404-4943-9ccf-5c35fa20cef5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753881965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3753881965
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2472384855
Short name T56
Test name
Test status
Simulation time 524358886 ps
CPU time 37.85 seconds
Started Aug 05 05:09:15 PM PDT 24
Finished Aug 05 05:09:53 PM PDT 24
Peak memory 256432 kb
Host smart-889f6ff5-d143-45ef-b248-401806246491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24723
84855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2472384855
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.4144898265
Short name T47
Test name
Test status
Simulation time 20322074 ps
CPU time 3.18 seconds
Started Aug 05 05:09:09 PM PDT 24
Finished Aug 05 05:09:12 PM PDT 24
Peak memory 240012 kb
Host smart-bd95e38c-4f5d-4544-8e75-d6db03841b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41448
98265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.4144898265
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.895122839
Short name T429
Test name
Test status
Simulation time 226229401 ps
CPU time 4.86 seconds
Started Aug 05 05:09:19 PM PDT 24
Finished Aug 05 05:09:24 PM PDT 24
Peak memory 239636 kb
Host smart-9f4d5bff-59e2-4402-97f8-212195c89e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89512
2839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.895122839
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1785114187
Short name T667
Test name
Test status
Simulation time 417524578 ps
CPU time 8.45 seconds
Started Aug 05 05:09:14 PM PDT 24
Finished Aug 05 05:09:23 PM PDT 24
Peak memory 251396 kb
Host smart-42de0d93-c527-4312-bdae-0ff882f249c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17851
14187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1785114187
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.632906241
Short name T92
Test name
Test status
Simulation time 29784720617 ps
CPU time 1864.64 seconds
Started Aug 05 05:09:12 PM PDT 24
Finished Aug 05 05:40:17 PM PDT 24
Peak memory 284200 kb
Host smart-1fe09f35-ecf3-4039-95e5-aafc7911e63b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632906241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.632906241
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3226250685
Short name T498
Test name
Test status
Simulation time 199404150343 ps
CPU time 2905.41 seconds
Started Aug 05 05:09:17 PM PDT 24
Finished Aug 05 05:57:43 PM PDT 24
Peak memory 288008 kb
Host smart-83f96730-ebd5-4541-b78f-9048670c8cae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226250685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3226250685
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1688735909
Short name T557
Test name
Test status
Simulation time 115598651 ps
CPU time 7.76 seconds
Started Aug 05 05:09:17 PM PDT 24
Finished Aug 05 05:09:25 PM PDT 24
Peak memory 248344 kb
Host smart-4d0c33f6-63ce-401d-8a41-17bbd4a93799
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1688735909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1688735909
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2292395480
Short name T387
Test name
Test status
Simulation time 626589533 ps
CPU time 56.47 seconds
Started Aug 05 05:09:13 PM PDT 24
Finished Aug 05 05:10:10 PM PDT 24
Peak memory 256032 kb
Host smart-8ae35017-9bea-47ae-9a1c-c664b0ca87cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22923
95480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2292395480
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1193240856
Short name T588
Test name
Test status
Simulation time 735692543 ps
CPU time 21.68 seconds
Started Aug 05 05:09:28 PM PDT 24
Finished Aug 05 05:09:50 PM PDT 24
Peak memory 247900 kb
Host smart-9a115b4c-5fea-45a2-8aee-86a6181403f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11932
40856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1193240856
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.277241971
Short name T213
Test name
Test status
Simulation time 78559426260 ps
CPU time 2016.15 seconds
Started Aug 05 05:09:16 PM PDT 24
Finished Aug 05 05:42:52 PM PDT 24
Peak memory 272216 kb
Host smart-3e43f1cc-c6cb-4cd1-8992-c71758843671
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277241971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.277241971
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2113655686
Short name T573
Test name
Test status
Simulation time 47783004165 ps
CPU time 1245.51 seconds
Started Aug 05 05:09:16 PM PDT 24
Finished Aug 05 05:30:02 PM PDT 24
Peak memory 265808 kb
Host smart-81f25ccb-7713-4744-bd81-f3a6816d2332
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113655686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2113655686
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1340695073
Short name T548
Test name
Test status
Simulation time 2279404711 ps
CPU time 64.22 seconds
Started Aug 05 05:09:26 PM PDT 24
Finished Aug 05 05:10:30 PM PDT 24
Peak memory 248440 kb
Host smart-26c59136-62b4-4ee8-835a-f9ae5b7d0e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13406
95073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1340695073
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2317240147
Short name T629
Test name
Test status
Simulation time 90662412 ps
CPU time 9.52 seconds
Started Aug 05 05:09:21 PM PDT 24
Finished Aug 05 05:09:31 PM PDT 24
Peak memory 247736 kb
Host smart-563601cf-a21d-4c27-9ee1-794f2feb934c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23172
40147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2317240147
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3033273154
Short name T606
Test name
Test status
Simulation time 1409167340 ps
CPU time 41.19 seconds
Started Aug 05 05:09:14 PM PDT 24
Finished Aug 05 05:09:55 PM PDT 24
Peak memory 247844 kb
Host smart-c9324722-795f-47e5-9d8f-7cf12c3c4c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30332
73154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3033273154
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3817451267
Short name T451
Test name
Test status
Simulation time 4589452063 ps
CPU time 32.53 seconds
Started Aug 05 05:09:12 PM PDT 24
Finished Aug 05 05:09:45 PM PDT 24
Peak memory 248880 kb
Host smart-c24e39d2-31d4-469b-8441-1a67a3f8ec20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38174
51267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3817451267
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2851987519
Short name T415
Test name
Test status
Simulation time 56052991150 ps
CPU time 1048.57 seconds
Started Aug 05 05:09:16 PM PDT 24
Finished Aug 05 05:26:45 PM PDT 24
Peak memory 272792 kb
Host smart-faa0dbf6-dfd4-44d6-b2bc-87d587143cd5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851987519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2851987519
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.528656111
Short name T193
Test name
Test status
Simulation time 62766538 ps
CPU time 3 seconds
Started Aug 05 05:09:28 PM PDT 24
Finished Aug 05 05:09:31 PM PDT 24
Peak memory 248512 kb
Host smart-67c87116-c20a-4ccf-80d6-ace5dc4a1f2f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=528656111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.528656111
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1470399282
Short name T63
Test name
Test status
Simulation time 236810582786 ps
CPU time 3499.36 seconds
Started Aug 05 05:09:15 PM PDT 24
Finished Aug 05 06:07:35 PM PDT 24
Peak memory 289104 kb
Host smart-a3632b12-d18d-472b-b0f3-f44f08375285
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470399282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1470399282
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.713635464
Short name T348
Test name
Test status
Simulation time 4498947887 ps
CPU time 46.18 seconds
Started Aug 05 05:09:18 PM PDT 24
Finished Aug 05 05:10:04 PM PDT 24
Peak memory 248396 kb
Host smart-14971bfa-e465-491b-aa84-f2322c2807a0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=713635464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.713635464
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.4168322622
Short name T220
Test name
Test status
Simulation time 268046202 ps
CPU time 16.96 seconds
Started Aug 05 05:09:21 PM PDT 24
Finished Aug 05 05:09:38 PM PDT 24
Peak memory 247844 kb
Host smart-84688ee2-806b-47e6-b656-4e5f03ef99e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41683
22622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.4168322622
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1689899351
Short name T554
Test name
Test status
Simulation time 964152867 ps
CPU time 30.55 seconds
Started Aug 05 05:09:16 PM PDT 24
Finished Aug 05 05:09:47 PM PDT 24
Peak memory 248196 kb
Host smart-8f85c7c7-4ef2-4f7e-8e15-d74555faabeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16898
99351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1689899351
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.4264874132
Short name T480
Test name
Test status
Simulation time 57194327542 ps
CPU time 1279.91 seconds
Started Aug 05 05:09:24 PM PDT 24
Finished Aug 05 05:30:44 PM PDT 24
Peak memory 288016 kb
Host smart-72468b31-5bc4-4012-96dc-05a4ade9bda4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264874132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.4264874132
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1737951044
Short name T531
Test name
Test status
Simulation time 82310923391 ps
CPU time 1354.67 seconds
Started Aug 05 05:09:18 PM PDT 24
Finished Aug 05 05:31:53 PM PDT 24
Peak memory 272968 kb
Host smart-66dfa21c-7566-4ff2-b03d-02afc4b0041b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737951044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1737951044
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.957382506
Short name T357
Test name
Test status
Simulation time 364119359 ps
CPU time 28.5 seconds
Started Aug 05 05:09:17 PM PDT 24
Finished Aug 05 05:09:46 PM PDT 24
Peak memory 256312 kb
Host smart-ce59d522-b430-4313-9a57-5d595ca376d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95738
2506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.957382506
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.632306221
Short name T88
Test name
Test status
Simulation time 531755913 ps
CPU time 9.77 seconds
Started Aug 05 05:09:23 PM PDT 24
Finished Aug 05 05:09:33 PM PDT 24
Peak memory 253268 kb
Host smart-d192e751-0fad-412d-8ef5-24a6292c8910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63230
6221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.632306221
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3952262804
Short name T258
Test name
Test status
Simulation time 1604034018 ps
CPU time 24.8 seconds
Started Aug 05 05:09:41 PM PDT 24
Finished Aug 05 05:10:06 PM PDT 24
Peak memory 255832 kb
Host smart-f0863415-767d-4489-982b-e6e2cf4057a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39522
62804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3952262804
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1762598217
Short name T12
Test name
Test status
Simulation time 1190052394 ps
CPU time 23.89 seconds
Started Aug 05 05:09:20 PM PDT 24
Finished Aug 05 05:09:44 PM PDT 24
Peak memory 256276 kb
Host smart-e476ba93-fbc2-43b9-8d26-4939ae647078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17625
98217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1762598217
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3903163127
Short name T406
Test name
Test status
Simulation time 29126384306 ps
CPU time 1236.08 seconds
Started Aug 05 05:09:15 PM PDT 24
Finished Aug 05 05:29:51 PM PDT 24
Peak memory 281068 kb
Host smart-4b34bfde-1b75-4658-9053-7fd5dfc6f063
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903163127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3903163127
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.4278947590
Short name T187
Test name
Test status
Simulation time 17835757 ps
CPU time 2.76 seconds
Started Aug 05 05:09:29 PM PDT 24
Finished Aug 05 05:09:32 PM PDT 24
Peak memory 248620 kb
Host smart-7584b91f-36af-4077-ab31-bf7f14edca01
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4278947590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.4278947590
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2772040402
Short name T396
Test name
Test status
Simulation time 195381339186 ps
CPU time 2757.12 seconds
Started Aug 05 05:09:17 PM PDT 24
Finished Aug 05 05:55:15 PM PDT 24
Peak memory 289284 kb
Host smart-8ea9863f-1df1-4290-a03d-376c4b9c0cd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772040402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2772040402
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3664923268
Short name T462
Test name
Test status
Simulation time 133524343 ps
CPU time 7.9 seconds
Started Aug 05 05:09:22 PM PDT 24
Finished Aug 05 05:09:30 PM PDT 24
Peak memory 248296 kb
Host smart-3456a607-9f73-4c84-bd97-467d0cce460e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3664923268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3664923268
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2095668437
Short name T389
Test name
Test status
Simulation time 10403763028 ps
CPU time 173.94 seconds
Started Aug 05 05:09:24 PM PDT 24
Finished Aug 05 05:12:18 PM PDT 24
Peak memory 256544 kb
Host smart-bd1c1634-7281-4224-9b31-37e16cb35074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20956
68437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2095668437
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1648199129
Short name T82
Test name
Test status
Simulation time 225431817 ps
CPU time 20.66 seconds
Started Aug 05 05:09:24 PM PDT 24
Finished Aug 05 05:09:45 PM PDT 24
Peak memory 248296 kb
Host smart-9074c377-f506-468f-a0e2-e2fba41ca208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16481
99129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1648199129
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3890326144
Short name T168
Test name
Test status
Simulation time 115843577287 ps
CPU time 1132.94 seconds
Started Aug 05 05:09:18 PM PDT 24
Finished Aug 05 05:28:11 PM PDT 24
Peak memory 283636 kb
Host smart-12237a58-b836-4e0a-9949-ef1ed72f38fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890326144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3890326144
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2749762011
Short name T275
Test name
Test status
Simulation time 43289479478 ps
CPU time 1103.49 seconds
Started Aug 05 05:09:16 PM PDT 24
Finished Aug 05 05:27:40 PM PDT 24
Peak memory 272512 kb
Host smart-3ddeb76f-18d4-48ed-afcd-f3c8e820733b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749762011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2749762011
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.27558300
Short name T397
Test name
Test status
Simulation time 3991678220 ps
CPU time 22.09 seconds
Started Aug 05 05:09:22 PM PDT 24
Finished Aug 05 05:09:44 PM PDT 24
Peak memory 256540 kb
Host smart-98173f8c-ae05-43e8-8843-247798092cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27558
300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.27558300
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3372978537
Short name T279
Test name
Test status
Simulation time 1181348424 ps
CPU time 12.95 seconds
Started Aug 05 05:09:36 PM PDT 24
Finished Aug 05 05:09:50 PM PDT 24
Peak memory 247864 kb
Host smart-48503979-0d0c-472b-8437-a5ed0c6dd83e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33729
78537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3372978537
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.4109956740
Short name T701
Test name
Test status
Simulation time 144513878 ps
CPU time 15.15 seconds
Started Aug 05 05:09:26 PM PDT 24
Finished Aug 05 05:09:41 PM PDT 24
Peak memory 247636 kb
Host smart-0b243c70-a580-4b59-a2a9-3f5c13b4e94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41099
56740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.4109956740
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.4031492876
Short name T369
Test name
Test status
Simulation time 2426157059 ps
CPU time 41.32 seconds
Started Aug 05 05:09:42 PM PDT 24
Finished Aug 05 05:10:24 PM PDT 24
Peak memory 256052 kb
Host smart-f4596c23-71a5-4a57-833d-023036c51942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40314
92876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.4031492876
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.80789323
Short name T377
Test name
Test status
Simulation time 20173575366 ps
CPU time 260.83 seconds
Started Aug 05 05:09:16 PM PDT 24
Finished Aug 05 05:13:37 PM PDT 24
Peak memory 256556 kb
Host smart-305dcf7b-17f8-48fc-950b-719017e0205a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80789323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_hand
ler_stress_all.80789323
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.243415312
Short name T192
Test name
Test status
Simulation time 56408036 ps
CPU time 2.8 seconds
Started Aug 05 05:09:21 PM PDT 24
Finished Aug 05 05:09:24 PM PDT 24
Peak memory 248592 kb
Host smart-6be7d323-5ccf-4c9d-8601-670b23cd26a9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=243415312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.243415312
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.772579078
Short name T221
Test name
Test status
Simulation time 6913180390 ps
CPU time 810.56 seconds
Started Aug 05 05:09:31 PM PDT 24
Finished Aug 05 05:23:02 PM PDT 24
Peak memory 272984 kb
Host smart-7f93a770-ad06-459d-8b41-02d8115c4a73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772579078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.772579078
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2730922818
Short name T632
Test name
Test status
Simulation time 311052514 ps
CPU time 15.14 seconds
Started Aug 05 05:09:25 PM PDT 24
Finished Aug 05 05:09:40 PM PDT 24
Peak memory 248340 kb
Host smart-401963e1-57a9-48a7-baac-7663f8e21c4d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2730922818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2730922818
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.4230902180
Short name T566
Test name
Test status
Simulation time 811987834 ps
CPU time 71.3 seconds
Started Aug 05 05:09:22 PM PDT 24
Finished Aug 05 05:10:33 PM PDT 24
Peak memory 256092 kb
Host smart-97422aad-7748-4975-88b9-65bae9b8f0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42309
02180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.4230902180
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3668296627
Short name T648
Test name
Test status
Simulation time 637236353 ps
CPU time 34.76 seconds
Started Aug 05 05:09:33 PM PDT 24
Finished Aug 05 05:10:08 PM PDT 24
Peak memory 248300 kb
Host smart-2c479693-56ae-48cd-8450-4d8d89510e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36682
96627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3668296627
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2141041531
Short name T97
Test name
Test status
Simulation time 97381341421 ps
CPU time 1554.14 seconds
Started Aug 05 05:09:44 PM PDT 24
Finished Aug 05 05:35:38 PM PDT 24
Peak memory 272304 kb
Host smart-f79d1629-4a02-4e0f-a8fd-a8544f5e91c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141041531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2141041531
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2559428485
Short name T431
Test name
Test status
Simulation time 67382652778 ps
CPU time 1417.57 seconds
Started Aug 05 05:09:15 PM PDT 24
Finished Aug 05 05:32:52 PM PDT 24
Peak memory 288244 kb
Host smart-1aeca28c-009f-425b-9e33-adf62e1adeef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559428485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2559428485
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1762423609
Short name T310
Test name
Test status
Simulation time 38857613384 ps
CPU time 417.67 seconds
Started Aug 05 05:09:16 PM PDT 24
Finished Aug 05 05:16:13 PM PDT 24
Peak memory 248340 kb
Host smart-dcfb20c7-5a9d-4039-97c3-33f54750ffcb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762423609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1762423609
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1558526169
Short name T439
Test name
Test status
Simulation time 2608694462 ps
CPU time 39.84 seconds
Started Aug 05 05:09:31 PM PDT 24
Finished Aug 05 05:10:11 PM PDT 24
Peak memory 255636 kb
Host smart-50ce8c57-7379-433e-a828-7bb2e83dc198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15585
26169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1558526169
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3956131242
Short name T50
Test name
Test status
Simulation time 1703524256 ps
CPU time 46.79 seconds
Started Aug 05 05:09:15 PM PDT 24
Finished Aug 05 05:10:02 PM PDT 24
Peak memory 256560 kb
Host smart-c7476ae0-e441-40b7-ae87-13b3330a77b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39561
31242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3956131242
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2015290537
Short name T428
Test name
Test status
Simulation time 50093752 ps
CPU time 4.56 seconds
Started Aug 05 05:09:17 PM PDT 24
Finished Aug 05 05:09:21 PM PDT 24
Peak memory 239628 kb
Host smart-e4c39d55-5cf2-438d-95c3-dedf4e2cdb76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20152
90537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2015290537
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1306451539
Short name T511
Test name
Test status
Simulation time 10142400711 ps
CPU time 53.5 seconds
Started Aug 05 05:09:25 PM PDT 24
Finished Aug 05 05:10:19 PM PDT 24
Peak memory 248292 kb
Host smart-aa351572-dd7f-4529-8f76-c82f2a4d759d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13064
51539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1306451539
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1728334713
Short name T551
Test name
Test status
Simulation time 15519325198 ps
CPU time 803.07 seconds
Started Aug 05 05:09:34 PM PDT 24
Finished Aug 05 05:22:57 PM PDT 24
Peak memory 272980 kb
Host smart-eb8f9478-53de-4f41-945d-b576a9d19de0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728334713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1728334713
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3685933262
Short name T189
Test name
Test status
Simulation time 48556385 ps
CPU time 3.87 seconds
Started Aug 05 05:09:38 PM PDT 24
Finished Aug 05 05:09:42 PM PDT 24
Peak memory 248584 kb
Host smart-2a152a81-23e4-42df-8c46-14a8e5c7e211
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3685933262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3685933262
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.897916316
Short name T441
Test name
Test status
Simulation time 187670450640 ps
CPU time 2866.42 seconds
Started Aug 05 05:09:44 PM PDT 24
Finished Aug 05 05:57:31 PM PDT 24
Peak memory 285112 kb
Host smart-72506c96-2069-44fa-9e35-3a32386ddbf6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897916316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.897916316
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.949710148
Short name T414
Test name
Test status
Simulation time 3771362932 ps
CPU time 39.19 seconds
Started Aug 05 05:09:35 PM PDT 24
Finished Aug 05 05:10:15 PM PDT 24
Peak memory 248344 kb
Host smart-a3fa0685-5d23-4267-9e89-8ba05884a707
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=949710148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.949710148
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.4037312086
Short name T489
Test name
Test status
Simulation time 13043364648 ps
CPU time 183.81 seconds
Started Aug 05 05:09:17 PM PDT 24
Finished Aug 05 05:12:21 PM PDT 24
Peak memory 256536 kb
Host smart-7cb50a49-ca2b-489c-b25a-4afe4d568ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40373
12086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.4037312086
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1634190046
Short name T624
Test name
Test status
Simulation time 6223973482 ps
CPU time 55.21 seconds
Started Aug 05 05:09:22 PM PDT 24
Finished Aug 05 05:10:17 PM PDT 24
Peak memory 248360 kb
Host smart-85ad1c92-2b9b-44c4-9467-7fda09c9e721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16341
90046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1634190046
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1183176653
Short name T327
Test name
Test status
Simulation time 37127504782 ps
CPU time 2372.17 seconds
Started Aug 05 05:09:28 PM PDT 24
Finished Aug 05 05:49:01 PM PDT 24
Peak memory 288692 kb
Host smart-7ca2d22f-c002-4802-9e19-91a5b5967f0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183176653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1183176653
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.4143948168
Short name T378
Test name
Test status
Simulation time 191445343264 ps
CPU time 2499.78 seconds
Started Aug 05 05:09:26 PM PDT 24
Finished Aug 05 05:51:06 PM PDT 24
Peak memory 288844 kb
Host smart-6df014aa-48c0-48dd-bfb6-bcb73faae962
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143948168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.4143948168
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3674502386
Short name T553
Test name
Test status
Simulation time 999412569 ps
CPU time 17.18 seconds
Started Aug 05 05:09:22 PM PDT 24
Finished Aug 05 05:09:39 PM PDT 24
Peak memory 255400 kb
Host smart-c805621f-ba2b-42e8-b421-262670b62153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36745
02386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3674502386
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2976665923
Short name T393
Test name
Test status
Simulation time 525380055 ps
CPU time 30.45 seconds
Started Aug 05 05:09:17 PM PDT 24
Finished Aug 05 05:09:48 PM PDT 24
Peak memory 255624 kb
Host smart-6a498166-e7ca-462f-9db2-9f919ab08a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29766
65923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2976665923
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3288655147
Short name T599
Test name
Test status
Simulation time 1113137312 ps
CPU time 38.13 seconds
Started Aug 05 05:09:26 PM PDT 24
Finished Aug 05 05:10:04 PM PDT 24
Peak memory 248208 kb
Host smart-93d744ee-b43a-4b12-85e5-1bcaa08df9dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32886
55147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3288655147
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1986973186
Short name T353
Test name
Test status
Simulation time 985759204 ps
CPU time 60.91 seconds
Started Aug 05 05:09:36 PM PDT 24
Finished Aug 05 05:10:37 PM PDT 24
Peak memory 256444 kb
Host smart-8a3b2fa5-f7e8-42a5-a90d-8e2ec4f5f3f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19869
73186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1986973186
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1681336654
Short name T517
Test name
Test status
Simulation time 85896249049 ps
CPU time 1917.56 seconds
Started Aug 05 05:09:27 PM PDT 24
Finished Aug 05 05:41:25 PM PDT 24
Peak memory 298340 kb
Host smart-09afcc47-a2f7-4b7d-a2ec-2ff315ea9213
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681336654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1681336654
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1258523277
Short name T199
Test name
Test status
Simulation time 161001997 ps
CPU time 3.67 seconds
Started Aug 05 05:08:52 PM PDT 24
Finished Aug 05 05:08:56 PM PDT 24
Peak memory 248608 kb
Host smart-026ea811-f151-47f0-9556-156417b1d57b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1258523277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1258523277
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1527676732
Short name T714
Test name
Test status
Simulation time 88533800319 ps
CPU time 2588.05 seconds
Started Aug 05 05:09:03 PM PDT 24
Finished Aug 05 05:52:11 PM PDT 24
Peak memory 287264 kb
Host smart-da60464d-43f3-45c7-8b4f-91e853ea168d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527676732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1527676732
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1571043536
Short name T663
Test name
Test status
Simulation time 1267159036 ps
CPU time 28.16 seconds
Started Aug 05 05:08:53 PM PDT 24
Finished Aug 05 05:09:21 PM PDT 24
Peak memory 248292 kb
Host smart-7ee3c53e-0465-42ad-898e-fd4785f17b82
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1571043536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1571043536
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3128313282
Short name T409
Test name
Test status
Simulation time 7480674081 ps
CPU time 86.32 seconds
Started Aug 05 05:08:52 PM PDT 24
Finished Aug 05 05:10:19 PM PDT 24
Peak memory 255796 kb
Host smart-f7c87da3-b386-4a22-8d79-dd5031220367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31283
13282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3128313282
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.575702346
Short name T507
Test name
Test status
Simulation time 1038703441 ps
CPU time 37.39 seconds
Started Aug 05 05:09:06 PM PDT 24
Finished Aug 05 05:09:43 PM PDT 24
Peak memory 256004 kb
Host smart-8366770a-1286-4e6e-8dd6-5228d10bf5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57570
2346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.575702346
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1163882413
Short name T569
Test name
Test status
Simulation time 104242421510 ps
CPU time 1409.67 seconds
Started Aug 05 05:09:11 PM PDT 24
Finished Aug 05 05:32:46 PM PDT 24
Peak memory 287096 kb
Host smart-838aea61-8e2d-481f-91fa-2f64287cbde6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163882413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1163882413
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2258094664
Short name T683
Test name
Test status
Simulation time 97656266271 ps
CPU time 1444.5 seconds
Started Aug 05 05:08:50 PM PDT 24
Finished Aug 05 05:32:55 PM PDT 24
Peak memory 271592 kb
Host smart-5d757cfb-a1c5-4dee-982c-bce161a5d71d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258094664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2258094664
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2458255747
Short name T698
Test name
Test status
Simulation time 4404870232 ps
CPU time 178.99 seconds
Started Aug 05 05:08:59 PM PDT 24
Finished Aug 05 05:11:58 PM PDT 24
Peak memory 248572 kb
Host smart-27e29c68-1343-4fa2-aa6e-5a5f95910c1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458255747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2458255747
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2309878187
Short name T351
Test name
Test status
Simulation time 3503033612 ps
CPU time 53.47 seconds
Started Aug 05 05:09:09 PM PDT 24
Finished Aug 05 05:10:02 PM PDT 24
Peak memory 256512 kb
Host smart-378cbdd5-8604-4459-968f-b42d804116cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23098
78187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2309878187
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2384169319
Short name T633
Test name
Test status
Simulation time 757937008 ps
CPU time 50.67 seconds
Started Aug 05 05:08:54 PM PDT 24
Finished Aug 05 05:09:45 PM PDT 24
Peak memory 256024 kb
Host smart-115d74c3-b0c3-44a1-b1c4-632ca6d4cb2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23841
69319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2384169319
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1456967257
Short name T424
Test name
Test status
Simulation time 84377368 ps
CPU time 10.46 seconds
Started Aug 05 05:09:00 PM PDT 24
Finished Aug 05 05:09:11 PM PDT 24
Peak memory 247812 kb
Host smart-3576c8b3-e649-4815-8669-6231ae1baada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14569
67257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1456967257
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2288472385
Short name T395
Test name
Test status
Simulation time 2244316167 ps
CPU time 24.84 seconds
Started Aug 05 05:09:05 PM PDT 24
Finished Aug 05 05:09:30 PM PDT 24
Peak memory 248432 kb
Host smart-62c47bea-4ca9-41e2-9eb8-9b6f45626fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22884
72385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2288472385
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2818712450
Short name T447
Test name
Test status
Simulation time 4344806019 ps
CPU time 74.34 seconds
Started Aug 05 05:09:07 PM PDT 24
Finished Aug 05 05:10:22 PM PDT 24
Peak memory 256568 kb
Host smart-6f1cc3f3-d778-44cc-a34f-cd19d2005d97
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818712450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2818712450
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.3179670619
Short name T296
Test name
Test status
Simulation time 27579192963 ps
CPU time 2036.78 seconds
Started Aug 05 05:09:05 PM PDT 24
Finished Aug 05 05:43:02 PM PDT 24
Peak memory 305516 kb
Host smart-55ab2b24-ad30-4b52-bf5e-0b40cabb5c5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179670619 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.3179670619
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3144245953
Short name T608
Test name
Test status
Simulation time 77222564401 ps
CPU time 1059 seconds
Started Aug 05 05:09:43 PM PDT 24
Finished Aug 05 05:27:22 PM PDT 24
Peak memory 272964 kb
Host smart-8f05145c-23b7-4217-a251-947b0216ed06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144245953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3144245953
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.833840106
Short name T42
Test name
Test status
Simulation time 2747874840 ps
CPU time 171.87 seconds
Started Aug 05 05:09:29 PM PDT 24
Finished Aug 05 05:12:21 PM PDT 24
Peak memory 256476 kb
Host smart-04206769-3ba9-48a0-a90c-ba0bfccc5a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83384
0106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.833840106
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.2378398878
Short name T84
Test name
Test status
Simulation time 1861695960 ps
CPU time 40.15 seconds
Started Aug 05 05:09:31 PM PDT 24
Finished Aug 05 05:10:12 PM PDT 24
Peak memory 247776 kb
Host smart-405388e6-2896-4c90-9485-4fa85c5e08a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23783
98878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2378398878
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.164902099
Short name T666
Test name
Test status
Simulation time 29047950078 ps
CPU time 771.79 seconds
Started Aug 05 05:09:26 PM PDT 24
Finished Aug 05 05:22:18 PM PDT 24
Peak memory 272208 kb
Host smart-9396c7dc-b189-4c75-9060-387f26352708
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164902099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.164902099
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1174224966
Short name T402
Test name
Test status
Simulation time 50427280772 ps
CPU time 2700.55 seconds
Started Aug 05 05:09:26 PM PDT 24
Finished Aug 05 05:54:27 PM PDT 24
Peak memory 281184 kb
Host smart-a53d5a8c-3580-40b7-a57a-37b925fdf670
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174224966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1174224966
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3422006513
Short name T305
Test name
Test status
Simulation time 55821364799 ps
CPU time 562.63 seconds
Started Aug 05 05:09:26 PM PDT 24
Finished Aug 05 05:18:48 PM PDT 24
Peak memory 248336 kb
Host smart-54f77601-0c86-490b-a6a0-3764e22feb30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422006513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3422006513
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.921795567
Short name T405
Test name
Test status
Simulation time 260985876 ps
CPU time 8.26 seconds
Started Aug 05 05:09:30 PM PDT 24
Finished Aug 05 05:09:38 PM PDT 24
Peak memory 253476 kb
Host smart-129074c2-27cc-4a52-a98b-b7829d822547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92179
5567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.921795567
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3956844050
Short name T367
Test name
Test status
Simulation time 390148604 ps
CPU time 32.35 seconds
Started Aug 05 05:09:29 PM PDT 24
Finished Aug 05 05:10:02 PM PDT 24
Peak memory 255712 kb
Host smart-50e55808-da30-4cbc-a274-74931331afa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39568
44050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3956844050
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1242925870
Short name T58
Test name
Test status
Simulation time 810613830 ps
CPU time 52.67 seconds
Started Aug 05 05:09:26 PM PDT 24
Finished Aug 05 05:10:19 PM PDT 24
Peak memory 248056 kb
Host smart-9934ac96-7bd8-4023-aa6c-501931da86c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12429
25870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1242925870
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1836455860
Short name T370
Test name
Test status
Simulation time 374566957 ps
CPU time 34.02 seconds
Started Aug 05 05:09:27 PM PDT 24
Finished Aug 05 05:10:01 PM PDT 24
Peak memory 256504 kb
Host smart-0f27c6b4-5a1a-48fb-94ad-0094308f1345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18364
55860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1836455860
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3297594495
Short name T688
Test name
Test status
Simulation time 7968569820 ps
CPU time 76.05 seconds
Started Aug 05 05:09:42 PM PDT 24
Finished Aug 05 05:10:58 PM PDT 24
Peak memory 256496 kb
Host smart-cd9f1bfa-7fb3-4246-8141-c91d7a1a20ca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297594495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3297594495
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1466926817
Short name T659
Test name
Test status
Simulation time 60047126433 ps
CPU time 1144.05 seconds
Started Aug 05 05:09:25 PM PDT 24
Finished Aug 05 05:28:29 PM PDT 24
Peak memory 283936 kb
Host smart-89bf0a6c-4189-4184-8d8d-36214faee70d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466926817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1466926817
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.4236317565
Short name T529
Test name
Test status
Simulation time 897892804 ps
CPU time 34.51 seconds
Started Aug 05 05:09:32 PM PDT 24
Finished Aug 05 05:10:07 PM PDT 24
Peak memory 255604 kb
Host smart-baa06ff9-9563-44cf-8ee1-4f415c20fbc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42363
17565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.4236317565
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3123887297
Short name T471
Test name
Test status
Simulation time 551447175 ps
CPU time 41 seconds
Started Aug 05 05:09:28 PM PDT 24
Finished Aug 05 05:10:10 PM PDT 24
Peak memory 247784 kb
Host smart-a0187cc3-187f-4f18-8e69-14ff66d9b721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31238
87297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3123887297
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.545616170
Short name T334
Test name
Test status
Simulation time 631280296820 ps
CPU time 2650.25 seconds
Started Aug 05 05:09:30 PM PDT 24
Finished Aug 05 05:53:40 PM PDT 24
Peak memory 288248 kb
Host smart-ee641491-bd13-4192-bc43-6917d5ccfeb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545616170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.545616170
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2034102418
Short name T417
Test name
Test status
Simulation time 60842133316 ps
CPU time 2128.18 seconds
Started Aug 05 05:09:45 PM PDT 24
Finished Aug 05 05:45:13 PM PDT 24
Peak memory 273048 kb
Host smart-9e09fe63-52e6-47ad-b81f-dd36eac3fa33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034102418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2034102418
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3204745311
Short name T307
Test name
Test status
Simulation time 16087194147 ps
CPU time 334.96 seconds
Started Aug 05 05:09:44 PM PDT 24
Finished Aug 05 05:15:20 PM PDT 24
Peak memory 248376 kb
Host smart-3b1f25ea-68b5-415e-a3e6-c54c1545ab99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204745311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3204745311
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3997807030
Short name T379
Test name
Test status
Simulation time 3220786499 ps
CPU time 14.64 seconds
Started Aug 05 05:09:29 PM PDT 24
Finished Aug 05 05:09:43 PM PDT 24
Peak memory 256476 kb
Host smart-351811a7-90d0-4c14-9252-ed8fe38b9c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39978
07030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3997807030
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3910717583
Short name T365
Test name
Test status
Simulation time 1174244718 ps
CPU time 27.9 seconds
Started Aug 05 05:09:27 PM PDT 24
Finished Aug 05 05:09:55 PM PDT 24
Peak memory 255896 kb
Host smart-e2284562-805e-4946-addf-7ef5acad2c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39107
17583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3910717583
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.809685800
Short name T260
Test name
Test status
Simulation time 3059971813 ps
CPU time 18.94 seconds
Started Aug 05 05:09:30 PM PDT 24
Finished Aug 05 05:09:49 PM PDT 24
Peak memory 247908 kb
Host smart-741d8a2c-77a9-4b38-880f-92535c96e09e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80968
5800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.809685800
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3275908479
Short name T440
Test name
Test status
Simulation time 85784822 ps
CPU time 11.61 seconds
Started Aug 05 05:09:31 PM PDT 24
Finished Aug 05 05:09:42 PM PDT 24
Peak memory 255452 kb
Host smart-d7d3cfba-f35f-4f2a-82b2-762de9c1c458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32759
08479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3275908479
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.452042851
Short name T239
Test name
Test status
Simulation time 48617563004 ps
CPU time 2794.69 seconds
Started Aug 05 05:09:34 PM PDT 24
Finished Aug 05 05:56:09 PM PDT 24
Peak memory 281180 kb
Host smart-9ed7e27e-15f0-4f86-aec8-09261b9c596a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452042851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_han
dler_stress_all.452042851
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.963653331
Short name T255
Test name
Test status
Simulation time 157959717592 ps
CPU time 4884.9 seconds
Started Aug 05 05:09:37 PM PDT 24
Finished Aug 05 06:31:03 PM PDT 24
Peak memory 301172 kb
Host smart-f4734733-c72e-4317-8918-ed8539a9160d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963653331 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.963653331
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3375606179
Short name T616
Test name
Test status
Simulation time 17802781141 ps
CPU time 1021.37 seconds
Started Aug 05 05:09:45 PM PDT 24
Finished Aug 05 05:26:47 PM PDT 24
Peak memory 289088 kb
Host smart-720c7dcd-fe4f-4fe6-856a-4ac14a1bfe71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375606179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3375606179
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2224878600
Short name T605
Test name
Test status
Simulation time 453685876 ps
CPU time 39.29 seconds
Started Aug 05 05:09:34 PM PDT 24
Finished Aug 05 05:10:13 PM PDT 24
Peak memory 256492 kb
Host smart-5ba73cdb-552a-4eb6-92ff-133f83877288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22248
78600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2224878600
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.4255551407
Short name T472
Test name
Test status
Simulation time 420456152 ps
CPU time 8.3 seconds
Started Aug 05 05:09:29 PM PDT 24
Finished Aug 05 05:09:38 PM PDT 24
Peak memory 253288 kb
Host smart-8645acb3-6a6c-41c3-90dc-a5f0c31ecf91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42555
51407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.4255551407
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2696557111
Short name T613
Test name
Test status
Simulation time 76738834160 ps
CPU time 2397.33 seconds
Started Aug 05 05:09:31 PM PDT 24
Finished Aug 05 05:49:29 PM PDT 24
Peak memory 288708 kb
Host smart-2aa2c9f2-9035-4228-aea9-39e3f0d175a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696557111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2696557111
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1363636239
Short name T501
Test name
Test status
Simulation time 94280069601 ps
CPU time 1287.04 seconds
Started Aug 05 05:09:26 PM PDT 24
Finished Aug 05 05:30:53 PM PDT 24
Peak memory 265768 kb
Host smart-c3a4dded-7857-44cc-9d59-8108695dc58f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363636239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1363636239
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1546059299
Short name T308
Test name
Test status
Simulation time 14152283479 ps
CPU time 168.46 seconds
Started Aug 05 05:09:28 PM PDT 24
Finished Aug 05 05:12:17 PM PDT 24
Peak memory 248372 kb
Host smart-d432c93a-fc5a-4516-83c6-3ba1456135d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546059299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1546059299
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.993276978
Short name T482
Test name
Test status
Simulation time 1201077952 ps
CPU time 20.69 seconds
Started Aug 05 05:09:44 PM PDT 24
Finished Aug 05 05:10:05 PM PDT 24
Peak memory 255860 kb
Host smart-0dd6cf3a-c50f-44db-b01e-c463141f2fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99327
6978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.993276978
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.4132862960
Short name T102
Test name
Test status
Simulation time 531242714 ps
CPU time 29.86 seconds
Started Aug 05 05:09:39 PM PDT 24
Finished Aug 05 05:10:09 PM PDT 24
Peak memory 247636 kb
Host smart-83ed3b21-302f-4716-abef-7b3bbb5cf43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41328
62960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.4132862960
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3521956245
Short name T349
Test name
Test status
Simulation time 494812374 ps
CPU time 14.65 seconds
Started Aug 05 05:09:29 PM PDT 24
Finished Aug 05 05:09:44 PM PDT 24
Peak memory 256208 kb
Host smart-a83f780e-cc2b-4b16-b4b8-d5a53328fb61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35219
56245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3521956245
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.168660140
Short name T171
Test name
Test status
Simulation time 84991150659 ps
CPU time 1782.69 seconds
Started Aug 05 05:09:37 PM PDT 24
Finished Aug 05 05:39:20 PM PDT 24
Peak memory 303176 kb
Host smart-46aefff8-7898-4838-83c0-02f7657cf8a1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168660140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.168660140
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.368061541
Short name T269
Test name
Test status
Simulation time 150135070218 ps
CPU time 1185.48 seconds
Started Aug 05 05:09:30 PM PDT 24
Finished Aug 05 05:29:16 PM PDT 24
Peak memory 287764 kb
Host smart-6c7d7de0-49ba-4c86-9ae4-db1cd3beb9df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368061541 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.368061541
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2637280915
Short name T292
Test name
Test status
Simulation time 26103954850 ps
CPU time 1595.24 seconds
Started Aug 05 05:09:36 PM PDT 24
Finished Aug 05 05:36:11 PM PDT 24
Peak memory 272488 kb
Host smart-3d09c50f-7804-4343-b38e-26fcb5598dd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637280915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2637280915
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3561474091
Short name T649
Test name
Test status
Simulation time 47150185 ps
CPU time 4.64 seconds
Started Aug 05 05:09:29 PM PDT 24
Finished Aug 05 05:09:33 PM PDT 24
Peak memory 239696 kb
Host smart-bc202edc-cc57-4a49-ac28-fe7b1b3fd532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35614
74091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3561474091
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3099745047
Short name T637
Test name
Test status
Simulation time 295874816 ps
CPU time 18.68 seconds
Started Aug 05 05:09:32 PM PDT 24
Finished Aug 05 05:09:51 PM PDT 24
Peak memory 254628 kb
Host smart-184bc62d-b65b-4ba8-bce7-e5f2450331ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30997
45047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3099745047
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2994044732
Short name T374
Test name
Test status
Simulation time 143858404431 ps
CPU time 2174.9 seconds
Started Aug 05 05:09:27 PM PDT 24
Finished Aug 05 05:45:42 PM PDT 24
Peak memory 288708 kb
Host smart-82480bac-c9e1-460e-8f33-d73868124e6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994044732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2994044732
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2923889115
Short name T710
Test name
Test status
Simulation time 3123871316 ps
CPU time 133.95 seconds
Started Aug 05 05:09:36 PM PDT 24
Finished Aug 05 05:11:50 PM PDT 24
Peak memory 248360 kb
Host smart-b60f4a6d-8dce-40fb-8812-f23d8436c334
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923889115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2923889115
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2059016492
Short name T204
Test name
Test status
Simulation time 135357633 ps
CPU time 11.32 seconds
Started Aug 05 05:09:34 PM PDT 24
Finished Aug 05 05:09:46 PM PDT 24
Peak memory 256188 kb
Host smart-fff2ffce-97ba-4445-8107-794fa69a56f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20590
16492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2059016492
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3544926625
Short name T570
Test name
Test status
Simulation time 194294916 ps
CPU time 4.03 seconds
Started Aug 05 05:09:43 PM PDT 24
Finished Aug 05 05:09:48 PM PDT 24
Peak memory 239700 kb
Host smart-174e9486-04b9-4abd-8ca2-381d55f3ba8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35449
26625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3544926625
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3351186662
Short name T508
Test name
Test status
Simulation time 5837805482 ps
CPU time 49.14 seconds
Started Aug 05 05:09:32 PM PDT 24
Finished Aug 05 05:10:21 PM PDT 24
Peak memory 255560 kb
Host smart-c39086fc-27d5-4c83-ad93-a8575532c9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33511
86662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3351186662
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.383749570
Short name T280
Test name
Test status
Simulation time 540314041 ps
CPU time 22.71 seconds
Started Aug 05 05:09:41 PM PDT 24
Finished Aug 05 05:10:03 PM PDT 24
Peak memory 256548 kb
Host smart-2d1582e0-d509-436e-bbc0-fab6a3460c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38374
9570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.383749570
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2273468550
Short name T654
Test name
Test status
Simulation time 43939090817 ps
CPU time 1567.74 seconds
Started Aug 05 05:09:31 PM PDT 24
Finished Aug 05 05:35:39 PM PDT 24
Peak memory 288984 kb
Host smart-f89cb44f-1a83-4db8-aa16-161eed0dc547
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273468550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2273468550
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2519453872
Short name T715
Test name
Test status
Simulation time 43207246875 ps
CPU time 2509 seconds
Started Aug 05 05:09:48 PM PDT 24
Finished Aug 05 05:51:38 PM PDT 24
Peak memory 289032 kb
Host smart-8680f6eb-4319-4db4-b84b-9e2c8a4e8e84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519453872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2519453872
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2634778099
Short name T383
Test name
Test status
Simulation time 774318916 ps
CPU time 35.98 seconds
Started Aug 05 05:09:44 PM PDT 24
Finished Aug 05 05:10:20 PM PDT 24
Peak memory 256004 kb
Host smart-5c2a7336-b561-4e24-8931-1c1cad15c0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26347
78099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2634778099
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2288366332
Short name T537
Test name
Test status
Simulation time 136637642 ps
CPU time 9.12 seconds
Started Aug 05 05:09:32 PM PDT 24
Finished Aug 05 05:09:41 PM PDT 24
Peak memory 248192 kb
Host smart-06f6eb02-d373-4bff-a292-60f1e8eee0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22883
66332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2288366332
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2908678892
Short name T404
Test name
Test status
Simulation time 117968142144 ps
CPU time 3182.23 seconds
Started Aug 05 05:09:29 PM PDT 24
Finished Aug 05 06:02:32 PM PDT 24
Peak memory 289256 kb
Host smart-3ec63648-d306-4b27-a8b6-e2c2ddeb65b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908678892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2908678892
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.791846
Short name T652
Test name
Test status
Simulation time 15597111295 ps
CPU time 585.6 seconds
Started Aug 05 05:09:42 PM PDT 24
Finished Aug 05 05:19:28 PM PDT 24
Peak memory 247212 kb
Host smart-34da3e03-9dc3-4a9f-9749-293163ea063f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.791846
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3547818121
Short name T386
Test name
Test status
Simulation time 793944736 ps
CPU time 12.6 seconds
Started Aug 05 05:09:29 PM PDT 24
Finished Aug 05 05:09:42 PM PDT 24
Peak memory 248272 kb
Host smart-e9bd4b1a-0713-43c8-939a-15a7b4b19996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35478
18121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3547818121
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2545394545
Short name T455
Test name
Test status
Simulation time 153712160 ps
CPU time 15.45 seconds
Started Aug 05 05:09:39 PM PDT 24
Finished Aug 05 05:09:54 PM PDT 24
Peak memory 255656 kb
Host smart-96741729-df6f-4f8c-adbe-ec85d230a4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25453
94545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2545394545
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2717657497
Short name T526
Test name
Test status
Simulation time 84392809 ps
CPU time 8.9 seconds
Started Aug 05 05:09:48 PM PDT 24
Finished Aug 05 05:09:57 PM PDT 24
Peak memory 248912 kb
Host smart-95d61e13-62c5-43e6-a1a6-6e4f85af3e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27176
57497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2717657497
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2572979068
Short name T412
Test name
Test status
Simulation time 30594240 ps
CPU time 3 seconds
Started Aug 05 05:09:39 PM PDT 24
Finished Aug 05 05:09:43 PM PDT 24
Peak memory 250628 kb
Host smart-aaddb4b2-9129-4243-af87-87077611d92a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25729
79068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2572979068
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3066989534
Short name T665
Test name
Test status
Simulation time 2838223227 ps
CPU time 213.9 seconds
Started Aug 05 05:09:39 PM PDT 24
Finished Aug 05 05:13:13 PM PDT 24
Peak memory 254920 kb
Host smart-5c146f5e-856d-42c7-bb9c-4e1ee52eeeca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066989534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3066989534
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3184649583
Short name T384
Test name
Test status
Simulation time 12120945661 ps
CPU time 1314.74 seconds
Started Aug 05 05:09:40 PM PDT 24
Finished Aug 05 05:31:35 PM PDT 24
Peak memory 289300 kb
Host smart-7b35f9a6-c192-46a9-9620-a9a82c87773a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184649583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3184649583
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2995743926
Short name T236
Test name
Test status
Simulation time 2109261015 ps
CPU time 128.17 seconds
Started Aug 05 05:09:34 PM PDT 24
Finished Aug 05 05:11:43 PM PDT 24
Peak memory 256412 kb
Host smart-4a579336-b586-4241-aadf-1882c775a877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29957
43926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2995743926
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2112306912
Short name T635
Test name
Test status
Simulation time 689268678 ps
CPU time 40.69 seconds
Started Aug 05 05:09:34 PM PDT 24
Finished Aug 05 05:10:15 PM PDT 24
Peak memory 248196 kb
Host smart-df0e9478-241c-43fa-89c6-f558c928467f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21123
06912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2112306912
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.491738314
Short name T512
Test name
Test status
Simulation time 27342366701 ps
CPU time 1908.92 seconds
Started Aug 05 05:09:45 PM PDT 24
Finished Aug 05 05:41:35 PM PDT 24
Peak memory 283480 kb
Host smart-a26d33e8-efbc-44f4-84e1-385fe097a454
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491738314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.491738314
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.122686440
Short name T582
Test name
Test status
Simulation time 299676407 ps
CPU time 28.24 seconds
Started Aug 05 05:09:42 PM PDT 24
Finished Aug 05 05:10:11 PM PDT 24
Peak memory 248308 kb
Host smart-761ce41c-9db8-46c7-b47d-8059679e7da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12268
6440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.122686440
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2055035929
Short name T442
Test name
Test status
Simulation time 1628106605 ps
CPU time 53.99 seconds
Started Aug 05 05:09:39 PM PDT 24
Finished Aug 05 05:10:33 PM PDT 24
Peak memory 255880 kb
Host smart-3f3861d5-e597-48d1-97a9-72190cb66547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20550
35929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2055035929
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3716706529
Short name T596
Test name
Test status
Simulation time 3517561848 ps
CPU time 53.11 seconds
Started Aug 05 05:09:44 PM PDT 24
Finished Aug 05 05:10:37 PM PDT 24
Peak memory 248148 kb
Host smart-4199a5e1-1441-4231-a529-4786e22a358a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37167
06529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3716706529
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.555761483
Short name T167
Test name
Test status
Simulation time 233945928 ps
CPU time 8.99 seconds
Started Aug 05 05:09:42 PM PDT 24
Finished Aug 05 05:09:52 PM PDT 24
Peak memory 248560 kb
Host smart-142a8bfd-032f-456e-b60d-3591b9b9a87b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55576
1483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.555761483
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3818382081
Short name T578
Test name
Test status
Simulation time 121067075306 ps
CPU time 2296.4 seconds
Started Aug 05 05:09:43 PM PDT 24
Finished Aug 05 05:48:00 PM PDT 24
Peak memory 289048 kb
Host smart-c879e122-47bc-40cd-9c11-18a52758c50e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818382081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3818382081
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.1190013216
Short name T230
Test name
Test status
Simulation time 81132249522 ps
CPU time 4800.78 seconds
Started Aug 05 05:09:46 PM PDT 24
Finished Aug 05 06:29:47 PM PDT 24
Peak memory 289068 kb
Host smart-92c181b2-42b7-42e8-b97b-1b90cf0535b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190013216 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.1190013216
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1197993551
Short name T713
Test name
Test status
Simulation time 231233971325 ps
CPU time 1462.57 seconds
Started Aug 05 05:09:48 PM PDT 24
Finished Aug 05 05:34:11 PM PDT 24
Peak memory 272880 kb
Host smart-bb9ed9b4-869b-4856-900e-61b81f94c769
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197993551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1197993551
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3224678176
Short name T670
Test name
Test status
Simulation time 14693165944 ps
CPU time 180.89 seconds
Started Aug 05 05:09:39 PM PDT 24
Finished Aug 05 05:12:40 PM PDT 24
Peak memory 255932 kb
Host smart-5546bd06-928e-4a2a-ab53-0bcdc50b54d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32246
78176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3224678176
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.999612245
Short name T622
Test name
Test status
Simulation time 197489838 ps
CPU time 12.32 seconds
Started Aug 05 05:09:45 PM PDT 24
Finished Aug 05 05:09:57 PM PDT 24
Peak memory 248360 kb
Host smart-19e73d6e-e149-4d7a-83ad-5ad184f4407a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99961
2245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.999612245
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.474466224
Short name T332
Test name
Test status
Simulation time 11191598369 ps
CPU time 906.11 seconds
Started Aug 05 05:09:43 PM PDT 24
Finished Aug 05 05:24:49 PM PDT 24
Peak memory 272356 kb
Host smart-f0e31fe7-833a-4bdf-b9fe-bdcd865630ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474466224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.474466224
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.468685887
Short name T209
Test name
Test status
Simulation time 8500310672 ps
CPU time 877.27 seconds
Started Aug 05 05:09:44 PM PDT 24
Finished Aug 05 05:24:22 PM PDT 24
Peak memory 272316 kb
Host smart-dc5c487b-fc83-40b1-b8cf-d3886f966e91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468685887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.468685887
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2220402252
Short name T309
Test name
Test status
Simulation time 14772843205 ps
CPU time 571.59 seconds
Started Aug 05 05:09:43 PM PDT 24
Finished Aug 05 05:19:15 PM PDT 24
Peak memory 248368 kb
Host smart-28689782-570d-41e5-8aa5-70e15faa906c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220402252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2220402252
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3497893591
Short name T500
Test name
Test status
Simulation time 1592617150 ps
CPU time 30.03 seconds
Started Aug 05 05:09:50 PM PDT 24
Finished Aug 05 05:10:20 PM PDT 24
Peak memory 255880 kb
Host smart-9cd78146-2f27-47f0-87d5-b2952337c92f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34978
93591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3497893591
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3199033321
Short name T34
Test name
Test status
Simulation time 426829006 ps
CPU time 13.07 seconds
Started Aug 05 05:09:36 PM PDT 24
Finished Aug 05 05:09:49 PM PDT 24
Peak memory 247588 kb
Host smart-268e907b-57f1-4d67-a0e8-572bc4c6b956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31990
33321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3199033321
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1415365384
Short name T64
Test name
Test status
Simulation time 177523479 ps
CPU time 25.95 seconds
Started Aug 05 05:09:45 PM PDT 24
Finished Aug 05 05:10:11 PM PDT 24
Peak memory 255764 kb
Host smart-fdbad023-cf8c-4f4a-904b-6946b6b19045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14153
65384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1415365384
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1850552795
Short name T206
Test name
Test status
Simulation time 847991804 ps
CPU time 46.26 seconds
Started Aug 05 05:09:36 PM PDT 24
Finished Aug 05 05:10:23 PM PDT 24
Peak memory 255812 kb
Host smart-5f1433a1-d838-4f4c-bcfe-e03f09e23956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18505
52795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1850552795
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2561733660
Short name T61
Test name
Test status
Simulation time 63732936886 ps
CPU time 1618.73 seconds
Started Aug 05 05:09:46 PM PDT 24
Finished Aug 05 05:36:45 PM PDT 24
Peak memory 289312 kb
Host smart-4cfda31f-d7c5-4914-8b18-b7cfb20370b4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561733660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2561733660
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.1715774243
Short name T229
Test name
Test status
Simulation time 21791189625 ps
CPU time 725.53 seconds
Started Aug 05 05:09:41 PM PDT 24
Finished Aug 05 05:21:46 PM PDT 24
Peak memory 273080 kb
Host smart-335f0437-655d-4e2d-8676-8a7073c29629
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715774243 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.1715774243
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2330325299
Short name T515
Test name
Test status
Simulation time 20948010658 ps
CPU time 1512.56 seconds
Started Aug 05 05:09:45 PM PDT 24
Finished Aug 05 05:34:59 PM PDT 24
Peak memory 288924 kb
Host smart-6bcb3027-1259-410d-98dc-a44a5d68e362
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330325299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2330325299
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3845512325
Short name T411
Test name
Test status
Simulation time 1901240665 ps
CPU time 138.94 seconds
Started Aug 05 05:09:49 PM PDT 24
Finished Aug 05 05:12:08 PM PDT 24
Peak memory 255696 kb
Host smart-f3bd0c0a-8bb0-40c2-b65a-bcd2c9913e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38455
12325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3845512325
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2552079521
Short name T591
Test name
Test status
Simulation time 2960019029 ps
CPU time 61 seconds
Started Aug 05 05:09:33 PM PDT 24
Finished Aug 05 05:10:34 PM PDT 24
Peak memory 256648 kb
Host smart-510897e8-a23c-478a-b0a7-7885815a9910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25520
79521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2552079521
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2319465923
Short name T335
Test name
Test status
Simulation time 36736904509 ps
CPU time 993.59 seconds
Started Aug 05 05:09:41 PM PDT 24
Finished Aug 05 05:26:15 PM PDT 24
Peak memory 272888 kb
Host smart-d7e8f9d5-5b85-4d21-b14a-66bcb2ad635c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319465923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2319465923
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.578020097
Short name T458
Test name
Test status
Simulation time 13811485590 ps
CPU time 1315.32 seconds
Started Aug 05 05:09:54 PM PDT 24
Finished Aug 05 05:31:50 PM PDT 24
Peak memory 281184 kb
Host smart-530fd98f-2d44-4447-8c60-e659647b3a48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578020097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.578020097
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1086917492
Short name T564
Test name
Test status
Simulation time 3142437472 ps
CPU time 127.94 seconds
Started Aug 05 05:09:45 PM PDT 24
Finished Aug 05 05:11:53 PM PDT 24
Peak memory 247952 kb
Host smart-08c5f549-6ff8-4204-a5eb-3492befcb675
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086917492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1086917492
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3048810154
Short name T504
Test name
Test status
Simulation time 3298620245 ps
CPU time 51.82 seconds
Started Aug 05 05:09:45 PM PDT 24
Finished Aug 05 05:10:37 PM PDT 24
Peak memory 255628 kb
Host smart-7de790c9-84eb-4cb8-b013-1d5500935c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30488
10154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3048810154
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3750467202
Short name T460
Test name
Test status
Simulation time 325485029 ps
CPU time 9.58 seconds
Started Aug 05 05:09:47 PM PDT 24
Finished Aug 05 05:09:57 PM PDT 24
Peak memory 254636 kb
Host smart-c09adaf4-b989-4d21-8f9f-1478a1688064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37504
67202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3750467202
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1043794881
Short name T464
Test name
Test status
Simulation time 920134997 ps
CPU time 54.19 seconds
Started Aug 05 05:09:44 PM PDT 24
Finished Aug 05 05:10:39 PM PDT 24
Peak memory 256456 kb
Host smart-9ff501e5-d251-45f1-85ae-5045c8a46664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10437
94881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1043794881
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.222700605
Short name T36
Test name
Test status
Simulation time 54086209426 ps
CPU time 3002.26 seconds
Started Aug 05 05:09:44 PM PDT 24
Finished Aug 05 05:59:46 PM PDT 24
Peak memory 289072 kb
Host smart-a7611d9b-e0c9-4ffd-a04c-50faa1d6bbff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222700605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.222700605
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2474982015
Short name T297
Test name
Test status
Simulation time 161413904245 ps
CPU time 2298.68 seconds
Started Aug 05 05:09:50 PM PDT 24
Finished Aug 05 05:48:09 PM PDT 24
Peak memory 284392 kb
Host smart-4021ecb5-309f-48b8-9750-6c13f6b77e91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474982015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2474982015
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.663818178
Short name T495
Test name
Test status
Simulation time 5263422459 ps
CPU time 264.32 seconds
Started Aug 05 05:09:42 PM PDT 24
Finished Aug 05 05:14:06 PM PDT 24
Peak memory 255488 kb
Host smart-b9b96fbe-c3a6-486e-ac0a-8cd1b147d94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66381
8178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.663818178
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1443476984
Short name T693
Test name
Test status
Simulation time 100697209 ps
CPU time 7.48 seconds
Started Aug 05 05:09:45 PM PDT 24
Finished Aug 05 05:09:53 PM PDT 24
Peak memory 247860 kb
Host smart-b483590c-ca20-4f58-8421-eb2bc48e7c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14434
76984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1443476984
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.4222466626
Short name T496
Test name
Test status
Simulation time 12296605171 ps
CPU time 1290.55 seconds
Started Aug 05 05:09:50 PM PDT 24
Finished Aug 05 05:31:21 PM PDT 24
Peak memory 285220 kb
Host smart-8402814c-0352-4808-952c-1a67894fa30c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222466626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.4222466626
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1455532288
Short name T419
Test name
Test status
Simulation time 32418919915 ps
CPU time 1478.84 seconds
Started Aug 05 05:09:49 PM PDT 24
Finished Aug 05 05:34:28 PM PDT 24
Peak memory 288600 kb
Host smart-38da7658-4ad8-4a6e-83a1-8abf26614c45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455532288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1455532288
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1566350393
Short name T325
Test name
Test status
Simulation time 47868744598 ps
CPU time 468.89 seconds
Started Aug 05 05:09:55 PM PDT 24
Finished Aug 05 05:17:44 PM PDT 24
Peak memory 247664 kb
Host smart-3acb66b1-3042-4841-b14a-98f14989fb87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566350393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1566350393
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3257998330
Short name T702
Test name
Test status
Simulation time 709725557 ps
CPU time 33.1 seconds
Started Aug 05 05:09:54 PM PDT 24
Finished Aug 05 05:10:28 PM PDT 24
Peak memory 248308 kb
Host smart-defaea31-dc94-4a6c-96b1-beea1d3158a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32579
98330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3257998330
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.380159644
Short name T692
Test name
Test status
Simulation time 2020682034 ps
CPU time 30.62 seconds
Started Aug 05 05:09:43 PM PDT 24
Finished Aug 05 05:10:14 PM PDT 24
Peak memory 255752 kb
Host smart-487c872d-c7ab-4016-9f0f-24eb85d8713a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38015
9644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.380159644
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2611428640
Short name T465
Test name
Test status
Simulation time 1293788011 ps
CPU time 16.49 seconds
Started Aug 05 05:09:57 PM PDT 24
Finished Aug 05 05:10:14 PM PDT 24
Peak memory 254044 kb
Host smart-3239ea8f-2687-41d3-8d08-c26b25077c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26114
28640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2611428640
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2842516690
Short name T174
Test name
Test status
Simulation time 1022980812 ps
CPU time 61.13 seconds
Started Aug 05 05:09:36 PM PDT 24
Finished Aug 05 05:10:37 PM PDT 24
Peak memory 256472 kb
Host smart-acdad271-8d53-4845-b1f1-2ee9ecd508d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28425
16690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2842516690
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3206439381
Short name T653
Test name
Test status
Simulation time 109320226529 ps
CPU time 2406.17 seconds
Started Aug 05 05:09:40 PM PDT 24
Finished Aug 05 05:49:47 PM PDT 24
Peak memory 288788 kb
Host smart-fbfbc016-0234-4c52-a0dd-6e4eda21e444
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206439381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3206439381
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.47030634
Short name T86
Test name
Test status
Simulation time 112504607212 ps
CPU time 6750.12 seconds
Started Aug 05 05:09:42 PM PDT 24
Finished Aug 05 07:02:13 PM PDT 24
Peak memory 338580 kb
Host smart-bdbbdb4f-2c49-425e-8235-d1df34cab38b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47030634 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.47030634
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.119639104
Short name T497
Test name
Test status
Simulation time 24504807378 ps
CPU time 1327.68 seconds
Started Aug 05 05:09:42 PM PDT 24
Finished Aug 05 05:31:50 PM PDT 24
Peak memory 288688 kb
Host smart-61ae46c1-edab-47e1-84b0-10985492a605
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119639104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.119639104
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3009008712
Short name T438
Test name
Test status
Simulation time 3151271515 ps
CPU time 175.24 seconds
Started Aug 05 05:09:55 PM PDT 24
Finished Aug 05 05:12:50 PM PDT 24
Peak memory 256560 kb
Host smart-5b7b4cd2-d3ca-46d2-a7f2-eefd35ad0aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30090
08712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3009008712
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1485809362
Short name T227
Test name
Test status
Simulation time 14287287558 ps
CPU time 1029.63 seconds
Started Aug 05 05:09:46 PM PDT 24
Finished Aug 05 05:26:56 PM PDT 24
Peak memory 272936 kb
Host smart-ad2bd7b1-9c4f-4c83-82cd-046219e33b05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485809362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1485809362
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.494749447
Short name T435
Test name
Test status
Simulation time 120961074693 ps
CPU time 1781.35 seconds
Started Aug 05 05:09:57 PM PDT 24
Finished Aug 05 05:39:39 PM PDT 24
Peak memory 272808 kb
Host smart-30ecdde2-ca11-481c-bc9a-54e8f19d2bf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494749447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.494749447
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3745641253
Short name T17
Test name
Test status
Simulation time 6231881947 ps
CPU time 97.17 seconds
Started Aug 05 05:09:42 PM PDT 24
Finished Aug 05 05:11:19 PM PDT 24
Peak memory 247756 kb
Host smart-d62db569-621e-487d-ba45-681adef2ab17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745641253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3745641253
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3458224488
Short name T399
Test name
Test status
Simulation time 47206838 ps
CPU time 4.93 seconds
Started Aug 05 05:09:46 PM PDT 24
Finished Aug 05 05:09:51 PM PDT 24
Peak memory 248280 kb
Host smart-17851f86-12ce-4abf-bfbb-a274d290ad80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34582
24488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3458224488
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3966460965
Short name T594
Test name
Test status
Simulation time 28030911 ps
CPU time 6.31 seconds
Started Aug 05 05:09:45 PM PDT 24
Finished Aug 05 05:09:52 PM PDT 24
Peak memory 251812 kb
Host smart-8972fe4f-4a4b-4070-93fb-bd627dca56f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39664
60965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3966460965
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3588878174
Short name T607
Test name
Test status
Simulation time 3931656855 ps
CPU time 62.06 seconds
Started Aug 05 05:09:48 PM PDT 24
Finished Aug 05 05:10:50 PM PDT 24
Peak memory 255628 kb
Host smart-365abd08-ba8f-4096-90f6-3c0e3c1eba4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35888
78174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3588878174
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.4132603065
Short name T350
Test name
Test status
Simulation time 372309788 ps
CPU time 24.65 seconds
Started Aug 05 05:09:39 PM PDT 24
Finished Aug 05 05:10:04 PM PDT 24
Peak memory 248372 kb
Host smart-f0b4663a-7dce-4946-aeae-2a84a8994909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41326
03065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.4132603065
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2246297646
Short name T188
Test name
Test status
Simulation time 43454539 ps
CPU time 2.29 seconds
Started Aug 05 05:09:04 PM PDT 24
Finished Aug 05 05:09:07 PM PDT 24
Peak memory 248620 kb
Host smart-c7c43c86-01c6-4d43-afb1-6078226a2795
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2246297646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2246297646
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.12861918
Short name T284
Test name
Test status
Simulation time 109022781169 ps
CPU time 882.48 seconds
Started Aug 05 05:09:12 PM PDT 24
Finished Aug 05 05:23:54 PM PDT 24
Peak memory 289248 kb
Host smart-db015424-8873-40e6-91d1-4a15e3507dee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12861918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.12861918
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.4289373245
Short name T638
Test name
Test status
Simulation time 84563805 ps
CPU time 6.27 seconds
Started Aug 05 05:08:59 PM PDT 24
Finished Aug 05 05:09:05 PM PDT 24
Peak memory 248280 kb
Host smart-18961d39-e930-4e7f-99d3-2ced108754e6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4289373245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.4289373245
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3715275942
Short name T628
Test name
Test status
Simulation time 2165562919 ps
CPU time 159.71 seconds
Started Aug 05 05:09:11 PM PDT 24
Finished Aug 05 05:11:51 PM PDT 24
Peak memory 255864 kb
Host smart-495cbb11-e23e-4082-b586-89c96f996767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37152
75942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3715275942
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.228106591
Short name T427
Test name
Test status
Simulation time 811665653 ps
CPU time 15.93 seconds
Started Aug 05 05:08:52 PM PDT 24
Finished Aug 05 05:09:08 PM PDT 24
Peak memory 248184 kb
Host smart-d51ac831-612c-427b-b0c7-09d61c9286ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22810
6591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.228106591
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1348149673
Short name T488
Test name
Test status
Simulation time 143242871693 ps
CPU time 1062.96 seconds
Started Aug 05 05:08:53 PM PDT 24
Finished Aug 05 05:26:36 PM PDT 24
Peak memory 272232 kb
Host smart-249ea71c-8f49-4af6-ab7c-24a48c5e0106
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348149673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1348149673
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.775828231
Short name T563
Test name
Test status
Simulation time 114227638407 ps
CPU time 1640.07 seconds
Started Aug 05 05:08:51 PM PDT 24
Finished Aug 05 05:36:11 PM PDT 24
Peak memory 272688 kb
Host smart-a467f54c-fae7-49c6-ba7d-f2f9026c3af1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775828231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.775828231
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.72797101
Short name T318
Test name
Test status
Simulation time 111442896933 ps
CPU time 317.32 seconds
Started Aug 05 05:08:51 PM PDT 24
Finished Aug 05 05:14:09 PM PDT 24
Peak memory 254060 kb
Host smart-bcdba442-69b2-49a2-8c7a-608e08614c6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72797101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.72797101
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2227824440
Short name T222
Test name
Test status
Simulation time 142008247 ps
CPU time 13.56 seconds
Started Aug 05 05:09:04 PM PDT 24
Finished Aug 05 05:09:17 PM PDT 24
Peak memory 255000 kb
Host smart-ae2a23a4-00bc-4377-819e-a3aa91590d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22278
24440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2227824440
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2694402155
Short name T33
Test name
Test status
Simulation time 423914886 ps
CPU time 14.3 seconds
Started Aug 05 05:09:03 PM PDT 24
Finished Aug 05 05:09:18 PM PDT 24
Peak memory 247936 kb
Host smart-d46cc691-0d50-4bf7-9f59-60826e15037b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26944
02155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2694402155
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.174070466
Short name T8
Test name
Test status
Simulation time 610122699 ps
CPU time 10.51 seconds
Started Aug 05 05:09:01 PM PDT 24
Finished Aug 05 05:09:12 PM PDT 24
Peak memory 278600 kb
Host smart-41612ebd-f994-42c5-a496-4f1f1806f3e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=174070466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.174070466
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.4075501116
Short name T104
Test name
Test status
Simulation time 126149326 ps
CPU time 9.13 seconds
Started Aug 05 05:08:51 PM PDT 24
Finished Aug 05 05:09:00 PM PDT 24
Peak memory 254252 kb
Host smart-68957d58-2b69-4fe0-9be5-84458f0b7e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40755
01116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.4075501116
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3219214626
Short name T484
Test name
Test status
Simulation time 2643283225 ps
CPU time 45.06 seconds
Started Aug 05 05:08:53 PM PDT 24
Finished Aug 05 05:09:38 PM PDT 24
Peak memory 248372 kb
Host smart-bc9f60ef-6e2b-4906-8995-62c36df82620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32192
14626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3219214626
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.383977188
Short name T35
Test name
Test status
Simulation time 72450997761 ps
CPU time 2723.34 seconds
Started Aug 05 05:09:11 PM PDT 24
Finished Aug 05 05:54:35 PM PDT 24
Peak memory 305752 kb
Host smart-56ae77c6-4f46-499f-9799-c45e91cdcdfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383977188 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.383977188
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1316124647
Short name T678
Test name
Test status
Simulation time 131154727526 ps
CPU time 1255.63 seconds
Started Aug 05 05:09:47 PM PDT 24
Finished Aug 05 05:30:43 PM PDT 24
Peak memory 272592 kb
Host smart-8e070b92-b24d-4a49-bdf1-4d705f6a083b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316124647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1316124647
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1328442809
Short name T626
Test name
Test status
Simulation time 8781816962 ps
CPU time 164.6 seconds
Started Aug 05 05:09:46 PM PDT 24
Finished Aug 05 05:12:31 PM PDT 24
Peak memory 256540 kb
Host smart-41ee2fdb-04ff-41ae-91d5-bf985eb2e72f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13284
42809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1328442809
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.231239140
Short name T580
Test name
Test status
Simulation time 80352545 ps
CPU time 7.58 seconds
Started Aug 05 05:09:52 PM PDT 24
Finished Aug 05 05:09:59 PM PDT 24
Peak memory 248304 kb
Host smart-b9e3718e-30b6-4f06-a3fc-89717a9ef3dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23123
9140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.231239140
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.260945135
Short name T368
Test name
Test status
Simulation time 17249633825 ps
CPU time 1644.35 seconds
Started Aug 05 05:09:54 PM PDT 24
Finished Aug 05 05:37:19 PM PDT 24
Peak memory 288396 kb
Host smart-56565afb-a110-4ec8-8f89-f30c45ef6075
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260945135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.260945135
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3467730961
Short name T317
Test name
Test status
Simulation time 3721617287 ps
CPU time 152.88 seconds
Started Aug 05 05:09:47 PM PDT 24
Finished Aug 05 05:12:20 PM PDT 24
Peak memory 247232 kb
Host smart-5276f0db-8ae4-4530-a44a-cab433846483
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467730961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3467730961
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1415735985
Short name T407
Test name
Test status
Simulation time 4177104275 ps
CPU time 27.18 seconds
Started Aug 05 05:09:58 PM PDT 24
Finished Aug 05 05:10:25 PM PDT 24
Peak memory 248364 kb
Host smart-0ebdb5ff-4f8a-487c-b3dd-edc0af918182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14157
35985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1415735985
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3604501695
Short name T586
Test name
Test status
Simulation time 718434513 ps
CPU time 25.25 seconds
Started Aug 05 05:09:58 PM PDT 24
Finished Aug 05 05:10:23 PM PDT 24
Peak memory 254904 kb
Host smart-8561b511-08c1-4e25-8e69-151760e23048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36045
01695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3604501695
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1295259567
Short name T704
Test name
Test status
Simulation time 3171678416 ps
CPU time 50.96 seconds
Started Aug 05 05:09:53 PM PDT 24
Finished Aug 05 05:10:44 PM PDT 24
Peak memory 255676 kb
Host smart-f1fde0e2-3912-41d9-a22e-fd1b4b8f2fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12952
59567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1295259567
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2840070126
Short name T684
Test name
Test status
Simulation time 335076362 ps
CPU time 31.48 seconds
Started Aug 05 05:09:49 PM PDT 24
Finished Aug 05 05:10:20 PM PDT 24
Peak memory 256416 kb
Host smart-8a6a7b8f-b195-48bf-ba28-8fb7aa13efef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28400
70126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2840070126
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3912272324
Short name T556
Test name
Test status
Simulation time 515855544417 ps
CPU time 2958 seconds
Started Aug 05 05:09:48 PM PDT 24
Finished Aug 05 05:59:06 PM PDT 24
Peak memory 304904 kb
Host smart-499d3e0e-a5a3-47ef-8ee6-70931459f493
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912272324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3912272324
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2282680704
Short name T300
Test name
Test status
Simulation time 14531935587 ps
CPU time 1253.48 seconds
Started Aug 05 05:09:57 PM PDT 24
Finished Aug 05 05:30:51 PM PDT 24
Peak memory 287508 kb
Host smart-02475d17-286b-48ee-814b-d4a2fdebe602
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282680704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2282680704
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.325018779
Short name T522
Test name
Test status
Simulation time 1263543733 ps
CPU time 115.25 seconds
Started Aug 05 05:13:20 PM PDT 24
Finished Aug 05 05:15:15 PM PDT 24
Peak memory 256024 kb
Host smart-b31d3972-1077-49ed-8018-932dfa81bb0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32501
8779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.325018779
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3315007211
Short name T400
Test name
Test status
Simulation time 252381069 ps
CPU time 27.64 seconds
Started Aug 05 05:09:57 PM PDT 24
Finished Aug 05 05:10:25 PM PDT 24
Peak memory 248028 kb
Host smart-0a64d759-9b28-433e-8260-8af880ccd674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33150
07211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3315007211
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.688271293
Short name T664
Test name
Test status
Simulation time 30464351117 ps
CPU time 1493.47 seconds
Started Aug 05 05:09:59 PM PDT 24
Finished Aug 05 05:34:53 PM PDT 24
Peak memory 288848 kb
Host smart-c99464d3-61c7-42b8-ac01-570666f58b29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688271293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.688271293
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3042031612
Short name T669
Test name
Test status
Simulation time 113374372706 ps
CPU time 1991.24 seconds
Started Aug 05 05:09:56 PM PDT 24
Finished Aug 05 05:43:07 PM PDT 24
Peak memory 283940 kb
Host smart-2965d19a-e6f3-4faf-b6c3-e7cb292e3d25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042031612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3042031612
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1734474930
Short name T45
Test name
Test status
Simulation time 12501204003 ps
CPU time 395.06 seconds
Started Aug 05 05:09:55 PM PDT 24
Finished Aug 05 05:16:30 PM PDT 24
Peak memory 254876 kb
Host smart-e8deac7c-582b-483d-ac32-1e377e0faeab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734474930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1734474930
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2117518367
Short name T358
Test name
Test status
Simulation time 5972222711 ps
CPU time 29.7 seconds
Started Aug 05 05:09:57 PM PDT 24
Finished Aug 05 05:10:27 PM PDT 24
Peak memory 256128 kb
Host smart-f1e5684d-c6d2-43ba-9b9b-924c653fe198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21175
18367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2117518367
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1007154988
Short name T19
Test name
Test status
Simulation time 178510786 ps
CPU time 21.94 seconds
Started Aug 05 05:10:03 PM PDT 24
Finished Aug 05 05:10:25 PM PDT 24
Peak memory 255824 kb
Host smart-644e1532-24a5-4b21-b57f-c9e255defa81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10071
54988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1007154988
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3456677075
Short name T561
Test name
Test status
Simulation time 588897509 ps
CPU time 20.35 seconds
Started Aug 05 05:09:57 PM PDT 24
Finished Aug 05 05:10:18 PM PDT 24
Peak memory 247992 kb
Host smart-086c5ded-2cd1-421d-b21b-d85cf45cc1a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34566
77075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3456677075
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3153648970
Short name T614
Test name
Test status
Simulation time 606801460 ps
CPU time 28.52 seconds
Started Aug 05 05:09:48 PM PDT 24
Finished Aug 05 05:10:17 PM PDT 24
Peak memory 256400 kb
Host smart-a2e848b9-550e-46ba-b302-a5cbe44d0aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31536
48970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3153648970
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3993210183
Short name T456
Test name
Test status
Simulation time 14565219867 ps
CPU time 1182.33 seconds
Started Aug 05 05:09:58 PM PDT 24
Finished Aug 05 05:29:40 PM PDT 24
Peak memory 288664 kb
Host smart-d1cd7b74-1866-4cbf-829b-7e998a90b695
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993210183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3993210183
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.963825843
Short name T54
Test name
Test status
Simulation time 32588250105 ps
CPU time 2975.38 seconds
Started Aug 05 05:09:54 PM PDT 24
Finished Aug 05 05:59:30 PM PDT 24
Peak memory 305076 kb
Host smart-3b6d00e9-1818-4a1e-935b-e544c9fd7fc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963825843 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.963825843
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1343967972
Short name T671
Test name
Test status
Simulation time 9822113531 ps
CPU time 160.08 seconds
Started Aug 05 05:09:57 PM PDT 24
Finished Aug 05 05:12:37 PM PDT 24
Peak memory 256540 kb
Host smart-59bcbe82-7d3c-4232-bdad-2fd2b93e468a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13439
67972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1343967972
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1267443970
Short name T437
Test name
Test status
Simulation time 523360462 ps
CPU time 21.23 seconds
Started Aug 05 05:09:54 PM PDT 24
Finished Aug 05 05:10:15 PM PDT 24
Peak memory 248304 kb
Host smart-c81da297-388e-4dbd-ab5f-a257eccff193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12674
43970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1267443970
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3193343466
Short name T333
Test name
Test status
Simulation time 102561851531 ps
CPU time 2013.31 seconds
Started Aug 05 05:09:53 PM PDT 24
Finished Aug 05 05:43:27 PM PDT 24
Peak memory 288240 kb
Host smart-97b25a5d-d993-4812-963c-1411c7d3dca1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193343466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3193343466
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1526817547
Short name T288
Test name
Test status
Simulation time 205394358678 ps
CPU time 2938.32 seconds
Started Aug 05 05:09:54 PM PDT 24
Finished Aug 05 05:58:53 PM PDT 24
Peak memory 289160 kb
Host smart-7c2eae6d-6ec2-4102-87e6-34fe8c909e12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526817547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1526817547
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.709311519
Short name T216
Test name
Test status
Simulation time 4133023111 ps
CPU time 173.99 seconds
Started Aug 05 05:09:53 PM PDT 24
Finished Aug 05 05:12:47 PM PDT 24
Peak memory 248336 kb
Host smart-2f7796d0-dabb-4bc4-a7b1-46a909821570
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709311519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.709311519
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.904963765
Short name T432
Test name
Test status
Simulation time 2151334901 ps
CPU time 39.78 seconds
Started Aug 05 05:09:55 PM PDT 24
Finished Aug 05 05:10:34 PM PDT 24
Peak memory 255736 kb
Host smart-dcc3b28d-c744-4594-aa28-014680e34439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90496
3765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.904963765
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1350388832
Short name T281
Test name
Test status
Simulation time 381144359 ps
CPU time 36.85 seconds
Started Aug 05 05:09:59 PM PDT 24
Finished Aug 05 05:10:36 PM PDT 24
Peak memory 255936 kb
Host smart-0745f730-c69e-4733-95f7-8e5955292281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13503
88832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1350388832
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.4264593907
Short name T1
Test name
Test status
Simulation time 500416764 ps
CPU time 31.54 seconds
Started Aug 05 05:09:54 PM PDT 24
Finished Aug 05 05:10:25 PM PDT 24
Peak memory 248304 kb
Host smart-d57c13e2-e563-4d78-ada5-cb02db40668c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42645
93907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.4264593907
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1540600618
Short name T477
Test name
Test status
Simulation time 647006787 ps
CPU time 19.56 seconds
Started Aug 05 05:09:58 PM PDT 24
Finished Aug 05 05:10:18 PM PDT 24
Peak memory 255620 kb
Host smart-714c87fe-128f-4644-a2dc-b985d52ba558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15406
00618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1540600618
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1479548291
Short name T251
Test name
Test status
Simulation time 28710845812 ps
CPU time 1689.45 seconds
Started Aug 05 05:09:59 PM PDT 24
Finished Aug 05 05:38:09 PM PDT 24
Peak memory 272812 kb
Host smart-685016e3-355a-4281-9a0a-8be7a7ba6dd1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479548291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1479548291
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.1054379979
Short name T76
Test name
Test status
Simulation time 16915931771 ps
CPU time 1853.43 seconds
Started Aug 05 05:09:54 PM PDT 24
Finished Aug 05 05:40:48 PM PDT 24
Peak memory 297568 kb
Host smart-a5b71e03-994d-4425-a1de-3c90b4ad86b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054379979 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.1054379979
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3951129374
Short name T55
Test name
Test status
Simulation time 52223265771 ps
CPU time 1093.54 seconds
Started Aug 05 05:09:57 PM PDT 24
Finished Aug 05 05:28:11 PM PDT 24
Peak memory 272724 kb
Host smart-5a87f1cb-813e-4463-8884-747b2e423464
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951129374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3951129374
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.429003903
Short name T214
Test name
Test status
Simulation time 10783396541 ps
CPU time 151.96 seconds
Started Aug 05 05:09:54 PM PDT 24
Finished Aug 05 05:12:26 PM PDT 24
Peak memory 256112 kb
Host smart-22ea961a-7a93-4148-a60d-2c4872d05036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42900
3903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.429003903
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.45683118
Short name T612
Test name
Test status
Simulation time 1736697998 ps
CPU time 25.76 seconds
Started Aug 05 05:09:55 PM PDT 24
Finished Aug 05 05:10:21 PM PDT 24
Peak memory 248080 kb
Host smart-3b8cab96-7eb2-4e4d-96fb-483ac8bb978b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45683
118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.45683118
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.355968086
Short name T336
Test name
Test status
Simulation time 41709713156 ps
CPU time 1264.04 seconds
Started Aug 05 05:09:52 PM PDT 24
Finished Aug 05 05:30:57 PM PDT 24
Peak memory 272828 kb
Host smart-8a0ba986-eac6-4823-9dcc-cacb19b1761c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355968086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.355968086
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1080499078
Short name T601
Test name
Test status
Simulation time 255370986549 ps
CPU time 2008.12 seconds
Started Aug 05 05:09:59 PM PDT 24
Finished Aug 05 05:43:28 PM PDT 24
Peak memory 272992 kb
Host smart-2d7b0580-6009-47ec-ac82-5f25b51f152a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080499078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1080499078
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.241262497
Short name T319
Test name
Test status
Simulation time 5427812104 ps
CPU time 121.35 seconds
Started Aug 05 05:09:53 PM PDT 24
Finished Aug 05 05:11:55 PM PDT 24
Peak memory 248228 kb
Host smart-864e6ac4-c35e-4efd-bf09-6de539b75d58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241262497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.241262497
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1597936025
Short name T636
Test name
Test status
Simulation time 199146700 ps
CPU time 5.37 seconds
Started Aug 05 05:09:55 PM PDT 24
Finished Aug 05 05:10:00 PM PDT 24
Peak memory 248212 kb
Host smart-c24986c2-44f2-428f-80b4-99c090f22904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15979
36025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1597936025
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3145227973
Short name T430
Test name
Test status
Simulation time 51419478 ps
CPU time 8.15 seconds
Started Aug 05 05:09:53 PM PDT 24
Finished Aug 05 05:10:01 PM PDT 24
Peak memory 247356 kb
Host smart-2be345e8-36c0-4934-83d4-1b489a9cd16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31452
27973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3145227973
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1979409159
Short name T360
Test name
Test status
Simulation time 474244209 ps
CPU time 30.97 seconds
Started Aug 05 05:10:00 PM PDT 24
Finished Aug 05 05:10:31 PM PDT 24
Peak memory 256380 kb
Host smart-203f8f2f-3f2d-4cfe-b34c-573d7475357e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19794
09159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1979409159
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.723408551
Short name T630
Test name
Test status
Simulation time 1686123392 ps
CPU time 34.82 seconds
Started Aug 05 05:10:02 PM PDT 24
Finished Aug 05 05:10:37 PM PDT 24
Peak memory 256060 kb
Host smart-29523825-cd9e-41f2-8936-3887f95010eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72340
8551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.723408551
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.4028660313
Short name T457
Test name
Test status
Simulation time 34261431254 ps
CPU time 514.93 seconds
Started Aug 05 05:09:55 PM PDT 24
Finished Aug 05 05:18:30 PM PDT 24
Peak memory 256600 kb
Host smart-c1f7ca04-f08a-48e9-8f76-f384749e0605
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028660313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.4028660313
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3977736467
Short name T610
Test name
Test status
Simulation time 103893687633 ps
CPU time 3029.46 seconds
Started Aug 05 05:10:04 PM PDT 24
Finished Aug 05 06:00:34 PM PDT 24
Peak memory 288648 kb
Host smart-0b30dc56-82f7-47ce-96f7-819131362f91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977736467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3977736467
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1676188850
Short name T352
Test name
Test status
Simulation time 3175619054 ps
CPU time 70.7 seconds
Started Aug 05 05:10:20 PM PDT 24
Finished Aug 05 05:11:30 PM PDT 24
Peak memory 255796 kb
Host smart-7f15a9a5-58fe-4699-9b96-d6abe6ba99c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16761
88850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1676188850
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.870210826
Short name T18
Test name
Test status
Simulation time 4214078961 ps
CPU time 40.59 seconds
Started Aug 05 05:10:06 PM PDT 24
Finished Aug 05 05:10:47 PM PDT 24
Peak memory 248300 kb
Host smart-692ae60b-6fdf-497a-82d6-ba409c4882b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87021
0826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.870210826
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2769343114
Short name T562
Test name
Test status
Simulation time 94481777965 ps
CPU time 2907.98 seconds
Started Aug 05 05:10:01 PM PDT 24
Finished Aug 05 05:58:29 PM PDT 24
Peak memory 288636 kb
Host smart-2e338c6c-35cc-4041-b7e3-c863a2f6413f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769343114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2769343114
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1767572434
Short name T426
Test name
Test status
Simulation time 17878039906 ps
CPU time 1055.34 seconds
Started Aug 05 05:10:03 PM PDT 24
Finished Aug 05 05:27:38 PM PDT 24
Peak memory 265656 kb
Host smart-95e603d4-93c2-49de-9021-3cfa8da1bfb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767572434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1767572434
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.127747993
Short name T311
Test name
Test status
Simulation time 35258045360 ps
CPU time 376.66 seconds
Started Aug 05 05:10:02 PM PDT 24
Finished Aug 05 05:16:19 PM PDT 24
Peak memory 248296 kb
Host smart-471700c0-2276-4a19-8b30-6e7bc487eaab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127747993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.127747993
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1161574482
Short name T205
Test name
Test status
Simulation time 595871871 ps
CPU time 35.09 seconds
Started Aug 05 05:10:05 PM PDT 24
Finished Aug 05 05:10:40 PM PDT 24
Peak memory 255760 kb
Host smart-156cfb42-2450-4a87-a396-2c7ee1946762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11615
74482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1161574482
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1792449331
Short name T567
Test name
Test status
Simulation time 861163041 ps
CPU time 59.72 seconds
Started Aug 05 05:10:06 PM PDT 24
Finished Aug 05 05:11:06 PM PDT 24
Peak memory 255944 kb
Host smart-548ecb0a-5b8b-4314-830a-465ebbc83eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17924
49331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1792449331
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1618045798
Short name T272
Test name
Test status
Simulation time 784672484 ps
CPU time 50.41 seconds
Started Aug 05 05:10:03 PM PDT 24
Finished Aug 05 05:10:53 PM PDT 24
Peak memory 255552 kb
Host smart-4bac1a72-7915-43b5-8b9a-2134bea01764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16180
45798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1618045798
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.4169310137
Short name T521
Test name
Test status
Simulation time 1303213473 ps
CPU time 43.16 seconds
Started Aug 05 05:10:00 PM PDT 24
Finished Aug 05 05:10:43 PM PDT 24
Peak memory 256456 kb
Host smart-8d73c042-967d-4d17-b2d7-e8d1481be5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41693
10137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.4169310137
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.210190232
Short name T32
Test name
Test status
Simulation time 93883939846 ps
CPU time 1122.29 seconds
Started Aug 05 05:10:03 PM PDT 24
Finished Aug 05 05:28:45 PM PDT 24
Peak memory 282624 kb
Host smart-d521ad6d-a7fd-4eb9-be75-84485419dc4a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210190232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.210190232
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.1035839225
Short name T41
Test name
Test status
Simulation time 25559744620 ps
CPU time 1657.09 seconds
Started Aug 05 05:10:02 PM PDT 24
Finished Aug 05 05:37:39 PM PDT 24
Peak memory 288124 kb
Host smart-1748fdee-127d-479b-9202-1c4db2cef9b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035839225 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.1035839225
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1974640014
Short name T366
Test name
Test status
Simulation time 44176068503 ps
CPU time 2588.94 seconds
Started Aug 05 05:10:06 PM PDT 24
Finished Aug 05 05:53:15 PM PDT 24
Peak memory 287380 kb
Host smart-f048377b-a467-461a-abb2-7d54e631134c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974640014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1974640014
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1250240785
Short name T486
Test name
Test status
Simulation time 1311846745 ps
CPU time 104.86 seconds
Started Aug 05 05:10:01 PM PDT 24
Finished Aug 05 05:11:46 PM PDT 24
Peak memory 256544 kb
Host smart-29b6461f-0b3f-4997-9a81-e225d4010e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12502
40785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1250240785
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.841416318
Short name T536
Test name
Test status
Simulation time 3131355781 ps
CPU time 52.32 seconds
Started Aug 05 05:10:01 PM PDT 24
Finished Aug 05 05:10:54 PM PDT 24
Peak memory 248280 kb
Host smart-eb683bd3-7631-4d9c-9743-ec7a1bab8760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84141
6318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.841416318
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.16307464
Short name T585
Test name
Test status
Simulation time 116034884671 ps
CPU time 1901.07 seconds
Started Aug 05 05:10:03 PM PDT 24
Finished Aug 05 05:41:44 PM PDT 24
Peak memory 281064 kb
Host smart-62d6057c-dbab-4e68-8537-48d85a1f5447
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16307464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.16307464
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1773104536
Short name T445
Test name
Test status
Simulation time 36678783169 ps
CPU time 2122.97 seconds
Started Aug 05 05:10:00 PM PDT 24
Finished Aug 05 05:45:24 PM PDT 24
Peak memory 282008 kb
Host smart-0dfefac2-f597-4770-b440-2bdde97e5dc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773104536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1773104536
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.502316991
Short name T313
Test name
Test status
Simulation time 7744889012 ps
CPU time 321.56 seconds
Started Aug 05 05:10:02 PM PDT 24
Finished Aug 05 05:15:23 PM PDT 24
Peak memory 248400 kb
Host smart-2e34a84c-5fce-42bb-9642-e83183f6ea1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502316991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.502316991
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3435085058
Short name T568
Test name
Test status
Simulation time 10132014857 ps
CPU time 31.94 seconds
Started Aug 05 05:10:03 PM PDT 24
Finished Aug 05 05:10:35 PM PDT 24
Peak memory 248436 kb
Host smart-10135965-ac49-4199-919b-f0ba7c4f10fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34350
85058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3435085058
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1949516635
Short name T475
Test name
Test status
Simulation time 244180876 ps
CPU time 27.03 seconds
Started Aug 05 05:09:59 PM PDT 24
Finished Aug 05 05:10:26 PM PDT 24
Peak memory 247612 kb
Host smart-c8ff7ce8-882b-4b55-80c5-e955dcb32208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19495
16635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1949516635
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1320386575
Short name T420
Test name
Test status
Simulation time 2634329669 ps
CPU time 50.94 seconds
Started Aug 05 05:10:06 PM PDT 24
Finished Aug 05 05:10:57 PM PDT 24
Peak memory 256480 kb
Host smart-a4f54e52-4124-4f8c-a966-da0aa00b9d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13203
86575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1320386575
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3291972463
Short name T247
Test name
Test status
Simulation time 227566761194 ps
CPU time 2344.74 seconds
Started Aug 05 05:10:04 PM PDT 24
Finished Aug 05 05:49:10 PM PDT 24
Peak memory 288664 kb
Host smart-7e7220ce-9ff2-4324-8f67-78de5dad8c67
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291972463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3291972463
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2331394254
Short name T532
Test name
Test status
Simulation time 14225204834 ps
CPU time 925.83 seconds
Started Aug 05 05:10:06 PM PDT 24
Finished Aug 05 05:25:32 PM PDT 24
Peak memory 272920 kb
Host smart-630bea57-a718-406d-8483-f03ad3b87472
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331394254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2331394254
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2032277354
Short name T449
Test name
Test status
Simulation time 16282583273 ps
CPU time 77.09 seconds
Started Aug 05 05:10:09 PM PDT 24
Finished Aug 05 05:11:26 PM PDT 24
Peak memory 248664 kb
Host smart-3ac56190-0d11-4c66-9da4-761271667b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20322
77354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2032277354
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.321561361
Short name T694
Test name
Test status
Simulation time 1643365895 ps
CPU time 42.77 seconds
Started Aug 05 05:10:07 PM PDT 24
Finished Aug 05 05:10:50 PM PDT 24
Peak memory 255632 kb
Host smart-3c491b8b-dff0-4743-9366-62dcaad6c5a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32156
1361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.321561361
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1748818464
Short name T14
Test name
Test status
Simulation time 29091001607 ps
CPU time 1731.3 seconds
Started Aug 05 05:10:06 PM PDT 24
Finished Aug 05 05:38:58 PM PDT 24
Peak memory 272980 kb
Host smart-f4c9751f-462c-4a0e-9467-9d0fb648028c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748818464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1748818464
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3245565464
Short name T408
Test name
Test status
Simulation time 2421014579 ps
CPU time 24.83 seconds
Started Aug 05 05:10:07 PM PDT 24
Finished Aug 05 05:10:32 PM PDT 24
Peak memory 255928 kb
Host smart-6bff6852-95a5-4cfb-b352-6444dec82b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32455
65464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3245565464
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2258997722
Short name T538
Test name
Test status
Simulation time 438601893 ps
CPU time 36.95 seconds
Started Aug 05 05:10:08 PM PDT 24
Finished Aug 05 05:10:45 PM PDT 24
Peak memory 256084 kb
Host smart-a71ae34f-5d6a-4ff1-a6c3-3a2ecffc9ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22589
97722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2258997722
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2849412335
Short name T661
Test name
Test status
Simulation time 1336813423 ps
CPU time 19.87 seconds
Started Aug 05 05:10:05 PM PDT 24
Finished Aug 05 05:10:25 PM PDT 24
Peak memory 248660 kb
Host smart-a391826d-8f1f-4959-af58-f9d0e8cf78ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28494
12335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2849412335
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1558592452
Short name T528
Test name
Test status
Simulation time 497146762 ps
CPU time 16.36 seconds
Started Aug 05 05:10:06 PM PDT 24
Finished Aug 05 05:10:22 PM PDT 24
Peak memory 255920 kb
Host smart-cc93fb0d-64a2-4c0b-a575-2ab1ca96e6da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15585
92452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1558592452
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1044699012
Short name T381
Test name
Test status
Simulation time 59341298250 ps
CPU time 1806.32 seconds
Started Aug 05 05:10:06 PM PDT 24
Finished Aug 05 05:40:13 PM PDT 24
Peak memory 289280 kb
Host smart-71b214e4-ef0d-4a1a-8792-71d06a672bda
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044699012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1044699012
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.2565359084
Short name T93
Test name
Test status
Simulation time 27399207781 ps
CPU time 1886.97 seconds
Started Aug 05 05:10:10 PM PDT 24
Finished Aug 05 05:41:38 PM PDT 24
Peak memory 287920 kb
Host smart-ae17498e-6e2b-4ea2-a8ed-799d0374b40f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565359084 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.2565359084
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1189373422
Short name T44
Test name
Test status
Simulation time 39999559786 ps
CPU time 2135.49 seconds
Started Aug 05 05:10:06 PM PDT 24
Finished Aug 05 05:45:42 PM PDT 24
Peak memory 289340 kb
Host smart-002d4be4-b109-42e5-b9ec-d4bb70606c4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189373422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1189373422
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2431029679
Short name T546
Test name
Test status
Simulation time 7418566514 ps
CPU time 124.97 seconds
Started Aug 05 05:10:06 PM PDT 24
Finished Aug 05 05:12:11 PM PDT 24
Peak memory 256652 kb
Host smart-b6c6a128-9f13-4877-8a11-d04a128c5476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24310
29679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2431029679
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3617973536
Short name T355
Test name
Test status
Simulation time 541257732 ps
CPU time 23.73 seconds
Started Aug 05 05:10:07 PM PDT 24
Finished Aug 05 05:10:30 PM PDT 24
Peak memory 256532 kb
Host smart-69558d58-d010-41d8-bb6a-90f118af68e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36179
73536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3617973536
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2388705831
Short name T74
Test name
Test status
Simulation time 41453153263 ps
CPU time 2405.12 seconds
Started Aug 05 05:10:11 PM PDT 24
Finished Aug 05 05:50:16 PM PDT 24
Peak memory 289184 kb
Host smart-71bbad74-0bd3-42e8-bc63-fa1d5065cf7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388705831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2388705831
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3410210009
Short name T362
Test name
Test status
Simulation time 37653670944 ps
CPU time 1822.98 seconds
Started Aug 05 05:10:09 PM PDT 24
Finished Aug 05 05:40:33 PM PDT 24
Peak memory 272660 kb
Host smart-2bea91e3-3381-46d1-964d-2641775145f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410210009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3410210009
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.270756831
Short name T662
Test name
Test status
Simulation time 10304574194 ps
CPU time 116.47 seconds
Started Aug 05 05:10:06 PM PDT 24
Finished Aug 05 05:12:03 PM PDT 24
Peak memory 248200 kb
Host smart-6428767a-766c-405e-9445-b700864a3a92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270756831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.270756831
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3650621448
Short name T503
Test name
Test status
Simulation time 247074874 ps
CPU time 26.74 seconds
Started Aug 05 05:10:11 PM PDT 24
Finished Aug 05 05:10:38 PM PDT 24
Peak memory 255820 kb
Host smart-cbe4b7f0-bc94-423a-a6ef-de9a3a9bf5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36506
21448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3650621448
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.24806472
Short name T217
Test name
Test status
Simulation time 147973970 ps
CPU time 15 seconds
Started Aug 05 05:10:05 PM PDT 24
Finished Aug 05 05:10:20 PM PDT 24
Peak memory 255676 kb
Host smart-c04806ee-74dd-401c-ad8e-1e2dfe91db9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24806
472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.24806472
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2290718067
Short name T271
Test name
Test status
Simulation time 1547056659 ps
CPU time 41.34 seconds
Started Aug 05 05:10:07 PM PDT 24
Finished Aug 05 05:10:48 PM PDT 24
Peak memory 256304 kb
Host smart-1e305894-9e80-4bdf-8e78-91e2d326215f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22907
18067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2290718067
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3185075814
Short name T541
Test name
Test status
Simulation time 1179892705 ps
CPU time 35.32 seconds
Started Aug 05 05:10:11 PM PDT 24
Finished Aug 05 05:10:46 PM PDT 24
Peak memory 248340 kb
Host smart-502c8fe3-9fc0-4f22-86a8-bb9432190fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31850
75814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3185075814
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1671579323
Short name T28
Test name
Test status
Simulation time 144708344869 ps
CPU time 1981.78 seconds
Started Aug 05 05:10:05 PM PDT 24
Finished Aug 05 05:43:07 PM PDT 24
Peak memory 283604 kb
Host smart-d90eb8ab-3f40-4e4e-b3d1-a3a807c76b55
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671579323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1671579323
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2909509686
Short name T81
Test name
Test status
Simulation time 80226356069 ps
CPU time 3207.35 seconds
Started Aug 05 05:10:05 PM PDT 24
Finished Aug 05 06:03:33 PM PDT 24
Peak memory 305072 kb
Host smart-903da2a9-4e89-4aee-970f-b357131d8ebc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909509686 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2909509686
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2359216372
Short name T602
Test name
Test status
Simulation time 213186476894 ps
CPU time 1970.73 seconds
Started Aug 05 05:10:11 PM PDT 24
Finished Aug 05 05:43:02 PM PDT 24
Peak memory 272332 kb
Host smart-c7dc9f58-ebe2-43b1-99a2-5d7b43c3f297
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359216372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2359216372
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1770451200
Short name T506
Test name
Test status
Simulation time 2966607841 ps
CPU time 156.32 seconds
Started Aug 05 05:10:11 PM PDT 24
Finished Aug 05 05:12:48 PM PDT 24
Peak memory 256592 kb
Host smart-5e53b589-119c-4a51-b8d7-c1e2911791a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17704
51200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1770451200
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.524202640
Short name T375
Test name
Test status
Simulation time 615566707 ps
CPU time 35.9 seconds
Started Aug 05 05:10:13 PM PDT 24
Finished Aug 05 05:10:49 PM PDT 24
Peak memory 255956 kb
Host smart-5405d249-1f0e-4bbd-9354-a2f4ce9a595d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52420
2640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.524202640
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3116924222
Short name T316
Test name
Test status
Simulation time 53206893590 ps
CPU time 2942.42 seconds
Started Aug 05 05:10:12 PM PDT 24
Finished Aug 05 05:59:15 PM PDT 24
Peak memory 286308 kb
Host smart-1d014593-4de9-456d-8cf4-4603d6cf500d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116924222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3116924222
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2689986156
Short name T712
Test name
Test status
Simulation time 32703960772 ps
CPU time 1223.84 seconds
Started Aug 05 05:10:12 PM PDT 24
Finished Aug 05 05:30:36 PM PDT 24
Peak memory 288604 kb
Host smart-1acc8602-f2ec-43df-8a93-3b259dea4316
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689986156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2689986156
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1812680655
Short name T303
Test name
Test status
Simulation time 20556351841 ps
CPU time 392.27 seconds
Started Aug 05 05:10:12 PM PDT 24
Finished Aug 05 05:16:45 PM PDT 24
Peak memory 248396 kb
Host smart-6bd988f0-24b5-466e-a190-861c401a1e80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812680655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1812680655
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1879732280
Short name T646
Test name
Test status
Simulation time 190445893 ps
CPU time 20.24 seconds
Started Aug 05 05:10:12 PM PDT 24
Finished Aug 05 05:10:33 PM PDT 24
Peak memory 248308 kb
Host smart-bdff4047-ea84-4c3c-b4e6-2ee68e67bc31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18797
32280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1879732280
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3759328085
Short name T555
Test name
Test status
Simulation time 1146696410 ps
CPU time 14.1 seconds
Started Aug 05 05:10:14 PM PDT 24
Finished Aug 05 05:10:28 PM PDT 24
Peak memory 254280 kb
Host smart-23e1996d-44aa-4c9f-8bfb-0b09ef420122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37593
28085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3759328085
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1827545520
Short name T468
Test name
Test status
Simulation time 229513472 ps
CPU time 5.11 seconds
Started Aug 05 05:10:13 PM PDT 24
Finished Aug 05 05:10:18 PM PDT 24
Peak memory 239708 kb
Host smart-5dd7faaa-3a25-4d0d-8530-e442be57dc74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18275
45520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1827545520
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.927126466
Short name T416
Test name
Test status
Simulation time 388725100 ps
CPU time 26.08 seconds
Started Aug 05 05:10:12 PM PDT 24
Finished Aug 05 05:10:39 PM PDT 24
Peak memory 256444 kb
Host smart-c7eb22ab-647e-4f35-bdbd-337b41ba91ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92712
6466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.927126466
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3090567198
Short name T262
Test name
Test status
Simulation time 57009317625 ps
CPU time 3155.06 seconds
Started Aug 05 05:10:13 PM PDT 24
Finished Aug 05 06:02:48 PM PDT 24
Peak memory 305000 kb
Host smart-979b9dd8-5702-498e-8d33-db4e64c6dd71
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090567198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3090567198
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.226368492
Short name T89
Test name
Test status
Simulation time 30282530616 ps
CPU time 1147.87 seconds
Started Aug 05 05:10:12 PM PDT 24
Finished Aug 05 05:29:20 PM PDT 24
Peak memory 271072 kb
Host smart-b4b01d1c-8203-44c3-b4df-646a20721200
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226368492 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.226368492
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2096446043
Short name T361
Test name
Test status
Simulation time 94207269197 ps
CPU time 1954.16 seconds
Started Aug 05 05:10:15 PM PDT 24
Finished Aug 05 05:42:49 PM PDT 24
Peak memory 285220 kb
Host smart-9ddac413-b98b-4494-b31d-4407438c860f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096446043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2096446043
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2289137781
Short name T22
Test name
Test status
Simulation time 4700316147 ps
CPU time 255.74 seconds
Started Aug 05 05:10:13 PM PDT 24
Finished Aug 05 05:14:29 PM PDT 24
Peak memory 256188 kb
Host smart-43130db7-3330-4d62-a75b-5012e5d55415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22891
37781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2289137781
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.632452399
Short name T359
Test name
Test status
Simulation time 340049469 ps
CPU time 31.88 seconds
Started Aug 05 05:10:14 PM PDT 24
Finished Aug 05 05:10:46 PM PDT 24
Peak memory 248356 kb
Host smart-b7b22b44-5d8b-4765-8af2-d0e412bc1ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63245
2399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.632452399
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1960300588
Short name T39
Test name
Test status
Simulation time 87504135234 ps
CPU time 1389.22 seconds
Started Aug 05 05:10:13 PM PDT 24
Finished Aug 05 05:33:22 PM PDT 24
Peak memory 272432 kb
Host smart-72f8648c-df1b-4928-bb1b-fa6416bbb5c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960300588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1960300588
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.238851747
Short name T519
Test name
Test status
Simulation time 8245203453 ps
CPU time 816.51 seconds
Started Aug 05 05:10:19 PM PDT 24
Finished Aug 05 05:23:56 PM PDT 24
Peak memory 272656 kb
Host smart-3eb7ecd8-b609-4166-9358-30c3538f1b06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238851747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.238851747
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3858443325
Short name T575
Test name
Test status
Simulation time 742519852 ps
CPU time 38.81 seconds
Started Aug 05 05:10:14 PM PDT 24
Finished Aug 05 05:10:53 PM PDT 24
Peak memory 255844 kb
Host smart-fefc9383-e887-4150-b6a4-822ddd65d43a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38584
43325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3858443325
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.3264521322
Short name T422
Test name
Test status
Simulation time 3398766614 ps
CPU time 61.05 seconds
Started Aug 05 05:10:14 PM PDT 24
Finished Aug 05 05:11:15 PM PDT 24
Peak memory 247972 kb
Host smart-16ea6344-38b5-4290-9afa-7d4c62f9da99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32645
21322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3264521322
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1069529054
Short name T266
Test name
Test status
Simulation time 2767783614 ps
CPU time 56.67 seconds
Started Aug 05 05:10:15 PM PDT 24
Finished Aug 05 05:11:12 PM PDT 24
Peak memory 248128 kb
Host smart-03bae406-9087-4222-8533-c4fd83fd4560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10695
29054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1069529054
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.789100326
Short name T373
Test name
Test status
Simulation time 2507543822 ps
CPU time 24.12 seconds
Started Aug 05 05:10:16 PM PDT 24
Finished Aug 05 05:10:40 PM PDT 24
Peak memory 256216 kb
Host smart-6146469b-f540-4c81-84b6-454a507e36dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78910
0326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.789100326
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1774247322
Short name T579
Test name
Test status
Simulation time 23657234672 ps
CPU time 982.97 seconds
Started Aug 05 05:10:18 PM PDT 24
Finished Aug 05 05:26:41 PM PDT 24
Peak memory 272728 kb
Host smart-4f81ef7d-36c0-49d5-a406-5c63957f1fbe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774247322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1774247322
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1134730425
Short name T549
Test name
Test status
Simulation time 65669630911 ps
CPU time 1989.3 seconds
Started Aug 05 05:10:19 PM PDT 24
Finished Aug 05 05:43:29 PM PDT 24
Peak memory 305076 kb
Host smart-edd12c67-1600-4595-908e-9a1577174ca9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134730425 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1134730425
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.52035900
Short name T201
Test name
Test status
Simulation time 47558527 ps
CPU time 3.69 seconds
Started Aug 05 05:09:10 PM PDT 24
Finished Aug 05 05:09:14 PM PDT 24
Peak memory 248588 kb
Host smart-6271c50b-89d4-425a-a659-798b978edb35
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=52035900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.52035900
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2779948498
Short name T294
Test name
Test status
Simulation time 9638268172 ps
CPU time 717.56 seconds
Started Aug 05 05:08:50 PM PDT 24
Finished Aug 05 05:20:48 PM PDT 24
Peak memory 265016 kb
Host smart-2e2cf67c-5a8b-4cf5-afc6-431efb615a23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779948498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2779948498
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1569386264
Short name T354
Test name
Test status
Simulation time 571341571 ps
CPU time 15.31 seconds
Started Aug 05 05:09:17 PM PDT 24
Finished Aug 05 05:09:32 PM PDT 24
Peak memory 248304 kb
Host smart-f5e86d0e-5199-4359-8578-554a0ade28b4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1569386264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1569386264
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3124487605
Short name T572
Test name
Test status
Simulation time 4665437091 ps
CPU time 275.03 seconds
Started Aug 05 05:08:58 PM PDT 24
Finished Aug 05 05:13:33 PM PDT 24
Peak memory 256152 kb
Host smart-cc649cd1-be65-4348-8463-39c4ad924d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31244
87605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3124487605
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.4153515973
Short name T533
Test name
Test status
Simulation time 171009788 ps
CPU time 6.17 seconds
Started Aug 05 05:08:55 PM PDT 24
Finished Aug 05 05:09:01 PM PDT 24
Peak memory 247924 kb
Host smart-69707539-0259-4acc-936a-d1ee4989ce23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41535
15973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.4153515973
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2915769314
Short name T576
Test name
Test status
Simulation time 21473631865 ps
CPU time 881.38 seconds
Started Aug 05 05:08:58 PM PDT 24
Finished Aug 05 05:23:39 PM PDT 24
Peak memory 272088 kb
Host smart-b0e6594b-7785-4b2a-8713-51e5bbc8a8ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915769314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2915769314
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1977401429
Short name T604
Test name
Test status
Simulation time 43357929570 ps
CPU time 1075.77 seconds
Started Aug 05 05:09:11 PM PDT 24
Finished Aug 05 05:27:07 PM PDT 24
Peak memory 272444 kb
Host smart-6f67dc69-b63a-4b25-b77f-08e971d7b2db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977401429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1977401429
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3069013
Short name T581
Test name
Test status
Simulation time 3112657868 ps
CPU time 130.37 seconds
Started Aug 05 05:08:58 PM PDT 24
Finished Aug 05 05:11:08 PM PDT 24
Peak memory 254596 kb
Host smart-2962ee09-cfd8-4f25-9822-6d2ffa272e23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3069013
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.966919622
Short name T545
Test name
Test status
Simulation time 1168968365 ps
CPU time 64 seconds
Started Aug 05 05:08:52 PM PDT 24
Finished Aug 05 05:09:56 PM PDT 24
Peak memory 255576 kb
Host smart-2bdb647d-05f5-4409-8862-ffee1c8af1fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96691
9622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.966919622
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2693366740
Short name T459
Test name
Test status
Simulation time 4365025599 ps
CPU time 64.87 seconds
Started Aug 05 05:09:09 PM PDT 24
Finished Aug 05 05:10:14 PM PDT 24
Peak memory 248372 kb
Host smart-88f4c870-c8fa-4e66-a97a-32bd8951eca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26933
66740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2693366740
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1324003724
Short name T10
Test name
Test status
Simulation time 238995894 ps
CPU time 14.17 seconds
Started Aug 05 05:08:57 PM PDT 24
Finished Aug 05 05:09:12 PM PDT 24
Peak memory 270564 kb
Host smart-02fe2389-a96b-48df-91ba-f191068dfc15
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1324003724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1324003724
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.712385837
Short name T446
Test name
Test status
Simulation time 1097576094 ps
CPU time 21.01 seconds
Started Aug 05 05:09:05 PM PDT 24
Finished Aug 05 05:09:26 PM PDT 24
Peak memory 255676 kb
Host smart-007df83c-9264-4e76-a3f9-f3d374db3d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71238
5837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.712385837
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3674242418
Short name T273
Test name
Test status
Simulation time 9859338880 ps
CPU time 566.03 seconds
Started Aug 05 05:09:12 PM PDT 24
Finished Aug 05 05:18:38 PM PDT 24
Peak memory 256624 kb
Host smart-77af70e1-e9bf-475d-963e-afaca6dbd15a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674242418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3674242418
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1183092730
Short name T587
Test name
Test status
Simulation time 31598236380 ps
CPU time 1746.82 seconds
Started Aug 05 05:10:22 PM PDT 24
Finished Aug 05 05:39:30 PM PDT 24
Peak memory 272300 kb
Host smart-c5515c6d-a72e-4a55-86fa-5111440583f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183092730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1183092730
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2484786644
Short name T540
Test name
Test status
Simulation time 2801382822 ps
CPU time 102.93 seconds
Started Aug 05 05:10:20 PM PDT 24
Finished Aug 05 05:12:03 PM PDT 24
Peak memory 256524 kb
Host smart-52cbaac5-17ec-4a99-b4bb-2247199ef850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24847
86644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2484786644
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1933842194
Short name T476
Test name
Test status
Simulation time 290987580 ps
CPU time 8.66 seconds
Started Aug 05 05:10:21 PM PDT 24
Finished Aug 05 05:10:29 PM PDT 24
Peak memory 256004 kb
Host smart-4a5c1ec0-2193-4778-92d2-c8798790c163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19338
42194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1933842194
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2836878025
Short name T295
Test name
Test status
Simulation time 20990019339 ps
CPU time 1456.52 seconds
Started Aug 05 05:10:20 PM PDT 24
Finished Aug 05 05:34:37 PM PDT 24
Peak memory 272136 kb
Host smart-d19ebffc-46cd-4101-9572-42d7a6117f6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836878025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2836878025
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2530357252
Short name T657
Test name
Test status
Simulation time 598048012403 ps
CPU time 2250.38 seconds
Started Aug 05 05:10:21 PM PDT 24
Finished Aug 05 05:47:52 PM PDT 24
Peak memory 284068 kb
Host smart-4ffbeb18-37b0-4864-b985-6a7a5e510efa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530357252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2530357252
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.527425157
Short name T706
Test name
Test status
Simulation time 19929206883 ps
CPU time 213.19 seconds
Started Aug 05 05:10:19 PM PDT 24
Finished Aug 05 05:13:52 PM PDT 24
Peak memory 255336 kb
Host smart-da3f6199-1bbb-40f8-a228-d1166ac9a61c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527425157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.527425157
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3187932081
Short name T623
Test name
Test status
Simulation time 365479044 ps
CPU time 29.2 seconds
Started Aug 05 05:10:18 PM PDT 24
Finished Aug 05 05:10:47 PM PDT 24
Peak memory 256480 kb
Host smart-92d92e56-ad9e-4f59-bc60-10fdab27deea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31879
32081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3187932081
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3833448384
Short name T363
Test name
Test status
Simulation time 4308540015 ps
CPU time 40.17 seconds
Started Aug 05 05:10:26 PM PDT 24
Finished Aug 05 05:11:06 PM PDT 24
Peak memory 248364 kb
Host smart-4d604f68-e95b-4ebe-adfc-125e470b2a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38334
48384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3833448384
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.554405874
Short name T263
Test name
Test status
Simulation time 2664301887 ps
CPU time 37.7 seconds
Started Aug 05 05:10:17 PM PDT 24
Finished Aug 05 05:10:55 PM PDT 24
Peak memory 248964 kb
Host smart-0f5bf715-eb13-4cc4-9cc9-e5b3b009ab41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55440
5874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.554405874
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2635970928
Short name T619
Test name
Test status
Simulation time 143016742 ps
CPU time 5.84 seconds
Started Aug 05 05:10:19 PM PDT 24
Finished Aug 05 05:10:25 PM PDT 24
Peak memory 248420 kb
Host smart-0c046401-5d54-4def-91ca-4dd3b83cc2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26359
70928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2635970928
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1608022151
Short name T99
Test name
Test status
Simulation time 65802459833 ps
CPU time 3880.93 seconds
Started Aug 05 05:10:18 PM PDT 24
Finished Aug 05 06:15:00 PM PDT 24
Peak memory 297456 kb
Host smart-957baedb-6db4-4e76-ae45-834017ff88b8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608022151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1608022151
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1835884380
Short name T705
Test name
Test status
Simulation time 23544029253 ps
CPU time 1338.47 seconds
Started Aug 05 05:10:23 PM PDT 24
Finished Aug 05 05:32:42 PM PDT 24
Peak memory 264672 kb
Host smart-f6d68f25-96d1-4f4a-9241-165fc320b258
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835884380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1835884380
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2024061222
Short name T103
Test name
Test status
Simulation time 10372011665 ps
CPU time 279.84 seconds
Started Aug 05 05:10:17 PM PDT 24
Finished Aug 05 05:14:57 PM PDT 24
Peak memory 256620 kb
Host smart-f1b952bd-2dc6-4aeb-b3b6-b57b238c78bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20240
61222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2024061222
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2377682030
Short name T78
Test name
Test status
Simulation time 1206041867 ps
CPU time 30.33 seconds
Started Aug 05 05:10:23 PM PDT 24
Finished Aug 05 05:10:54 PM PDT 24
Peak memory 247928 kb
Host smart-1f57af10-38ae-4312-b6d2-d6227421e3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23776
82030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2377682030
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3109448300
Short name T322
Test name
Test status
Simulation time 28957344047 ps
CPU time 1195.88 seconds
Started Aug 05 05:10:21 PM PDT 24
Finished Aug 05 05:30:17 PM PDT 24
Peak memory 288408 kb
Host smart-898c83e9-1054-48b7-a5c0-47476e6b4bdf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109448300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3109448300
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3076171645
Short name T469
Test name
Test status
Simulation time 576046461481 ps
CPU time 2094.08 seconds
Started Aug 05 05:10:21 PM PDT 24
Finished Aug 05 05:45:15 PM PDT 24
Peak memory 281744 kb
Host smart-250195f1-e885-402f-961d-b0227639573b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076171645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3076171645
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.795840637
Short name T16
Test name
Test status
Simulation time 10849963844 ps
CPU time 440.49 seconds
Started Aug 05 05:10:18 PM PDT 24
Finished Aug 05 05:17:39 PM PDT 24
Peak memory 248332 kb
Host smart-d917543f-d461-43f0-af46-ec2d6642aad3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795840637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.795840637
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1603700305
Short name T544
Test name
Test status
Simulation time 129760100 ps
CPU time 9.73 seconds
Started Aug 05 05:10:18 PM PDT 24
Finished Aug 05 05:10:28 PM PDT 24
Peak memory 248360 kb
Host smart-a057c881-f277-44f4-b039-96f0fbc40574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16037
00305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1603700305
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1013640458
Short name T21
Test name
Test status
Simulation time 1830647856 ps
CPU time 26.31 seconds
Started Aug 05 05:10:18 PM PDT 24
Finished Aug 05 05:10:44 PM PDT 24
Peak memory 247892 kb
Host smart-06e8e6b9-f858-4688-87ec-ca2515af5e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10136
40458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1013640458
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1495889517
Short name T527
Test name
Test status
Simulation time 1978920142 ps
CPU time 62.27 seconds
Started Aug 05 05:10:26 PM PDT 24
Finished Aug 05 05:11:28 PM PDT 24
Peak memory 256472 kb
Host smart-459056ca-a726-4747-9d86-6b8eafbf3cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14958
89517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1495889517
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1980941428
Short name T250
Test name
Test status
Simulation time 969694830 ps
CPU time 90.92 seconds
Started Aug 05 05:10:21 PM PDT 24
Finished Aug 05 05:11:52 PM PDT 24
Peak memory 256484 kb
Host smart-9b680b56-4ea6-43d8-b8a2-413cb34e9d87
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980941428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1980941428
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.4166920409
Short name T452
Test name
Test status
Simulation time 56001843410 ps
CPU time 1783.1 seconds
Started Aug 05 05:10:22 PM PDT 24
Finished Aug 05 05:40:06 PM PDT 24
Peak memory 288908 kb
Host smart-e607ada7-8dc5-45d3-9b39-588927cfc187
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166920409 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.4166920409
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.846608986
Short name T443
Test name
Test status
Simulation time 87268317330 ps
CPU time 2762.02 seconds
Started Aug 05 05:10:22 PM PDT 24
Finished Aug 05 05:56:24 PM PDT 24
Peak memory 285244 kb
Host smart-1e2720f5-45fd-4610-9043-8707798f528e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846608986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.846608986
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1729875091
Short name T85
Test name
Test status
Simulation time 24447693040 ps
CPU time 384.65 seconds
Started Aug 05 05:10:18 PM PDT 24
Finished Aug 05 05:16:43 PM PDT 24
Peak memory 255932 kb
Host smart-0b1f087e-8862-4e16-b7b5-308526e67e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17298
75091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1729875091
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3548519062
Short name T598
Test name
Test status
Simulation time 638691220 ps
CPU time 30.23 seconds
Started Aug 05 05:10:26 PM PDT 24
Finished Aug 05 05:10:56 PM PDT 24
Peak memory 247876 kb
Host smart-7c127c7d-2bc1-405c-8e47-1241379b9f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35485
19062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3548519062
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.218990470
Short name T444
Test name
Test status
Simulation time 23471195799 ps
CPU time 1421.26 seconds
Started Aug 05 05:10:19 PM PDT 24
Finished Aug 05 05:34:01 PM PDT 24
Peak memory 272192 kb
Host smart-90864b6e-b0c9-4228-a101-5c7c9cff7f69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218990470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.218990470
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3090653885
Short name T315
Test name
Test status
Simulation time 58858301207 ps
CPU time 638.22 seconds
Started Aug 05 05:10:23 PM PDT 24
Finished Aug 05 05:21:02 PM PDT 24
Peak memory 248332 kb
Host smart-9d5a17e6-6439-4cee-8f3d-df402140ea04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090653885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3090653885
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2500832346
Short name T48
Test name
Test status
Simulation time 151653602 ps
CPU time 4.12 seconds
Started Aug 05 05:10:26 PM PDT 24
Finished Aug 05 05:10:30 PM PDT 24
Peak memory 250556 kb
Host smart-79ecfcb2-7095-4a10-b0ca-3cf07465b92f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25008
32346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2500832346
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1216785158
Short name T617
Test name
Test status
Simulation time 970379927 ps
CPU time 60.16 seconds
Started Aug 05 05:10:19 PM PDT 24
Finished Aug 05 05:11:19 PM PDT 24
Peak memory 248356 kb
Host smart-58ee434a-ce0e-446d-aaac-b572216b4804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12167
85158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1216785158
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2861114711
Short name T523
Test name
Test status
Simulation time 836677666 ps
CPU time 23.26 seconds
Started Aug 05 05:10:19 PM PDT 24
Finished Aug 05 05:10:43 PM PDT 24
Peak memory 248264 kb
Host smart-f20dcb3b-a1f6-430a-a4c4-1a8eac97dea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28611
14711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2861114711
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.4006685781
Short name T600
Test name
Test status
Simulation time 792753844 ps
CPU time 48.35 seconds
Started Aug 05 05:10:19 PM PDT 24
Finished Aug 05 05:11:07 PM PDT 24
Peak memory 256480 kb
Host smart-17ce24eb-739a-4d32-a20e-95aa04117776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40066
85781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.4006685781
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1571186326
Short name T40
Test name
Test status
Simulation time 65649551038 ps
CPU time 3728.56 seconds
Started Aug 05 05:10:25 PM PDT 24
Finished Aug 05 06:12:34 PM PDT 24
Peak memory 305044 kb
Host smart-88557b05-ef3a-432a-be30-886efb350b33
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571186326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1571186326
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.445641093
Short name T474
Test name
Test status
Simulation time 31795578377 ps
CPU time 2050.89 seconds
Started Aug 05 05:10:27 PM PDT 24
Finished Aug 05 05:44:38 PM PDT 24
Peak memory 288112 kb
Host smart-dfe5058b-1978-49f5-9b75-5c0fa4c32682
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445641093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.445641093
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1487957917
Short name T434
Test name
Test status
Simulation time 2485400768 ps
CPU time 151.17 seconds
Started Aug 05 05:10:24 PM PDT 24
Finished Aug 05 05:12:56 PM PDT 24
Peak memory 256172 kb
Host smart-e533b3c6-33bd-47d4-a91b-1f5227dbf1f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14879
57917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1487957917
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3573671144
Short name T645
Test name
Test status
Simulation time 852999417 ps
CPU time 30.92 seconds
Started Aug 05 05:10:23 PM PDT 24
Finished Aug 05 05:10:55 PM PDT 24
Peak memory 248352 kb
Host smart-c6e51e87-74d0-4794-a9a9-055e5a7c1b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35736
71144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3573671144
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.411374772
Short name T651
Test name
Test status
Simulation time 69325522242 ps
CPU time 2175.04 seconds
Started Aug 05 05:10:25 PM PDT 24
Finished Aug 05 05:46:41 PM PDT 24
Peak memory 288136 kb
Host smart-0517d1fb-6e6d-4df2-b4be-c65b3c4e9dd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411374772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.411374772
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.794334059
Short name T274
Test name
Test status
Simulation time 41006344424 ps
CPU time 2213.72 seconds
Started Aug 05 05:10:24 PM PDT 24
Finished Aug 05 05:47:18 PM PDT 24
Peak memory 289120 kb
Host smart-1680768a-5f4d-4c7e-8df7-aecd3158528b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794334059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.794334059
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1885583653
Short name T306
Test name
Test status
Simulation time 17598277414 ps
CPU time 190.42 seconds
Started Aug 05 05:10:26 PM PDT 24
Finished Aug 05 05:13:37 PM PDT 24
Peak memory 247204 kb
Host smart-637b1919-08a8-4399-aad2-9ce34c5d765f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885583653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1885583653
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.943907897
Short name T547
Test name
Test status
Simulation time 9342985099 ps
CPU time 43.53 seconds
Started Aug 05 05:10:26 PM PDT 24
Finished Aug 05 05:11:10 PM PDT 24
Peak memory 248376 kb
Host smart-6d0fe502-231a-4b9e-9199-a0e56fea5f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94390
7897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.943907897
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1132635241
Short name T492
Test name
Test status
Simulation time 356783458 ps
CPU time 9.16 seconds
Started Aug 05 05:10:25 PM PDT 24
Finished Aug 05 05:10:35 PM PDT 24
Peak memory 248352 kb
Host smart-b1136436-5c62-4da5-80a0-6cbe60f7d265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11326
35241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1132635241
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2552328949
Short name T603
Test name
Test status
Simulation time 1462203889 ps
CPU time 15.56 seconds
Started Aug 05 05:10:25 PM PDT 24
Finished Aug 05 05:10:41 PM PDT 24
Peak memory 253728 kb
Host smart-0af4667c-b2d8-4d70-84bd-18233d3543c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25523
28949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2552328949
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2964286938
Short name T238
Test name
Test status
Simulation time 5979700737 ps
CPU time 39.4 seconds
Started Aug 05 05:10:23 PM PDT 24
Finished Aug 05 05:11:03 PM PDT 24
Peak memory 256180 kb
Host smart-6a4ed559-aacf-4bcc-8d52-398a77d2943f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29642
86938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2964286938
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.2027462729
Short name T689
Test name
Test status
Simulation time 20567878924 ps
CPU time 2001.19 seconds
Started Aug 05 05:10:28 PM PDT 24
Finished Aug 05 05:43:50 PM PDT 24
Peak memory 304820 kb
Host smart-766314c0-325a-4bc4-a7ba-2b3b115686f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027462729 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.2027462729
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3990756132
Short name T218
Test name
Test status
Simulation time 39145504241 ps
CPU time 2128.82 seconds
Started Aug 05 05:10:25 PM PDT 24
Finished Aug 05 05:45:54 PM PDT 24
Peak memory 285768 kb
Host smart-39f67d4e-c88c-4727-9b72-d8132fe9a0d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990756132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3990756132
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.486181450
Short name T248
Test name
Test status
Simulation time 1137173524 ps
CPU time 57.19 seconds
Started Aug 05 05:10:25 PM PDT 24
Finished Aug 05 05:11:22 PM PDT 24
Peak memory 249328 kb
Host smart-89648e55-4c30-4a4f-a4cc-8d9d92ef2f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48618
1450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.486181450
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1091061522
Short name T253
Test name
Test status
Simulation time 407726961 ps
CPU time 12.47 seconds
Started Aug 05 05:10:24 PM PDT 24
Finished Aug 05 05:10:36 PM PDT 24
Peak memory 252736 kb
Host smart-bd255aa6-6fa9-4c45-895e-fccb608e8e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10910
61522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1091061522
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2559372034
Short name T323
Test name
Test status
Simulation time 154278868602 ps
CPU time 2036.24 seconds
Started Aug 05 05:10:26 PM PDT 24
Finished Aug 05 05:44:22 PM PDT 24
Peak memory 272936 kb
Host smart-da20d42b-02bd-457d-a686-c255f1208e7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559372034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2559372034
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2155780819
Short name T525
Test name
Test status
Simulation time 66512676090 ps
CPU time 1526.92 seconds
Started Aug 05 05:10:25 PM PDT 24
Finished Aug 05 05:35:52 PM PDT 24
Peak memory 287304 kb
Host smart-f81e2f64-765d-48c1-96e4-18385f63d8e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155780819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2155780819
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.2026372215
Short name T711
Test name
Test status
Simulation time 20218260559 ps
CPU time 423.66 seconds
Started Aug 05 05:10:25 PM PDT 24
Finished Aug 05 05:17:29 PM PDT 24
Peak memory 248332 kb
Host smart-bba3a5a8-1a78-4c24-95e5-9edfb6453b42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026372215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2026372215
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.35935254
Short name T71
Test name
Test status
Simulation time 2376777386 ps
CPU time 37.9 seconds
Started Aug 05 05:10:24 PM PDT 24
Finished Aug 05 05:11:02 PM PDT 24
Peak memory 256304 kb
Host smart-e62bd129-d908-48c2-bde1-4fb8ead8b9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35935
254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.35935254
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.812053947
Short name T95
Test name
Test status
Simulation time 1463928860 ps
CPU time 22.21 seconds
Started Aug 05 05:10:28 PM PDT 24
Finished Aug 05 05:10:50 PM PDT 24
Peak memory 255492 kb
Host smart-3c156dba-87e5-4f91-912f-3217b0b13ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81205
3947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.812053947
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.4113721767
Short name T228
Test name
Test status
Simulation time 193580151 ps
CPU time 14.12 seconds
Started Aug 05 05:10:24 PM PDT 24
Finished Aug 05 05:10:38 PM PDT 24
Peak memory 255972 kb
Host smart-3b1a78d4-f2e6-4489-8f94-2d9aa08676e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41137
21767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.4113721767
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2067247693
Short name T490
Test name
Test status
Simulation time 209152190 ps
CPU time 18.26 seconds
Started Aug 05 05:10:24 PM PDT 24
Finished Aug 05 05:10:43 PM PDT 24
Peak memory 255636 kb
Host smart-d7d7028a-74f1-4019-89e5-efeb4ee60e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20672
47693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2067247693
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3723544359
Short name T627
Test name
Test status
Simulation time 173173741794 ps
CPU time 1356.7 seconds
Started Aug 05 05:10:25 PM PDT 24
Finished Aug 05 05:33:02 PM PDT 24
Peak memory 288720 kb
Host smart-fdc59869-d966-4254-bdad-90d816c6048b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723544359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3723544359
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3937242049
Short name T707
Test name
Test status
Simulation time 909854902229 ps
CPU time 9563.73 seconds
Started Aug 05 05:10:24 PM PDT 24
Finished Aug 05 07:49:49 PM PDT 24
Peak memory 369324 kb
Host smart-5a979917-0596-4e36-b800-876726403ff5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937242049 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3937242049
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3222154234
Short name T618
Test name
Test status
Simulation time 143818071095 ps
CPU time 2022.9 seconds
Started Aug 05 05:10:32 PM PDT 24
Finished Aug 05 05:44:15 PM PDT 24
Peak memory 273092 kb
Host smart-ee91a6d7-e48b-45a2-9071-350a1ad97145
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222154234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3222154234
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1401757892
Short name T463
Test name
Test status
Simulation time 10733804405 ps
CPU time 169.43 seconds
Started Aug 05 05:10:26 PM PDT 24
Finished Aug 05 05:13:16 PM PDT 24
Peak memory 256156 kb
Host smart-aa6d5dd8-6748-4ae1-9591-7c38c2efdd88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14017
57892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1401757892
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.887249201
Short name T237
Test name
Test status
Simulation time 919556880 ps
CPU time 50.51 seconds
Started Aug 05 05:10:26 PM PDT 24
Finished Aug 05 05:11:16 PM PDT 24
Peak memory 247980 kb
Host smart-83550700-7109-41c4-be83-c5e2f03c1825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88724
9201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.887249201
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.781344034
Short name T330
Test name
Test status
Simulation time 63329413485 ps
CPU time 1791.86 seconds
Started Aug 05 05:10:31 PM PDT 24
Finished Aug 05 05:40:23 PM PDT 24
Peak memory 272780 kb
Host smart-b104c408-9a4a-4b72-b5c1-070c2cf96cce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781344034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.781344034
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2305245477
Short name T647
Test name
Test status
Simulation time 89416272860 ps
CPU time 1421.35 seconds
Started Aug 05 05:10:32 PM PDT 24
Finished Aug 05 05:34:13 PM PDT 24
Peak memory 272632 kb
Host smart-bd066547-f7a9-4241-a071-be3ee1bec682
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305245477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2305245477
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1333514823
Short name T326
Test name
Test status
Simulation time 160703799553 ps
CPU time 638.3 seconds
Started Aug 05 05:10:39 PM PDT 24
Finished Aug 05 05:21:17 PM PDT 24
Peak memory 248368 kb
Host smart-808de927-7d24-4fcc-b40d-5dba3ae1aa8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333514823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1333514823
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2395074839
Short name T371
Test name
Test status
Simulation time 2081315477 ps
CPU time 36.28 seconds
Started Aug 05 05:10:24 PM PDT 24
Finished Aug 05 05:11:00 PM PDT 24
Peak memory 255724 kb
Host smart-025cfb54-9f3b-4c22-a2a3-42744a8ce982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23950
74839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2395074839
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2496093577
Short name T290
Test name
Test status
Simulation time 903352234 ps
CPU time 34 seconds
Started Aug 05 05:10:24 PM PDT 24
Finished Aug 05 05:10:59 PM PDT 24
Peak memory 248208 kb
Host smart-cae7384c-9577-4b22-95df-b5b2dca74641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24960
93577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2496093577
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.553441364
Short name T641
Test name
Test status
Simulation time 257388042 ps
CPU time 36.51 seconds
Started Aug 05 05:10:32 PM PDT 24
Finished Aug 05 05:11:08 PM PDT 24
Peak memory 249416 kb
Host smart-af265d24-45e4-47cb-82d4-b941ac360e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55344
1364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.553441364
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.4133769885
Short name T493
Test name
Test status
Simulation time 416337312 ps
CPU time 36.65 seconds
Started Aug 05 05:10:24 PM PDT 24
Finished Aug 05 05:11:00 PM PDT 24
Peak memory 256084 kb
Host smart-b8242393-038a-4eb7-9af5-5b0f0acf411f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41337
69885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.4133769885
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.4102909377
Short name T534
Test name
Test status
Simulation time 51436408878 ps
CPU time 326.71 seconds
Started Aug 05 05:10:31 PM PDT 24
Finished Aug 05 05:15:58 PM PDT 24
Peak memory 256524 kb
Host smart-41676f2a-4613-486c-848d-5b4f497d6050
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102909377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.4102909377
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1876094359
Short name T470
Test name
Test status
Simulation time 425089807320 ps
CPU time 10383.5 seconds
Started Aug 05 05:10:32 PM PDT 24
Finished Aug 05 08:03:37 PM PDT 24
Peak memory 392488 kb
Host smart-62c16b2b-6689-4a1c-bb82-a886eca40417
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876094359 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1876094359
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.918610673
Short name T539
Test name
Test status
Simulation time 57264232957 ps
CPU time 1091.13 seconds
Started Aug 05 05:10:30 PM PDT 24
Finished Aug 05 05:28:41 PM PDT 24
Peak memory 288416 kb
Host smart-2076bef0-3043-4b3a-a0a9-4cc67fd6081e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918610673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.918610673
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1158876602
Short name T208
Test name
Test status
Simulation time 3624866202 ps
CPU time 249.2 seconds
Started Aug 05 05:10:34 PM PDT 24
Finished Aug 05 05:14:44 PM PDT 24
Peak memory 256064 kb
Host smart-5418c8a8-11ee-484e-b4f9-5a107668d320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11588
76602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1158876602
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2266691092
Short name T454
Test name
Test status
Simulation time 149955508 ps
CPU time 10.48 seconds
Started Aug 05 05:10:31 PM PDT 24
Finished Aug 05 05:10:42 PM PDT 24
Peak memory 247900 kb
Host smart-142e02af-475b-4906-9ec7-4f5621018e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22666
91092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2266691092
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3002877529
Short name T552
Test name
Test status
Simulation time 15242017332 ps
CPU time 849.88 seconds
Started Aug 05 05:10:32 PM PDT 24
Finished Aug 05 05:24:42 PM PDT 24
Peak memory 272892 kb
Host smart-e80e13b2-5bc1-4f48-bdef-2aae5ebaa3b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002877529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3002877529
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3936442271
Short name T380
Test name
Test status
Simulation time 32293949532 ps
CPU time 1851.23 seconds
Started Aug 05 05:10:31 PM PDT 24
Finished Aug 05 05:41:23 PM PDT 24
Peak memory 267848 kb
Host smart-aa048598-fcc1-4b12-8ff8-059fc07c7781
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936442271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3936442271
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2700075301
Short name T304
Test name
Test status
Simulation time 9885803520 ps
CPU time 411.76 seconds
Started Aug 05 05:10:30 PM PDT 24
Finished Aug 05 05:17:22 PM PDT 24
Peak memory 247280 kb
Host smart-17dceec7-a1e5-41e8-9c33-7d9970517cfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700075301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2700075301
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1770086189
Short name T592
Test name
Test status
Simulation time 197901024 ps
CPU time 26.15 seconds
Started Aug 05 05:10:34 PM PDT 24
Finished Aug 05 05:11:00 PM PDT 24
Peak memory 255696 kb
Host smart-6dd3f81d-7463-4205-99cb-fdf4e6e045eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17700
86189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1770086189
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1379832512
Short name T513
Test name
Test status
Simulation time 362125197 ps
CPU time 8.32 seconds
Started Aug 05 05:10:30 PM PDT 24
Finished Aug 05 05:10:38 PM PDT 24
Peak memory 254372 kb
Host smart-f7b288ae-b889-472b-bd14-ba38ad8091f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13798
32512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1379832512
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3029827413
Short name T265
Test name
Test status
Simulation time 493242367 ps
CPU time 28.24 seconds
Started Aug 05 05:10:32 PM PDT 24
Finished Aug 05 05:11:00 PM PDT 24
Peak memory 255768 kb
Host smart-83b12aa2-bea1-4be8-b313-fa165f49af2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30298
27413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3029827413
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1867586397
Short name T401
Test name
Test status
Simulation time 628286392 ps
CPU time 13.06 seconds
Started Aug 05 05:10:34 PM PDT 24
Finished Aug 05 05:10:47 PM PDT 24
Peak memory 248344 kb
Host smart-1c092c5a-a46b-4947-84bd-af50eb1299c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18675
86397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1867586397
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1991431334
Short name T597
Test name
Test status
Simulation time 7184579645 ps
CPU time 424 seconds
Started Aug 05 05:10:32 PM PDT 24
Finished Aug 05 05:17:36 PM PDT 24
Peak memory 256060 kb
Host smart-7fd4ca77-d5e6-4a73-8550-ed4f80a26676
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991431334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1991431334
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.533205404
Short name T453
Test name
Test status
Simulation time 13659257953 ps
CPU time 1535.75 seconds
Started Aug 05 05:10:31 PM PDT 24
Finished Aug 05 05:36:07 PM PDT 24
Peak memory 289124 kb
Host smart-c031ef9b-48b8-41d0-ba57-a8e28ab4762f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533205404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.533205404
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3687577481
Short name T293
Test name
Test status
Simulation time 2385855589 ps
CPU time 154.6 seconds
Started Aug 05 05:10:32 PM PDT 24
Finished Aug 05 05:13:07 PM PDT 24
Peak memory 256552 kb
Host smart-fd0d1258-4278-4c77-9bfd-e1d1bff8a521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36875
77481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3687577481
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1894483209
Short name T478
Test name
Test status
Simulation time 2144642163 ps
CPU time 41.38 seconds
Started Aug 05 05:10:32 PM PDT 24
Finished Aug 05 05:11:13 PM PDT 24
Peak memory 256556 kb
Host smart-2c708429-9544-42b2-a9ed-24cf89b7fa57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18944
83209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1894483209
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1819380391
Short name T6
Test name
Test status
Simulation time 108231408848 ps
CPU time 2864.48 seconds
Started Aug 05 05:10:39 PM PDT 24
Finished Aug 05 05:58:24 PM PDT 24
Peak memory 289036 kb
Host smart-ef8ba214-5b08-405c-afcb-30ff056d567a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819380391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1819380391
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.737326225
Short name T675
Test name
Test status
Simulation time 21660646808 ps
CPU time 472.47 seconds
Started Aug 05 05:10:38 PM PDT 24
Finished Aug 05 05:18:31 PM PDT 24
Peak memory 248392 kb
Host smart-fee52a58-127d-4225-ab07-5ae9e1c551ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737326225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.737326225
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2865896621
Short name T590
Test name
Test status
Simulation time 3230259715 ps
CPU time 52.17 seconds
Started Aug 05 05:10:34 PM PDT 24
Finished Aug 05 05:11:26 PM PDT 24
Peak memory 256384 kb
Host smart-5df018a9-086e-4f89-964a-2426da1e8658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28658
96621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2865896621
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3509114766
Short name T94
Test name
Test status
Simulation time 831277217 ps
CPU time 18.82 seconds
Started Aug 05 05:10:32 PM PDT 24
Finished Aug 05 05:10:51 PM PDT 24
Peak memory 247824 kb
Host smart-7203f801-df3d-4818-a0a6-7e1335ca3fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35091
14766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3509114766
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1815747980
Short name T621
Test name
Test status
Simulation time 901744075 ps
CPU time 37.59 seconds
Started Aug 05 05:10:34 PM PDT 24
Finished Aug 05 05:11:11 PM PDT 24
Peak memory 256472 kb
Host smart-b2423556-c11c-4dc0-809f-e696edda5985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18157
47980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1815747980
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2103507498
Short name T625
Test name
Test status
Simulation time 236066406 ps
CPU time 17.92 seconds
Started Aug 05 05:10:29 PM PDT 24
Finished Aug 05 05:10:48 PM PDT 24
Peak memory 255644 kb
Host smart-3499529b-f9e2-414b-85bd-b56bc99c700d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21035
07498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2103507498
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.242726489
Short name T388
Test name
Test status
Simulation time 124797648882 ps
CPU time 1747.89 seconds
Started Aug 05 05:10:38 PM PDT 24
Finished Aug 05 05:39:47 PM PDT 24
Peak memory 273012 kb
Host smart-9aca9feb-d20d-4fee-8c15-c6350d535e0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242726489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.242726489
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3516207740
Short name T467
Test name
Test status
Simulation time 945729543 ps
CPU time 18.81 seconds
Started Aug 05 05:10:40 PM PDT 24
Finished Aug 05 05:10:58 PM PDT 24
Peak memory 254460 kb
Host smart-f7a00c81-b073-4ed6-bb36-2c9d88a29ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35162
07740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3516207740
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1220850081
Short name T520
Test name
Test status
Simulation time 340599473 ps
CPU time 30.36 seconds
Started Aug 05 05:10:37 PM PDT 24
Finished Aug 05 05:11:08 PM PDT 24
Peak memory 248032 kb
Host smart-873b1ca6-6073-47ca-a30a-5170636f645a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12208
50081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1220850081
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.365328454
Short name T234
Test name
Test status
Simulation time 90823526573 ps
CPU time 2347.45 seconds
Started Aug 05 05:10:40 PM PDT 24
Finished Aug 05 05:49:47 PM PDT 24
Peak memory 289248 kb
Host smart-f64ad627-3f45-4e22-b3b0-4fb5ce3dd212
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365328454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.365328454
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2419342325
Short name T175
Test name
Test status
Simulation time 45814547406 ps
CPU time 2365.82 seconds
Started Aug 05 05:10:37 PM PDT 24
Finished Aug 05 05:50:03 PM PDT 24
Peak memory 282552 kb
Host smart-8ac13334-765d-471e-a51a-6207d2b2096c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419342325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2419342325
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.294196983
Short name T583
Test name
Test status
Simulation time 84711982235 ps
CPU time 250.44 seconds
Started Aug 05 05:10:43 PM PDT 24
Finished Aug 05 05:14:53 PM PDT 24
Peak memory 255396 kb
Host smart-92e4da3e-8595-4f58-bd80-8e95f2db10b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294196983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.294196983
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.947835825
Short name T26
Test name
Test status
Simulation time 1398100046 ps
CPU time 26.62 seconds
Started Aug 05 05:10:38 PM PDT 24
Finished Aug 05 05:11:04 PM PDT 24
Peak memory 256184 kb
Host smart-7e9fc686-527d-49dd-8c62-0b44e6293ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94783
5825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.947835825
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2056487147
Short name T385
Test name
Test status
Simulation time 2243028285 ps
CPU time 39.01 seconds
Started Aug 05 05:10:37 PM PDT 24
Finished Aug 05 05:11:17 PM PDT 24
Peak memory 255912 kb
Host smart-ff8e3fcb-88c5-4887-8664-a94c5a2407e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20564
87147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2056487147
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2841291565
Short name T485
Test name
Test status
Simulation time 2977843996 ps
CPU time 27.82 seconds
Started Aug 05 05:10:50 PM PDT 24
Finished Aug 05 05:11:17 PM PDT 24
Peak memory 256584 kb
Host smart-97378324-3afd-4289-b747-b947a8798df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28412
91565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2841291565
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1486389645
Short name T394
Test name
Test status
Simulation time 7724604849 ps
CPU time 241.76 seconds
Started Aug 05 05:10:50 PM PDT 24
Finished Aug 05 05:14:52 PM PDT 24
Peak memory 256108 kb
Host smart-00e87a39-57e0-49d3-bf5b-104f2b761db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14863
89645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1486389645
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.704084784
Short name T673
Test name
Test status
Simulation time 129484585 ps
CPU time 8.92 seconds
Started Aug 05 05:10:50 PM PDT 24
Finished Aug 05 05:10:59 PM PDT 24
Peak memory 251164 kb
Host smart-40ff6829-acbf-4ab7-90f1-859387ea914b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70408
4784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.704084784
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2244876356
Short name T686
Test name
Test status
Simulation time 13946218911 ps
CPU time 1527.34 seconds
Started Aug 05 05:10:50 PM PDT 24
Finished Aug 05 05:36:18 PM PDT 24
Peak memory 289008 kb
Host smart-c26005ed-6d6f-42e9-b6f6-45b548b144de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244876356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2244876356
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1202636863
Short name T90
Test name
Test status
Simulation time 48626521118 ps
CPU time 2584.54 seconds
Started Aug 05 05:10:51 PM PDT 24
Finished Aug 05 05:53:56 PM PDT 24
Peak memory 288652 kb
Host smart-c90cbaad-79c8-4a97-87d9-4785ad826e00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202636863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1202636863
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3542544271
Short name T681
Test name
Test status
Simulation time 10122643222 ps
CPU time 111.8 seconds
Started Aug 05 05:10:50 PM PDT 24
Finished Aug 05 05:12:42 PM PDT 24
Peak memory 248372 kb
Host smart-f78d91fb-6893-4f8e-967c-6828153ca995
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542544271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3542544271
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.916922462
Short name T543
Test name
Test status
Simulation time 113619974 ps
CPU time 11.85 seconds
Started Aug 05 05:10:50 PM PDT 24
Finished Aug 05 05:11:02 PM PDT 24
Peak memory 248372 kb
Host smart-5b2abce8-0b75-40d4-b825-6c43de1e36be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91692
2462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.916922462
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.654732245
Short name T425
Test name
Test status
Simulation time 403046110 ps
CPU time 15.74 seconds
Started Aug 05 05:10:42 PM PDT 24
Finished Aug 05 05:10:58 PM PDT 24
Peak memory 253408 kb
Host smart-4079ca8f-722c-4ef5-972e-bc2dd2dbae20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65473
2245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.654732245
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2681160299
Short name T60
Test name
Test status
Simulation time 2217710151 ps
CPU time 43.09 seconds
Started Aug 05 05:10:54 PM PDT 24
Finished Aug 05 05:11:37 PM PDT 24
Peak memory 248944 kb
Host smart-c3982146-7dde-4e82-a71c-7766fc72d0bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26811
60299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2681160299
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.2162762251
Short name T219
Test name
Test status
Simulation time 1946656620 ps
CPU time 23.45 seconds
Started Aug 05 05:10:37 PM PDT 24
Finished Aug 05 05:11:01 PM PDT 24
Peak memory 256432 kb
Host smart-84f42b99-2ff3-452c-9159-e69d989d70de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21627
62251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2162762251
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2315828473
Short name T268
Test name
Test status
Simulation time 73609560931 ps
CPU time 4303.91 seconds
Started Aug 05 05:10:51 PM PDT 24
Finished Aug 05 06:22:35 PM PDT 24
Peak memory 297336 kb
Host smart-a1aa4d0f-d4ff-43dd-9c44-712a1501e1d2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315828473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2315828473
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1032371877
Short name T202
Test name
Test status
Simulation time 52695464 ps
CPU time 3.05 seconds
Started Aug 05 05:09:06 PM PDT 24
Finished Aug 05 05:09:09 PM PDT 24
Peak memory 248588 kb
Host smart-00345999-a006-4245-a5f1-b4ec2a590beb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1032371877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1032371877
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2061770840
Short name T510
Test name
Test status
Simulation time 238975963951 ps
CPU time 3544.75 seconds
Started Aug 05 05:09:12 PM PDT 24
Finished Aug 05 06:08:17 PM PDT 24
Peak memory 289244 kb
Host smart-c119151a-6ae1-4f3c-b282-bf39f57599be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061770840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2061770840
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.76564843
Short name T660
Test name
Test status
Simulation time 213995446 ps
CPU time 12.21 seconds
Started Aug 05 05:08:56 PM PDT 24
Finished Aug 05 05:09:08 PM PDT 24
Peak memory 248220 kb
Host smart-3f5808ea-59a5-40af-a9d8-6d6e223b154b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=76564843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.76564843
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1338572876
Short name T502
Test name
Test status
Simulation time 1104768287 ps
CPU time 103.46 seconds
Started Aug 05 05:08:57 PM PDT 24
Finished Aug 05 05:10:41 PM PDT 24
Peak memory 255524 kb
Host smart-9311ca4d-d319-4fba-99b8-d2477e22636d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13385
72876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1338572876
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1434579823
Short name T410
Test name
Test status
Simulation time 714103503 ps
CPU time 30.02 seconds
Started Aug 05 05:09:10 PM PDT 24
Finished Aug 05 05:09:40 PM PDT 24
Peak memory 255968 kb
Host smart-e752a445-4668-4be1-88ba-502acc7c6052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14345
79823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1434579823
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2014204944
Short name T708
Test name
Test status
Simulation time 203926220954 ps
CPU time 2889.08 seconds
Started Aug 05 05:09:00 PM PDT 24
Finished Aug 05 05:57:09 PM PDT 24
Peak memory 285764 kb
Host smart-28e70c8d-cb92-42e0-a928-3ef179913af8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014204944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2014204944
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1977735276
Short name T505
Test name
Test status
Simulation time 26584806714 ps
CPU time 1488.43 seconds
Started Aug 05 05:08:55 PM PDT 24
Finished Aug 05 05:33:44 PM PDT 24
Peak memory 272080 kb
Host smart-e851d0a1-93ec-45c7-a64a-d72d6d39e33b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977735276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1977735276
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2661859536
Short name T173
Test name
Test status
Simulation time 9358548048 ps
CPU time 337.26 seconds
Started Aug 05 05:09:01 PM PDT 24
Finished Aug 05 05:14:39 PM PDT 24
Peak memory 256264 kb
Host smart-332f35b2-0b46-4e78-b533-2ed10b0ead90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661859536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2661859536
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2792875110
Short name T52
Test name
Test status
Simulation time 431151012 ps
CPU time 26.47 seconds
Started Aug 05 05:09:17 PM PDT 24
Finished Aug 05 05:09:43 PM PDT 24
Peak memory 255468 kb
Host smart-4a835f0b-1649-4832-bb90-1423baff560b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27928
75110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2792875110
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.709905703
Short name T450
Test name
Test status
Simulation time 505855858 ps
CPU time 36.07 seconds
Started Aug 05 05:09:06 PM PDT 24
Finished Aug 05 05:09:42 PM PDT 24
Peak memory 255956 kb
Host smart-cc203c7e-4271-40ef-a539-2b7f46876a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70990
5703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.709905703
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2735410358
Short name T267
Test name
Test status
Simulation time 1243713452 ps
CPU time 42.44 seconds
Started Aug 05 05:09:09 PM PDT 24
Finished Aug 05 05:09:51 PM PDT 24
Peak memory 256560 kb
Host smart-abf73ed6-4583-4e0a-b692-e2ceffbdc8ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27354
10358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2735410358
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3021355011
Short name T364
Test name
Test status
Simulation time 263043169 ps
CPU time 10.3 seconds
Started Aug 05 05:09:14 PM PDT 24
Finished Aug 05 05:09:25 PM PDT 24
Peak memory 256452 kb
Host smart-70ad3f41-1580-4f60-a07a-afa0fb5df0ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30213
55011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3021355011
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3670810883
Short name T252
Test name
Test status
Simulation time 17719081557 ps
CPU time 908.19 seconds
Started Aug 05 05:09:00 PM PDT 24
Finished Aug 05 05:24:08 PM PDT 24
Peak memory 282224 kb
Host smart-0966a00b-d8f4-4b24-ad09-b3bd65037345
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670810883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3670810883
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2147471871
Short name T57
Test name
Test status
Simulation time 26171595576 ps
CPU time 1872.73 seconds
Started Aug 05 05:09:12 PM PDT 24
Finished Aug 05 05:40:25 PM PDT 24
Peak memory 287716 kb
Host smart-db6aea82-2998-4abb-89d2-bbf03a3bccb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147471871 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2147471871
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3960853164
Short name T196
Test name
Test status
Simulation time 150737051 ps
CPU time 3.4 seconds
Started Aug 05 05:09:13 PM PDT 24
Finished Aug 05 05:09:16 PM PDT 24
Peak memory 248448 kb
Host smart-7a18af16-c9c8-489e-b9ea-5e314f86cff2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3960853164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3960853164
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3940873396
Short name T690
Test name
Test status
Simulation time 103212388832 ps
CPU time 1354.11 seconds
Started Aug 05 05:09:03 PM PDT 24
Finished Aug 05 05:31:38 PM PDT 24
Peak memory 272352 kb
Host smart-77b2cd1a-a290-40f1-8cc4-37fb997567b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940873396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3940873396
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1853011656
Short name T382
Test name
Test status
Simulation time 3383927388 ps
CPU time 16.84 seconds
Started Aug 05 05:08:59 PM PDT 24
Finished Aug 05 05:09:16 PM PDT 24
Peak memory 248400 kb
Host smart-bd7864cf-e7af-4c7a-8f90-85af25e8f64e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1853011656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1853011656
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.5566127
Short name T233
Test name
Test status
Simulation time 17204027784 ps
CPU time 223.13 seconds
Started Aug 05 05:09:27 PM PDT 24
Finished Aug 05 05:13:10 PM PDT 24
Peak memory 256404 kb
Host smart-6b3799b0-0698-41ef-9a8b-a706d19646e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55661
27 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.5566127
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2422034843
Short name T25
Test name
Test status
Simulation time 269781774 ps
CPU time 28.11 seconds
Started Aug 05 05:09:14 PM PDT 24
Finished Aug 05 05:09:42 PM PDT 24
Peak memory 247840 kb
Host smart-049261b3-ca9d-4c72-8981-ec51a6a3df77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24220
34843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2422034843
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3906872645
Short name T320
Test name
Test status
Simulation time 215792902219 ps
CPU time 2812.28 seconds
Started Aug 05 05:09:02 PM PDT 24
Finished Aug 05 05:55:54 PM PDT 24
Peak memory 288720 kb
Host smart-39298171-de85-4697-9394-447f0374f10b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906872645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3906872645
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2380592413
Short name T609
Test name
Test status
Simulation time 391906644470 ps
CPU time 2523.36 seconds
Started Aug 05 05:09:13 PM PDT 24
Finished Aug 05 05:51:17 PM PDT 24
Peak memory 289080 kb
Host smart-16671317-0d56-49ef-8722-1d040b49bb0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380592413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2380592413
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2592287909
Short name T696
Test name
Test status
Simulation time 11231257231 ps
CPU time 120.79 seconds
Started Aug 05 05:08:58 PM PDT 24
Finished Aug 05 05:10:58 PM PDT 24
Peak memory 255492 kb
Host smart-620e6dbb-48ab-4b42-a3fb-aeea5a447e8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592287909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2592287909
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1117481527
Short name T682
Test name
Test status
Simulation time 829417062 ps
CPU time 25.08 seconds
Started Aug 05 05:09:09 PM PDT 24
Finished Aug 05 05:09:34 PM PDT 24
Peak memory 248264 kb
Host smart-6e9cacb3-22ab-4a79-83e9-541bee4e9b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11174
81527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1117481527
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.12543077
Short name T643
Test name
Test status
Simulation time 208475116 ps
CPU time 9.12 seconds
Started Aug 05 05:08:58 PM PDT 24
Finished Aug 05 05:09:07 PM PDT 24
Peak memory 255468 kb
Host smart-f5850e93-9d7f-4104-a649-4b8f6954c531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12543
077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.12543077
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.172246860
Short name T516
Test name
Test status
Simulation time 189091399 ps
CPU time 12.24 seconds
Started Aug 05 05:09:13 PM PDT 24
Finished Aug 05 05:09:25 PM PDT 24
Peak memory 248732 kb
Host smart-08590f83-afdd-4c65-a93c-c45ecee677cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17224
6860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.172246860
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2532100904
Short name T639
Test name
Test status
Simulation time 1283079120 ps
CPU time 37.39 seconds
Started Aug 05 05:09:00 PM PDT 24
Finished Aug 05 05:09:38 PM PDT 24
Peak memory 256508 kb
Host smart-c06efe2b-5f3b-44f9-80e1-8b649fa1df3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25321
00904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2532100904
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.2230710779
Short name T494
Test name
Test status
Simulation time 79895926824 ps
CPU time 1939.77 seconds
Started Aug 05 05:09:02 PM PDT 24
Finished Aug 05 05:41:22 PM PDT 24
Peak memory 297612 kb
Host smart-31373aeb-6452-45a8-b7c7-efb710f7a009
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230710779 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.2230710779
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.4024431065
Short name T194
Test name
Test status
Simulation time 241333393 ps
CPU time 4.04 seconds
Started Aug 05 05:09:18 PM PDT 24
Finished Aug 05 05:09:22 PM PDT 24
Peak memory 248600 kb
Host smart-e7738f04-a71c-49a7-bf31-a57d817d753e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4024431065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.4024431065
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.323604589
Short name T640
Test name
Test status
Simulation time 171631656548 ps
CPU time 1758.24 seconds
Started Aug 05 05:09:01 PM PDT 24
Finished Aug 05 05:38:20 PM PDT 24
Peak memory 272572 kb
Host smart-7895eb47-5616-41fe-ba20-848cef361bda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323604589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.323604589
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3949512690
Short name T650
Test name
Test status
Simulation time 1697064867 ps
CPU time 20.44 seconds
Started Aug 05 05:09:16 PM PDT 24
Finished Aug 05 05:09:37 PM PDT 24
Peak memory 248184 kb
Host smart-41b2923b-499e-4953-9557-10e0bf0cc989
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3949512690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3949512690
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.519383122
Short name T565
Test name
Test status
Simulation time 1434180607 ps
CPU time 75.37 seconds
Started Aug 05 05:08:55 PM PDT 24
Finished Aug 05 05:10:10 PM PDT 24
Peak memory 256412 kb
Host smart-62987c7d-b8aa-4043-a9cc-9f4a2249f830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51938
3122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.519383122
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2410445250
Short name T687
Test name
Test status
Simulation time 6741088150 ps
CPU time 50.34 seconds
Started Aug 05 05:09:03 PM PDT 24
Finished Aug 05 05:09:54 PM PDT 24
Peak memory 248084 kb
Host smart-5bdff62c-97f4-43ca-8ab9-47aa52cb41b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24104
45250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2410445250
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3522136234
Short name T481
Test name
Test status
Simulation time 152142982051 ps
CPU time 2131.88 seconds
Started Aug 05 05:09:13 PM PDT 24
Finished Aug 05 05:44:46 PM PDT 24
Peak memory 288572 kb
Host smart-94d0a712-297e-405e-b739-c42604525405
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522136234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3522136234
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.4015921086
Short name T46
Test name
Test status
Simulation time 9172773958 ps
CPU time 896.89 seconds
Started Aug 05 05:08:55 PM PDT 24
Finished Aug 05 05:23:52 PM PDT 24
Peak memory 272284 kb
Host smart-6371a2c9-a1c7-417a-8ac3-adb7bc523a8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015921086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.4015921086
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2554195830
Short name T677
Test name
Test status
Simulation time 42676639079 ps
CPU time 259.65 seconds
Started Aug 05 05:09:15 PM PDT 24
Finished Aug 05 05:13:35 PM PDT 24
Peak memory 248192 kb
Host smart-6673ef3a-4704-4010-8190-7a500dfe5c4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554195830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2554195830
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2311794143
Short name T413
Test name
Test status
Simulation time 459559051 ps
CPU time 19.4 seconds
Started Aug 05 05:09:03 PM PDT 24
Finished Aug 05 05:09:22 PM PDT 24
Peak memory 255744 kb
Host smart-392259fa-0255-4193-b5d8-51d8000a0951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23117
94143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2311794143
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1212276354
Short name T67
Test name
Test status
Simulation time 211771026 ps
CPU time 24.26 seconds
Started Aug 05 05:09:13 PM PDT 24
Finished Aug 05 05:09:37 PM PDT 24
Peak memory 248084 kb
Host smart-3b9e31fb-ed63-466a-907b-763f213281ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12122
76354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1212276354
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.4258713203
Short name T483
Test name
Test status
Simulation time 178937568 ps
CPU time 19.39 seconds
Started Aug 05 05:08:56 PM PDT 24
Finished Aug 05 05:09:15 PM PDT 24
Peak memory 256064 kb
Host smart-7a04f438-9856-4107-b6a0-be73bc39c227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42587
13203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.4258713203
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2982943054
Short name T433
Test name
Test status
Simulation time 317937209 ps
CPU time 28.4 seconds
Started Aug 05 05:09:01 PM PDT 24
Finished Aug 05 05:09:30 PM PDT 24
Peak memory 256188 kb
Host smart-e0f39a8e-a16f-4939-b3ab-95cd7bd30956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29829
43054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2982943054
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3525414567
Short name T423
Test name
Test status
Simulation time 53472714373 ps
CPU time 3186.35 seconds
Started Aug 05 05:08:57 PM PDT 24
Finished Aug 05 06:02:04 PM PDT 24
Peak memory 304224 kb
Host smart-530c581e-7e4f-4b4f-9bef-891011aee1a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525414567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3525414567
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2168370985
Short name T198
Test name
Test status
Simulation time 102640513 ps
CPU time 3.96 seconds
Started Aug 05 05:09:04 PM PDT 24
Finished Aug 05 05:09:08 PM PDT 24
Peak memory 248576 kb
Host smart-f8c921f3-e2a8-4b27-82ce-e855401ec02d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2168370985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2168370985
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3539110338
Short name T593
Test name
Test status
Simulation time 30231521182 ps
CPU time 1603.66 seconds
Started Aug 05 05:09:11 PM PDT 24
Finished Aug 05 05:35:54 PM PDT 24
Peak memory 264732 kb
Host smart-6504a40c-f3cf-452c-8fb8-4ea5e68cfeeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539110338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3539110338
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2659040575
Short name T403
Test name
Test status
Simulation time 1640084201 ps
CPU time 15.56 seconds
Started Aug 05 05:09:16 PM PDT 24
Finished Aug 05 05:09:32 PM PDT 24
Peak memory 248268 kb
Host smart-a0ee5ac7-5d52-4ced-a869-878d24354165
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2659040575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2659040575
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.4108557138
Short name T246
Test name
Test status
Simulation time 1362469744 ps
CPU time 112.08 seconds
Started Aug 05 05:09:01 PM PDT 24
Finished Aug 05 05:10:53 PM PDT 24
Peak memory 256456 kb
Host smart-c0a02123-d74f-4df1-b938-c6f71790b2f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41085
57138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.4108557138
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2396991929
Short name T421
Test name
Test status
Simulation time 560716254 ps
CPU time 11.35 seconds
Started Aug 05 05:09:13 PM PDT 24
Finished Aug 05 05:09:24 PM PDT 24
Peak memory 255352 kb
Host smart-213e91df-5293-4d67-95f0-b18364f0bd66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23969
91929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2396991929
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.4085997176
Short name T100
Test name
Test status
Simulation time 9818149947 ps
CPU time 1043.52 seconds
Started Aug 05 05:09:05 PM PDT 24
Finished Aug 05 05:26:29 PM PDT 24
Peak memory 281068 kb
Host smart-74e3111d-e119-496d-bba7-3f101d1294ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085997176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.4085997176
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.161801381
Short name T302
Test name
Test status
Simulation time 40681583126 ps
CPU time 223.55 seconds
Started Aug 05 05:09:03 PM PDT 24
Finished Aug 05 05:12:47 PM PDT 24
Peak memory 248340 kb
Host smart-abab0caa-99ee-42dd-ac57-0908ede53b74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161801381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.161801381
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1339965480
Short name T473
Test name
Test status
Simulation time 327249745 ps
CPU time 8.78 seconds
Started Aug 05 05:09:01 PM PDT 24
Finished Aug 05 05:09:10 PM PDT 24
Peak memory 248344 kb
Host smart-8879c065-73ae-4bc4-ac45-5662e79e4840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13399
65480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1339965480
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3136207776
Short name T479
Test name
Test status
Simulation time 144448991 ps
CPU time 10.55 seconds
Started Aug 05 05:09:14 PM PDT 24
Finished Aug 05 05:09:25 PM PDT 24
Peak memory 247484 kb
Host smart-a31c2345-7592-4111-8049-973dbee85325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31362
07776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3136207776
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3380763091
Short name T584
Test name
Test status
Simulation time 165897940 ps
CPU time 12.24 seconds
Started Aug 05 05:09:03 PM PDT 24
Finished Aug 05 05:09:15 PM PDT 24
Peak memory 247760 kb
Host smart-e31e1e9b-f0c4-4acd-b30e-c13bd5803c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33807
63091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3380763091
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3192642776
Short name T203
Test name
Test status
Simulation time 175636867 ps
CPU time 11.75 seconds
Started Aug 05 05:09:01 PM PDT 24
Finished Aug 05 05:09:13 PM PDT 24
Peak memory 255060 kb
Host smart-f8d19d1c-e6f9-427d-a161-64e2f049fafc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31926
42776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3192642776
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.236945222
Short name T51
Test name
Test status
Simulation time 12010684224 ps
CPU time 1555.58 seconds
Started Aug 05 05:09:17 PM PDT 24
Finished Aug 05 05:35:12 PM PDT 24
Peak memory 289328 kb
Host smart-3f6b6867-e4dc-4df0-b118-0c46ef3300a3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236945222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.236945222
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.3526481629
Short name T574
Test name
Test status
Simulation time 79949498265 ps
CPU time 3608.73 seconds
Started Aug 05 05:09:18 PM PDT 24
Finished Aug 05 06:09:27 PM PDT 24
Peak memory 304992 kb
Host smart-f3e11cbc-80c5-4edc-a2c4-38b8a23a1fe1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526481629 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.3526481629
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3020016469
Short name T185
Test name
Test status
Simulation time 43686347 ps
CPU time 2.32 seconds
Started Aug 05 05:09:06 PM PDT 24
Finished Aug 05 05:09:09 PM PDT 24
Peak memory 248596 kb
Host smart-42e1a2c1-8c1e-4ce6-a574-99e845e44e49
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3020016469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3020016469
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3743492987
Short name T658
Test name
Test status
Simulation time 10790780963 ps
CPU time 1139.67 seconds
Started Aug 05 05:09:15 PM PDT 24
Finished Aug 05 05:28:15 PM PDT 24
Peak memory 289260 kb
Host smart-8a3476fe-a8bf-440e-b885-fda620242b2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743492987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3743492987
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2435038921
Short name T226
Test name
Test status
Simulation time 1576798772 ps
CPU time 33.71 seconds
Started Aug 05 05:09:23 PM PDT 24
Finished Aug 05 05:09:57 PM PDT 24
Peak memory 248364 kb
Host smart-e6aa99ed-f005-447a-8b0b-e28a8080b005
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2435038921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2435038921
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1041074019
Short name T668
Test name
Test status
Simulation time 11097082344 ps
CPU time 63.17 seconds
Started Aug 05 05:09:03 PM PDT 24
Finished Aug 05 05:10:07 PM PDT 24
Peak memory 255808 kb
Host smart-c667f777-d1b5-4500-a947-b76fcaa50462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10410
74019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1041074019
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.4208662662
Short name T672
Test name
Test status
Simulation time 2933647371 ps
CPU time 40.32 seconds
Started Aug 05 05:09:28 PM PDT 24
Finished Aug 05 05:10:09 PM PDT 24
Peak memory 248368 kb
Host smart-92dfd2d0-1ce2-4adc-b837-83be1363d063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42086
62662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.4208662662
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3467039832
Short name T461
Test name
Test status
Simulation time 43344842328 ps
CPU time 2369.4 seconds
Started Aug 05 05:09:17 PM PDT 24
Finished Aug 05 05:48:47 PM PDT 24
Peak memory 282380 kb
Host smart-ef35c30d-0c06-4d11-ab6c-31be13fb230d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467039832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3467039832
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1645660906
Short name T324
Test name
Test status
Simulation time 7481520656 ps
CPU time 163.19 seconds
Started Aug 05 05:09:30 PM PDT 24
Finished Aug 05 05:12:13 PM PDT 24
Peak memory 248428 kb
Host smart-4bfe5565-d73b-4596-8ff4-976704f63b8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645660906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1645660906
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2292378491
Short name T448
Test name
Test status
Simulation time 9307250149 ps
CPU time 62.2 seconds
Started Aug 05 05:09:17 PM PDT 24
Finished Aug 05 05:10:19 PM PDT 24
Peak memory 256588 kb
Host smart-6acd783d-2515-4909-9aa4-c167a449ea52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22923
78491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2292378491
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.582283539
Short name T560
Test name
Test status
Simulation time 1077587446 ps
CPU time 31.2 seconds
Started Aug 05 05:09:13 PM PDT 24
Finished Aug 05 05:09:44 PM PDT 24
Peak memory 255620 kb
Host smart-716459dd-eca4-447d-b7fb-a27e10bbd116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58228
3539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.582283539
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.4094405371
Short name T289
Test name
Test status
Simulation time 752917708 ps
CPU time 41.47 seconds
Started Aug 05 05:09:02 PM PDT 24
Finished Aug 05 05:09:43 PM PDT 24
Peak memory 256012 kb
Host smart-98d320ae-27e7-42da-ab24-4c6d04b0665a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40944
05371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.4094405371
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.130782955
Short name T20
Test name
Test status
Simulation time 124182086 ps
CPU time 13.23 seconds
Started Aug 05 05:09:31 PM PDT 24
Finished Aug 05 05:09:44 PM PDT 24
Peak memory 255560 kb
Host smart-4c80e7d7-e7a3-4807-85c3-c2d16998e447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13078
2955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.130782955
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1825565386
Short name T642
Test name
Test status
Simulation time 23370752209 ps
CPU time 1413.07 seconds
Started Aug 05 05:09:03 PM PDT 24
Finished Aug 05 05:32:36 PM PDT 24
Peak memory 289288 kb
Host smart-6749cfb2-629d-4e3e-bbbb-e6b312cb6413
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825565386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1825565386
Directory /workspace/9.alert_handler_stress_all/latest
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