Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	52877	1			T15	58		T37	17		T19	16
class_i[0x1]	76697	1			T11	94		T7	5		T15	15
class_i[0x2]	49446	1			T15	590		T31	2337		T20	7
class_i[0x3]	57744	1			T15	308		T20	1		T64	8

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	58261	1			T11	19		T7	2		T15	186
alert[0x1]	59155	1			T11	19		T7	1		T15	209
alert[0x2]	58684	1			T11	26		T7	1		T15	347
alert[0x3]	60664	1			T11	30		T7	1		T15	229

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

236482

1

T11

94

T15

971

T31

2343

esc_ping_fail

282

1

T7

5

T19

7

T20

11

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	58177	1			T11	19		T15	186		T31	531
esc_integrity_fail	alert[0x1]	59096	1			T11	19		T15	209		T31	601
esc_integrity_fail	alert[0x2]	58606	1			T11	26		T15	347		T31	582
esc_integrity_fail	alert[0x3]	60603	1			T11	30		T15	229		T31	629
esc_ping_fail	alert[0x0]	84	1			T7	2		T19	2		T20	4
esc_ping_fail	alert[0x1]	59	1			T7	1		T19	1		T20	2
esc_ping_fail	alert[0x2]	78	1			T7	1		T19	2		T20	4
esc_ping_fail	alert[0x3]	61	1			T7	1		T19	2		T20	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	52809	1			T15	58		T37	17		T19	16
esc_integrity_fail	class_i[0x1]	76632	1			T11	94		T15	15		T31	6
esc_integrity_fail	class_i[0x2]	49354	1			T15	590		T31	2337		T23	1
esc_integrity_fail	class_i[0x3]	57687	1			T15	308		T64	8		T59	2835
esc_ping_fail	class_i[0x0]	68	1			T20	2		T233	2		T306	1
esc_ping_fail	class_i[0x1]	65	1			T7	5		T19	7		T20	1
esc_ping_fail	class_i[0x2]	92	1			T20	7		T233	3		T96	1
esc_ping_fail	class_i[0x3]	57	1			T20	1		T306	1		T310	9