Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	657025895	0	0	617
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	657025895	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	657025895	656856599	0	0
tb.dut.CheckAccuCntDw	0	0	617	617	0	0
tb.dut.CheckEscCntDw	0	0	617	617	0	0
tb.dut.CheckNAlerts	0	0	617	617	0	0
tb.dut.CheckNClasses	0	0	617	617	0	0
tb.dut.CheckNEscSev	0	0	617	617	0	0
tb.dut.CrashdumpKnownO_A	0	0	657025895	656856599	0	0
tb.dut.EdnKnownO_A	0	0	657025895	656856599	0	0
tb.dut.EscPKnownO_A	0	0	657025895	656856599	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	657025895	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	657025895	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	657025895	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	657025895	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	657025895	80	0	0
tb.dut.IrqAKnownO_A	0	0	657025895	656856599	0	0
tb.dut.IrqBKnownO_A	0	0	657025895	656856599	0	0
tb.dut.IrqCKnownO_A	0	0	657025895	656856599	0	0
tb.dut.IrqDKnownO_A	0	0	657025895	656856599	0	0
tb.dut.TlAReadyKnownO_A	0	0	657025895	656856599	0	0
tb.dut.TlDValidKnownO_A	0	0	657025895	656856599	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	684900579	2915582	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	684900579	20410	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	684900579	20881	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	684900579	20451	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	684900579	20805	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	684900579	20795	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	684900579	20122	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	684900579	20184	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	684900579	20486	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	684900579	20571	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	684900579	20410	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	684900579	20102	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	684900579	20437	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	684900579	20358	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	684900579	20284	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	684900579	20617	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	684900579	20636	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	684900579	20686	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	684900579	20662	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	684900579	20248	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	684900579	20177	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	684900579	20379	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	684900579	20285	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	684900579	20602	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	684900579	20715	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	684900579	20798	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	684900579	20386	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	684900579	20494	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	684900579	20540	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	684900579	20625	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	684900579	20226	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	684900579	20223	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	684900579	20505	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	684900579	20456	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	684900579	20530	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	684900579	20469	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	684900579	20658	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	684900579	20353	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	684900579	20489	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	684900579	20496	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	684900579	20520	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	684900579	20819	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	684900579	20606	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	684900579	20388	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	684900579	20449	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	684900579	20655	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	684900579	20655	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	684900579	20498	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	684900579	20577	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	684900579	20687	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	684900579	20581	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	684900579	20697	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	684900579	19915	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	684900579	20223	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	684900579	20542	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	684900579	20222	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	684900579	20451	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	684900579	20127	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	684900579	20258	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	684900579	20727	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	684900579	20312	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	684900579	20166	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	684900579	20317	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	684900579	20751	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	684900579	20638	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	684900579	20104	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	684900579	20453	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	684900579	20320	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	684900579	20632	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	684900579	20871	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	684900579	41511	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	684900579	20840	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	684900579	20611	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	684900579	20524	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	684900579	20549	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	684900579	20019	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	684900579	20474	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	684900579	20637	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	684900579	20565	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	657025895	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	657025895	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	657025895	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	657025895	5160	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	657025895	244091	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	657025895	288349021	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	657025895	237	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	657025895	829	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	657025895	46	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	657025895	402	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	656891199	226675189	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	657025895	898	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	657025895	881	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	657025895	864	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	657025895	839	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	657025895	1234	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	657025895	132352	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	657025895	1135	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	657025895	50	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	657025895	1326	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	657025895	1086	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	656890505	656823380	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	617	617	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	657025895	656856599	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	657025895	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	657025895	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	657025895	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	657025895	2827	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	657025895	202273	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	657025895	372643440	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	657025895	239	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	657025895	446	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	657025895	31	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	657025895	194	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	656891199	301396051	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	657025895	528	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	657025895	517	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	657025895	511	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	657025895	499	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	657025895	1119	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	657025895	109813	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	657025895	1032	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	657025895	55	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	657025895	1251	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	657025895	1011	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	656890505	656823380	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	617	617	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	657025895	656856599	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	657025895	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	657025895	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	657025895	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	657025895	2228	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	657025895	187874	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	657025895	356254905	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	657025895	246	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	657025895	471	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	657025895	15	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	657025895	199	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	656891199	288540315	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	657025895	531	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	657025895	527	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	657025895	513	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	657025895	500	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	657025895	1446	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	657025895	139504	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	657025895	1375	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	657025895	55	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	657025895	1346	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	657025895	1106	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	656890505	656823380	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	617	617	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	657025895	656856599	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	657025895	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	657025895	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	657025895	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	657025895	5497	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	657025895	166124	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	657025895	383155373	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	657025895	293	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	657025895	509	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	657025895	15	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	657025895	221	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	656891199	300519277	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	657025895	563	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	657025895	557	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	657025895	545	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	657025895	536	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	657025895	1078	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	657025895	116632	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	657025895	1016	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	657025895	45	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	657025895	1333	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	657025895	1093	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	656890505	656823380	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	617	617	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	657025895	656856599	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	684900579	129698741	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	684900579	684195231	0	0
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