Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	160	1			T39	1		T41	1		T42	1
index[0x1]	166	1			T6	1		T12	1		T18	1
index[0x2]	150	1			T6	1		T18	1		T13	1
index[0x3]	176	1			T7	1		T18	1		T22	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	191	1			T6	2		T12	1		T18	1
lens_less_than_1000[1]	123	1			T15	2		T22	3		T38	1
lens_less_than_1000[2]	81	1			T7	1		T18	1		T31	2
lens_less_than_1000[3]	73	1			T62	1		T66	2		T24	2
lens_less_than_1000[4]	62	1			T18	1		T13	1		T14	1
lens_less_than_1000[5]	52	1			T64	1		T41	1		T26	1
lens_less_than_1000[6]	24	1			T27	1		T276	1		T92	1
lens_less_than_1000[7]	10	1			T72	1		T77	1		T52	1
lens_less_than_1000[8]	14	1			T59	1		T277	2		T77	5
lens_less_than_1000[9]	5	1			T237	3		T278	2		-	-
len_2	17	1			T100	1		T273	1		T279	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[9]]	0	1	1
[index[0x2]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	42	1			T39	1		T62	1		T24	1
index[0x0]	lens_less_than_1000[1]	28	1			T42	1		T30	1		T28	1
index[0x0]	lens_less_than_1000[2]	21	1			T29	1		T280	1		T218	1
index[0x0]	lens_less_than_1000[3]	29	1			T62	1		T66	2		T106	5
index[0x0]	lens_less_than_1000[4]	14	1			T276	1		T72	1		T281	1
index[0x0]	lens_less_than_1000[5]	18	1			T41	1		T224	1		T282	1
index[0x0]	lens_less_than_1000[6]	5	1			T283	1		T284	1		T285	1
index[0x0]	lens_less_than_1000[7]	1	1			T72	1		-	-		-	-
index[0x0]	lens_less_than_1000[8]	1	1			T277	1		-	-		-	-
index[0x0]	len_2	1	1			T273	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	55	1			T6	1		T12	1		T13	1
index[0x1]	lens_less_than_1000[1]	30	1			T22	2		T286	1		T273	1
index[0x1]	lens_less_than_1000[2]	24	1			T18	1		T31	1		T20	1
index[0x1]	lens_less_than_1000[3]	18	1			T25	1		T245	1		T257	1
index[0x1]	lens_less_than_1000[4]	19	1			T14	1		T54	1		T27	1
index[0x1]	lens_less_than_1000[5]	7	1			T64	1		T68	1		T48	1
index[0x1]	lens_less_than_1000[6]	5	1			T287	1		T102	1		T288	1
index[0x1]	lens_less_than_1000[7]	3	1			T77	1		T52	1		T289	1
index[0x1]	lens_less_than_1000[8]	3	1			T59	1		T259	1		T290	1
index[0x1]	lens_less_than_1000[9]	1	1			T237	1		-	-		-	-
index[0x1]	len_2	1	1			T172	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	37	1			T6	1		T18	1		T39	1
index[0x2]	lens_less_than_1000[1]	35	1			T15	2		T63	1		T24	2
index[0x2]	lens_less_than_1000[2]	15	1			T31	1		T20	1		T291	1
index[0x2]	lens_less_than_1000[3]	11	1			T45	1		T236	1		T245	1
index[0x2]	lens_less_than_1000[4]	17	1			T13	1		T292	1		T27	2
index[0x2]	lens_less_than_1000[5]	12	1			T85	1		T224	1		T270	1
index[0x2]	lens_less_than_1000[6]	5	1			T27	1		T92	1		T76	1
index[0x2]	lens_less_than_1000[7]	2	1			T293	1		T248	1		-	-
index[0x2]	lens_less_than_1000[8]	9	1			T277	1		T77	5		T105	2
index[0x2]	len_2	7	1			T100	1		T294	6		-	-
index[0x3]	lens_less_than_1000[0]	57	1			T37	1		T40	1		T41	2
index[0x3]	lens_less_than_1000[1]	30	1			T22	1		T38	1		T39	1
index[0x3]	lens_less_than_1000[2]	21	1			T7	1		T30	1		T48	1
index[0x3]	lens_less_than_1000[3]	15	1			T24	2		T29	2		T295	1
index[0x3]	lens_less_than_1000[4]	12	1			T18	1		T64	1		T190	1
index[0x3]	lens_less_than_1000[5]	15	1			T26	1		T48	1		T52	1
index[0x3]	lens_less_than_1000[6]	9	1			T276	1		T291	1		T93	1
index[0x3]	lens_less_than_1000[7]	4	1			T188	1		T296	1		T297	1
index[0x3]	lens_less_than_1000[8]	1	1			T298	1		-	-		-	-
index[0x3]	lens_less_than_1000[9]	4	1			T237	2		T278	2		-	-
index[0x3]	len_2	8	1			T279	1		T299	1		T300	1