Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	50	1			T15	1		T64	1		T45	2
class_index[0x1]	55	1			T13	2		T62	1		T25	1
class_index[0x2]	55	1			T15	2		T22	2		T66	1
class_index[0x3]	46	1			T64	1		T25	1		T27	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	72	1			T13	2		T15	2		T62	1
intr_timeout_cnt[1]	51	1			T15	1		T22	2		T25	1
intr_timeout_cnt[2]	14	1			T64	1		T29	1		T72	1
intr_timeout_cnt[3]	15	1			T27	1		T111	1		T86	1
intr_timeout_cnt[4]	11	1			T72	2		T249	1		T250	1
intr_timeout_cnt[5]	12	1			T27	1		T71	1		T251	1
intr_timeout_cnt[6]	14	1			T27	2		T71	1		T52	1
intr_timeout_cnt[7]	11	1			T64	1		T27	1		T69	1
intr_timeout_cnt[8]	1	1			T252	1		-	-		-	-
intr_timeout_cnt[9]	5	1			T66	1		T102	1		T105	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0] , class_index[0x1]]	[intr_timeout_cnt[8]]	--	--	2
[class_index[0x3]]	[intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	2

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	15	1			T45	1		T27	1		T48	1
class_index[0x0]	intr_timeout_cnt[1]	14	1			T15	1		T45	1		T30	2
class_index[0x0]	intr_timeout_cnt[2]	4	1			T29	1		T253	1		T254	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T254	1		T255	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	4	1			T72	2		T237	1		T256	1
class_index[0x0]	intr_timeout_cnt[5]	4	1			T27	1		T71	1		T257	1
class_index[0x0]	intr_timeout_cnt[6]	3	1			T237	1		T255	2		-	-
class_index[0x0]	intr_timeout_cnt[7]	3	1			T64	1		T27	1		T258	1
class_index[0x0]	intr_timeout_cnt[9]	1	1			T105	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	24	1			T13	2		T62	1		T25	1
class_index[0x1]	intr_timeout_cnt[1]	14	1			T52	3		T101	1		T237	1
class_index[0x1]	intr_timeout_cnt[2]	4	1			T172	1		T90	1		T259	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T27	1		T260	1		T261	1
class_index[0x1]	intr_timeout_cnt[4]	2	1			T262	1		T255	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	2	1			T263	1		T264	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	1	1			T265	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	4	1			T69	1		T266	2		T237	1
class_index[0x1]	intr_timeout_cnt[9]	1	1			T102	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	16	1			T15	2		T45	1		T51	1
class_index[0x2]	intr_timeout_cnt[1]	14	1			T22	2		T25	1		T47	1
class_index[0x2]	intr_timeout_cnt[2]	2	1			T72	1		T267	1		-	-
class_index[0x2]	intr_timeout_cnt[3]	6	1			T102	1		T103	1		T268	1
class_index[0x2]	intr_timeout_cnt[4]	2	1			T250	1		T269	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	2	1			T251	1		T237	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	6	1			T27	1		T71	1		T86	1
class_index[0x2]	intr_timeout_cnt[7]	3	1			T72	1		T270	1		T268	1
class_index[0x2]	intr_timeout_cnt[8]	1	1			T252	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	3	1			T66	1		T87	1		T252	1
class_index[0x3]	intr_timeout_cnt[0]	17	1			T25	1		T112	1		T99	1
class_index[0x3]	intr_timeout_cnt[1]	9	1			T27	1		T30	1		T113	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T64	1		T247	1		T271	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T111	1		T86	1		T263	1
class_index[0x3]	intr_timeout_cnt[4]	3	1			T249	1		T272	2		-	-
class_index[0x3]	intr_timeout_cnt[5]	4	1			T273	1		T258	1		T274	1
class_index[0x3]	intr_timeout_cnt[6]	4	1			T27	1		T52	1		T102	1
class_index[0x3]	intr_timeout_cnt[7]	1	1			T266	1		-	-		-	-