Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	343617	1			T2	23		T3	5		T6	897
all_values[1]	343617	1			T2	23		T3	5		T6	897
all_values[2]	343617	1			T2	23		T3	5		T6	897
all_values[3]	343617	1			T2	23		T3	5		T6	897

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

684405

1

T2

51

T3

12

T6

1767

auto[1]

690063

1

T2

41

T3

8

T6

1821

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

806494

1

T2

87

T3

18

T6

2816

auto[1]

567974

1

T2

5

T3

2

T6

772

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	97579	1			T2	5		T3	3		T6	336
all_values[0]	auto[0]	auto[1]	73323	1			T2	3		T3	2		T6	110
all_values[0]	auto[1]	auto[0]	99017	1			T2	13		T6	343		T11	11
all_values[0]	auto[1]	auto[1]	73698	1			T2	2		T6	108		T11	6
all_values[1]	auto[0]	auto[0]	101208	1			T2	15		T3	2		T6	271
all_values[1]	auto[0]	auto[1]	70033	1			T6	164		T11	6		T17	247
all_values[1]	auto[1]	auto[0]	102289	1			T2	8		T3	3		T6	286
all_values[1]	auto[1]	auto[1]	70087	1			T6	176		T11	8		T7	5
all_values[2]	auto[0]	auto[0]	101192	1			T2	14		T6	332		T11	4
all_values[2]	auto[0]	auto[1]	70214	1			T6	104		T11	4		T17	257
all_values[2]	auto[1]	auto[0]	102073	1			T2	9		T3	5		T6	353
all_values[2]	auto[1]	auto[1]	70138	1			T6	108		T11	9		T7	4
all_values[3]	auto[0]	auto[0]	100799	1			T2	14		T3	5		T6	449
all_values[3]	auto[0]	auto[1]	70057	1			T6	1		T11	6		T17	248
all_values[3]	auto[1]	auto[0]	102337	1			T2	9		T6	446		T11	7
all_values[3]	auto[1]	auto[1]	70424	1			T6	1		T11	7		T17	230