Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	343617	1			T2	23		T3	5		T6	897
all_pins[1]	343617	1			T2	23		T3	5		T6	897
all_pins[2]	343617	1			T2	23		T3	5		T6	897
all_pins[3]	343617	1			T2	23		T3	5		T6	897

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1090121	1			T2	90		T3	20		T6	3195
values[0x1]	284347	1			T2	2		T6	393		T11	30
transitions[0x0=>0x1]	188690	1			T2	2		T6	301		T11	15
transitions[0x1=>0x0]	188959	1			T2	2		T6	301		T11	15

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	269919	1			T2	21		T3	5		T6	789
all_pins[0]	values[0x1]	73698	1			T2	2		T6	108		T11	6
all_pins[0]	transitions[0x0=>0x1]	72994	1			T2	2		T6	108		T11	6
all_pins[0]	transitions[0x1=>0x0]	69989	1			T6	1		T11	7		T17	230
all_pins[1]	values[0x0]	273530	1			T2	23		T3	5		T6	721
all_pins[1]	values[0x1]	70087	1			T6	176		T11	8		T7	5
all_pins[1]	transitions[0x0=>0x1]	38054	1			T6	129		T11	4		T7	5
all_pins[1]	transitions[0x1=>0x0]	41665	1			T2	2		T6	61		T11	2
all_pins[2]	values[0x0]	273479	1			T2	23		T3	5		T6	789
all_pins[2]	values[0x1]	70138	1			T6	108		T11	9		T7	4
all_pins[2]	transitions[0x0=>0x1]	38803	1			T6	63		T11	3		T7	3
all_pins[2]	transitions[0x1=>0x0]	38752	1			T6	131		T11	2		T7	4
all_pins[3]	values[0x0]	273193	1			T2	23		T3	5		T6	896
all_pins[3]	values[0x1]	70424	1			T6	1		T11	7		T17	230
all_pins[3]	transitions[0x0=>0x1]	38839	1			T6	1		T11	2		T17	130
all_pins[3]	transitions[0x1=>0x0]	38553	1			T6	108		T11	4		T7	4