Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287	1			T152	7		T153	4		T234	7
all_values[1]	287	1			T152	7		T153	4		T234	7
all_values[2]	287	1			T152	7		T153	4		T234	7
all_values[3]	287	1			T152	7		T153	4		T234	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

587

1

T152

17

T153

10

T234

9

auto[1]

561

1

T152

11

T153

6

T234

19

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

425

1

T152

12

T153

11

T234

11

auto[1]

723

1

T152

16

T153

5

T234

17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

672

1

T152

16

T153

12

T234

17

auto[1]

476

1

T152

12

T153

4

T234

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

56

1

T152

3

T153

1

T234

2

all_values[0]

auto[0]

auto[0]

auto[1]

26

1

T152

1

T346

1

T347

1

all_values[0]

auto[0]

auto[1]

auto[0]

66

1

T152

1

T153

2

T346

1

all_values[0]

auto[0]

auto[1]

auto[1]

24

1

T234

2

T348

1

T347

2

all_values[0]

auto[1]

auto[0]

auto[1]

56

1

T152

1

T153

1

T346

1

all_values[0]

auto[1]

auto[1]

auto[1]

59

1

T152

1

T234

3

T346

1

all_values[1]

auto[0]

auto[0]

auto[0]

50

1

T152

3

T153

4

T234

2

all_values[1]

auto[0]

auto[0]

auto[1]

32

1

T348

2

T349

1

T350

2

all_values[1]

auto[0]

auto[1]

auto[0]

41

1

T234

2

T346

1

T348

1

all_values[1]

auto[0]

auto[1]

auto[1]

38

1

T152

1

T348

1

T347

1

all_values[1]

auto[1]

auto[0]

auto[1]

58

1

T234

1

T348

1

T243

3

all_values[1]

auto[1]

auto[1]

auto[1]

68

1

T152

3

T234

2

T346

2

all_values[2]

auto[0]

auto[0]

auto[0]

58

1

T152

1

T153

1

T234

1

all_values[2]

auto[0]

auto[0]

auto[1]

33

1

T152

2

T153

1

T234

1

all_values[2]

auto[0]

auto[1]

auto[0]

48

1

T152

1

T348

1

T347

2

all_values[2]

auto[0]

auto[1]

auto[1]

35

1

T234

2

T346

1

T348

2

all_values[2]

auto[1]

auto[0]

auto[1]

62

1

T152

3

T153

1

T346

1

all_values[2]

auto[1]

auto[1]

auto[1]

51

1

T153

1

T234

3

T346

1

all_values[3]

auto[0]

auto[0]

auto[0]

53

1

T153

1

T234

2

T243

1

all_values[3]

auto[0]

auto[0]

auto[1]

30

1

T346

1

T243

2

T351

1

all_values[3]

auto[0]

auto[1]

auto[0]

53

1

T152

3

T153

2

T234

2

all_values[3]

auto[0]

auto[1]

auto[1]

29

1

T234

1

T346

1

T348

2

all_values[3]

auto[1]

auto[0]

auto[1]

73

1

T152

3

T346

2

T348

3

all_values[3]

auto[1]

auto[1]

auto[1]

49

1

T152

1

T153

1

T234

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal