Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	87479	1			T14	878		T15	5		T21	1204
accum_cnt_1000	227962	1			T4	49		T18	511		T14	1235
accum_cnt_100	26214	1			T4	49		T18	121		T14	84
accum_cnt_50	57431	1			T11	31		T12	3		T4	39
accum_cnt_10	182805	1			T2	8		T3	2		T6	1341
accum_cnt_0	388512	1			T2	60		T3	10		T6	1379

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	254056	1			T2	17		T3	3		T6	680
class_index[0x1]	254056	1			T2	17		T3	3		T6	680
class_index[0x2]	254056	1			T2	17		T3	3		T6	680
class_index[0x3]	254056	1			T2	17		T3	3		T6	680

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	25458	1			T21	585		T39	632		T23	254
class_index[0x0]	accum_cnt_1000	67405	1			T4	17		T18	511		T21	494
class_index[0x0]	accum_cnt_100	8691	1			T4	28		T18	121		T15	12
class_index[0x0]	accum_cnt_50	16160	1			T11	7		T12	3		T4	23
class_index[0x0]	accum_cnt_10	45883	1			T2	8		T3	2		T11	12
class_index[0x0]	accum_cnt_0	77060	1			T2	9		T3	1		T6	680
class_index[0x1]	accum_cnt_2000	20829	1			T14	443		T54	32		T39	367
class_index[0x1]	accum_cnt_1000	52182	1			T4	32		T14	406		T15	150
class_index[0x1]	accum_cnt_100	5515	1			T4	21		T14	25		T15	78
class_index[0x1]	accum_cnt_50	15122	1			T11	20		T4	16		T13	22
class_index[0x1]	accum_cnt_10	46253	1			T6	673		T11	1		T7	15
class_index[0x1]	accum_cnt_0	101844	1			T2	17		T3	3		T6	7
class_index[0x2]	accum_cnt_2000	23151	1			T21	619		T31	241		T39	683
class_index[0x2]	accum_cnt_1000	59620	1			T21	590		T31	210		T38	1073
class_index[0x2]	accum_cnt_100	6375	1			T15	37		T21	28		T31	9
class_index[0x2]	accum_cnt_50	9605	1			T13	22		T15	8		T21	24
class_index[0x2]	accum_cnt_10	45126	1			T4	73		T13	8		T16	1336
class_index[0x2]	accum_cnt_0	99932	1			T2	17		T3	3		T6	680
class_index[0x3]	accum_cnt_2000	18041	1			T14	435		T15	5		T54	118
class_index[0x3]	accum_cnt_1000	48755	1			T14	829		T15	228		T54	522
class_index[0x3]	accum_cnt_100	5633	1			T14	59		T15	103		T54	27
class_index[0x3]	accum_cnt_50	16544	1			T11	4		T14	46		T15	97
class_index[0x3]	accum_cnt_10	45543	1			T6	668		T11	10		T4	74
class_index[0x3]	accum_cnt_0	109676	1			T2	17		T3	3		T6	12