Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3697	1			T15	5		T20	1		T39	44
alert[0x1]	6157	1			T11	3		T59	613		T66	4
alert[0x2]	5683	1			T15	12		T39	57		T42	72
alert[0x3]	13856	1			T233	1		T23	72		T24	7
alert[0x4]	6875	1			T19	1		T39	208		T42	7
alert[0x5]	2217	1			T37	18		T59	27		T68	37
alert[0x6]	3555	1			T15	7		T23	139		T306	1
alert[0x7]	6269	1			T20	1		T39	229		T59	96
alert[0x8]	4836	1			T39	23		T42	291		T59	199
alert[0x9]	10085	1			T19	1		T23	275		T59	80
alert[0xa]	10985	1			T11	10		T15	1		T22	1
alert[0xb]	5650	1			T7	1		T19	1		T39	8
alert[0xc]	6119	1			T15	3		T19	1		T39	16
alert[0xd]	8513	1			T23	243		T59	28		T25	2518
alert[0xe]	2233	1			T22	13		T19	1		T20	2
alert[0xf]	8246	1			T15	3		T22	1		T20	1
alert[0x10]	8294	1			T15	3		T31	4		T66	3
alert[0x11]	4745	1			T23	380		T42	24		T66	5
alert[0x12]	6570	1			T22	7		T39	11		T46	26
alert[0x13]	2517	1			T11	2		T15	3		T19	1
alert[0x14]	7078	1			T19	1		T20	1		T59	520
alert[0x15]	10918	1			T22	3		T39	40		T23	104
alert[0x16]	4844	1			T15	1		T37	2		T19	2
alert[0x17]	2494	1			T23	3		T46	4		T27	986
alert[0x18]	5054	1			T15	5		T19	1		T23	294
alert[0x19]	13403	1			T7	1		T15	316		T39	9
alert[0x1a]	5467	1			T7	1		T15	1		T23	127
alert[0x1b]	8373	1			T19	1		T39	1		T23	91
alert[0x1c]	5282	1			T11	1		T37	2		T42	474
alert[0x1d]	14677	1			T66	5		T25	2802		T306	1
alert[0x1e]	11276	1			T19	1		T39	277		T233	2
alert[0x1f]	4542	1			T18	1		T19	1		T20	1
alert[0x20]	12264	1			T42	35		T59	4		T24	3
alert[0x21]	11709	1			T15	10		T19	1		T20	1
alert[0x22]	4286	1			T39	542		T23	92		T96	1
alert[0x23]	7603	1			T15	1		T19	1		T23	24
alert[0x24]	8252	1			T11	3		T15	1		T23	100
alert[0x25]	3445	1			T42	146		T68	228		T29	18
alert[0x26]	8801	1			T15	140		T19	1		T20	1
alert[0x27]	14287	1			T7	1		T20	1		T23	469
alert[0x28]	11081	1			T18	1		T42	37		T45	45
alert[0x29]	3188	1			T15	30		T20	1		T23	52
alert[0x2a]	9903	1			T20	1		T96	1		T64	13
alert[0x2b]	4855	1			T15	3		T20	2		T39	33
alert[0x2c]	8752	1			T233	1		T42	35		T59	18
alert[0x2d]	2828	1			T11	3		T7	1		T15	7
alert[0x2e]	6477	1			T15	19		T39	320		T45	44
alert[0x2f]	6623	1			T15	507		T20	1		T233	1
alert[0x30]	6689	1			T19	1		T20	2		T39	223
alert[0x31]	7505	1			T15	70		T39	627		T23	530
alert[0x32]	8141	1			T15	4		T37	2		T96	1
alert[0x33]	5388	1			T11	8		T22	1		T42	418
alert[0x34]	5176	1			T15	49		T37	1		T39	67
alert[0x35]	4179	1			T11	2		T15	9		T39	136
alert[0x36]	7174	1			T15	9		T37	1		T20	1
alert[0x37]	6361	1			T15	2		T19	1		T42	43
alert[0x38]	5703	1			T19	1		T39	243		T233	1
alert[0x39]	5948	1			T7	1		T23	4		T59	6
alert[0x3a]	2338	1			T15	20		T37	1		T39	8
alert[0x3b]	7849	1			T39	18		T59	23		T46	503
alert[0x3c]	5373	1			T15	9		T22	1		T39	42
alert[0x3d]	4254	1			T22	22		T19	1		T39	136
alert[0x3e]	2236	1			T11	7		T19	1		T59	39
alert[0x3f]	5430	1			T20	1		T39	52		T66	2
alert[0x40]	12105	1			T15	4		T23	182		T42	33

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	109106	1			T7	2		T15	70		T31	4
class_i[0x1]	128026	1			T233	2		T23	10		T42	8897
class_i[0x2]	88053	1			T11	36		T7	4		T15	99
class_i[0x3]	121528	1			T11	3		T18	2		T15	1085

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

446001

1

T11

39

T15

1254

T31

4

alert_ping_fail

712

1

T7

6

T18

2

T19

21

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3687	1			T15	5		T39	44		T42	259
alert_integrity_fail	alert[0x1]	6148	1			T11	3		T59	613		T66	4
alert_integrity_fail	alert[0x2]	5673	1			T15	12		T39	57		T42	72
alert_integrity_fail	alert[0x3]	13845	1			T23	72		T24	7		T29	7
alert_integrity_fail	alert[0x4]	6867	1			T39	208		T42	7		T307	2
alert_integrity_fail	alert[0x5]	2203	1			T37	18		T59	27		T68	37
alert_integrity_fail	alert[0x6]	3547	1			T15	7		T23	139		T68	9
alert_integrity_fail	alert[0x7]	6246	1			T39	229		T59	96		T25	988
alert_integrity_fail	alert[0x8]	4826	1			T39	23		T42	291		T59	199
alert_integrity_fail	alert[0x9]	10072	1			T23	275		T59	80		T68	41
alert_integrity_fail	alert[0xa]	10973	1			T11	10		T15	1		T22	1
alert_integrity_fail	alert[0xb]	5642	1			T39	8		T59	770		T25	223
alert_integrity_fail	alert[0xc]	6108	1			T15	3		T39	16		T23	1
alert_integrity_fail	alert[0xd]	8506	1			T23	243		T59	28		T25	2518
alert_integrity_fail	alert[0xe]	2220	1			T22	13		T39	191		T23	25
alert_integrity_fail	alert[0xf]	8231	1			T15	3		T22	1		T46	35
alert_integrity_fail	alert[0x10]	8280	1			T15	3		T31	4		T66	3
alert_integrity_fail	alert[0x11]	4739	1			T23	380		T42	24		T66	5
alert_integrity_fail	alert[0x12]	6562	1			T22	7		T39	11		T46	26
alert_integrity_fail	alert[0x13]	2500	1			T11	2		T15	3		T23	48
alert_integrity_fail	alert[0x14]	7060	1			T59	520		T45	372		T68	171
alert_integrity_fail	alert[0x15]	10905	1			T22	3		T39	40		T23	104
alert_integrity_fail	alert[0x16]	4824	1			T15	1		T37	2		T23	1795
alert_integrity_fail	alert[0x17]	2482	1			T23	3		T46	4		T27	986
alert_integrity_fail	alert[0x18]	5043	1			T15	5		T23	294		T42	7
alert_integrity_fail	alert[0x19]	13391	1			T15	316		T39	9		T64	4
alert_integrity_fail	alert[0x1a]	5457	1			T15	1		T23	127		T68	269
alert_integrity_fail	alert[0x1b]	8362	1			T39	1		T23	91		T42	69
alert_integrity_fail	alert[0x1c]	5266	1			T11	1		T37	2		T42	474
alert_integrity_fail	alert[0x1d]	14665	1			T66	5		T25	2802		T68	20
alert_integrity_fail	alert[0x1e]	11261	1			T39	277		T23	2857		T59	18
alert_integrity_fail	alert[0x1f]	4525	1			T23	18		T42	6		T66	69
alert_integrity_fail	alert[0x20]	12256	1			T42	35		T59	4		T24	3
alert_integrity_fail	alert[0x21]	11700	1			T15	10		T39	369		T23	16
alert_integrity_fail	alert[0x22]	4272	1			T39	542		T23	92		T59	52
alert_integrity_fail	alert[0x23]	7587	1			T15	1		T23	24		T42	11
alert_integrity_fail	alert[0x24]	8246	1			T11	3		T15	1		T23	100
alert_integrity_fail	alert[0x25]	3440	1			T42	146		T68	228		T29	18
alert_integrity_fail	alert[0x26]	8795	1			T15	140		T42	190		T25	39
alert_integrity_fail	alert[0x27]	14278	1			T23	469		T42	2945		T45	37
alert_integrity_fail	alert[0x28]	11065	1			T42	37		T45	45		T68	474
alert_integrity_fail	alert[0x29]	3182	1			T15	30		T23	52		T59	102
alert_integrity_fail	alert[0x2a]	9889	1			T64	13		T42	67		T62	3
alert_integrity_fail	alert[0x2b]	4845	1			T15	3		T39	33		T23	51
alert_integrity_fail	alert[0x2c]	8735	1			T42	35		T59	18		T68	35
alert_integrity_fail	alert[0x2d]	2818	1			T11	3		T15	7		T25	72
alert_integrity_fail	alert[0x2e]	6468	1			T15	19		T39	320		T45	44
alert_integrity_fail	alert[0x2f]	6615	1			T15	507		T23	33		T59	2
alert_integrity_fail	alert[0x30]	6675	1			T39	223		T23	18		T42	165
alert_integrity_fail	alert[0x31]	7496	1			T15	70		T39	627		T23	530
alert_integrity_fail	alert[0x32]	8135	1			T15	4		T37	2		T42	133
alert_integrity_fail	alert[0x33]	5380	1			T11	8		T22	1		T42	418
alert_integrity_fail	alert[0x34]	5165	1			T15	49		T37	1		T39	67
alert_integrity_fail	alert[0x35]	4170	1			T11	2		T15	9		T39	136
alert_integrity_fail	alert[0x36]	7160	1			T15	9		T37	1		T39	247
alert_integrity_fail	alert[0x37]	6354	1			T15	2		T42	43		T45	9
alert_integrity_fail	alert[0x38]	5688	1			T39	243		T59	63		T45	5
alert_integrity_fail	alert[0x39]	5940	1			T23	4		T59	6		T45	5
alert_integrity_fail	alert[0x3a]	2333	1			T15	20		T37	1		T39	8
alert_integrity_fail	alert[0x3b]	7843	1			T39	18		T59	23		T46	503
alert_integrity_fail	alert[0x3c]	5361	1			T15	9		T22	1		T39	42
alert_integrity_fail	alert[0x3d]	4242	1			T22	22		T39	136		T66	3
alert_integrity_fail	alert[0x3e]	2227	1			T11	7		T59	39		T68	29
alert_integrity_fail	alert[0x3f]	5425	1			T39	52		T66	2		T68	191
alert_integrity_fail	alert[0x40]	12100	1			T15	4		T23	182		T42	33
alert_ping_fail	alert[0x0]	10	1			T20	1		T308	1		T309	2
alert_ping_fail	alert[0x1]	9	1			T310	1		T309	2		T277	1
alert_ping_fail	alert[0x2]	10	1			T309	1		T281	1		T93	1
alert_ping_fail	alert[0x3]	11	1			T233	1		T310	1		T309	1
alert_ping_fail	alert[0x4]	8	1			T19	1		T311	1		T175	1
alert_ping_fail	alert[0x5]	14	1			T309	1		T311	1		T312	1
alert_ping_fail	alert[0x6]	8	1			T306	1		T175	1		T313	1
alert_ping_fail	alert[0x7]	23	1			T20	1		T314	1		T97	1
alert_ping_fail	alert[0x8]	10	1			T301	1		T93	1		T315	1
alert_ping_fail	alert[0x9]	13	1			T19	1		T310	1		T309	1
alert_ping_fail	alert[0xa]	12	1			T301	1		T189	1		T175	1
alert_ping_fail	alert[0xb]	8	1			T7	1		T19	1		T311	1
alert_ping_fail	alert[0xc]	11	1			T19	1		T277	1		T312	1
alert_ping_fail	alert[0xd]	7	1			T314	2		T281	1		T175	1
alert_ping_fail	alert[0xe]	13	1			T19	1		T20	2		T233	1
alert_ping_fail	alert[0xf]	15	1			T20	1		T309	2		T277	1
alert_ping_fail	alert[0x10]	14	1			T310	2		T309	1		T316	1
alert_ping_fail	alert[0x11]	6	1			T308	1		T277	1		T317	1
alert_ping_fail	alert[0x12]	8	1			T314	1		T97	1		T318	1
alert_ping_fail	alert[0x13]	17	1			T19	1		T233	1		T311	1
alert_ping_fail	alert[0x14]	18	1			T19	1		T20	1		T306	1
alert_ping_fail	alert[0x15]	13	1			T310	2		T97	1		T93	1
alert_ping_fail	alert[0x16]	20	1			T19	2		T309	1		T277	1
alert_ping_fail	alert[0x17]	12	1			T314	1		T309	2		T311	1
alert_ping_fail	alert[0x18]	11	1			T19	1		T306	1		T314	1
alert_ping_fail	alert[0x19]	12	1			T7	1		T305	1		T318	1
alert_ping_fail	alert[0x1a]	10	1			T7	1		T93	1		T175	1
alert_ping_fail	alert[0x1b]	11	1			T19	1		T319	1		T320	1
alert_ping_fail	alert[0x1c]	16	1			T314	1		T309	1		T321	1
alert_ping_fail	alert[0x1d]	12	1			T306	1		T314	2		T311	1
alert_ping_fail	alert[0x1e]	15	1			T19	1		T233	2		T308	1
alert_ping_fail	alert[0x1f]	17	1			T18	1		T19	1		T20	1
alert_ping_fail	alert[0x20]	8	1			T306	1		T310	1		T308	1
alert_ping_fail	alert[0x21]	9	1			T19	1		T20	1		T93	1
alert_ping_fail	alert[0x22]	14	1			T96	1		T306	2		T309	1
alert_ping_fail	alert[0x23]	16	1			T19	1		T310	1		T308	1
alert_ping_fail	alert[0x24]	6	1			T310	1		T322	1		T323	1
alert_ping_fail	alert[0x25]	5	1			T175	1		T324	1		T325	1
alert_ping_fail	alert[0x26]	6	1			T19	1		T20	1		T176	1
alert_ping_fail	alert[0x27]	9	1			T7	1		T20	1		T97	1
alert_ping_fail	alert[0x28]	16	1			T18	1		T310	1		T305	2
alert_ping_fail	alert[0x29]	6	1			T20	1		T314	1		T312	1
alert_ping_fail	alert[0x2a]	14	1			T20	1		T96	1		T277	1
alert_ping_fail	alert[0x2b]	10	1			T20	2		T96	1		T310	1
alert_ping_fail	alert[0x2c]	17	1			T233	1		T310	1		T314	2
alert_ping_fail	alert[0x2d]	10	1			T7	1		T326	1		T320	1
alert_ping_fail	alert[0x2e]	9	1			T93	1		T327	1		T317	2
alert_ping_fail	alert[0x2f]	8	1			T20	1		T233	1		T304	1
alert_ping_fail	alert[0x30]	14	1			T19	1		T20	2		T310	1
alert_ping_fail	alert[0x31]	9	1			T97	1		T311	1		T93	1
alert_ping_fail	alert[0x32]	6	1			T96	1		T281	1		T175	1
alert_ping_fail	alert[0x33]	8	1			T314	1		T311	1		T319	1
alert_ping_fail	alert[0x34]	11	1			T233	1		T306	1		T97	1
alert_ping_fail	alert[0x35]	9	1			T97	1		T277	1		T281	1
alert_ping_fail	alert[0x36]	14	1			T20	1		T97	1		T309	1
alert_ping_fail	alert[0x37]	7	1			T19	1		T311	1		T175	1
alert_ping_fail	alert[0x38]	15	1			T19	1		T233	1		T314	1
alert_ping_fail	alert[0x39]	8	1			T7	1		T328	2		T329	1
alert_ping_fail	alert[0x3a]	5	1			T306	1		T277	1		T330	1
alert_ping_fail	alert[0x3b]	6	1			T320	1		T331	1		T332	2
alert_ping_fail	alert[0x3c]	12	1			T233	1		T310	1		T314	1
alert_ping_fail	alert[0x3d]	12	1			T19	1		T314	2		T281	1
alert_ping_fail	alert[0x3e]	9	1			T19	1		T310	2		T314	1
alert_ping_fail	alert[0x3f]	5	1			T20	1		T310	1		T328	1
alert_ping_fail	alert[0x40]	5	1			T310	1		T277	2		T320	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	108832	1			T15	70		T31	4		T22	1
alert_integrity_fail	class_i[0x1]	127915	1			T23	10		T42	8897		T62	2
alert_integrity_fail	class_i[0x2]	87879	1			T11	36		T15	99		T22	48
alert_integrity_fail	class_i[0x3]	121375	1			T11	3		T15	1085		T37	3
alert_ping_fail	class_i[0x0]	274	1			T7	2		T19	21		T20	19
alert_ping_fail	class_i[0x1]	111	1			T233	2		T310	3		T309	1
alert_ping_fail	class_i[0x2]	174	1			T7	4		T306	5		T310	11
alert_ping_fail	class_i[0x3]	153	1			T18	2		T96	2		T306	3