Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.24 99.99 98.67 97.09 100.00 100.00 99.38 99.56


Total test records in report: 822
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T767 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1799698646 Aug 06 06:27:18 PM PDT 24 Aug 06 06:27:29 PM PDT 24 243062963 ps
T768 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2314651623 Aug 06 06:26:02 PM PDT 24 Aug 06 06:26:29 PM PDT 24 4360419498 ps
T140 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.291393501 Aug 06 06:26:00 PM PDT 24 Aug 06 06:32:15 PM PDT 24 26422174896 ps
T769 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2994374335 Aug 06 06:25:20 PM PDT 24 Aug 06 06:25:29 PM PDT 24 123037312 ps
T770 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3975029049 Aug 06 06:27:51 PM PDT 24 Aug 06 06:27:52 PM PDT 24 14974315 ps
T771 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2539913179 Aug 06 06:27:16 PM PDT 24 Aug 06 06:27:49 PM PDT 24 1066182333 ps
T772 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.616243873 Aug 06 06:27:33 PM PDT 24 Aug 06 06:27:34 PM PDT 24 6788235 ps
T159 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.469136452 Aug 06 06:26:47 PM PDT 24 Aug 06 06:27:29 PM PDT 24 2156303385 ps
T773 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1958750674 Aug 06 06:27:02 PM PDT 24 Aug 06 06:27:09 PM PDT 24 69016384 ps
T774 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1014796010 Aug 06 06:25:21 PM PDT 24 Aug 06 06:25:41 PM PDT 24 185090841 ps
T775 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1586328016 Aug 06 06:27:48 PM PDT 24 Aug 06 06:27:49 PM PDT 24 11356499 ps
T167 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2999573421 Aug 06 06:25:52 PM PDT 24 Aug 06 06:25:55 PM PDT 24 108161726 ps
T776 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3518766999 Aug 06 06:26:16 PM PDT 24 Aug 06 06:26:28 PM PDT 24 224612632 ps
T777 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1764706952 Aug 06 06:27:21 PM PDT 24 Aug 06 06:27:22 PM PDT 24 10367045 ps
T778 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.8519676 Aug 06 06:27:16 PM PDT 24 Aug 06 06:27:40 PM PDT 24 518339291 ps
T160 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.81613259 Aug 06 06:27:17 PM PDT 24 Aug 06 06:28:00 PM PDT 24 559733435 ps
T779 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3976664694 Aug 06 06:27:32 PM PDT 24 Aug 06 06:27:33 PM PDT 24 6773761 ps
T780 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1280032882 Aug 06 06:27:17 PM PDT 24 Aug 06 06:27:18 PM PDT 24 18283962 ps
T781 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.423510836 Aug 06 06:26:47 PM PDT 24 Aug 06 06:26:57 PM PDT 24 100609137 ps
T782 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.38743353 Aug 06 06:26:47 PM PDT 24 Aug 06 06:26:52 PM PDT 24 126063291 ps
T783 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3142381945 Aug 06 06:27:00 PM PDT 24 Aug 06 06:27:03 PM PDT 24 291020888 ps
T784 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1098461558 Aug 06 06:27:49 PM PDT 24 Aug 06 06:27:50 PM PDT 24 21980610 ps
T785 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1789212003 Aug 06 06:27:18 PM PDT 24 Aug 06 06:27:27 PM PDT 24 356281037 ps
T352 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2517624538 Aug 06 06:26:47 PM PDT 24 Aug 06 06:33:53 PM PDT 24 6377833015 ps
T142 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1069955739 Aug 06 06:25:36 PM PDT 24 Aug 06 06:29:17 PM PDT 24 6815475131 ps
T786 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1637769993 Aug 06 06:25:20 PM PDT 24 Aug 06 06:29:33 PM PDT 24 45880093410 ps
T787 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1166699717 Aug 06 06:27:48 PM PDT 24 Aug 06 06:27:50 PM PDT 24 7639006 ps
T144 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2935101654 Aug 06 06:26:47 PM PDT 24 Aug 06 06:30:53 PM PDT 24 7713359721 ps
T788 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2274708159 Aug 06 06:26:47 PM PDT 24 Aug 06 06:26:48 PM PDT 24 8270770 ps
T789 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3365270576 Aug 06 06:26:58 PM PDT 24 Aug 06 06:27:02 PM PDT 24 19607437 ps
T790 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2487444061 Aug 06 06:26:51 PM PDT 24 Aug 06 06:26:59 PM PDT 24 1269780432 ps
T791 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1355560907 Aug 06 06:26:47 PM PDT 24 Aug 06 06:26:56 PM PDT 24 51716910 ps
T161 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1033672188 Aug 06 06:24:57 PM PDT 24 Aug 06 06:25:00 PM PDT 24 30920649 ps
T792 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3423812489 Aug 06 06:24:56 PM PDT 24 Aug 06 06:24:57 PM PDT 24 6281301 ps
T793 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.967464056 Aug 06 06:27:15 PM PDT 24 Aug 06 06:27:19 PM PDT 24 50326300 ps
T794 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2403146532 Aug 06 06:25:36 PM PDT 24 Aug 06 06:25:42 PM PDT 24 40226231 ps
T795 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2416995160 Aug 06 06:26:47 PM PDT 24 Aug 06 06:27:07 PM PDT 24 281994112 ps
T146 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1009893288 Aug 06 06:25:34 PM PDT 24 Aug 06 06:34:52 PM PDT 24 32434242513 ps
T796 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1410291381 Aug 06 06:26:01 PM PDT 24 Aug 06 06:26:05 PM PDT 24 22143362 ps
T797 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2866877858 Aug 06 06:25:22 PM PDT 24 Aug 06 06:28:45 PM PDT 24 12955497338 ps
T798 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2578394257 Aug 06 06:26:48 PM PDT 24 Aug 06 06:26:55 PM PDT 24 348726233 ps
T147 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1403653092 Aug 06 06:26:01 PM PDT 24 Aug 06 06:32:23 PM PDT 24 5448891208 ps
T799 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1239683190 Aug 06 06:26:00 PM PDT 24 Aug 06 06:35:52 PM PDT 24 31863175931 ps
T800 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1802268242 Aug 06 06:25:20 PM PDT 24 Aug 06 06:25:42 PM PDT 24 3191911875 ps
T801 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2899602197 Aug 06 06:26:46 PM PDT 24 Aug 06 06:27:06 PM PDT 24 239009365 ps
T802 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2806611827 Aug 06 06:25:18 PM PDT 24 Aug 06 06:25:19 PM PDT 24 11396369 ps
T353 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3490796701 Aug 06 06:26:46 PM PDT 24 Aug 06 06:37:56 PM PDT 24 8886364177 ps
T803 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1923125252 Aug 06 06:27:17 PM PDT 24 Aug 06 06:27:44 PM PDT 24 634341856 ps
T163 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.99375834 Aug 06 06:25:20 PM PDT 24 Aug 06 06:25:23 PM PDT 24 112984259 ps
T143 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1540596142 Aug 06 06:27:18 PM PDT 24 Aug 06 06:32:19 PM PDT 24 13173858097 ps
T804 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.237151246 Aug 06 06:26:47 PM PDT 24 Aug 06 06:26:49 PM PDT 24 18419969 ps
T805 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1130808067 Aug 06 06:24:57 PM PDT 24 Aug 06 06:29:30 PM PDT 24 6533527848 ps
T806 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.341286412 Aug 06 06:26:47 PM PDT 24 Aug 06 06:26:53 PM PDT 24 194996669 ps
T807 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1119465308 Aug 06 06:27:32 PM PDT 24 Aug 06 06:27:34 PM PDT 24 8792232 ps
T808 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2612809171 Aug 06 06:25:36 PM PDT 24 Aug 06 06:26:03 PM PDT 24 336333788 ps
T809 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.826960633 Aug 06 06:25:53 PM PDT 24 Aug 06 06:26:11 PM PDT 24 940707285 ps
T810 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.636819078 Aug 06 06:27:21 PM PDT 24 Aug 06 06:27:28 PM PDT 24 88099867 ps
T811 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2137759471 Aug 06 06:25:36 PM PDT 24 Aug 06 06:25:54 PM PDT 24 294869552 ps
T812 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.367748666 Aug 06 06:27:01 PM PDT 24 Aug 06 06:27:02 PM PDT 24 7472092 ps
T354 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2158308761 Aug 06 06:26:47 PM PDT 24 Aug 06 06:34:27 PM PDT 24 18979734720 ps
T813 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1589157433 Aug 06 06:26:47 PM PDT 24 Aug 06 06:26:49 PM PDT 24 33249642 ps
T814 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.60719600 Aug 06 06:24:57 PM PDT 24 Aug 06 06:25:01 PM PDT 24 29674912 ps
T815 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3311269686 Aug 06 06:26:48 PM PDT 24 Aug 06 06:27:11 PM PDT 24 677528727 ps
T816 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3975479326 Aug 06 06:27:00 PM PDT 24 Aug 06 06:27:13 PM PDT 24 94235627 ps
T817 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1525060564 Aug 06 06:26:47 PM PDT 24 Aug 06 06:26:56 PM PDT 24 865206291 ps
T145 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3250707811 Aug 06 06:26:16 PM PDT 24 Aug 06 06:28:51 PM PDT 24 2098436592 ps
T818 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.634230934 Aug 06 06:26:51 PM PDT 24 Aug 06 06:26:53 PM PDT 24 19558322 ps
T819 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1006621600 Aug 06 06:26:16 PM PDT 24 Aug 06 06:26:18 PM PDT 24 33409440 ps
T820 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1561274762 Aug 06 06:25:20 PM PDT 24 Aug 06 06:27:11 PM PDT 24 3270121085 ps
T821 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.4169294124 Aug 06 06:27:48 PM PDT 24 Aug 06 06:27:50 PM PDT 24 11060454 ps
T822 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2838611995 Aug 06 06:26:52 PM PDT 24 Aug 06 06:37:55 PM PDT 24 18943148308 ps
T148 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.54437842 Aug 06 06:26:45 PM PDT 24 Aug 06 06:28:16 PM PDT 24 4837990705 ps

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1103058561
Short name T11
Test name
Test status
Simulation time 1332921910 ps
CPU time 42.17 seconds
Started Aug 06 05:29:36 PM PDT 24
Finished Aug 06 05:30:18 PM PDT 24
Peak memory 256012 kb
Host smart-5a83e49e-2004-471e-aae7-b539b54344be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11030
58561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1103058561
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.3830473067
Short name T15
Test name
Test status
Simulation time 45285987808 ps
CPU time 2931.67 seconds
Started Aug 06 05:30:36 PM PDT 24
Finished Aug 06 06:19:28 PM PDT 24
Peak memory 283988 kb
Host smart-deeccc00-e62e-40c4-81bd-0473fb0bf82a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830473067 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.3830473067
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3412101016
Short name T8
Test name
Test status
Simulation time 1462459410 ps
CPU time 19.61 seconds
Started Aug 06 05:28:05 PM PDT 24
Finished Aug 06 05:28:25 PM PDT 24
Peak memory 276244 kb
Host smart-748fd2d7-e66d-4f71-9408-fe3c2176049b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3412101016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3412101016
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3405975886
Short name T30
Test name
Test status
Simulation time 226686375732 ps
CPU time 3472.35 seconds
Started Aug 06 05:28:59 PM PDT 24
Finished Aug 06 06:26:52 PM PDT 24
Peak memory 288928 kb
Host smart-4490150e-5508-4738-abd1-c4becb9d3506
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405975886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3405975886
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1458330771
Short name T151
Test name
Test status
Simulation time 1301339795 ps
CPU time 90.63 seconds
Started Aug 06 06:25:18 PM PDT 24
Finished Aug 06 06:26:49 PM PDT 24
Peak memory 240564 kb
Host smart-60504718-9022-40c6-97f7-ec75da355f36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1458330771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1458330771
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3035910379
Short name T5
Test name
Test status
Simulation time 622097901 ps
CPU time 10.2 seconds
Started Aug 06 05:28:05 PM PDT 24
Finished Aug 06 05:28:16 PM PDT 24
Peak memory 248340 kb
Host smart-e0e77270-3e91-4ca1-a01a-9faa3d388f43
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3035910379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3035910379
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.804795013
Short name T52
Test name
Test status
Simulation time 200591154238 ps
CPU time 2534.22 seconds
Started Aug 06 05:29:54 PM PDT 24
Finished Aug 06 06:12:08 PM PDT 24
Peak memory 288516 kb
Host smart-abfd6d9f-9bfd-45e0-b322-b2ca69761cfc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804795013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.804795013
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.4058591599
Short name T117
Test name
Test status
Simulation time 15444215848 ps
CPU time 326.58 seconds
Started Aug 06 06:25:20 PM PDT 24
Finished Aug 06 06:30:47 PM PDT 24
Peak memory 265660 kb
Host smart-f03809c0-0889-468f-8430-ae3d71e41a2d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4058591599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.4058591599
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1343692609
Short name T48
Test name
Test status
Simulation time 252223290565 ps
CPU time 6668.21 seconds
Started Aug 06 05:30:05 PM PDT 24
Finished Aug 06 07:21:14 PM PDT 24
Peak memory 394572 kb
Host smart-afe027ab-d205-4a9a-b082-61291c2c57ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343692609 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1343692609
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2505113207
Short name T32
Test name
Test status
Simulation time 15550690375 ps
CPU time 1533.73 seconds
Started Aug 06 05:30:00 PM PDT 24
Finished Aug 06 05:55:34 PM PDT 24
Peak memory 287864 kb
Host smart-8ce1f6f4-fd94-4bfe-bb66-84bd9e551662
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505113207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2505113207
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3248424683
Short name T133
Test name
Test status
Simulation time 5644517822 ps
CPU time 632.94 seconds
Started Aug 06 06:26:15 PM PDT 24
Finished Aug 06 06:36:49 PM PDT 24
Peak memory 265652 kb
Host smart-873ed42e-84e5-412c-b88d-83d14422a8e8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248424683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3248424683
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.999694455
Short name T335
Test name
Test status
Simulation time 67852055665 ps
CPU time 2165.77 seconds
Started Aug 06 05:28:31 PM PDT 24
Finished Aug 06 06:04:37 PM PDT 24
Peak memory 287028 kb
Host smart-fed108d8-8655-41df-a21e-00a578604a2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999694455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.999694455
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3873294930
Short name T93
Test name
Test status
Simulation time 90010638838 ps
CPU time 405.2 seconds
Started Aug 06 05:29:56 PM PDT 24
Finished Aug 06 05:36:41 PM PDT 24
Peak memory 248548 kb
Host smart-e4bf0ecb-c3b2-44e9-98e0-307e78671edd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873294930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3873294930
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2100975011
Short name T124
Test name
Test status
Simulation time 6139001538 ps
CPU time 198.39 seconds
Started Aug 06 06:27:17 PM PDT 24
Finished Aug 06 06:30:36 PM PDT 24
Peak memory 265616 kb
Host smart-66bf9441-e65e-446b-ac72-78b3045b83cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2100975011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.2100975011
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3735319290
Short name T18
Test name
Test status
Simulation time 63021093958 ps
CPU time 1830.33 seconds
Started Aug 06 05:29:25 PM PDT 24
Finished Aug 06 05:59:56 PM PDT 24
Peak memory 273084 kb
Host smart-bb7c8d08-67b6-456b-b43d-e575ccfaf3cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735319290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3735319290
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3068138842
Short name T86
Test name
Test status
Simulation time 3162246275 ps
CPU time 57.4 seconds
Started Aug 06 05:30:01 PM PDT 24
Finished Aug 06 05:30:59 PM PDT 24
Peak memory 249572 kb
Host smart-c35e82ac-8ffb-41ba-ac64-50a75724a5f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30681
38842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3068138842
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1352681754
Short name T59
Test name
Test status
Simulation time 128899622757 ps
CPU time 1950.27 seconds
Started Aug 06 05:29:06 PM PDT 24
Finished Aug 06 06:01:37 PM PDT 24
Peak memory 289468 kb
Host smart-b5fbc35c-2bc3-4930-9bc1-5a03052254b5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352681754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1352681754
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2785614061
Short name T123
Test name
Test status
Simulation time 34872005657 ps
CPU time 1102.11 seconds
Started Aug 06 06:25:18 PM PDT 24
Finished Aug 06 06:43:40 PM PDT 24
Peak memory 265644 kb
Host smart-0f28e294-0ce3-4967-871e-18ad9a506067
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785614061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2785614061
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2947039831
Short name T348
Test name
Test status
Simulation time 18586813 ps
CPU time 1.42 seconds
Started Aug 06 06:27:48 PM PDT 24
Finished Aug 06 06:27:50 PM PDT 24
Peak memory 236792 kb
Host smart-1f93dd21-1389-4ca9-b2e7-d0db1f27911d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2947039831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2947039831
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.638610603
Short name T19
Test name
Test status
Simulation time 12104122567 ps
CPU time 451.57 seconds
Started Aug 06 05:29:56 PM PDT 24
Finished Aug 06 05:37:28 PM PDT 24
Peak memory 248548 kb
Host smart-edd042ba-1114-4943-a840-f2f4bc5f56a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638610603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.638610603
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2934015508
Short name T125
Test name
Test status
Simulation time 94766974410 ps
CPU time 1036.22 seconds
Started Aug 06 06:25:34 PM PDT 24
Finished Aug 06 06:42:51 PM PDT 24
Peak memory 265816 kb
Host smart-211e7785-e4c6-4fdf-b1bf-d74e6350e00b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934015508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2934015508
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1126309022
Short name T321
Test name
Test status
Simulation time 148783845439 ps
CPU time 2054 seconds
Started Aug 06 05:28:41 PM PDT 24
Finished Aug 06 06:02:55 PM PDT 24
Peak memory 272440 kb
Host smart-6e6fe93a-123b-4800-8623-86499708a936
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126309022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1126309022
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.122047290
Short name T121
Test name
Test status
Simulation time 2221718837 ps
CPU time 201.38 seconds
Started Aug 06 06:24:57 PM PDT 24
Finished Aug 06 06:28:19 PM PDT 24
Peak memory 273280 kb
Host smart-e1759a14-8bf8-40a5-a447-5b8fa3569979
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=122047290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.122047290
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1217802678
Short name T27
Test name
Test status
Simulation time 257324579091 ps
CPU time 4731.57 seconds
Started Aug 06 05:30:19 PM PDT 24
Finished Aug 06 06:49:11 PM PDT 24
Peak memory 305280 kb
Host smart-1636fc78-3e36-43e2-a04b-99a492f1aa1b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217802678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1217802678
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2389553104
Short name T20
Test name
Test status
Simulation time 64085644938 ps
CPU time 664.99 seconds
Started Aug 06 05:28:09 PM PDT 24
Finished Aug 06 05:39:14 PM PDT 24
Peak memory 247368 kb
Host smart-f68bab94-6514-411e-8adc-ae6bb4d0a0e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389553104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2389553104
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.345397165
Short name T333
Test name
Test status
Simulation time 33772551863 ps
CPU time 1986.57 seconds
Started Aug 06 05:28:20 PM PDT 24
Finished Aug 06 06:01:27 PM PDT 24
Peak memory 272864 kb
Host smart-8b2e2779-f489-4370-890d-067dc1c6a30e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345397165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.345397165
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1323230052
Short name T122
Test name
Test status
Simulation time 32792061824 ps
CPU time 1191.81 seconds
Started Aug 06 06:27:02 PM PDT 24
Finished Aug 06 06:46:54 PM PDT 24
Peak memory 273468 kb
Host smart-5cc12779-919f-4f3b-b8fa-d5affbbd83ca
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323230052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1323230052
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2839065526
Short name T237
Test name
Test status
Simulation time 247371888199 ps
CPU time 2950.8 seconds
Started Aug 06 05:29:13 PM PDT 24
Finished Aug 06 06:18:24 PM PDT 24
Peak memory 297824 kb
Host smart-3166286d-c581-47c2-9353-cb16ed502e49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839065526 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2839065526
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3435895785
Short name T64
Test name
Test status
Simulation time 20073115350 ps
CPU time 2103.63 seconds
Started Aug 06 05:29:06 PM PDT 24
Finished Aug 06 06:04:10 PM PDT 24
Peak memory 299092 kb
Host smart-d0b2c371-0533-4d94-80a2-fd9302a50ca9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435895785 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3435895785
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.122092596
Short name T305
Test name
Test status
Simulation time 418558444055 ps
CPU time 2780.72 seconds
Started Aug 06 05:29:14 PM PDT 24
Finished Aug 06 06:15:35 PM PDT 24
Peak memory 287828 kb
Host smart-1a051343-df4c-4c23-bd41-583989a4da5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122092596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.122092596
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1546242271
Short name T243
Test name
Test status
Simulation time 12293195 ps
CPU time 1.68 seconds
Started Aug 06 06:27:48 PM PDT 24
Finished Aug 06 06:27:50 PM PDT 24
Peak memory 236696 kb
Host smart-5feb7e4b-2a91-4b62-9256-739da1f4384c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1546242271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1546242271
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.792518593
Short name T668
Test name
Test status
Simulation time 31290090267 ps
CPU time 1498.43 seconds
Started Aug 06 05:28:35 PM PDT 24
Finished Aug 06 05:53:34 PM PDT 24
Peak memory 272996 kb
Host smart-84280e57-87ce-444f-9cea-175207f3e991
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792518593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.792518593
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.929309725
Short name T320
Test name
Test status
Simulation time 12927921160 ps
CPU time 510.8 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 05:37:36 PM PDT 24
Peak memory 248620 kb
Host smart-880bbfab-6794-4f15-b67f-d59e1391f7e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929309725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.929309725
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.2667441994
Short name T102
Test name
Test status
Simulation time 49488639295 ps
CPU time 4249.22 seconds
Started Aug 06 05:29:35 PM PDT 24
Finished Aug 06 06:40:24 PM PDT 24
Peak memory 322280 kb
Host smart-cfa3a9b0-a229-4d28-a45e-107dd100173e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667441994 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.2667441994
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1407413288
Short name T134
Test name
Test status
Simulation time 2110753691 ps
CPU time 133.83 seconds
Started Aug 06 06:25:34 PM PDT 24
Finished Aug 06 06:27:48 PM PDT 24
Peak memory 265512 kb
Host smart-07cc183e-5850-4f6a-9a29-e1750cf5b7bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1407413288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1407413288
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3565427404
Short name T175
Test name
Test status
Simulation time 45334887314 ps
CPU time 491.85 seconds
Started Aug 06 05:30:34 PM PDT 24
Finished Aug 06 05:38:46 PM PDT 24
Peak memory 248564 kb
Host smart-caf9c32c-434c-4839-8fcd-0ce5c8a9d136
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565427404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3565427404
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3229619067
Short name T344
Test name
Test status
Simulation time 482727563886 ps
CPU time 1811.83 seconds
Started Aug 06 05:29:41 PM PDT 24
Finished Aug 06 05:59:54 PM PDT 24
Peak memory 273164 kb
Host smart-34817dc5-cf31-4cbb-ad3e-1b994fddc988
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229619067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3229619067
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.367629016
Short name T45
Test name
Test status
Simulation time 326233850865 ps
CPU time 2032.8 seconds
Started Aug 06 05:30:35 PM PDT 24
Finished Aug 06 06:04:28 PM PDT 24
Peak memory 283660 kb
Host smart-6cae19e5-d4a0-4296-b022-e589cdcb8191
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367629016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.367629016
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.458459908
Short name T129
Test name
Test status
Simulation time 58380025299 ps
CPU time 940.83 seconds
Started Aug 06 06:27:18 PM PDT 24
Finished Aug 06 06:42:59 PM PDT 24
Peak memory 265616 kb
Host smart-3a0db857-fccb-4a59-9969-9c641e7f792b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458459908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.458459908
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.743910531
Short name T277
Test name
Test status
Simulation time 21076248756 ps
CPU time 444.84 seconds
Started Aug 06 05:28:41 PM PDT 24
Finished Aug 06 05:36:06 PM PDT 24
Peak memory 248500 kb
Host smart-a26d59d9-523b-4fb0-8237-2ea7c123f3bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743910531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.743910531
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3432366164
Short name T273
Test name
Test status
Simulation time 42331218487 ps
CPU time 271.17 seconds
Started Aug 06 05:29:18 PM PDT 24
Finished Aug 06 05:33:49 PM PDT 24
Peak memory 256760 kb
Host smart-013ef02f-bf63-44a3-8f51-610900369e4e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432366164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3432366164
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.4027477391
Short name T169
Test name
Test status
Simulation time 126361105 ps
CPU time 2.58 seconds
Started Aug 06 06:26:15 PM PDT 24
Finished Aug 06 06:26:17 PM PDT 24
Peak memory 237632 kb
Host smart-93a5ecb7-b1fa-401c-98d5-7447ce4f7cad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4027477391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.4027477391
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.225548586
Short name T252
Test name
Test status
Simulation time 368772213 ps
CPU time 19.63 seconds
Started Aug 06 05:28:35 PM PDT 24
Finished Aug 06 05:28:55 PM PDT 24
Peak memory 247592 kb
Host smart-993927f1-e254-4028-9775-b4c6416e68c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22554
8586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.225548586
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3541050291
Short name T72
Test name
Test status
Simulation time 142853019 ps
CPU time 16.89 seconds
Started Aug 06 05:29:01 PM PDT 24
Finished Aug 06 05:29:18 PM PDT 24
Peak memory 247944 kb
Host smart-238538e1-9cd4-41bd-8718-e35ae93871f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35410
50291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3541050291
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3098150811
Short name T116
Test name
Test status
Simulation time 17482820310 ps
CPU time 639.17 seconds
Started Aug 06 06:26:16 PM PDT 24
Finished Aug 06 06:36:56 PM PDT 24
Peak memory 265660 kb
Host smart-40e82e51-7bcf-4605-b9e9-c2fcd30dac82
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098150811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3098150811
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1068640642
Short name T115
Test name
Test status
Simulation time 18170811251 ps
CPU time 211.07 seconds
Started Aug 06 06:26:46 PM PDT 24
Finished Aug 06 06:30:18 PM PDT 24
Peak memory 266660 kb
Host smart-6c486060-6fd3-496c-8cc6-f9ddeeb52588
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1068640642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1068640642
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3367082984
Short name T174
Test name
Test status
Simulation time 48320582 ps
CPU time 4.14 seconds
Started Aug 06 05:28:06 PM PDT 24
Finished Aug 06 05:28:10 PM PDT 24
Peak memory 248620 kb
Host smart-810f9153-b7cb-445c-b19b-0eca48a298c0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3367082984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3367082984
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1216408567
Short name T217
Test name
Test status
Simulation time 59519987 ps
CPU time 2.86 seconds
Started Aug 06 05:28:16 PM PDT 24
Finished Aug 06 05:28:19 PM PDT 24
Peak memory 248700 kb
Host smart-ef5a251a-6cce-4c36-b2a1-6ef8f7ab366e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1216408567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1216408567
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.337928920
Short name T201
Test name
Test status
Simulation time 170650504 ps
CPU time 3.64 seconds
Started Aug 06 05:28:38 PM PDT 24
Finished Aug 06 05:28:42 PM PDT 24
Peak memory 248656 kb
Host smart-ae13737e-f642-4624-b12c-11a78a1fa49e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=337928920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.337928920
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2136017785
Short name T208
Test name
Test status
Simulation time 74140895 ps
CPU time 3.47 seconds
Started Aug 06 05:28:32 PM PDT 24
Finished Aug 06 05:28:36 PM PDT 24
Peak memory 248592 kb
Host smart-9a8854f2-57ab-4d6d-98ee-e84f0a080c34
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2136017785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2136017785
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1601031813
Short name T188
Test name
Test status
Simulation time 93675807237 ps
CPU time 1341.44 seconds
Started Aug 06 05:28:37 PM PDT 24
Finished Aug 06 05:50:59 PM PDT 24
Peak memory 272048 kb
Host smart-15de265b-0c93-40cd-bdcc-1078dc4826ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601031813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1601031813
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.93254538
Short name T327
Test name
Test status
Simulation time 72083700244 ps
CPU time 617.12 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 05:39:22 PM PDT 24
Peak memory 248252 kb
Host smart-92902e4d-a06b-480d-b2de-6dac0cba14d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93254538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.93254538
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2256250109
Short name T254
Test name
Test status
Simulation time 9987050604 ps
CPU time 749.41 seconds
Started Aug 06 05:29:07 PM PDT 24
Finished Aug 06 05:41:37 PM PDT 24
Peak memory 273092 kb
Host smart-eeda90ce-b3f0-452d-aa0f-4ca7aac54d0a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256250109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2256250109
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.293569086
Short name T24
Test name
Test status
Simulation time 356326688248 ps
CPU time 2779.23 seconds
Started Aug 06 05:29:25 PM PDT 24
Finished Aug 06 06:15:44 PM PDT 24
Peak memory 316580 kb
Host smart-aa8c6c63-1aba-4e3a-8ba1-4de20f9be017
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293569086 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.293569086
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.2722976401
Short name T172
Test name
Test status
Simulation time 216330641867 ps
CPU time 4264.89 seconds
Started Aug 06 05:29:26 PM PDT 24
Finished Aug 06 06:40:32 PM PDT 24
Peak memory 321360 kb
Host smart-c0805c7c-bdf1-408d-84db-00cc12cb82ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722976401 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.2722976401
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1197289543
Short name T526
Test name
Test status
Simulation time 15093062878 ps
CPU time 1486.21 seconds
Started Aug 06 05:29:29 PM PDT 24
Finished Aug 06 05:54:16 PM PDT 24
Peak memory 289164 kb
Host smart-69e2d3ce-01a8-489a-819e-6390ea905b1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197289543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1197289543
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1185804936
Short name T299
Test name
Test status
Simulation time 49626614656 ps
CPU time 1063.14 seconds
Started Aug 06 05:29:40 PM PDT 24
Finished Aug 06 05:47:23 PM PDT 24
Peak memory 273132 kb
Host smart-388fbe52-9bad-4d77-bfda-ca52644a3b3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185804936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1185804936
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.241004891
Short name T322
Test name
Test status
Simulation time 25237591400 ps
CPU time 514.95 seconds
Started Aug 06 05:29:47 PM PDT 24
Finished Aug 06 05:38:22 PM PDT 24
Peak memory 247500 kb
Host smart-ba8ca796-be9a-4cff-afa3-35d03fdc3dcc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241004891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.241004891
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1555867207
Short name T543
Test name
Test status
Simulation time 78969946676 ps
CPU time 1409.25 seconds
Started Aug 06 05:30:35 PM PDT 24
Finished Aug 06 05:54:05 PM PDT 24
Peak memory 289428 kb
Host smart-1139d41b-bf8f-4016-9926-cb2abcb7c0f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555867207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1555867207
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.330830581
Short name T265
Test name
Test status
Simulation time 461517965543 ps
CPU time 1930.4 seconds
Started Aug 06 05:28:30 PM PDT 24
Finished Aug 06 06:00:41 PM PDT 24
Peak memory 273104 kb
Host smart-34c10d51-32d3-46a1-aac7-21a18179b3e6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330830581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_hand
ler_stress_all.330830581
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1486602630
Short name T135
Test name
Test status
Simulation time 12719054084 ps
CPU time 356.85 seconds
Started Aug 06 06:27:03 PM PDT 24
Finished Aug 06 06:33:00 PM PDT 24
Peak memory 265540 kb
Host smart-b742fd2f-1edc-4a2c-8d1f-79bda9de7f4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1486602630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1486602630
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.415623584
Short name T157
Test name
Test status
Simulation time 408775320 ps
CPU time 41.99 seconds
Started Aug 06 06:25:37 PM PDT 24
Finished Aug 06 06:26:19 PM PDT 24
Peak memory 240652 kb
Host smart-841c0e58-1f18-4526-8127-815b1e6a04f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=415623584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.415623584
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2279530931
Short name T131
Test name
Test status
Simulation time 45646912965 ps
CPU time 1212.29 seconds
Started Aug 06 06:24:58 PM PDT 24
Finished Aug 06 06:45:10 PM PDT 24
Peak memory 265596 kb
Host smart-839d7fe0-2c9f-4bb5-bd78-73a27be32e67
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279530931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2279530931
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.4215027457
Short name T346
Test name
Test status
Simulation time 10570767 ps
CPU time 1.38 seconds
Started Aug 06 06:27:01 PM PDT 24
Finished Aug 06 06:27:03 PM PDT 24
Peak memory 235732 kb
Host smart-0bbb4b0d-d2dd-43af-910f-e97a3a4c292f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4215027457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.4215027457
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3526652351
Short name T262
Test name
Test status
Simulation time 247648006 ps
CPU time 7.67 seconds
Started Aug 06 05:28:35 PM PDT 24
Finished Aug 06 05:28:43 PM PDT 24
Peak memory 250852 kb
Host smart-84132bda-4c73-4c3c-85cf-92566310dfa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35266
52351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3526652351
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3914588802
Short name T334
Test name
Test status
Simulation time 48140982402 ps
CPU time 2606 seconds
Started Aug 06 05:29:01 PM PDT 24
Finished Aug 06 06:12:27 PM PDT 24
Peak memory 285792 kb
Host smart-7f41dd1f-1879-4002-b246-815a8b749f88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914588802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3914588802
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3744288430
Short name T264
Test name
Test status
Simulation time 1254594876 ps
CPU time 20.95 seconds
Started Aug 06 05:29:14 PM PDT 24
Finished Aug 06 05:29:35 PM PDT 24
Peak memory 248408 kb
Host smart-6f43a588-e863-44e7-87e2-b57ec51befc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37442
88430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3744288430
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1788716778
Short name T249
Test name
Test status
Simulation time 1558368561 ps
CPU time 20.54 seconds
Started Aug 06 05:29:09 PM PDT 24
Finished Aug 06 05:29:30 PM PDT 24
Peak memory 255644 kb
Host smart-b2c601e5-49c5-4413-b3c8-47df311fc990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17887
16778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1788716778
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.20959117
Short name T294
Test name
Test status
Simulation time 662884903 ps
CPU time 39.76 seconds
Started Aug 06 05:29:07 PM PDT 24
Finished Aug 06 05:29:47 PM PDT 24
Peak memory 248324 kb
Host smart-229b9c0d-787d-453e-9ba3-1673f139ef07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20959
117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.20959117
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1568834327
Short name T298
Test name
Test status
Simulation time 2930038028 ps
CPU time 15.42 seconds
Started Aug 06 05:29:16 PM PDT 24
Finished Aug 06 05:29:32 PM PDT 24
Peak memory 248544 kb
Host smart-c1b2e9d0-87ea-41f6-85a1-74ee47435b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15688
34327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1568834327
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1952098780
Short name T266
Test name
Test status
Simulation time 25911520938 ps
CPU time 1667.89 seconds
Started Aug 06 05:30:14 PM PDT 24
Finished Aug 06 05:58:02 PM PDT 24
Peak memory 282848 kb
Host smart-f34de110-a35b-4f48-aa46-11769d22ffb8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952098780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1952098780
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3870906762
Short name T105
Test name
Test status
Simulation time 766061664 ps
CPU time 50.11 seconds
Started Aug 06 05:30:14 PM PDT 24
Finished Aug 06 05:31:04 PM PDT 24
Peak memory 255828 kb
Host smart-d194decb-6389-4b81-be5f-ab0599b137a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38709
06762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3870906762
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1113591156
Short name T269
Test name
Test status
Simulation time 377883559 ps
CPU time 22.32 seconds
Started Aug 06 05:30:22 PM PDT 24
Finished Aug 06 05:30:44 PM PDT 24
Peak memory 255636 kb
Host smart-14806d7e-b870-45d0-83c8-9865c339229f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11135
91156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1113591156
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2724158698
Short name T293
Test name
Test status
Simulation time 3687008995 ps
CPU time 101.36 seconds
Started Aug 06 05:30:42 PM PDT 24
Finished Aug 06 05:32:24 PM PDT 24
Peak memory 256220 kb
Host smart-c9cd7a13-1d25-4bc7-949d-a15f53d429ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27241
58698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2724158698
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.97545343
Short name T10
Test name
Test status
Simulation time 663128889 ps
CPU time 20.07 seconds
Started Aug 06 05:28:15 PM PDT 24
Finished Aug 06 05:28:35 PM PDT 24
Peak memory 276596 kb
Host smart-3af05fed-d6e4-410d-8009-858485c5c397
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=97545343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.97545343
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.4223239844
Short name T480
Test name
Test status
Simulation time 174899656864 ps
CPU time 3485 seconds
Started Aug 06 05:28:03 PM PDT 24
Finished Aug 06 06:26:08 PM PDT 24
Peak memory 305052 kb
Host smart-ff8fb696-7604-48d3-a58c-2d269239a849
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223239844 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.4223239844
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1281086494
Short name T136
Test name
Test status
Simulation time 33566519574 ps
CPU time 558.99 seconds
Started Aug 06 06:26:01 PM PDT 24
Finished Aug 06 06:35:20 PM PDT 24
Peak memory 265588 kb
Host smart-be024cd0-7540-4564-9d75-5d26d11c217b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281086494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1281086494
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2687388564
Short name T127
Test name
Test status
Simulation time 7628660981 ps
CPU time 157.09 seconds
Started Aug 06 06:25:21 PM PDT 24
Finished Aug 06 06:27:58 PM PDT 24
Peak memory 265596 kb
Host smart-53854d08-d065-4358-bdab-e9f168ea4c23
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2687388564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2687388564
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2935101654
Short name T144
Test name
Test status
Simulation time 7713359721 ps
CPU time 246.24 seconds
Started Aug 06 06:26:47 PM PDT 24
Finished Aug 06 06:30:53 PM PDT 24
Peak memory 264972 kb
Host smart-211ed685-832e-4e2e-bfa4-63fcd78cd845
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2935101654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2935101654
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.4062753462
Short name T155
Test name
Test status
Simulation time 4418297708 ps
CPU time 74.51 seconds
Started Aug 06 06:25:22 PM PDT 24
Finished Aug 06 06:26:37 PM PDT 24
Peak memory 240724 kb
Host smart-a1bebc14-1004-4008-80e0-df13a3ebd29f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4062753462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.4062753462
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1981594188
Short name T158
Test name
Test status
Simulation time 3661270066 ps
CPU time 61.64 seconds
Started Aug 06 06:25:36 PM PDT 24
Finished Aug 06 06:26:38 PM PDT 24
Peak memory 240680 kb
Host smart-3263efe2-c03d-4eab-a5b2-0670dbe0740f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1981594188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1981594188
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2453046315
Short name T162
Test name
Test status
Simulation time 2220233167 ps
CPU time 78.36 seconds
Started Aug 06 06:26:59 PM PDT 24
Finished Aug 06 06:28:17 PM PDT 24
Peak memory 237852 kb
Host smart-30261955-d744-44df-ba81-7c5e418e629c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2453046315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2453046315
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.895794375
Short name T120
Test name
Test status
Simulation time 100074902130 ps
CPU time 352.37 seconds
Started Aug 06 06:26:16 PM PDT 24
Finished Aug 06 06:32:08 PM PDT 24
Peak memory 265616 kb
Host smart-e1d7ca4d-b345-4283-858a-8ae0049ccf05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=895794375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.895794375
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2383754089
Short name T156
Test name
Test status
Simulation time 6163208004 ps
CPU time 97.85 seconds
Started Aug 06 06:26:16 PM PDT 24
Finished Aug 06 06:27:54 PM PDT 24
Peak memory 239052 kb
Host smart-0f09127f-28b2-4b37-b042-1e54fde0cfa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2383754089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2383754089
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.469136452
Short name T159
Test name
Test status
Simulation time 2156303385 ps
CPU time 42.39 seconds
Started Aug 06 06:26:47 PM PDT 24
Finished Aug 06 06:27:29 PM PDT 24
Peak memory 240744 kb
Host smart-7a90147d-282b-45e9-9220-244079e12836
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=469136452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.469136452
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2999573421
Short name T167
Test name
Test status
Simulation time 108161726 ps
CPU time 2.58 seconds
Started Aug 06 06:25:52 PM PDT 24
Finished Aug 06 06:25:55 PM PDT 24
Peak memory 237688 kb
Host smart-1ad40ec5-4537-4a83-8b08-cf401daf2150
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2999573421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2999573421
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1033672188
Short name T161
Test name
Test status
Simulation time 30920649 ps
CPU time 2.96 seconds
Started Aug 06 06:24:57 PM PDT 24
Finished Aug 06 06:25:00 PM PDT 24
Peak memory 237672 kb
Host smart-7e56ff7f-905e-4d93-9fc0-fd8deaaadc95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1033672188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1033672188
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.959135675
Short name T150
Test name
Test status
Simulation time 119253588 ps
CPU time 2.25 seconds
Started Aug 06 06:26:50 PM PDT 24
Finished Aug 06 06:26:52 PM PDT 24
Peak memory 237712 kb
Host smart-99432c19-633d-441b-bc97-14105b37df8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=959135675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.959135675
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2668885801
Short name T168
Test name
Test status
Simulation time 31176327 ps
CPU time 2.63 seconds
Started Aug 06 06:26:51 PM PDT 24
Finished Aug 06 06:26:54 PM PDT 24
Peak memory 237572 kb
Host smart-f58133c5-814f-49dd-a1d6-45b5344c8be2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2668885801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2668885801
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.81613259
Short name T160
Test name
Test status
Simulation time 559733435 ps
CPU time 42.72 seconds
Started Aug 06 06:27:17 PM PDT 24
Finished Aug 06 06:28:00 PM PDT 24
Peak memory 246360 kb
Host smart-f00333f7-9665-4dec-b2da-08a84e682268
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=81613259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.81613259
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.99375834
Short name T163
Test name
Test status
Simulation time 112984259 ps
CPU time 3.24 seconds
Started Aug 06 06:25:20 PM PDT 24
Finished Aug 06 06:25:23 PM PDT 24
Peak memory 237704 kb
Host smart-79b994bd-9157-4c1d-ab61-6c616a58cca5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=99375834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.99375834
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.741328793
Short name T149
Test name
Test status
Simulation time 3560100682 ps
CPU time 73.82 seconds
Started Aug 06 06:25:59 PM PDT 24
Finished Aug 06 06:27:13 PM PDT 24
Peak memory 240680 kb
Host smart-b23b2b26-4284-4612-ae92-3541df29a334
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=741328793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.741328793
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.4017520737
Short name T164
Test name
Test status
Simulation time 316388330 ps
CPU time 24.62 seconds
Started Aug 06 06:25:52 PM PDT 24
Finished Aug 06 06:26:16 PM PDT 24
Peak memory 240636 kb
Host smart-9ce759d6-d0f9-445c-8903-36ae09128719
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4017520737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.4017520737
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1274891920
Short name T166
Test name
Test status
Simulation time 611788819 ps
CPU time 74.31 seconds
Started Aug 06 06:24:58 PM PDT 24
Finished Aug 06 06:26:12 PM PDT 24
Peak memory 240656 kb
Host smart-9ac5a3bb-9526-499f-b5d9-dd33ff400008
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1274891920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1274891920
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1130808067
Short name T805
Test name
Test status
Simulation time 6533527848 ps
CPU time 272.36 seconds
Started Aug 06 06:24:57 PM PDT 24
Finished Aug 06 06:29:30 PM PDT 24
Peak memory 237824 kb
Host smart-dca70324-cd95-4cc4-9763-053a52f4e9c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1130808067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1130808067
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2723247520
Short name T154
Test name
Test status
Simulation time 1877934209 ps
CPU time 12.66 seconds
Started Aug 06 06:24:57 PM PDT 24
Finished Aug 06 06:25:10 PM PDT 24
Peak memory 248864 kb
Host smart-8e0e4d4f-5466-4838-9f33-ffab5716afc3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2723247520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2723247520
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3919006857
Short name T714
Test name
Test status
Simulation time 114904814 ps
CPU time 9.74 seconds
Started Aug 06 06:25:17 PM PDT 24
Finished Aug 06 06:25:27 PM PDT 24
Peak memory 240656 kb
Host smart-4736a579-0c1b-45be-9f32-79cc418beed7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919006857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3919006857
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.60719600
Short name T814
Test name
Test status
Simulation time 29674912 ps
CPU time 3.76 seconds
Started Aug 06 06:24:57 PM PDT 24
Finished Aug 06 06:25:01 PM PDT 24
Peak memory 240584 kb
Host smart-5ad39c00-d5cb-4611-bf7c-96ffb6b5c82f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=60719600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.60719600
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3423812489
Short name T792
Test name
Test status
Simulation time 6281301 ps
CPU time 1.44 seconds
Started Aug 06 06:24:56 PM PDT 24
Finished Aug 06 06:24:57 PM PDT 24
Peak memory 237660 kb
Host smart-bccb7f64-a9d7-44de-b64e-5726f8b0a05f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3423812489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3423812489
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3853038063
Short name T740
Test name
Test status
Simulation time 92078247 ps
CPU time 14.24 seconds
Started Aug 06 06:25:18 PM PDT 24
Finished Aug 06 06:25:32 PM PDT 24
Peak memory 245880 kb
Host smart-334a4b72-6ced-45ab-9b73-1e1d6a8e4729
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3853038063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3853038063
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.829204320
Short name T700
Test name
Test status
Simulation time 130070612 ps
CPU time 5.92 seconds
Started Aug 06 06:24:58 PM PDT 24
Finished Aug 06 06:25:04 PM PDT 24
Peak memory 246080 kb
Host smart-eed799d7-86cd-4ad9-bde2-eab0b07fcbdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=829204320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.829204320
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1637769993
Short name T786
Test name
Test status
Simulation time 45880093410 ps
CPU time 253.23 seconds
Started Aug 06 06:25:20 PM PDT 24
Finished Aug 06 06:29:33 PM PDT 24
Peak memory 239492 kb
Host smart-b00047ff-f4d1-46ae-8fe1-c6b11a419eab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1637769993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1637769993
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2866877858
Short name T797
Test name
Test status
Simulation time 12955497338 ps
CPU time 202.93 seconds
Started Aug 06 06:25:22 PM PDT 24
Finished Aug 06 06:28:45 PM PDT 24
Peak memory 237828 kb
Host smart-5cf4ea09-493e-439f-812e-528610d3224a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2866877858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2866877858
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1462876641
Short name T716
Test name
Test status
Simulation time 105336808 ps
CPU time 10.13 seconds
Started Aug 06 06:25:19 PM PDT 24
Finished Aug 06 06:25:30 PM PDT 24
Peak memory 249304 kb
Host smart-62e84f8c-c7cd-494e-a852-996c643aa467
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1462876641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1462876641
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.4044956938
Short name T239
Test name
Test status
Simulation time 197163322 ps
CPU time 15.35 seconds
Started Aug 06 06:25:19 PM PDT 24
Finished Aug 06 06:25:35 PM PDT 24
Peak memory 251920 kb
Host smart-e63e490a-d6a7-479b-9a03-c4cb63c404d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044956938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.4044956938
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1349401353
Short name T242
Test name
Test status
Simulation time 216587428 ps
CPU time 4.53 seconds
Started Aug 06 06:25:19 PM PDT 24
Finished Aug 06 06:25:23 PM PDT 24
Peak memory 236820 kb
Host smart-a7962f62-3873-4ca9-849d-0fd3dde50d19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1349401353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1349401353
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2806611827
Short name T802
Test name
Test status
Simulation time 11396369 ps
CPU time 1.25 seconds
Started Aug 06 06:25:18 PM PDT 24
Finished Aug 06 06:25:19 PM PDT 24
Peak memory 237668 kb
Host smart-1642d901-cb9d-4f3a-80ab-625044037bed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2806611827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2806611827
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1802268242
Short name T800
Test name
Test status
Simulation time 3191911875 ps
CPU time 21.98 seconds
Started Aug 06 06:25:20 PM PDT 24
Finished Aug 06 06:25:42 PM PDT 24
Peak memory 240740 kb
Host smart-16e7e097-e76f-498c-95ad-abd75cf11e01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1802268242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1802268242
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1261010641
Short name T701
Test name
Test status
Simulation time 91828488 ps
CPU time 14.86 seconds
Started Aug 06 06:25:18 PM PDT 24
Finished Aug 06 06:25:33 PM PDT 24
Peak memory 254952 kb
Host smart-62003648-3b60-40cd-840e-1b89212149f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1261010641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1261010641
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2922711730
Short name T720
Test name
Test status
Simulation time 64773102 ps
CPU time 6.04 seconds
Started Aug 06 06:26:48 PM PDT 24
Finished Aug 06 06:26:54 PM PDT 24
Peak memory 254056 kb
Host smart-55a87901-f1a1-4539-9267-4edfd5fa59cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922711730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2922711730
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1003089354
Short name T198
Test name
Test status
Simulation time 65021624 ps
CPU time 5.42 seconds
Started Aug 06 06:26:46 PM PDT 24
Finished Aug 06 06:26:51 PM PDT 24
Peak memory 240536 kb
Host smart-54c5187a-5aa5-43c0-9f4a-11414743dca4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1003089354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1003089354
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.634230934
Short name T818
Test name
Test status
Simulation time 19558322 ps
CPU time 1.77 seconds
Started Aug 06 06:26:51 PM PDT 24
Finished Aug 06 06:26:53 PM PDT 24
Peak memory 237672 kb
Host smart-2c0d4214-851b-4c23-8726-1e76c08bdc57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=634230934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.634230934
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2416995160
Short name T795
Test name
Test status
Simulation time 281994112 ps
CPU time 19.71 seconds
Started Aug 06 06:26:47 PM PDT 24
Finished Aug 06 06:27:07 PM PDT 24
Peak memory 244964 kb
Host smart-3433158a-6015-437e-a9d1-a5eb289052e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2416995160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2416995160
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.930368643
Short name T755
Test name
Test status
Simulation time 2211577727 ps
CPU time 19.82 seconds
Started Aug 06 06:26:17 PM PDT 24
Finished Aug 06 06:26:37 PM PDT 24
Peak memory 248164 kb
Host smart-a920cc21-08f9-4923-b7c4-0b436ab39987
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=930368643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.930368643
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.423510836
Short name T781
Test name
Test status
Simulation time 100609137 ps
CPU time 9.14 seconds
Started Aug 06 06:26:47 PM PDT 24
Finished Aug 06 06:26:57 PM PDT 24
Peak memory 239748 kb
Host smart-cb6b8ec9-64ee-4118-b0b7-2533b087ba2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423510836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.alert_handler_csr_mem_rw_with_rand_reset.423510836
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2487444061
Short name T790
Test name
Test status
Simulation time 1269780432 ps
CPU time 7.62 seconds
Started Aug 06 06:26:51 PM PDT 24
Finished Aug 06 06:26:59 PM PDT 24
Peak memory 240548 kb
Host smart-a3da1f4e-797e-4846-bfeb-4d71a54d2332
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2487444061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2487444061
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1589157433
Short name T813
Test name
Test status
Simulation time 33249642 ps
CPU time 1.46 seconds
Started Aug 06 06:26:47 PM PDT 24
Finished Aug 06 06:26:49 PM PDT 24
Peak memory 237684 kb
Host smart-b148d69c-01a3-4eda-a65c-428b986ad556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1589157433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1589157433
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1536216385
Short name T729
Test name
Test status
Simulation time 519899572 ps
CPU time 39.63 seconds
Started Aug 06 06:26:51 PM PDT 24
Finished Aug 06 06:27:31 PM PDT 24
Peak memory 248748 kb
Host smart-72bd60b4-f608-45e2-a21a-6fb9b5bf0eda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1536216385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1536216385
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.54437842
Short name T148
Test name
Test status
Simulation time 4837990705 ps
CPU time 90.63 seconds
Started Aug 06 06:26:45 PM PDT 24
Finished Aug 06 06:28:16 PM PDT 24
Peak memory 265668 kb
Host smart-6744c922-e938-454e-91be-ef94b7563b0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54437842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_error
s.54437842
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2517624538
Short name T352
Test name
Test status
Simulation time 6377833015 ps
CPU time 425.04 seconds
Started Aug 06 06:26:47 PM PDT 24
Finished Aug 06 06:33:53 PM PDT 24
Peak memory 269044 kb
Host smart-b5730acc-7f44-4495-bdf1-835dc0cf5d05
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517624538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2517624538
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1525060564
Short name T817
Test name
Test status
Simulation time 865206291 ps
CPU time 8.77 seconds
Started Aug 06 06:26:47 PM PDT 24
Finished Aug 06 06:26:56 PM PDT 24
Peak memory 254204 kb
Host smart-63bfa2d4-4b89-446f-81e6-34edf9f991b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1525060564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1525060564
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.84229891
Short name T275
Test name
Test status
Simulation time 4025698211 ps
CPU time 65.44 seconds
Started Aug 06 06:26:49 PM PDT 24
Finished Aug 06 06:27:55 PM PDT 24
Peak memory 240688 kb
Host smart-3f0e8e34-c552-4f03-919b-496279dd04d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=84229891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.84229891
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2578394257
Short name T798
Test name
Test status
Simulation time 348726233 ps
CPU time 7.3 seconds
Started Aug 06 06:26:48 PM PDT 24
Finished Aug 06 06:26:55 PM PDT 24
Peak memory 240880 kb
Host smart-86805c29-6b4d-4d30-919c-d383d5bdc9cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578394257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2578394257
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3782159544
Short name T711
Test name
Test status
Simulation time 66102172 ps
CPU time 6.17 seconds
Started Aug 06 06:26:47 PM PDT 24
Finished Aug 06 06:26:54 PM PDT 24
Peak memory 237608 kb
Host smart-9939092b-8e2d-498e-939a-877110761014
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3782159544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3782159544
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.237151246
Short name T804
Test name
Test status
Simulation time 18419969 ps
CPU time 1.39 seconds
Started Aug 06 06:26:47 PM PDT 24
Finished Aug 06 06:26:49 PM PDT 24
Peak memory 236780 kb
Host smart-387ed58e-dec2-4d9e-9b83-e0a3f3f2b4f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=237151246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.237151246
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2899602197
Short name T801
Test name
Test status
Simulation time 239009365 ps
CPU time 19.77 seconds
Started Aug 06 06:26:46 PM PDT 24
Finished Aug 06 06:27:06 PM PDT 24
Peak memory 245024 kb
Host smart-4971720f-7f01-4c9e-9e46-f343b503ffa7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2899602197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2899602197
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2158308761
Short name T354
Test name
Test status
Simulation time 18979734720 ps
CPU time 460.02 seconds
Started Aug 06 06:26:47 PM PDT 24
Finished Aug 06 06:34:27 PM PDT 24
Peak memory 265488 kb
Host smart-570ba46d-83f3-4fed-95e0-d7ec661fbccb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158308761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2158308761
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1697159734
Short name T702
Test name
Test status
Simulation time 176002245 ps
CPU time 9.34 seconds
Started Aug 06 06:26:49 PM PDT 24
Finished Aug 06 06:26:59 PM PDT 24
Peak memory 248576 kb
Host smart-2ba0da15-b879-4161-a416-7dca23377e7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1697159734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1697159734
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1585418470
Short name T731
Test name
Test status
Simulation time 101060250 ps
CPU time 8.49 seconds
Started Aug 06 06:26:46 PM PDT 24
Finished Aug 06 06:26:55 PM PDT 24
Peak memory 238740 kb
Host smart-40437b5b-f56b-4890-8739-a6c6b5e70eef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585418470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1585418470
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.38743353
Short name T782
Test name
Test status
Simulation time 126063291 ps
CPU time 5.23 seconds
Started Aug 06 06:26:47 PM PDT 24
Finished Aug 06 06:26:52 PM PDT 24
Peak memory 237656 kb
Host smart-b2a194d6-249c-4903-a564-8d3a2ae0c1a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=38743353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.38743353
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2240285322
Short name T748
Test name
Test status
Simulation time 11560021 ps
CPU time 1.45 seconds
Started Aug 06 06:26:51 PM PDT 24
Finished Aug 06 06:26:52 PM PDT 24
Peak memory 237620 kb
Host smart-0d574697-ffdb-4a3e-b88c-36c3277f9766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2240285322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2240285322
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.4169335247
Short name T753
Test name
Test status
Simulation time 2056614527 ps
CPU time 38.97 seconds
Started Aug 06 06:26:47 PM PDT 24
Finished Aug 06 06:27:26 PM PDT 24
Peak memory 245916 kb
Host smart-11a0b0a3-b7aa-4f5a-a64c-ade19a90f6d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4169335247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.4169335247
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2927101219
Short name T119
Test name
Test status
Simulation time 5113936229 ps
CPU time 135.17 seconds
Started Aug 06 06:26:46 PM PDT 24
Finished Aug 06 06:29:01 PM PDT 24
Peak memory 265648 kb
Host smart-9710116b-02c8-4e76-be8a-0996f515494e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2927101219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2927101219
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3490796701
Short name T353
Test name
Test status
Simulation time 8886364177 ps
CPU time 669.56 seconds
Started Aug 06 06:26:46 PM PDT 24
Finished Aug 06 06:37:56 PM PDT 24
Peak memory 265844 kb
Host smart-cdbea503-0a99-478a-ab50-863a48d440c3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490796701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3490796701
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1355560907
Short name T791
Test name
Test status
Simulation time 51716910 ps
CPU time 8.69 seconds
Started Aug 06 06:26:47 PM PDT 24
Finished Aug 06 06:26:56 PM PDT 24
Peak memory 248852 kb
Host smart-aff383dd-c581-40dd-a764-48ad84ce3767
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1355560907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1355560907
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1958750674
Short name T773
Test name
Test status
Simulation time 69016384 ps
CPU time 6.95 seconds
Started Aug 06 06:27:02 PM PDT 24
Finished Aug 06 06:27:09 PM PDT 24
Peak memory 248976 kb
Host smart-5b09a949-1e77-4085-a322-68cd9fd938b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958750674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1958750674
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.341286412
Short name T806
Test name
Test status
Simulation time 194996669 ps
CPU time 5.73 seconds
Started Aug 06 06:26:47 PM PDT 24
Finished Aug 06 06:26:53 PM PDT 24
Peak memory 237700 kb
Host smart-80010aee-36bb-4c51-b150-11b300dff102
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=341286412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.341286412
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2274708159
Short name T788
Test name
Test status
Simulation time 8270770 ps
CPU time 1.36 seconds
Started Aug 06 06:26:47 PM PDT 24
Finished Aug 06 06:26:48 PM PDT 24
Peak memory 237756 kb
Host smart-0cdaa1a9-cc16-48cd-ad95-bc885830873f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2274708159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2274708159
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.619169399
Short name T742
Test name
Test status
Simulation time 697069562 ps
CPU time 24.26 seconds
Started Aug 06 06:26:59 PM PDT 24
Finished Aug 06 06:27:23 PM PDT 24
Peak memory 248780 kb
Host smart-5582ad1e-6bf8-44b1-9398-0a4562bd5052
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=619169399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.619169399
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2838611995
Short name T822
Test name
Test status
Simulation time 18943148308 ps
CPU time 663.28 seconds
Started Aug 06 06:26:52 PM PDT 24
Finished Aug 06 06:37:55 PM PDT 24
Peak memory 265644 kb
Host smart-0af093e4-06e6-4df6-858d-29d382787892
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838611995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2838611995
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3311269686
Short name T815
Test name
Test status
Simulation time 677528727 ps
CPU time 23.1 seconds
Started Aug 06 06:26:48 PM PDT 24
Finished Aug 06 06:27:11 PM PDT 24
Peak memory 248884 kb
Host smart-cbe8ed3d-d72c-4f69-8716-e6ae4baad6a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3311269686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3311269686
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.4034341471
Short name T724
Test name
Test status
Simulation time 158059556 ps
CPU time 13.32 seconds
Started Aug 06 06:26:59 PM PDT 24
Finished Aug 06 06:27:13 PM PDT 24
Peak memory 252140 kb
Host smart-da164b72-42b0-4b56-acbe-b21c8f938541
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034341471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.4034341471
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3365270576
Short name T789
Test name
Test status
Simulation time 19607437 ps
CPU time 3.5 seconds
Started Aug 06 06:26:58 PM PDT 24
Finished Aug 06 06:27:02 PM PDT 24
Peak memory 236764 kb
Host smart-7a43fcc0-8289-49cb-992b-a2f2d99fde78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3365270576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3365270576
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.367748666
Short name T812
Test name
Test status
Simulation time 7472092 ps
CPU time 1.39 seconds
Started Aug 06 06:27:01 PM PDT 24
Finished Aug 06 06:27:02 PM PDT 24
Peak memory 235828 kb
Host smart-b9572384-ec80-4498-886f-554d92e1484d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=367748666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.367748666
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.4048151012
Short name T766
Test name
Test status
Simulation time 2412443111 ps
CPU time 41.35 seconds
Started Aug 06 06:27:01 PM PDT 24
Finished Aug 06 06:27:42 PM PDT 24
Peak memory 245032 kb
Host smart-e2b07f80-1116-4470-8e7d-4aca8da43813
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4048151012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.4048151012
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2408763442
Short name T141
Test name
Test status
Simulation time 15302941904 ps
CPU time 440.76 seconds
Started Aug 06 06:27:03 PM PDT 24
Finished Aug 06 06:34:24 PM PDT 24
Peak memory 268716 kb
Host smart-9559a02e-bd6a-42c1-9a93-c3bc20bc2bc6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408763442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2408763442
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1180863955
Short name T763
Test name
Test status
Simulation time 205084681 ps
CPU time 14.71 seconds
Started Aug 06 06:26:59 PM PDT 24
Finished Aug 06 06:27:14 PM PDT 24
Peak memory 248140 kb
Host smart-63b6cef0-0d94-4737-9445-f27bcadaed6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1180863955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1180863955
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.459722917
Short name T765
Test name
Test status
Simulation time 806093021 ps
CPU time 12.41 seconds
Started Aug 06 06:27:02 PM PDT 24
Finished Aug 06 06:27:15 PM PDT 24
Peak memory 251136 kb
Host smart-4bb3f49e-6957-44bb-b478-881694499387
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459722917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.459722917
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1036145175
Short name T185
Test name
Test status
Simulation time 135794665 ps
CPU time 10.19 seconds
Started Aug 06 06:27:00 PM PDT 24
Finished Aug 06 06:27:10 PM PDT 24
Peak memory 240560 kb
Host smart-9602f6bc-e19c-46c5-a26d-24cfeaf492c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1036145175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1036145175
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3975479326
Short name T816
Test name
Test status
Simulation time 94235627 ps
CPU time 13.13 seconds
Started Aug 06 06:27:00 PM PDT 24
Finished Aug 06 06:27:13 PM PDT 24
Peak memory 245884 kb
Host smart-4d837ea9-4753-4fe9-8221-57a700dcc882
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3975479326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3975479326
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1603247676
Short name T132
Test name
Test status
Simulation time 4623959872 ps
CPU time 337.46 seconds
Started Aug 06 06:27:03 PM PDT 24
Finished Aug 06 06:32:41 PM PDT 24
Peak memory 273152 kb
Host smart-9b1cff26-aff5-4fed-b2cb-b8b9d870dbdb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1603247676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1603247676
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1030862905
Short name T704
Test name
Test status
Simulation time 491626885 ps
CPU time 20.79 seconds
Started Aug 06 06:26:58 PM PDT 24
Finished Aug 06 06:27:19 PM PDT 24
Peak memory 248796 kb
Host smart-18f0fe1c-8afa-4a10-837b-fb7425feff65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1030862905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1030862905
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3142381945
Short name T783
Test name
Test status
Simulation time 291020888 ps
CPU time 2.93 seconds
Started Aug 06 06:27:00 PM PDT 24
Finished Aug 06 06:27:03 PM PDT 24
Peak memory 238088 kb
Host smart-673b34f8-17fa-4713-a3a4-9f59873de263
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3142381945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3142381945
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.636819078
Short name T810
Test name
Test status
Simulation time 88099867 ps
CPU time 7.54 seconds
Started Aug 06 06:27:21 PM PDT 24
Finished Aug 06 06:27:28 PM PDT 24
Peak memory 239652 kb
Host smart-b63f01e8-f625-4586-9cdc-e2b4d7df26a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636819078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.636819078
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.967464056
Short name T793
Test name
Test status
Simulation time 50326300 ps
CPU time 4.44 seconds
Started Aug 06 06:27:15 PM PDT 24
Finished Aug 06 06:27:19 PM PDT 24
Peak memory 237656 kb
Host smart-b9a5e0d4-f13f-4a7a-bfff-14fa356ad91f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=967464056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.967464056
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.535496392
Short name T730
Test name
Test status
Simulation time 17557056 ps
CPU time 1.37 seconds
Started Aug 06 06:27:18 PM PDT 24
Finished Aug 06 06:27:19 PM PDT 24
Peak memory 236740 kb
Host smart-0d0a9f7d-669e-4057-b832-6dd4de44cc1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=535496392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.535496392
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2362840924
Short name T710
Test name
Test status
Simulation time 987494952 ps
CPU time 24.56 seconds
Started Aug 06 06:27:20 PM PDT 24
Finished Aug 06 06:27:45 PM PDT 24
Peak memory 248820 kb
Host smart-fd5e18f8-6505-43fb-a6e9-88e64b1047ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2362840924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2362840924
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.655446333
Short name T118
Test name
Test status
Simulation time 2003988419 ps
CPU time 134.83 seconds
Started Aug 06 06:27:03 PM PDT 24
Finished Aug 06 06:29:18 PM PDT 24
Peak memory 265468 kb
Host smart-6052df6d-2aaf-4487-bf1b-8b5dcd0ea34c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=655446333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.655446333
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.188378513
Short name T126
Test name
Test status
Simulation time 31525158369 ps
CPU time 592.72 seconds
Started Aug 06 06:27:02 PM PDT 24
Finished Aug 06 06:36:55 PM PDT 24
Peak memory 265600 kb
Host smart-51367bab-7f4b-4cbf-8e88-ced4e98e8b01
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188378513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.188378513
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1416977091
Short name T736
Test name
Test status
Simulation time 86502358 ps
CPU time 5.33 seconds
Started Aug 06 06:27:03 PM PDT 24
Finished Aug 06 06:27:09 PM PDT 24
Peak memory 249696 kb
Host smart-30d2244f-185d-41f4-95a3-96dc25ac7696
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1416977091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1416977091
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1379082649
Short name T712
Test name
Test status
Simulation time 127219210 ps
CPU time 11.24 seconds
Started Aug 06 06:27:18 PM PDT 24
Finished Aug 06 06:27:30 PM PDT 24
Peak memory 251960 kb
Host smart-e780169d-40b5-4fab-a9f0-aeb9943eb3ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379082649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1379082649
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3935426562
Short name T703
Test name
Test status
Simulation time 51167768 ps
CPU time 4.61 seconds
Started Aug 06 06:27:17 PM PDT 24
Finished Aug 06 06:27:21 PM PDT 24
Peak memory 237672 kb
Host smart-5a2f1183-196e-446e-a266-e93f59c6f7aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3935426562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3935426562
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.4034560308
Short name T723
Test name
Test status
Simulation time 9615305 ps
CPU time 1.58 seconds
Started Aug 06 06:27:18 PM PDT 24
Finished Aug 06 06:27:20 PM PDT 24
Peak memory 237728 kb
Host smart-cdab0adc-149f-487a-b156-7b9d09ff2cce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4034560308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.4034560308
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1505227685
Short name T761
Test name
Test status
Simulation time 263320998 ps
CPU time 20.91 seconds
Started Aug 06 06:27:18 PM PDT 24
Finished Aug 06 06:27:39 PM PDT 24
Peak memory 245892 kb
Host smart-1598574d-da6c-490f-bbfd-74e0d36f39cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1505227685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1505227685
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1540596142
Short name T143
Test name
Test status
Simulation time 13173858097 ps
CPU time 300.63 seconds
Started Aug 06 06:27:18 PM PDT 24
Finished Aug 06 06:32:19 PM PDT 24
Peak memory 265872 kb
Host smart-2c298a8c-696c-4415-8f4c-58e868b493be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1540596142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1540596142
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3377157362
Short name T128
Test name
Test status
Simulation time 17171444488 ps
CPU time 1237.99 seconds
Started Aug 06 06:27:19 PM PDT 24
Finished Aug 06 06:47:57 PM PDT 24
Peak memory 265712 kb
Host smart-ddb55f4f-cef5-418a-bc9f-a1db22e979f5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377157362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.3377157362
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.451134960
Short name T722
Test name
Test status
Simulation time 281166135 ps
CPU time 17.53 seconds
Started Aug 06 06:27:19 PM PDT 24
Finished Aug 06 06:27:37 PM PDT 24
Peak memory 254388 kb
Host smart-0143f2ad-940a-4bc1-abed-60388a952bb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=451134960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.451134960
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1923125252
Short name T803
Test name
Test status
Simulation time 634341856 ps
CPU time 27.6 seconds
Started Aug 06 06:27:17 PM PDT 24
Finished Aug 06 06:27:44 PM PDT 24
Peak memory 240640 kb
Host smart-8831cffb-661a-4d78-8cfe-2c8bdf074d3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1923125252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1923125252
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1799698646
Short name T767
Test name
Test status
Simulation time 243062963 ps
CPU time 11.52 seconds
Started Aug 06 06:27:18 PM PDT 24
Finished Aug 06 06:27:29 PM PDT 24
Peak memory 243748 kb
Host smart-798f5014-5e9a-472a-a1d7-76c0bde855f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799698646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1799698646
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1789212003
Short name T785
Test name
Test status
Simulation time 356281037 ps
CPU time 9.02 seconds
Started Aug 06 06:27:18 PM PDT 24
Finished Aug 06 06:27:27 PM PDT 24
Peak memory 237608 kb
Host smart-01f9d62d-e682-4e36-968b-f204fae40296
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1789212003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1789212003
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1854612308
Short name T349
Test name
Test status
Simulation time 9798508 ps
CPU time 1.38 seconds
Started Aug 06 06:27:18 PM PDT 24
Finished Aug 06 06:27:19 PM PDT 24
Peak memory 237664 kb
Host smart-4a33621a-87bb-40f4-894d-8e7d19748924
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1854612308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1854612308
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3486472362
Short name T734
Test name
Test status
Simulation time 172798067 ps
CPU time 22.17 seconds
Started Aug 06 06:27:18 PM PDT 24
Finished Aug 06 06:27:41 PM PDT 24
Peak memory 245848 kb
Host smart-badcb72b-22b5-4378-84a3-3a81ab9675e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3486472362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3486472362
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.8519676
Short name T778
Test name
Test status
Simulation time 518339291 ps
CPU time 23.32 seconds
Started Aug 06 06:27:16 PM PDT 24
Finished Aug 06 06:27:40 PM PDT 24
Peak memory 248872 kb
Host smart-d5055bd5-b386-4ffe-a1b3-2460e2f73ab6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=8519676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.8519676
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2539913179
Short name T771
Test name
Test status
Simulation time 1066182333 ps
CPU time 33.7 seconds
Started Aug 06 06:27:16 PM PDT 24
Finished Aug 06 06:27:49 PM PDT 24
Peak memory 237900 kb
Host smart-cb11f5d6-9963-4442-be05-d0c33b9b1e8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2539913179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2539913179
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.36110976
Short name T184
Test name
Test status
Simulation time 1196413962 ps
CPU time 137.84 seconds
Started Aug 06 06:25:21 PM PDT 24
Finished Aug 06 06:27:39 PM PDT 24
Peak memory 241276 kb
Host smart-978c2b54-1b40-4d24-8024-6f0e8d2706b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=36110976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.36110976
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1561274762
Short name T820
Test name
Test status
Simulation time 3270121085 ps
CPU time 110.58 seconds
Started Aug 06 06:25:20 PM PDT 24
Finished Aug 06 06:27:11 PM PDT 24
Peak memory 240560 kb
Host smart-423b8ad4-2536-4143-99a5-a0751712319c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1561274762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1561274762
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.348310271
Short name T754
Test name
Test status
Simulation time 40004553 ps
CPU time 3.81 seconds
Started Aug 06 06:25:21 PM PDT 24
Finished Aug 06 06:25:25 PM PDT 24
Peak memory 240600 kb
Host smart-e5300b08-705f-4e76-ab09-1fd8b33af8e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=348310271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.348310271
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2994374335
Short name T769
Test name
Test status
Simulation time 123037312 ps
CPU time 8.71 seconds
Started Aug 06 06:25:20 PM PDT 24
Finished Aug 06 06:25:29 PM PDT 24
Peak memory 240652 kb
Host smart-cd1068a2-594a-46de-bb18-8a93b4462214
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994374335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2994374335
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2520330517
Short name T752
Test name
Test status
Simulation time 30149116 ps
CPU time 3.59 seconds
Started Aug 06 06:25:21 PM PDT 24
Finished Aug 06 06:25:25 PM PDT 24
Peak memory 237632 kb
Host smart-09ba87ed-f4af-48f9-b239-49d441148e9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2520330517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2520330517
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2849164467
Short name T351
Test name
Test status
Simulation time 8704246 ps
CPU time 1.52 seconds
Started Aug 06 06:25:21 PM PDT 24
Finished Aug 06 06:25:23 PM PDT 24
Peak memory 237704 kb
Host smart-174789cb-c49f-4b06-a469-abf1561181bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2849164467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2849164467
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1014796010
Short name T774
Test name
Test status
Simulation time 185090841 ps
CPU time 19.48 seconds
Started Aug 06 06:25:21 PM PDT 24
Finished Aug 06 06:25:41 PM PDT 24
Peak memory 244940 kb
Host smart-010268fc-e9fb-424c-bbba-ff19ec5f8219
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1014796010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1014796010
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.182281028
Short name T130
Test name
Test status
Simulation time 33800078399 ps
CPU time 1160.52 seconds
Started Aug 06 06:25:19 PM PDT 24
Finished Aug 06 06:44:40 PM PDT 24
Peak memory 272500 kb
Host smart-b7268ab8-6ccf-47f1-be8f-30969e27be8c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182281028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.182281028
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2652170965
Short name T706
Test name
Test status
Simulation time 1677747106 ps
CPU time 19.84 seconds
Started Aug 06 06:25:21 PM PDT 24
Finished Aug 06 06:25:40 PM PDT 24
Peak memory 254260 kb
Host smart-cd959a54-5711-46b7-87ed-ddb753961571
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2652170965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2652170965
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1764706952
Short name T777
Test name
Test status
Simulation time 10367045 ps
CPU time 1.28 seconds
Started Aug 06 06:27:21 PM PDT 24
Finished Aug 06 06:27:22 PM PDT 24
Peak memory 237700 kb
Host smart-519ef487-64b1-4323-b50f-63f043ea263b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1764706952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1764706952
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1280032882
Short name T780
Test name
Test status
Simulation time 18283962 ps
CPU time 1.34 seconds
Started Aug 06 06:27:17 PM PDT 24
Finished Aug 06 06:27:18 PM PDT 24
Peak memory 235700 kb
Host smart-64bfce18-e222-47b7-bbec-db85bdab2de7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1280032882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1280032882
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2855010263
Short name T152
Test name
Test status
Simulation time 6781113 ps
CPU time 1.47 seconds
Started Aug 06 06:27:32 PM PDT 24
Finished Aug 06 06:27:33 PM PDT 24
Peak memory 236724 kb
Host smart-f351b52d-9b6f-46d0-98ad-eb5729084651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2855010263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2855010263
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1203304877
Short name T725
Test name
Test status
Simulation time 18976857 ps
CPU time 1.86 seconds
Started Aug 06 06:27:32 PM PDT 24
Finished Aug 06 06:27:34 PM PDT 24
Peak memory 237756 kb
Host smart-35fddcd5-3cd6-4003-b617-e99f0de4b493
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1203304877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1203304877
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3343260311
Short name T758
Test name
Test status
Simulation time 11260234 ps
CPU time 1.38 seconds
Started Aug 06 06:27:31 PM PDT 24
Finished Aug 06 06:27:33 PM PDT 24
Peak memory 237584 kb
Host smart-4a284f80-c33e-41a4-bd1e-cd99e132ef1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3343260311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3343260311
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3890733828
Short name T721
Test name
Test status
Simulation time 11728095 ps
CPU time 1.49 seconds
Started Aug 06 06:27:34 PM PDT 24
Finished Aug 06 06:27:36 PM PDT 24
Peak memory 237696 kb
Host smart-936e648f-77a4-41d4-bab0-8273c1be50ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3890733828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3890733828
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.4149892927
Short name T749
Test name
Test status
Simulation time 9121325 ps
CPU time 1.56 seconds
Started Aug 06 06:27:31 PM PDT 24
Finished Aug 06 06:27:33 PM PDT 24
Peak memory 237652 kb
Host smart-583f2854-6def-4e7d-996b-63b220272ab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4149892927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.4149892927
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2259492571
Short name T728
Test name
Test status
Simulation time 17256713 ps
CPU time 1.47 seconds
Started Aug 06 06:27:32 PM PDT 24
Finished Aug 06 06:27:34 PM PDT 24
Peak memory 237708 kb
Host smart-5d053f9f-082f-4765-828d-dc3d38c064c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2259492571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2259492571
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3976664694
Short name T779
Test name
Test status
Simulation time 6773761 ps
CPU time 1.47 seconds
Started Aug 06 06:27:32 PM PDT 24
Finished Aug 06 06:27:33 PM PDT 24
Peak memory 236768 kb
Host smart-c1a66b02-56f4-4ffd-a1db-b23d1e53ca4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3976664694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3976664694
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3861700871
Short name T727
Test name
Test status
Simulation time 9832243 ps
CPU time 1.62 seconds
Started Aug 06 06:27:32 PM PDT 24
Finished Aug 06 06:27:34 PM PDT 24
Peak memory 236636 kb
Host smart-e910ae26-82cc-4483-9f49-14000f0a3f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3861700871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3861700871
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1358102789
Short name T739
Test name
Test status
Simulation time 1139013296 ps
CPU time 75.15 seconds
Started Aug 06 06:25:22 PM PDT 24
Finished Aug 06 06:26:38 PM PDT 24
Peak memory 237684 kb
Host smart-b7ab7b25-e595-4338-857c-8fef2dcf1050
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1358102789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1358102789
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.867042087
Short name T182
Test name
Test status
Simulation time 855252234 ps
CPU time 133.34 seconds
Started Aug 06 06:25:21 PM PDT 24
Finished Aug 06 06:27:34 PM PDT 24
Peak memory 237684 kb
Host smart-cec39369-6e23-46c7-992a-455489496419
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=867042087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.867042087
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.522651737
Short name T737
Test name
Test status
Simulation time 809655973 ps
CPU time 5.6 seconds
Started Aug 06 06:25:19 PM PDT 24
Finished Aug 06 06:25:25 PM PDT 24
Peak memory 248760 kb
Host smart-1b984326-01c3-45dd-be91-cf8092a5ec14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=522651737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.522651737
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1725728371
Short name T747
Test name
Test status
Simulation time 72607042 ps
CPU time 6.68 seconds
Started Aug 06 06:25:36 PM PDT 24
Finished Aug 06 06:25:42 PM PDT 24
Peak memory 257008 kb
Host smart-c48b4cb0-a2f2-4753-9c48-b2e5b75498b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725728371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1725728371
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.339161555
Short name T165
Test name
Test status
Simulation time 171340102 ps
CPU time 4.35 seconds
Started Aug 06 06:25:22 PM PDT 24
Finished Aug 06 06:25:27 PM PDT 24
Peak memory 237680 kb
Host smart-b63ac78c-fa1e-41a3-b72a-a3aab4dfa5a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=339161555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.339161555
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.148290404
Short name T234
Test name
Test status
Simulation time 10531306 ps
CPU time 1.69 seconds
Started Aug 06 06:25:22 PM PDT 24
Finished Aug 06 06:25:24 PM PDT 24
Peak memory 236676 kb
Host smart-bba86512-28ec-4b8b-ad57-1a5619b969b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=148290404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.148290404
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3114913821
Short name T738
Test name
Test status
Simulation time 88914306 ps
CPU time 11.33 seconds
Started Aug 06 06:25:36 PM PDT 24
Finished Aug 06 06:25:47 PM PDT 24
Peak memory 240516 kb
Host smart-c542a2a5-17f3-499e-9810-2d3e7c053d8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3114913821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3114913821
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.887360582
Short name T137
Test name
Test status
Simulation time 2353847626 ps
CPU time 188.41 seconds
Started Aug 06 06:25:21 PM PDT 24
Finished Aug 06 06:28:29 PM PDT 24
Peak memory 271836 kb
Host smart-59fc6ae8-fa85-4d6e-bdfe-71298f8427ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=887360582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.887360582
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3169781708
Short name T138
Test name
Test status
Simulation time 2346776085 ps
CPU time 302 seconds
Started Aug 06 06:25:22 PM PDT 24
Finished Aug 06 06:30:24 PM PDT 24
Peak memory 269836 kb
Host smart-316159da-42ab-4c77-bc18-71e4fedbdcd9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169781708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3169781708
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1388238690
Short name T762
Test name
Test status
Simulation time 303893347 ps
CPU time 19.46 seconds
Started Aug 06 06:25:21 PM PDT 24
Finished Aug 06 06:25:41 PM PDT 24
Peak memory 254612 kb
Host smart-4bc444d4-7a0b-4d71-a538-c318c471f544
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1388238690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1388238690
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1119465308
Short name T807
Test name
Test status
Simulation time 8792232 ps
CPU time 1.53 seconds
Started Aug 06 06:27:32 PM PDT 24
Finished Aug 06 06:27:34 PM PDT 24
Peak memory 237660 kb
Host smart-c6ea3252-d164-4fd7-bb8e-a6e413ae0ae3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1119465308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1119465308
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.616243873
Short name T772
Test name
Test status
Simulation time 6788235 ps
CPU time 1.43 seconds
Started Aug 06 06:27:33 PM PDT 24
Finished Aug 06 06:27:34 PM PDT 24
Peak memory 237672 kb
Host smart-775d19e9-d3d4-46d6-9484-d5dce65dcfb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=616243873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.616243873
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.333435310
Short name T350
Test name
Test status
Simulation time 12058480 ps
CPU time 1.27 seconds
Started Aug 06 06:27:31 PM PDT 24
Finished Aug 06 06:27:32 PM PDT 24
Peak memory 237684 kb
Host smart-711de0ad-2948-4921-9b7e-d238cb098f78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=333435310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.333435310
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1820256897
Short name T764
Test name
Test status
Simulation time 14482037 ps
CPU time 1.32 seconds
Started Aug 06 06:27:32 PM PDT 24
Finished Aug 06 06:27:34 PM PDT 24
Peak memory 237612 kb
Host smart-caa36965-992d-4030-aa5e-8643ed2b098a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1820256897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1820256897
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2402744558
Short name T756
Test name
Test status
Simulation time 9551224 ps
CPU time 1.53 seconds
Started Aug 06 06:27:31 PM PDT 24
Finished Aug 06 06:27:33 PM PDT 24
Peak memory 237692 kb
Host smart-122af409-fac8-4bbd-a604-42052a1682cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2402744558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2402744558
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3076069804
Short name T750
Test name
Test status
Simulation time 14697806 ps
CPU time 1.74 seconds
Started Aug 06 06:27:31 PM PDT 24
Finished Aug 06 06:27:33 PM PDT 24
Peak memory 237688 kb
Host smart-4c1a1a30-d15f-4625-894d-2ba0cf241085
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3076069804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3076069804
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1586328016
Short name T775
Test name
Test status
Simulation time 11356499 ps
CPU time 1.62 seconds
Started Aug 06 06:27:48 PM PDT 24
Finished Aug 06 06:27:49 PM PDT 24
Peak memory 236780 kb
Host smart-960c184c-0757-4433-b956-c31d972835e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1586328016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1586328016
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.4169294124
Short name T821
Test name
Test status
Simulation time 11060454 ps
CPU time 1.69 seconds
Started Aug 06 06:27:48 PM PDT 24
Finished Aug 06 06:27:50 PM PDT 24
Peak memory 237632 kb
Host smart-5ec6b6ce-abaa-4659-8d7c-3aecec86196c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4169294124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.4169294124
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1116033528
Short name T347
Test name
Test status
Simulation time 18191871 ps
CPU time 1.81 seconds
Started Aug 06 06:27:49 PM PDT 24
Finished Aug 06 06:27:51 PM PDT 24
Peak memory 235648 kb
Host smart-53436be3-72fe-4cd0-832f-3d4a46c1e274
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1116033528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1116033528
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1098461558
Short name T784
Test name
Test status
Simulation time 21980610 ps
CPU time 1.45 seconds
Started Aug 06 06:27:49 PM PDT 24
Finished Aug 06 06:27:50 PM PDT 24
Peak memory 236848 kb
Host smart-0aff7acd-4146-4b66-8e4f-28596d4add64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1098461558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1098461558
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3077029522
Short name T187
Test name
Test status
Simulation time 10524317474 ps
CPU time 111.14 seconds
Started Aug 06 06:25:36 PM PDT 24
Finished Aug 06 06:27:27 PM PDT 24
Peak memory 237796 kb
Host smart-f600edfe-8c64-407b-b824-413146679372
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3077029522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3077029522
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2695606674
Short name T713
Test name
Test status
Simulation time 5944531853 ps
CPU time 190.7 seconds
Started Aug 06 06:25:35 PM PDT 24
Finished Aug 06 06:28:46 PM PDT 24
Peak memory 237776 kb
Host smart-57367e3d-8849-4126-bc95-ea506fcba6ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2695606674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2695606674
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2403146532
Short name T794
Test name
Test status
Simulation time 40226231 ps
CPU time 6.52 seconds
Started Aug 06 06:25:36 PM PDT 24
Finished Aug 06 06:25:42 PM PDT 24
Peak memory 248860 kb
Host smart-5bd6959d-102c-472b-a707-bc3581026069
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2403146532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2403146532
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2938671576
Short name T741
Test name
Test status
Simulation time 35279664 ps
CPU time 6.13 seconds
Started Aug 06 06:25:33 PM PDT 24
Finished Aug 06 06:25:39 PM PDT 24
Peak memory 251328 kb
Host smart-fc222995-6a72-4d0a-a0e4-e78265c22c84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938671576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2938671576
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2857316801
Short name T186
Test name
Test status
Simulation time 120601201 ps
CPU time 5.78 seconds
Started Aug 06 06:25:36 PM PDT 24
Finished Aug 06 06:25:42 PM PDT 24
Peak memory 240632 kb
Host smart-0a36c8c9-dbf7-483c-a1b1-baea5e3772c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2857316801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2857316801
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2532233106
Short name T732
Test name
Test status
Simulation time 9010306 ps
CPU time 1.54 seconds
Started Aug 06 06:25:36 PM PDT 24
Finished Aug 06 06:25:38 PM PDT 24
Peak memory 236804 kb
Host smart-5e1cac65-7a52-41c3-8cfe-56221f0a729d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2532233106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2532233106
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2137759471
Short name T811
Test name
Test status
Simulation time 294869552 ps
CPU time 17.87 seconds
Started Aug 06 06:25:36 PM PDT 24
Finished Aug 06 06:25:54 PM PDT 24
Peak memory 244964 kb
Host smart-4fce86c6-6d12-42e2-876d-7afb1d35d557
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2137759471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2137759471
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1614709859
Short name T705
Test name
Test status
Simulation time 76138767 ps
CPU time 9.64 seconds
Started Aug 06 06:25:35 PM PDT 24
Finished Aug 06 06:25:45 PM PDT 24
Peak memory 248992 kb
Host smart-bbeffd7e-0eec-43eb-b2c1-e95c6cf152dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1614709859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1614709859
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1546896420
Short name T708
Test name
Test status
Simulation time 19420295 ps
CPU time 1.36 seconds
Started Aug 06 06:27:48 PM PDT 24
Finished Aug 06 06:27:50 PM PDT 24
Peak memory 236752 kb
Host smart-7c0dadee-c600-44f6-9945-ae4bdd72eb4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1546896420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.1546896420
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3682017916
Short name T718
Test name
Test status
Simulation time 8097479 ps
CPU time 1.47 seconds
Started Aug 06 06:27:50 PM PDT 24
Finished Aug 06 06:27:51 PM PDT 24
Peak memory 235716 kb
Host smart-c3620a23-0d26-4e8a-ba28-1e8230ef9acb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3682017916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3682017916
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1166699717
Short name T787
Test name
Test status
Simulation time 7639006 ps
CPU time 1.51 seconds
Started Aug 06 06:27:48 PM PDT 24
Finished Aug 06 06:27:50 PM PDT 24
Peak memory 237716 kb
Host smart-97a7e1c3-5439-4e66-906c-1a64984a6491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1166699717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1166699717
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3975029049
Short name T770
Test name
Test status
Simulation time 14974315 ps
CPU time 1.34 seconds
Started Aug 06 06:27:51 PM PDT 24
Finished Aug 06 06:27:52 PM PDT 24
Peak memory 236688 kb
Host smart-3fc6b262-9ef0-4b38-8196-0f3848bcbe70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3975029049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3975029049
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.920783247
Short name T751
Test name
Test status
Simulation time 11988667 ps
CPU time 1.62 seconds
Started Aug 06 06:27:47 PM PDT 24
Finished Aug 06 06:27:49 PM PDT 24
Peak memory 236776 kb
Host smart-d2bf3cd5-0c45-45bf-9bdf-caf05229ab8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=920783247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.920783247
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.4055365183
Short name T746
Test name
Test status
Simulation time 12295535 ps
CPU time 1.62 seconds
Started Aug 06 06:27:49 PM PDT 24
Finished Aug 06 06:27:51 PM PDT 24
Peak memory 237628 kb
Host smart-1d4904eb-51a0-4745-8e90-4d7905a87d40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4055365183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.4055365183
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1651048726
Short name T153
Test name
Test status
Simulation time 6092236 ps
CPU time 1.46 seconds
Started Aug 06 06:27:47 PM PDT 24
Finished Aug 06 06:27:49 PM PDT 24
Peak memory 235664 kb
Host smart-424ec863-4532-44c7-ba5f-03776d436432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1651048726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1651048726
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1825951408
Short name T757
Test name
Test status
Simulation time 7970761 ps
CPU time 1.49 seconds
Started Aug 06 06:27:46 PM PDT 24
Finished Aug 06 06:27:48 PM PDT 24
Peak memory 237712 kb
Host smart-5e04c170-6aa7-47b8-b073-07da330fe8e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1825951408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1825951408
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.829506289
Short name T199
Test name
Test status
Simulation time 266431445 ps
CPU time 9.96 seconds
Started Aug 06 06:25:37 PM PDT 24
Finished Aug 06 06:25:47 PM PDT 24
Peak memory 239824 kb
Host smart-8261c905-6993-42a3-b033-a0e3067d3c83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829506289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.829506289
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2408959686
Short name T197
Test name
Test status
Simulation time 62571156 ps
CPU time 5.71 seconds
Started Aug 06 06:25:37 PM PDT 24
Finished Aug 06 06:25:43 PM PDT 24
Peak memory 237700 kb
Host smart-033bd520-fffb-4a41-b8ca-75cf62b348e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2408959686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2408959686
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.442392807
Short name T726
Test name
Test status
Simulation time 8053425 ps
CPU time 1.36 seconds
Started Aug 06 06:25:35 PM PDT 24
Finished Aug 06 06:25:37 PM PDT 24
Peak memory 236824 kb
Host smart-6f66c213-cdb0-4131-b1b6-fec3ced53d95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=442392807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.442392807
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2968882491
Short name T717
Test name
Test status
Simulation time 411414802 ps
CPU time 10.53 seconds
Started Aug 06 06:25:34 PM PDT 24
Finished Aug 06 06:25:44 PM PDT 24
Peak memory 245008 kb
Host smart-df0a89a2-e881-4a73-96fe-04e59545579b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2968882491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2968882491
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1069955739
Short name T142
Test name
Test status
Simulation time 6815475131 ps
CPU time 220.42 seconds
Started Aug 06 06:25:36 PM PDT 24
Finished Aug 06 06:29:17 PM PDT 24
Peak memory 272752 kb
Host smart-3d3ad8d4-2440-4a91-9a24-6710bc98cf1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1069955739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1069955739
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1009893288
Short name T146
Test name
Test status
Simulation time 32434242513 ps
CPU time 557.7 seconds
Started Aug 06 06:25:34 PM PDT 24
Finished Aug 06 06:34:52 PM PDT 24
Peak memory 265660 kb
Host smart-3aa67dad-4420-4690-a40c-9f8f94cf8562
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009893288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1009893288
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2612809171
Short name T808
Test name
Test status
Simulation time 336333788 ps
CPU time 26.95 seconds
Started Aug 06 06:25:36 PM PDT 24
Finished Aug 06 06:26:03 PM PDT 24
Peak memory 248692 kb
Host smart-2f881de5-9af8-46e5-ab11-c29b3995e04d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2612809171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2612809171
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1869629801
Short name T735
Test name
Test status
Simulation time 63557196 ps
CPU time 10.8 seconds
Started Aug 06 06:25:59 PM PDT 24
Finished Aug 06 06:26:10 PM PDT 24
Peak memory 253556 kb
Host smart-8c25a220-4821-43a3-af2f-6e71ca51b290
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869629801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1869629801
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.4289725856
Short name T183
Test name
Test status
Simulation time 101579408 ps
CPU time 9.06 seconds
Started Aug 06 06:26:02 PM PDT 24
Finished Aug 06 06:26:11 PM PDT 24
Peak memory 237740 kb
Host smart-f77cd8c9-40ba-4e68-8638-5420e9057b3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4289725856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.4289725856
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.38186150
Short name T707
Test name
Test status
Simulation time 7999511 ps
CPU time 1.33 seconds
Started Aug 06 06:26:01 PM PDT 24
Finished Aug 06 06:26:03 PM PDT 24
Peak memory 236800 kb
Host smart-775da19f-2ad3-45f1-95e0-823c6b825ba3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=38186150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.38186150
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2477195998
Short name T733
Test name
Test status
Simulation time 700680352 ps
CPU time 21.5 seconds
Started Aug 06 06:26:01 PM PDT 24
Finished Aug 06 06:26:23 PM PDT 24
Peak memory 248792 kb
Host smart-318b134a-f3d5-4601-8f2b-496b0bd5d3a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2477195998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2477195998
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2857155389
Short name T139
Test name
Test status
Simulation time 2603990278 ps
CPU time 188.22 seconds
Started Aug 06 06:25:52 PM PDT 24
Finished Aug 06 06:29:00 PM PDT 24
Peak memory 265616 kb
Host smart-0a362917-e656-4e11-8daf-856fb510b9b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2857155389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2857155389
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1239683190
Short name T799
Test name
Test status
Simulation time 31863175931 ps
CPU time 591.71 seconds
Started Aug 06 06:26:00 PM PDT 24
Finished Aug 06 06:35:52 PM PDT 24
Peak memory 265700 kb
Host smart-c49c88d4-71d9-405b-82bd-94481702ffb6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239683190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1239683190
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1832389791
Short name T241
Test name
Test status
Simulation time 1200436266 ps
CPU time 19.04 seconds
Started Aug 06 06:25:59 PM PDT 24
Finished Aug 06 06:26:18 PM PDT 24
Peak memory 248472 kb
Host smart-45d2f10f-f300-4a02-975f-720681d98f2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1832389791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1832389791
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.4191179315
Short name T759
Test name
Test status
Simulation time 193097376 ps
CPU time 13.96 seconds
Started Aug 06 06:26:01 PM PDT 24
Finished Aug 06 06:26:15 PM PDT 24
Peak memory 242704 kb
Host smart-9cad8c1c-9118-4296-8d0b-1f087ba0bb80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191179315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.4191179315
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2121306940
Short name T355
Test name
Test status
Simulation time 131395419 ps
CPU time 5.32 seconds
Started Aug 06 06:26:01 PM PDT 24
Finished Aug 06 06:26:07 PM PDT 24
Peak memory 237652 kb
Host smart-5c9811da-47c8-4e41-9155-35c54b55f168
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2121306940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2121306940
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3328297084
Short name T744
Test name
Test status
Simulation time 16993401 ps
CPU time 1.32 seconds
Started Aug 06 06:25:52 PM PDT 24
Finished Aug 06 06:25:54 PM PDT 24
Peak memory 237696 kb
Host smart-49bbd572-5204-49c3-888d-01ca726ca79c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3328297084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3328297084
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2314651623
Short name T768
Test name
Test status
Simulation time 4360419498 ps
CPU time 27.31 seconds
Started Aug 06 06:26:02 PM PDT 24
Finished Aug 06 06:26:29 PM PDT 24
Peak memory 245924 kb
Host smart-59c34cdf-de45-417a-8391-a84b61d7c17e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2314651623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2314651623
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.291393501
Short name T140
Test name
Test status
Simulation time 26422174896 ps
CPU time 375.77 seconds
Started Aug 06 06:26:00 PM PDT 24
Finished Aug 06 06:32:15 PM PDT 24
Peak memory 265664 kb
Host smart-74d46c23-9087-494f-a1ef-ff140e9211aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=291393501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.291393501
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.461218386
Short name T114
Test name
Test status
Simulation time 17320134080 ps
CPU time 591.35 seconds
Started Aug 06 06:26:02 PM PDT 24
Finished Aug 06 06:35:53 PM PDT 24
Peak memory 273832 kb
Host smart-74629071-94f1-4008-988e-0a937a61757f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461218386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.461218386
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.4285315662
Short name T715
Test name
Test status
Simulation time 729070381 ps
CPU time 22.27 seconds
Started Aug 06 06:26:01 PM PDT 24
Finished Aug 06 06:26:23 PM PDT 24
Peak memory 253892 kb
Host smart-31192a92-529a-4272-8ed7-a87101687903
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4285315662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.4285315662
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.734537454
Short name T745
Test name
Test status
Simulation time 61622496 ps
CPU time 11.62 seconds
Started Aug 06 06:26:16 PM PDT 24
Finished Aug 06 06:26:28 PM PDT 24
Peak memory 253612 kb
Host smart-cfa0691d-373f-4c75-b495-577cab2c6d6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734537454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.alert_handler_csr_mem_rw_with_rand_reset.734537454
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1410291381
Short name T796
Test name
Test status
Simulation time 22143362 ps
CPU time 3.72 seconds
Started Aug 06 06:26:01 PM PDT 24
Finished Aug 06 06:26:05 PM PDT 24
Peak memory 240340 kb
Host smart-31b26a36-26e3-4449-919a-0cb9fd41dd23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1410291381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1410291381
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.285339730
Short name T709
Test name
Test status
Simulation time 20223222 ps
CPU time 1.43 seconds
Started Aug 06 06:25:58 PM PDT 24
Finished Aug 06 06:25:59 PM PDT 24
Peak memory 236840 kb
Host smart-e020a828-211a-48e7-9877-0dfb45cfd297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=285339730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.285339730
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1617615086
Short name T743
Test name
Test status
Simulation time 1056045360 ps
CPU time 19.16 seconds
Started Aug 06 06:25:58 PM PDT 24
Finished Aug 06 06:26:17 PM PDT 24
Peak memory 244980 kb
Host smart-7291db78-adb4-4c34-b7e5-8ad421dff704
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1617615086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1617615086
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1403653092
Short name T147
Test name
Test status
Simulation time 5448891208 ps
CPU time 380.96 seconds
Started Aug 06 06:26:01 PM PDT 24
Finished Aug 06 06:32:23 PM PDT 24
Peak memory 264508 kb
Host smart-7b8aa619-43d2-4b71-a796-a84bb07da073
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1403653092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1403653092
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.826960633
Short name T809
Test name
Test status
Simulation time 940707285 ps
CPU time 17.7 seconds
Started Aug 06 06:25:53 PM PDT 24
Finished Aug 06 06:26:11 PM PDT 24
Peak memory 254908 kb
Host smart-ab7abc17-3702-4711-869d-249589611efb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=826960633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.826960633
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3518766999
Short name T776
Test name
Test status
Simulation time 224612632 ps
CPU time 12.16 seconds
Started Aug 06 06:26:16 PM PDT 24
Finished Aug 06 06:26:28 PM PDT 24
Peak memory 257032 kb
Host smart-e9b72dab-6b79-49c1-b10e-68222289af68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518766999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3518766999
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.4081661654
Short name T240
Test name
Test status
Simulation time 131430714 ps
CPU time 9.62 seconds
Started Aug 06 06:26:17 PM PDT 24
Finished Aug 06 06:26:27 PM PDT 24
Peak memory 237652 kb
Host smart-5ce6d834-afbc-4354-b7ac-f6f6bfa258b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4081661654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.4081661654
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1006621600
Short name T819
Test name
Test status
Simulation time 33409440 ps
CPU time 1.32 seconds
Started Aug 06 06:26:16 PM PDT 24
Finished Aug 06 06:26:18 PM PDT 24
Peak memory 237696 kb
Host smart-6df39ee6-b4a7-4e47-8ce7-c7ef4b46dbba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1006621600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1006621600
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.451897518
Short name T719
Test name
Test status
Simulation time 5954751356 ps
CPU time 24.75 seconds
Started Aug 06 06:26:16 PM PDT 24
Finished Aug 06 06:26:40 PM PDT 24
Peak memory 248944 kb
Host smart-1c7fe3a7-89a7-487e-868b-a08199e5a43e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=451897518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outs
tanding.451897518
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3250707811
Short name T145
Test name
Test status
Simulation time 2098436592 ps
CPU time 154.65 seconds
Started Aug 06 06:26:16 PM PDT 24
Finished Aug 06 06:28:51 PM PDT 24
Peak memory 265492 kb
Host smart-fb1a0eef-0898-4902-a0d3-79fb46fb990b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3250707811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3250707811
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4100374942
Short name T760
Test name
Test status
Simulation time 146869982 ps
CPU time 9.68 seconds
Started Aug 06 06:26:15 PM PDT 24
Finished Aug 06 06:26:25 PM PDT 24
Peak memory 254484 kb
Host smart-ca2ce7de-b2f4-4bed-8115-a9bb1b9ca3fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4100374942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.4100374942
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1240254332
Short name T44
Test name
Test status
Simulation time 28756469666 ps
CPU time 1427.93 seconds
Started Aug 06 05:28:14 PM PDT 24
Finished Aug 06 05:52:02 PM PDT 24
Peak memory 288664 kb
Host smart-5ed71b1f-3375-4a2e-a62d-02477bd4095f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240254332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1240254332
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1146442462
Short name T404
Test name
Test status
Simulation time 1163367791 ps
CPU time 26.59 seconds
Started Aug 06 05:28:07 PM PDT 24
Finished Aug 06 05:28:33 PM PDT 24
Peak memory 248340 kb
Host smart-1485ed7b-ff5a-46fd-baa4-10c01c308af3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1146442462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1146442462
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3160509779
Short name T631
Test name
Test status
Simulation time 5821344213 ps
CPU time 120.3 seconds
Started Aug 06 05:28:06 PM PDT 24
Finished Aug 06 05:30:06 PM PDT 24
Peak memory 256784 kb
Host smart-4276d4f6-a9d8-4d4f-95bd-b4ebfd6859c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31605
09779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3160509779
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1286939464
Short name T657
Test name
Test status
Simulation time 320908688 ps
CPU time 31.76 seconds
Started Aug 06 05:28:07 PM PDT 24
Finished Aug 06 05:28:39 PM PDT 24
Peak memory 248188 kb
Host smart-28253d63-e66e-4886-bc7e-a5e495cb1910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12869
39464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1286939464
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2278689565
Short name T221
Test name
Test status
Simulation time 21175375686 ps
CPU time 1323.72 seconds
Started Aug 06 05:28:14 PM PDT 24
Finished Aug 06 05:50:18 PM PDT 24
Peak memory 272396 kb
Host smart-5681c30f-4a65-435b-8b5f-bb6ea0cf0a35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278689565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2278689565
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3403954473
Short name T427
Test name
Test status
Simulation time 44668756642 ps
CPU time 2690.3 seconds
Started Aug 06 05:28:10 PM PDT 24
Finished Aug 06 06:13:00 PM PDT 24
Peak memory 285196 kb
Host smart-2ae027b9-3d37-4e5b-b90a-1128d181c97d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403954473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3403954473
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2303539714
Short name T312
Test name
Test status
Simulation time 17377986283 ps
CPU time 339.72 seconds
Started Aug 06 05:28:15 PM PDT 24
Finished Aug 06 05:33:55 PM PDT 24
Peak memory 248360 kb
Host smart-2cd6c283-ed1e-45ce-90f0-1d9dd52223cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303539714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2303539714
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3222092297
Short name T360
Test name
Test status
Simulation time 3021325842 ps
CPU time 44.66 seconds
Started Aug 06 05:28:06 PM PDT 24
Finished Aug 06 05:28:51 PM PDT 24
Peak memory 255912 kb
Host smart-54afbf88-3b43-49c4-b8e1-d92570aa315b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32220
92297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3222092297
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.1072919598
Short name T497
Test name
Test status
Simulation time 469313771 ps
CPU time 11.33 seconds
Started Aug 06 05:28:08 PM PDT 24
Finished Aug 06 05:28:19 PM PDT 24
Peak memory 247680 kb
Host smart-6dbc5c82-ec74-417b-87b5-5a79833ced2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10729
19598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1072919598
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3900080956
Short name T69
Test name
Test status
Simulation time 3386545675 ps
CPU time 54.51 seconds
Started Aug 06 05:28:12 PM PDT 24
Finished Aug 06 05:29:07 PM PDT 24
Peak memory 248564 kb
Host smart-db6ea7c8-9bc0-4db6-834a-f61075ab4ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39000
80956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3900080956
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3956735197
Short name T485
Test name
Test status
Simulation time 8319969121 ps
CPU time 67.58 seconds
Started Aug 06 05:28:07 PM PDT 24
Finished Aug 06 05:29:15 PM PDT 24
Peak memory 256740 kb
Host smart-24b5f191-2e07-4572-84a8-3695ddd2dbca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39567
35197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3956735197
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2604661988
Short name T536
Test name
Test status
Simulation time 27398076873 ps
CPU time 1719.87 seconds
Started Aug 06 05:28:17 PM PDT 24
Finished Aug 06 05:56:57 PM PDT 24
Peak memory 284180 kb
Host smart-384dc95e-215e-4450-9008-e880211110bd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604661988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2604661988
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.873566209
Short name T507
Test name
Test status
Simulation time 237391138737 ps
CPU time 6045.71 seconds
Started Aug 06 05:28:09 PM PDT 24
Finished Aug 06 07:08:56 PM PDT 24
Peak memory 354456 kb
Host smart-add065e6-c012-4de0-8029-64b1b7184e03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873566209 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.873566209
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2811761394
Short name T578
Test name
Test status
Simulation time 13154045033 ps
CPU time 562.96 seconds
Started Aug 06 05:28:17 PM PDT 24
Finished Aug 06 05:37:40 PM PDT 24
Peak memory 272460 kb
Host smart-8d9a5f03-c7df-4799-b01d-4dc865de57db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811761394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2811761394
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.721666089
Short name T573
Test name
Test status
Simulation time 304319930 ps
CPU time 15.13 seconds
Started Aug 06 05:28:12 PM PDT 24
Finished Aug 06 05:28:27 PM PDT 24
Peak memory 248332 kb
Host smart-c0815c1b-615e-47ec-a2a6-874d5fb409ef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=721666089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.721666089
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.53130531
Short name T574
Test name
Test status
Simulation time 2180008851 ps
CPU time 56.81 seconds
Started Aug 06 05:28:18 PM PDT 24
Finished Aug 06 05:29:15 PM PDT 24
Peak memory 256668 kb
Host smart-f3aceae4-9c40-45e8-b04b-47ba28392438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53130
531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.53130531
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2366243797
Short name T395
Test name
Test status
Simulation time 5199126159 ps
CPU time 31.62 seconds
Started Aug 06 05:28:09 PM PDT 24
Finished Aug 06 05:28:40 PM PDT 24
Peak memory 248524 kb
Host smart-c91aac55-db56-450f-ae9d-7dc733787500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23662
43797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2366243797
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.723762213
Short name T605
Test name
Test status
Simulation time 26608778126 ps
CPU time 1209.88 seconds
Started Aug 06 05:28:16 PM PDT 24
Finished Aug 06 05:48:26 PM PDT 24
Peak memory 283400 kb
Host smart-cc6494b4-a878-4bc7-bc55-9c48933f11ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723762213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.723762213
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.4248396610
Short name T424
Test name
Test status
Simulation time 205943739790 ps
CPU time 1365.06 seconds
Started Aug 06 05:28:12 PM PDT 24
Finished Aug 06 05:50:58 PM PDT 24
Peak memory 289120 kb
Host smart-f34f5490-5864-41c1-9805-516d401ce449
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248396610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.4248396610
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.4106380682
Short name T281
Test name
Test status
Simulation time 84856182191 ps
CPU time 340.24 seconds
Started Aug 06 05:28:15 PM PDT 24
Finished Aug 06 05:33:56 PM PDT 24
Peak memory 247468 kb
Host smart-c0712636-9cb0-407c-8ec1-aab1e8fbe80a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106380682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.4106380682
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.215473439
Short name T413
Test name
Test status
Simulation time 798981538 ps
CPU time 52.53 seconds
Started Aug 06 05:28:18 PM PDT 24
Finished Aug 06 05:29:10 PM PDT 24
Peak memory 248420 kb
Host smart-b06284dc-0b1e-40f1-9460-695be9440b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21547
3439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.215473439
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.175154212
Short name T515
Test name
Test status
Simulation time 1170885815 ps
CPU time 16.2 seconds
Started Aug 06 05:28:08 PM PDT 24
Finished Aug 06 05:28:24 PM PDT 24
Peak memory 248284 kb
Host smart-81c87e7d-8ecb-4e8c-b013-b55e64872071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17515
4212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.175154212
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2525406122
Short name T558
Test name
Test status
Simulation time 1209170270 ps
CPU time 30.46 seconds
Started Aug 06 05:28:06 PM PDT 24
Finished Aug 06 05:28:36 PM PDT 24
Peak memory 255856 kb
Host smart-7bf54811-e8e8-407b-8c23-ec87ed6d5bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25254
06122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2525406122
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.903378562
Short name T195
Test name
Test status
Simulation time 1248191985 ps
CPU time 20.67 seconds
Started Aug 06 05:28:15 PM PDT 24
Finished Aug 06 05:28:36 PM PDT 24
Peak memory 255460 kb
Host smart-6e643e12-5911-43f6-9d20-abab691cf842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90337
8562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.903378562
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2740571339
Short name T111
Test name
Test status
Simulation time 888701278 ps
CPU time 15.25 seconds
Started Aug 06 05:28:16 PM PDT 24
Finished Aug 06 05:28:32 PM PDT 24
Peak memory 256520 kb
Host smart-5e90f561-f3b6-4dcc-af1c-c2e7e30a4400
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740571339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2740571339
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3111373199
Short name T202
Test name
Test status
Simulation time 202802394 ps
CPU time 4.55 seconds
Started Aug 06 05:28:35 PM PDT 24
Finished Aug 06 05:28:40 PM PDT 24
Peak memory 248616 kb
Host smart-79172a62-b663-4614-b15f-ce8533ccb020
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3111373199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3111373199
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.524328392
Short name T225
Test name
Test status
Simulation time 18098378157 ps
CPU time 714.18 seconds
Started Aug 06 05:28:36 PM PDT 24
Finished Aug 06 05:40:31 PM PDT 24
Peak memory 266872 kb
Host smart-863c7e8e-b5e3-44db-934d-6b5d5106af23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524328392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.524328392
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.511146594
Short name T496
Test name
Test status
Simulation time 267593115 ps
CPU time 13.89 seconds
Started Aug 06 05:28:34 PM PDT 24
Finished Aug 06 05:28:48 PM PDT 24
Peak memory 248324 kb
Host smart-bda38c82-5d89-405f-8a38-b5f319145a64
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=511146594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.511146594
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1055526177
Short name T524
Test name
Test status
Simulation time 10267610780 ps
CPU time 112.6 seconds
Started Aug 06 05:28:35 PM PDT 24
Finished Aug 06 05:30:28 PM PDT 24
Peak memory 249524 kb
Host smart-f9347129-ca16-4356-8867-632a040de728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10555
26177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1055526177
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.4216007257
Short name T13
Test name
Test status
Simulation time 817811654 ps
CPU time 51.81 seconds
Started Aug 06 05:28:37 PM PDT 24
Finished Aug 06 05:29:29 PM PDT 24
Peak memory 248420 kb
Host smart-8ee69b74-e0f1-498a-b7ab-78442fbb362e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42160
07257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.4216007257
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.488590943
Short name T227
Test name
Test status
Simulation time 36594553069 ps
CPU time 1865.26 seconds
Started Aug 06 05:28:37 PM PDT 24
Finished Aug 06 05:59:42 PM PDT 24
Peak memory 285596 kb
Host smart-b24fe453-95f1-4e0b-bfae-a628d58cb2b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488590943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.488590943
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.4284285828
Short name T584
Test name
Test status
Simulation time 14505971498 ps
CPU time 100.46 seconds
Started Aug 06 05:28:38 PM PDT 24
Finished Aug 06 05:30:19 PM PDT 24
Peak memory 247440 kb
Host smart-42151fbc-bbb2-4022-8b63-caae052b4ffd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284285828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.4284285828
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3626244991
Short name T443
Test name
Test status
Simulation time 7758613460 ps
CPU time 40.39 seconds
Started Aug 06 05:28:35 PM PDT 24
Finished Aug 06 05:29:15 PM PDT 24
Peak memory 248548 kb
Host smart-55775648-6d21-4d9a-9c14-c81a68a3a22e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36262
44991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3626244991
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3126427697
Short name T471
Test name
Test status
Simulation time 58932480 ps
CPU time 7.65 seconds
Started Aug 06 05:28:22 PM PDT 24
Finished Aug 06 05:28:30 PM PDT 24
Peak memory 247768 kb
Host smart-d90b78b6-cc68-446b-bc7a-460b4854ac04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31264
27697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3126427697
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.4041864562
Short name T615
Test name
Test status
Simulation time 1327267569 ps
CPU time 35.06 seconds
Started Aug 06 05:28:28 PM PDT 24
Finished Aug 06 05:29:03 PM PDT 24
Peak memory 255956 kb
Host smart-e7a250f5-91f2-4f2f-933f-ea17808ff1e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40418
64562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.4041864562
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3158892146
Short name T462
Test name
Test status
Simulation time 198018903348 ps
CPU time 1552.65 seconds
Started Aug 06 05:28:36 PM PDT 24
Finished Aug 06 05:54:29 PM PDT 24
Peak memory 284052 kb
Host smart-71110ffc-33a0-4cb6-9606-e79954860cbe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158892146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3158892146
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.958773802
Short name T46
Test name
Test status
Simulation time 28747720068 ps
CPU time 1276.48 seconds
Started Aug 06 05:28:34 PM PDT 24
Finished Aug 06 05:49:51 PM PDT 24
Peak memory 272648 kb
Host smart-145e08cc-06e6-42ba-aec5-cf2887a7a23d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958773802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.958773802
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2090026446
Short name T566
Test name
Test status
Simulation time 202247423 ps
CPU time 12.15 seconds
Started Aug 06 05:28:34 PM PDT 24
Finished Aug 06 05:28:46 PM PDT 24
Peak memory 248396 kb
Host smart-7c21efd1-b303-4e28-a20d-ac7ddff95ab8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2090026446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2090026446
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.533464301
Short name T405
Test name
Test status
Simulation time 21912502570 ps
CPU time 156.44 seconds
Started Aug 06 05:28:38 PM PDT 24
Finished Aug 06 05:31:15 PM PDT 24
Peak memory 249564 kb
Host smart-5273c245-bbdd-411f-a1e2-92a665f20b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53346
4301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.533464301
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1535713796
Short name T654
Test name
Test status
Simulation time 3940071733 ps
CPU time 69.58 seconds
Started Aug 06 05:28:35 PM PDT 24
Finished Aug 06 05:29:44 PM PDT 24
Peak memory 248544 kb
Host smart-8cb032f3-58cc-49eb-829e-630de773e93b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15357
13796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1535713796
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3059779372
Short name T470
Test name
Test status
Simulation time 36296909046 ps
CPU time 2163.39 seconds
Started Aug 06 05:28:39 PM PDT 24
Finished Aug 06 06:04:42 PM PDT 24
Peak memory 289172 kb
Host smart-8a93bd02-da59-422a-843b-6e06e7cbb6c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059779372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3059779372
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3846431259
Short name T7
Test name
Test status
Simulation time 9649267941 ps
CPU time 111.38 seconds
Started Aug 06 05:28:38 PM PDT 24
Finished Aug 06 05:30:29 PM PDT 24
Peak memory 254096 kb
Host smart-30068e52-6d11-464a-819e-8e2e43d9af33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846431259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3846431259
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.407341543
Short name T397
Test name
Test status
Simulation time 532969563 ps
CPU time 9.43 seconds
Started Aug 06 05:28:35 PM PDT 24
Finished Aug 06 05:28:44 PM PDT 24
Peak memory 248396 kb
Host smart-5d162431-f07e-47da-8109-6fe6b234483e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40734
1543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.407341543
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.4289107202
Short name T651
Test name
Test status
Simulation time 2292800215 ps
CPU time 70.4 seconds
Started Aug 06 05:28:37 PM PDT 24
Finished Aug 06 05:29:48 PM PDT 24
Peak memory 256196 kb
Host smart-c32dc411-6dd6-4182-a387-deca3bab5899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42891
07202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.4289107202
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1064130713
Short name T287
Test name
Test status
Simulation time 1279274926 ps
CPU time 25.28 seconds
Started Aug 06 05:28:38 PM PDT 24
Finished Aug 06 05:29:03 PM PDT 24
Peak memory 255736 kb
Host smart-a56ca397-feda-4f13-ad4f-7a4c5f93dacf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10641
30713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1064130713
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.423752841
Short name T557
Test name
Test status
Simulation time 107162011182 ps
CPU time 1846.39 seconds
Started Aug 06 05:28:35 PM PDT 24
Finished Aug 06 05:59:21 PM PDT 24
Peak memory 280764 kb
Host smart-d7d2a5b9-b006-4109-af84-98e6cbf652eb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423752841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.423752841
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1129297190
Short name T220
Test name
Test status
Simulation time 34034030552 ps
CPU time 640.11 seconds
Started Aug 06 05:28:27 PM PDT 24
Finished Aug 06 05:39:07 PM PDT 24
Peak memory 272176 kb
Host smart-530768a7-6d9d-4aa6-bde9-2cc3c7f706cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129297190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1129297190
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.923305137
Short name T482
Test name
Test status
Simulation time 627721887 ps
CPU time 15.05 seconds
Started Aug 06 05:28:26 PM PDT 24
Finished Aug 06 05:28:41 PM PDT 24
Peak memory 248396 kb
Host smart-706b526e-af8d-420c-9b83-c4d4559f4b73
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=923305137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.923305137
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.4054248071
Short name T583
Test name
Test status
Simulation time 2346022942 ps
CPU time 65.38 seconds
Started Aug 06 05:28:37 PM PDT 24
Finished Aug 06 05:29:43 PM PDT 24
Peak memory 256308 kb
Host smart-bb3cbfcd-8678-460f-9299-fec4b3fa358f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40542
48071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.4054248071
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.4147072366
Short name T527
Test name
Test status
Simulation time 618339651 ps
CPU time 30.79 seconds
Started Aug 06 05:28:32 PM PDT 24
Finished Aug 06 05:29:03 PM PDT 24
Peak memory 248352 kb
Host smart-bba6feee-c786-4ad3-b993-f2072a40972f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41470
72366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.4147072366
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3290729680
Short name T681
Test name
Test status
Simulation time 64878923931 ps
CPU time 603.91 seconds
Started Aug 06 05:28:31 PM PDT 24
Finished Aug 06 05:38:35 PM PDT 24
Peak memory 273032 kb
Host smart-19b2fa17-ace2-4d62-b231-dc5c9c486bfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290729680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3290729680
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1382192105
Short name T695
Test name
Test status
Simulation time 37753381776 ps
CPU time 1882.02 seconds
Started Aug 06 05:28:27 PM PDT 24
Finished Aug 06 05:59:50 PM PDT 24
Peak memory 285432 kb
Host smart-7e39a203-c59d-499d-9f71-051cf1379bd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382192105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1382192105
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.990380389
Short name T555
Test name
Test status
Simulation time 33760399895 ps
CPU time 420.68 seconds
Started Aug 06 05:28:27 PM PDT 24
Finished Aug 06 05:35:28 PM PDT 24
Peak memory 248512 kb
Host smart-6b78461e-e8e2-4be8-9c18-250b7050e4e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990380389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.990380389
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2035863606
Short name T429
Test name
Test status
Simulation time 1480377573 ps
CPU time 10.13 seconds
Started Aug 06 05:28:38 PM PDT 24
Finished Aug 06 05:28:48 PM PDT 24
Peak memory 248408 kb
Host smart-a69f0239-d276-4e10-996f-928315950202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20358
63606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2035863606
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.964818463
Short name T381
Test name
Test status
Simulation time 441621657 ps
CPU time 9.56 seconds
Started Aug 06 05:28:32 PM PDT 24
Finished Aug 06 05:28:42 PM PDT 24
Peak memory 252380 kb
Host smart-c8a45180-9952-40d1-8956-c77b7635b90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96481
8463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.964818463
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.759236494
Short name T518
Test name
Test status
Simulation time 2730953932 ps
CPU time 37.64 seconds
Started Aug 06 05:28:32 PM PDT 24
Finished Aug 06 05:29:09 PM PDT 24
Peak memory 247792 kb
Host smart-ca40788c-907a-485a-a0e9-54fb0ac47c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75923
6494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.759236494
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.540970164
Short name T109
Test name
Test status
Simulation time 4458128743 ps
CPU time 64.04 seconds
Started Aug 06 05:28:32 PM PDT 24
Finished Aug 06 05:29:36 PM PDT 24
Peak memory 256656 kb
Host smart-db3dda19-775d-4841-b8c7-dfa69d189d95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54097
0164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.540970164
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1360491142
Short name T101
Test name
Test status
Simulation time 14567992394 ps
CPU time 752.4 seconds
Started Aug 06 05:28:32 PM PDT 24
Finished Aug 06 05:41:04 PM PDT 24
Peak memory 264928 kb
Host smart-9c85e58a-09d1-44bf-97ca-d490ec9e297e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360491142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1360491142
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2372172833
Short name T215
Test name
Test status
Simulation time 38684163 ps
CPU time 2.2 seconds
Started Aug 06 05:28:44 PM PDT 24
Finished Aug 06 05:28:46 PM PDT 24
Peak memory 248652 kb
Host smart-0ea4d73a-c513-47ff-84d5-7b397f825ec2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2372172833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2372172833
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2581011661
Short name T378
Test name
Test status
Simulation time 161698387964 ps
CPU time 2567.77 seconds
Started Aug 06 05:28:41 PM PDT 24
Finished Aug 06 06:11:29 PM PDT 24
Peak memory 288692 kb
Host smart-88f2eab5-6936-426b-bfb4-66fbd2d1d4ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581011661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2581011661
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1267865356
Short name T540
Test name
Test status
Simulation time 3967221730 ps
CPU time 10.6 seconds
Started Aug 06 05:28:40 PM PDT 24
Finished Aug 06 05:28:51 PM PDT 24
Peak memory 248420 kb
Host smart-9df1d425-7ac7-486f-a772-a9da31c4ba22
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1267865356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1267865356
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2651016596
Short name T535
Test name
Test status
Simulation time 1261857124 ps
CPU time 71.88 seconds
Started Aug 06 05:28:42 PM PDT 24
Finished Aug 06 05:29:54 PM PDT 24
Peak memory 256196 kb
Host smart-dd18c74f-2d22-4433-896c-6f577f020b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26510
16596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2651016596
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.179204154
Short name T222
Test name
Test status
Simulation time 483465126 ps
CPU time 4.6 seconds
Started Aug 06 05:28:39 PM PDT 24
Finished Aug 06 05:28:43 PM PDT 24
Peak memory 240228 kb
Host smart-0e12e0b9-431b-4ff2-9c53-ea7fc1e39963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17920
4154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.179204154
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3418607560
Short name T337
Test name
Test status
Simulation time 72327812906 ps
CPU time 2011.74 seconds
Started Aug 06 05:28:42 PM PDT 24
Finished Aug 06 06:02:14 PM PDT 24
Peak memory 283668 kb
Host smart-e1a8c543-5ca6-4736-9de6-c54af657ea02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418607560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3418607560
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2448649368
Short name T586
Test name
Test status
Simulation time 38546602477 ps
CPU time 2218.42 seconds
Started Aug 06 05:28:38 PM PDT 24
Finished Aug 06 06:05:37 PM PDT 24
Peak memory 272908 kb
Host smart-87d14a68-0834-4082-b692-5b2dd21a14ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448649368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2448649368
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.4235735280
Short name T309
Test name
Test status
Simulation time 37983784734 ps
CPU time 408.04 seconds
Started Aug 06 05:28:43 PM PDT 24
Finished Aug 06 05:35:31 PM PDT 24
Peak memory 247444 kb
Host smart-cf4d300a-3bb8-4f77-be58-312bbca43907
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235735280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.4235735280
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1111257752
Short name T367
Test name
Test status
Simulation time 1061019588 ps
CPU time 63 seconds
Started Aug 06 05:28:38 PM PDT 24
Finished Aug 06 05:29:41 PM PDT 24
Peak memory 256492 kb
Host smart-1ac55839-ea60-41f7-9dbd-54779e9f9f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11112
57752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1111257752
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1295555263
Short name T85
Test name
Test status
Simulation time 613001569 ps
CPU time 11.08 seconds
Started Aug 06 05:28:42 PM PDT 24
Finished Aug 06 05:28:53 PM PDT 24
Peak memory 254240 kb
Host smart-232829f0-32cf-4b6c-a507-68bf860ffea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12955
55263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1295555263
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3452586308
Short name T257
Test name
Test status
Simulation time 919385046 ps
CPU time 29.21 seconds
Started Aug 06 05:28:39 PM PDT 24
Finished Aug 06 05:29:08 PM PDT 24
Peak memory 248492 kb
Host smart-56cb3fea-0d07-4fa1-ba8c-c030cd4282d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34525
86308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3452586308
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1731450468
Short name T110
Test name
Test status
Simulation time 1620867360 ps
CPU time 37.34 seconds
Started Aug 06 05:28:38 PM PDT 24
Finished Aug 06 05:29:16 PM PDT 24
Peak memory 256616 kb
Host smart-1ba14b84-a239-417d-ab52-154ef401f911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17314
50468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1731450468
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3678446784
Short name T516
Test name
Test status
Simulation time 15596926859 ps
CPU time 232.64 seconds
Started Aug 06 05:28:37 PM PDT 24
Finished Aug 06 05:32:30 PM PDT 24
Peak memory 256648 kb
Host smart-998a3244-ce95-4756-bbff-4d5d3e385fdf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678446784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3678446784
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1287152914
Short name T204
Test name
Test status
Simulation time 117237850 ps
CPU time 3.44 seconds
Started Aug 06 05:29:02 PM PDT 24
Finished Aug 06 05:29:06 PM PDT 24
Peak memory 248652 kb
Host smart-e28b4322-ea45-403b-987c-a338f71a0a64
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1287152914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1287152914
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.827976106
Short name T453
Test name
Test status
Simulation time 212850005438 ps
CPU time 2815.91 seconds
Started Aug 06 05:28:38 PM PDT 24
Finished Aug 06 06:15:35 PM PDT 24
Peak memory 288468 kb
Host smart-adcc795f-c5cd-468d-917b-2161ef05bedc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827976106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.827976106
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1751465374
Short name T400
Test name
Test status
Simulation time 255499864 ps
CPU time 13.84 seconds
Started Aug 06 05:28:58 PM PDT 24
Finished Aug 06 05:29:12 PM PDT 24
Peak memory 248440 kb
Host smart-7f3585fc-e3a4-4635-8b4f-3c4c4c19b189
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1751465374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1751465374
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.4102941636
Short name T458
Test name
Test status
Simulation time 18187229435 ps
CPU time 252.33 seconds
Started Aug 06 05:28:41 PM PDT 24
Finished Aug 06 05:32:53 PM PDT 24
Peak memory 256016 kb
Host smart-2b677b24-12ee-4f87-90b5-c633d16d7bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41029
41636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.4102941636
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3752117712
Short name T617
Test name
Test status
Simulation time 694181472 ps
CPU time 46.17 seconds
Started Aug 06 05:28:45 PM PDT 24
Finished Aug 06 05:29:32 PM PDT 24
Peak memory 249032 kb
Host smart-a1a9fc3e-6e58-4ed8-b05d-b02f80a053a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37521
17712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3752117712
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1092392315
Short name T403
Test name
Test status
Simulation time 35347856904 ps
CPU time 2027.96 seconds
Started Aug 06 05:28:59 PM PDT 24
Finished Aug 06 06:02:47 PM PDT 24
Peak memory 271028 kb
Host smart-880352ae-8ec6-4d55-b0b0-cfb8b0c73d35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092392315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1092392315
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3007021902
Short name T49
Test name
Test status
Simulation time 141034924 ps
CPU time 9.02 seconds
Started Aug 06 05:28:40 PM PDT 24
Finished Aug 06 05:28:49 PM PDT 24
Peak memory 248460 kb
Host smart-0c02e46a-288e-4643-8e53-723ca2226060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30070
21902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3007021902
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.4010345787
Short name T561
Test name
Test status
Simulation time 4115711124 ps
CPU time 66.18 seconds
Started Aug 06 05:28:42 PM PDT 24
Finished Aug 06 05:29:49 PM PDT 24
Peak memory 256296 kb
Host smart-3a22e340-61b0-4f7f-9bb7-fb459dd9b26d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40103
45787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.4010345787
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.556675754
Short name T260
Test name
Test status
Simulation time 2725187516 ps
CPU time 20.67 seconds
Started Aug 06 05:28:45 PM PDT 24
Finished Aug 06 05:29:06 PM PDT 24
Peak memory 247844 kb
Host smart-92b3e941-0496-435b-8b02-0af5fb8eb804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55667
5754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.556675754
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.310914896
Short name T570
Test name
Test status
Simulation time 759404514 ps
CPU time 39.7 seconds
Started Aug 06 05:28:44 PM PDT 24
Finished Aug 06 05:29:25 PM PDT 24
Peak memory 248464 kb
Host smart-5843225d-3840-4bf4-bac1-9c2f09d4389f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31091
4896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.310914896
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.2356928836
Short name T632
Test name
Test status
Simulation time 7437237408 ps
CPU time 849.3 seconds
Started Aug 06 05:29:01 PM PDT 24
Finished Aug 06 05:43:11 PM PDT 24
Peak memory 272456 kb
Host smart-ad686adb-7672-4e20-bdf3-580214ee8fe3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356928836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.2356928836
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1517857600
Short name T216
Test name
Test status
Simulation time 13821723 ps
CPU time 2.57 seconds
Started Aug 06 05:29:00 PM PDT 24
Finished Aug 06 05:29:02 PM PDT 24
Peak memory 248536 kb
Host smart-f56fe683-d5e7-444a-a983-4763d7b8dc9b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1517857600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1517857600
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.356129204
Short name T388
Test name
Test status
Simulation time 258701343770 ps
CPU time 2545.09 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 06:11:31 PM PDT 24
Peak memory 288052 kb
Host smart-db6778e6-a48f-44a3-8bf9-26aaf89c2ca5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356129204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.356129204
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1490850594
Short name T435
Test name
Test status
Simulation time 1903998912 ps
CPU time 12 seconds
Started Aug 06 05:29:03 PM PDT 24
Finished Aug 06 05:29:15 PM PDT 24
Peak memory 248472 kb
Host smart-f54d1855-eca2-4cf6-8163-6a39eddab42b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1490850594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1490850594
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.720959173
Short name T550
Test name
Test status
Simulation time 24265729715 ps
CPU time 331.26 seconds
Started Aug 06 05:29:00 PM PDT 24
Finished Aug 06 05:34:32 PM PDT 24
Peak memory 256712 kb
Host smart-f3674fb4-398e-4d66-803b-97238606c1d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72095
9173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.720959173
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1583929456
Short name T99
Test name
Test status
Simulation time 184848687 ps
CPU time 11.76 seconds
Started Aug 06 05:29:00 PM PDT 24
Finished Aug 06 05:29:12 PM PDT 24
Peak memory 256484 kb
Host smart-adbf2765-58f7-481f-ae81-15d368b0df0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15839
29456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1583929456
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2836151520
Short name T179
Test name
Test status
Simulation time 69130688221 ps
CPU time 1375.55 seconds
Started Aug 06 05:28:59 PM PDT 24
Finished Aug 06 05:51:55 PM PDT 24
Peak memory 288536 kb
Host smart-e6356064-623f-4df0-8ba6-9be53fd50ca5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836151520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2836151520
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1406008119
Short name T529
Test name
Test status
Simulation time 78239402297 ps
CPU time 1339.04 seconds
Started Aug 06 05:28:58 PM PDT 24
Finished Aug 06 05:51:17 PM PDT 24
Peak memory 273108 kb
Host smart-1e3c8005-48e6-479c-ab09-d22e1a65727d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406008119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1406008119
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1456410301
Short name T575
Test name
Test status
Simulation time 2821902942 ps
CPU time 47.12 seconds
Started Aug 06 05:29:06 PM PDT 24
Finished Aug 06 05:29:53 PM PDT 24
Peak memory 248476 kb
Host smart-393e8d02-8a78-48cb-9aee-b4bc30790991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14564
10301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1456410301
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3357592120
Short name T577
Test name
Test status
Simulation time 293175951 ps
CPU time 22.38 seconds
Started Aug 06 05:29:00 PM PDT 24
Finished Aug 06 05:29:23 PM PDT 24
Peak memory 248452 kb
Host smart-59447e02-0446-40a6-9554-140784519aa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33575
92120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3357592120
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.4287687050
Short name T423
Test name
Test status
Simulation time 572617518 ps
CPU time 11.05 seconds
Started Aug 06 05:29:00 PM PDT 24
Finished Aug 06 05:29:11 PM PDT 24
Peak memory 253368 kb
Host smart-ab6d8cbe-40a1-4447-8322-f2d77cfe7491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42876
87050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.4287687050
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3197749009
Short name T598
Test name
Test status
Simulation time 443537966 ps
CPU time 14.12 seconds
Started Aug 06 05:29:02 PM PDT 24
Finished Aug 06 05:29:16 PM PDT 24
Peak memory 254108 kb
Host smart-5c3a317f-bd4c-4c94-b4df-a1bdb5d4a739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31977
49009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3197749009
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.1473161162
Short name T477
Test name
Test status
Simulation time 27656001992 ps
CPU time 1750.54 seconds
Started Aug 06 05:28:59 PM PDT 24
Finished Aug 06 05:58:10 PM PDT 24
Peak memory 289436 kb
Host smart-8d92d2a4-9ecf-459a-aa29-6800cb150f77
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473161162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.1473161162
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.332234138
Short name T564
Test name
Test status
Simulation time 99886408646 ps
CPU time 5367.61 seconds
Started Aug 06 05:28:59 PM PDT 24
Finished Aug 06 06:58:27 PM PDT 24
Peak memory 338332 kb
Host smart-2c5aa815-3865-4c28-b83b-c395f42a3c6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332234138 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.332234138
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1496860668
Short name T200
Test name
Test status
Simulation time 42766455 ps
CPU time 3.94 seconds
Started Aug 06 05:29:03 PM PDT 24
Finished Aug 06 05:29:07 PM PDT 24
Peak memory 248644 kb
Host smart-2edb13dc-60cb-4415-8376-6a0b240ba72c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1496860668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1496860668
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.4222210074
Short name T23
Test name
Test status
Simulation time 12097705850 ps
CPU time 1270.26 seconds
Started Aug 06 05:29:02 PM PDT 24
Finished Aug 06 05:50:13 PM PDT 24
Peak memory 288796 kb
Host smart-850403da-c11b-4ea9-b634-d3d2825a9638
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222210074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.4222210074
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2473860564
Short name T473
Test name
Test status
Simulation time 183830281 ps
CPU time 10.5 seconds
Started Aug 06 05:29:01 PM PDT 24
Finished Aug 06 05:29:11 PM PDT 24
Peak memory 248392 kb
Host smart-68cc937f-90cc-4aea-8a9e-3e27ef14642e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2473860564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2473860564
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1429473918
Short name T446
Test name
Test status
Simulation time 12108903266 ps
CPU time 195.65 seconds
Started Aug 06 05:29:00 PM PDT 24
Finished Aug 06 05:32:16 PM PDT 24
Peak memory 256324 kb
Host smart-901a191c-da76-4363-90e7-ca43a1fc025b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14294
73918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1429473918
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1142793211
Short name T434
Test name
Test status
Simulation time 318709871 ps
CPU time 23.91 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 05:29:29 PM PDT 24
Peak memory 247992 kb
Host smart-0f544e44-89c7-4a0c-922a-f633b7937606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11427
93211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1142793211
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3538784944
Short name T449
Test name
Test status
Simulation time 41586871507 ps
CPU time 680.12 seconds
Started Aug 06 05:29:02 PM PDT 24
Finished Aug 06 05:40:23 PM PDT 24
Peak memory 264984 kb
Host smart-b4159262-9607-4cb7-883d-0cfe9d657385
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538784944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3538784944
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1164079180
Short name T691
Test name
Test status
Simulation time 698326814 ps
CPU time 11.72 seconds
Started Aug 06 05:28:59 PM PDT 24
Finished Aug 06 05:29:11 PM PDT 24
Peak memory 248468 kb
Host smart-15d57390-964e-4e9f-a6e7-06bb8ece93b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11640
79180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1164079180
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.4172376067
Short name T375
Test name
Test status
Simulation time 9043029474 ps
CPU time 47.03 seconds
Started Aug 06 05:29:03 PM PDT 24
Finished Aug 06 05:29:50 PM PDT 24
Peak memory 255092 kb
Host smart-f8a626a8-6941-42e5-bab7-1f14395dbb61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41723
76067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.4172376067
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.4238245029
Short name T501
Test name
Test status
Simulation time 185806594 ps
CPU time 11.49 seconds
Started Aug 06 05:29:00 PM PDT 24
Finished Aug 06 05:29:12 PM PDT 24
Peak memory 255068 kb
Host smart-09cf0b70-b5c3-41e9-aded-82c1d9980e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42382
45029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.4238245029
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3774690421
Short name T205
Test name
Test status
Simulation time 325417476 ps
CPU time 3.6 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 05:29:09 PM PDT 24
Peak memory 248704 kb
Host smart-d414cd2f-4e23-4d49-860d-fe56927367db
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3774690421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3774690421
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.905795631
Short name T698
Test name
Test status
Simulation time 411086507 ps
CPU time 12.75 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 05:29:18 PM PDT 24
Peak memory 248464 kb
Host smart-46327b65-807a-4b47-b11a-a72835a92ad4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=905795631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.905795631
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1334921350
Short name T366
Test name
Test status
Simulation time 1301229108 ps
CPU time 46.21 seconds
Started Aug 06 05:29:02 PM PDT 24
Finished Aug 06 05:29:48 PM PDT 24
Peak memory 256032 kb
Host smart-47f03ab9-adb9-42ae-9677-64a7c448e4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13349
21350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1334921350
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1798390649
Short name T640
Test name
Test status
Simulation time 743820526 ps
CPU time 16.4 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 05:29:22 PM PDT 24
Peak memory 247908 kb
Host smart-0b75d36e-71ec-44ba-988c-2d5f10c3c0db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17983
90649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1798390649
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2800238584
Short name T180
Test name
Test status
Simulation time 71711291965 ps
CPU time 1465.37 seconds
Started Aug 06 05:29:03 PM PDT 24
Finished Aug 06 05:53:29 PM PDT 24
Peak memory 288780 kb
Host smart-ec1cfc96-6fd0-4943-b1a6-bf9e0d18d6b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800238584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2800238584
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.963300687
Short name T603
Test name
Test status
Simulation time 71337453019 ps
CPU time 2389.01 seconds
Started Aug 06 05:29:01 PM PDT 24
Finished Aug 06 06:08:51 PM PDT 24
Peak memory 287452 kb
Host smart-f323e644-70bf-4835-b9ca-663d53341763
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963300687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.963300687
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.305301190
Short name T318
Test name
Test status
Simulation time 9580119310 ps
CPU time 395.1 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 05:35:41 PM PDT 24
Peak memory 248588 kb
Host smart-f8687581-5032-460b-9289-5ea6c9fb20cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305301190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.305301190
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.2447275509
Short name T532
Test name
Test status
Simulation time 4144257788 ps
CPU time 30.24 seconds
Started Aug 06 05:29:02 PM PDT 24
Finished Aug 06 05:29:33 PM PDT 24
Peak memory 256072 kb
Host smart-5fe4461d-2adb-44d3-800e-cbe4ac4e63a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24472
75509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2447275509
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2692464326
Short name T528
Test name
Test status
Simulation time 484622373 ps
CPU time 21.49 seconds
Started Aug 06 05:29:01 PM PDT 24
Finished Aug 06 05:29:23 PM PDT 24
Peak memory 255188 kb
Host smart-9f8b074c-8dc9-41ca-a6ef-3a960bfb580f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26924
64326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2692464326
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1672204493
Short name T595
Test name
Test status
Simulation time 2022941141 ps
CPU time 36.48 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 05:29:41 PM PDT 24
Peak memory 255948 kb
Host smart-d9f293bc-751d-48e5-ab9c-7d49b8367940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16722
04493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1672204493
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.4091702159
Short name T455
Test name
Test status
Simulation time 774687570 ps
CPU time 50.42 seconds
Started Aug 06 05:29:03 PM PDT 24
Finished Aug 06 05:29:53 PM PDT 24
Peak memory 256580 kb
Host smart-de308451-83b6-449d-984e-0c0716136730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40917
02159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.4091702159
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.4253062714
Short name T481
Test name
Test status
Simulation time 127794475666 ps
CPU time 3668.48 seconds
Started Aug 06 05:29:02 PM PDT 24
Finished Aug 06 06:30:11 PM PDT 24
Peak memory 305536 kb
Host smart-e8808bcd-fdd4-4d11-bce5-f49a5948b36e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253062714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.4253062714
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.988215404
Short name T669
Test name
Test status
Simulation time 43555218915 ps
CPU time 2655.96 seconds
Started Aug 06 05:29:02 PM PDT 24
Finished Aug 06 06:13:19 PM PDT 24
Peak memory 297868 kb
Host smart-af19f3d1-5d0b-47ba-85ea-083122ac4668
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988215404 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.988215404
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2396574118
Short name T55
Test name
Test status
Simulation time 43326824 ps
CPU time 3.7 seconds
Started Aug 06 05:29:04 PM PDT 24
Finished Aug 06 05:29:08 PM PDT 24
Peak memory 248520 kb
Host smart-8c8c5866-f06a-4d91-ae23-903b251b2798
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2396574118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2396574118
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3320852158
Short name T297
Test name
Test status
Simulation time 8666679935 ps
CPU time 746.14 seconds
Started Aug 06 05:29:02 PM PDT 24
Finished Aug 06 05:41:29 PM PDT 24
Peak memory 264984 kb
Host smart-15f5bed4-5f84-4567-8deb-b1e1a059aec1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320852158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3320852158
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3116684106
Short name T549
Test name
Test status
Simulation time 421691707 ps
CPU time 8.29 seconds
Started Aug 06 05:29:03 PM PDT 24
Finished Aug 06 05:29:11 PM PDT 24
Peak memory 248472 kb
Host smart-5256ce86-f903-417d-942e-7aa883648298
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3116684106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3116684106
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2785918775
Short name T463
Test name
Test status
Simulation time 821714583 ps
CPU time 45.37 seconds
Started Aug 06 05:29:02 PM PDT 24
Finished Aug 06 05:29:48 PM PDT 24
Peak memory 256020 kb
Host smart-0b264430-7808-4345-b3df-2a4e8af5365a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27859
18775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2785918775
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3253892650
Short name T538
Test name
Test status
Simulation time 1439205736 ps
CPU time 48.72 seconds
Started Aug 06 05:29:03 PM PDT 24
Finished Aug 06 05:29:52 PM PDT 24
Peak memory 256620 kb
Host smart-bc804dca-4519-4460-bd77-8b30d7b775b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32538
92650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3253892650
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.319280464
Short name T521
Test name
Test status
Simulation time 34928959440 ps
CPU time 1142.09 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 05:48:07 PM PDT 24
Peak memory 272428 kb
Host smart-ee31befe-64cf-45ac-8502-ce8976c02933
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319280464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.319280464
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.903781057
Short name T16
Test name
Test status
Simulation time 97988939610 ps
CPU time 1202.78 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 05:49:09 PM PDT 24
Peak memory 289324 kb
Host smart-a35b4000-d600-4ff2-a5b2-f2fd80bbd3d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903781057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.903781057
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.4240332387
Short name T176
Test name
Test status
Simulation time 6104964916 ps
CPU time 241.66 seconds
Started Aug 06 05:29:06 PM PDT 24
Finished Aug 06 05:33:07 PM PDT 24
Peak memory 248428 kb
Host smart-df247acf-438e-4dab-8a0f-c43ef194b463
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240332387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.4240332387
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2457471493
Short name T697
Test name
Test status
Simulation time 1346829871 ps
CPU time 20.33 seconds
Started Aug 06 05:29:03 PM PDT 24
Finished Aug 06 05:29:23 PM PDT 24
Peak memory 255584 kb
Host smart-ad4f6be6-d1aa-4bba-a269-288329fbd1c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24574
71493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2457471493
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3274224179
Short name T546
Test name
Test status
Simulation time 1291420271 ps
CPU time 35.09 seconds
Started Aug 06 05:29:02 PM PDT 24
Finished Aug 06 05:29:37 PM PDT 24
Peak memory 255684 kb
Host smart-5a0dee8a-9f93-4801-8a5f-ccdd9dd215d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32742
24179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3274224179
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2905306679
Short name T692
Test name
Test status
Simulation time 547923483 ps
CPU time 40.97 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 05:29:47 PM PDT 24
Peak memory 256532 kb
Host smart-72d50405-74d0-4071-98ce-da1c33003403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29053
06679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2905306679
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1209790390
Short name T401
Test name
Test status
Simulation time 2463164688 ps
CPU time 44.29 seconds
Started Aug 06 05:29:01 PM PDT 24
Finished Aug 06 05:29:46 PM PDT 24
Peak memory 256608 kb
Host smart-bfe4031b-68f0-46ac-98e0-33836d1dd8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12097
90390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1209790390
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3566322087
Short name T98
Test name
Test status
Simulation time 3271934639 ps
CPU time 75.01 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 05:30:20 PM PDT 24
Peak memory 256724 kb
Host smart-69def0eb-648e-4781-96ba-b44bd2c74ab8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566322087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3566322087
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3796305758
Short name T238
Test name
Test status
Simulation time 13733592521 ps
CPU time 894.83 seconds
Started Aug 06 05:29:07 PM PDT 24
Finished Aug 06 05:44:02 PM PDT 24
Peak memory 272620 kb
Host smart-24d1ca5d-2efb-4a75-9dd1-be13af94cf4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796305758 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3796305758
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3059030161
Short name T210
Test name
Test status
Simulation time 48289881 ps
CPU time 3.55 seconds
Started Aug 06 05:29:09 PM PDT 24
Finished Aug 06 05:29:13 PM PDT 24
Peak memory 248680 kb
Host smart-169934ad-b34e-4da5-984c-6d65ea144a18
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3059030161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3059030161
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.380050674
Short name T28
Test name
Test status
Simulation time 94935788010 ps
CPU time 3073.91 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 06:20:19 PM PDT 24
Peak memory 289080 kb
Host smart-c17ceeb3-2450-4d22-9afc-3d2d2e76eca5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380050674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.380050674
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1623035869
Short name T394
Test name
Test status
Simulation time 428627002 ps
CPU time 7.16 seconds
Started Aug 06 05:29:11 PM PDT 24
Finished Aug 06 05:29:18 PM PDT 24
Peak memory 248416 kb
Host smart-0f4519df-73e8-418a-b768-859381f9a9bf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1623035869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1623035869
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.588723818
Short name T467
Test name
Test status
Simulation time 1392930106 ps
CPU time 125.18 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 05:31:10 PM PDT 24
Peak memory 251544 kb
Host smart-2d0b5587-1a40-4065-bad3-b4bd51058c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58872
3818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.588723818
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2602965227
Short name T487
Test name
Test status
Simulation time 309172078 ps
CPU time 27.7 seconds
Started Aug 06 05:29:06 PM PDT 24
Finished Aug 06 05:29:34 PM PDT 24
Peak memory 256004 kb
Host smart-87f28f80-57cb-45e8-b371-243ce51d38bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26029
65227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2602965227
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3381623020
Short name T342
Test name
Test status
Simulation time 32698094539 ps
CPU time 968.1 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 05:45:13 PM PDT 24
Peak memory 272716 kb
Host smart-40db5a26-d5ca-4783-9b79-75cfbb6078f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381623020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3381623020
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2628368867
Short name T587
Test name
Test status
Simulation time 21429388941 ps
CPU time 937.88 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 05:44:43 PM PDT 24
Peak memory 271140 kb
Host smart-0b56925f-6d40-4eeb-a012-ccc0197c886a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628368867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2628368867
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.1967068176
Short name T325
Test name
Test status
Simulation time 6496773216 ps
CPU time 259.55 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 05:33:24 PM PDT 24
Peak memory 247496 kb
Host smart-ebbc1ce9-d04f-40ab-b618-b38bf641e4ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967068176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1967068176
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3169869564
Short name T283
Test name
Test status
Simulation time 290295988 ps
CPU time 20.81 seconds
Started Aug 06 05:29:04 PM PDT 24
Finished Aug 06 05:29:25 PM PDT 24
Peak memory 255904 kb
Host smart-4d28476a-a8fa-4de7-97ac-23414121c66d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31698
69564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3169869564
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.4218761756
Short name T77
Test name
Test status
Simulation time 8935349594 ps
CPU time 48.76 seconds
Started Aug 06 05:29:07 PM PDT 24
Finished Aug 06 05:29:56 PM PDT 24
Peak memory 256776 kb
Host smart-6af66fa8-e4c1-47ba-a8a8-06aedd848561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42187
61756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.4218761756
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3975923146
Short name T62
Test name
Test status
Simulation time 703320678 ps
CPU time 45.46 seconds
Started Aug 06 05:29:03 PM PDT 24
Finished Aug 06 05:29:49 PM PDT 24
Peak memory 256008 kb
Host smart-d1f7a52c-5198-408a-9fe7-73ade446cc90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39759
23146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3975923146
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2393508685
Short name T26
Test name
Test status
Simulation time 7943825851 ps
CPU time 45.83 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 05:29:51 PM PDT 24
Peak memory 256692 kb
Host smart-26b75ba9-1c50-4f80-b915-6b66c6008c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23935
08685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2393508685
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2589278835
Short name T385
Test name
Test status
Simulation time 6357365892 ps
CPU time 383.51 seconds
Started Aug 06 05:29:04 PM PDT 24
Finished Aug 06 05:35:27 PM PDT 24
Peak memory 256792 kb
Host smart-653559c1-95d7-4ecc-a693-3011be5bf015
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589278835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2589278835
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.2564170639
Short name T259
Test name
Test status
Simulation time 58602888967 ps
CPU time 3911.29 seconds
Started Aug 06 05:29:09 PM PDT 24
Finished Aug 06 06:34:21 PM PDT 24
Peak memory 321692 kb
Host smart-6654a9ca-86a5-4b11-a4e9-c306bf3baa30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564170639 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.2564170639
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1557207952
Short name T214
Test name
Test status
Simulation time 47622351 ps
CPU time 3.92 seconds
Started Aug 06 05:28:08 PM PDT 24
Finished Aug 06 05:28:12 PM PDT 24
Peak memory 248676 kb
Host smart-2b5417d6-8556-41d5-ba38-85c943bfbafe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1557207952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1557207952
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2805634472
Short name T452
Test name
Test status
Simulation time 94177695707 ps
CPU time 1609.91 seconds
Started Aug 06 05:28:03 PM PDT 24
Finished Aug 06 05:54:53 PM PDT 24
Peak memory 272920 kb
Host smart-eba9ce30-b5f7-4e10-85ee-1d8f3f1a792d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805634472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2805634472
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3368909469
Short name T483
Test name
Test status
Simulation time 2409196237 ps
CPU time 32.48 seconds
Started Aug 06 05:28:05 PM PDT 24
Finished Aug 06 05:28:37 PM PDT 24
Peak memory 256324 kb
Host smart-e948d65a-dbcd-497f-96b7-5f0641bf1ef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33689
09469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3368909469
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2340796551
Short name T596
Test name
Test status
Simulation time 514200815 ps
CPU time 15.14 seconds
Started Aug 06 05:28:02 PM PDT 24
Finished Aug 06 05:28:18 PM PDT 24
Peak memory 256116 kb
Host smart-c54fdfd3-2856-4c81-bd33-d7b19cdd352d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23407
96551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2340796551
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2050847858
Short name T326
Test name
Test status
Simulation time 65438125148 ps
CPU time 1377.17 seconds
Started Aug 06 05:28:08 PM PDT 24
Finished Aug 06 05:51:05 PM PDT 24
Peak memory 288796 kb
Host smart-3123d7cb-65e3-4b04-b331-508e29943868
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050847858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2050847858
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.906964912
Short name T476
Test name
Test status
Simulation time 59623075221 ps
CPU time 1743.75 seconds
Started Aug 06 05:28:05 PM PDT 24
Finished Aug 06 05:57:09 PM PDT 24
Peak memory 288688 kb
Host smart-9205d596-78bc-44b4-b149-edc10d3c0654
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906964912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.906964912
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.33699906
Short name T315
Test name
Test status
Simulation time 8532850207 ps
CPU time 181.81 seconds
Started Aug 06 05:28:09 PM PDT 24
Finished Aug 06 05:31:11 PM PDT 24
Peak memory 255640 kb
Host smart-8a673af8-7a92-4623-b002-9a4c1cc78c70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33699906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.33699906
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1927569726
Short name T667
Test name
Test status
Simulation time 857432892 ps
CPU time 22.75 seconds
Started Aug 06 05:28:08 PM PDT 24
Finished Aug 06 05:28:31 PM PDT 24
Peak memory 255820 kb
Host smart-9b34e1d8-abcf-482f-9d5f-8ee0806c3b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19275
69726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1927569726
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.4073292770
Short name T508
Test name
Test status
Simulation time 3626805198 ps
CPU time 50.76 seconds
Started Aug 06 05:28:04 PM PDT 24
Finished Aug 06 05:28:54 PM PDT 24
Peak memory 247736 kb
Host smart-5c136b3f-c40a-42d0-a19c-5a6417742046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40732
92770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.4073292770
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.1074071925
Short name T34
Test name
Test status
Simulation time 1856002720 ps
CPU time 20.25 seconds
Started Aug 06 05:28:06 PM PDT 24
Finished Aug 06 05:28:26 PM PDT 24
Peak memory 273536 kb
Host smart-d7d53286-1521-4e8a-af6a-a666d28ec4da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1074071925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1074071925
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2570884448
Short name T368
Test name
Test status
Simulation time 309434932 ps
CPU time 15.57 seconds
Started Aug 06 05:28:05 PM PDT 24
Finished Aug 06 05:28:21 PM PDT 24
Peak memory 248016 kb
Host smart-925aa32b-5370-4fe5-82c5-c459f0662247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25708
84448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2570884448
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.4020992440
Short name T106
Test name
Test status
Simulation time 3594103137 ps
CPU time 56.66 seconds
Started Aug 06 05:28:02 PM PDT 24
Finished Aug 06 05:28:59 PM PDT 24
Peak memory 256496 kb
Host smart-531cf0fe-fccd-4e56-931e-dbb29001e63d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40209
92440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.4020992440
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.598089305
Short name T82
Test name
Test status
Simulation time 185478530218 ps
CPU time 2965.19 seconds
Started Aug 06 05:28:07 PM PDT 24
Finished Aug 06 06:17:32 PM PDT 24
Peak memory 288996 kb
Host smart-a84c8edf-9893-486e-a6a4-e1eba29564ff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598089305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.598089305
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2965583806
Short name T29
Test name
Test status
Simulation time 175268006728 ps
CPU time 5753.72 seconds
Started Aug 06 05:28:05 PM PDT 24
Finished Aug 06 07:04:00 PM PDT 24
Peak memory 338672 kb
Host smart-4fb1869e-98b0-42ff-bbee-7f3be80d5568
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965583806 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2965583806
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3459691597
Short name T506
Test name
Test status
Simulation time 4943083148 ps
CPU time 525.5 seconds
Started Aug 06 05:29:08 PM PDT 24
Finished Aug 06 05:37:53 PM PDT 24
Peak memory 273144 kb
Host smart-0495a0b0-905a-4b2b-a5ef-c8f2a958ba07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459691597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3459691597
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1238553053
Short name T364
Test name
Test status
Simulation time 3505604430 ps
CPU time 199.48 seconds
Started Aug 06 05:29:02 PM PDT 24
Finished Aug 06 05:32:22 PM PDT 24
Peak memory 256692 kb
Host smart-efb9e0ff-fc2d-416f-9314-948fb85e83b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12385
53053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1238553053
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.801102254
Short name T493
Test name
Test status
Simulation time 1007315003 ps
CPU time 37.66 seconds
Started Aug 06 05:29:07 PM PDT 24
Finished Aug 06 05:29:45 PM PDT 24
Peak memory 256420 kb
Host smart-05239d3d-d2b8-407f-9d70-f662a2ffeac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80110
2254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.801102254
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.983606661
Short name T641
Test name
Test status
Simulation time 17957688853 ps
CPU time 1470.96 seconds
Started Aug 06 05:29:06 PM PDT 24
Finished Aug 06 05:53:38 PM PDT 24
Peak memory 289476 kb
Host smart-4b82641e-2b22-4b95-8232-81eeafc6cdda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983606661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.983606661
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.4022687271
Short name T61
Test name
Test status
Simulation time 28941267660 ps
CPU time 1634.72 seconds
Started Aug 06 05:29:06 PM PDT 24
Finished Aug 06 05:56:21 PM PDT 24
Peak memory 288556 kb
Host smart-da93bb21-98e4-47ff-b99f-980e2699aa83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022687271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.4022687271
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3181112224
Short name T610
Test name
Test status
Simulation time 3796212723 ps
CPU time 162.01 seconds
Started Aug 06 05:29:07 PM PDT 24
Finished Aug 06 05:31:49 PM PDT 24
Peak memory 248512 kb
Host smart-72e1a113-6d96-4211-bbfa-a22f3bd39456
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181112224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3181112224
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.470618679
Short name T399
Test name
Test status
Simulation time 1743452701 ps
CPU time 51.72 seconds
Started Aug 06 05:29:10 PM PDT 24
Finished Aug 06 05:30:02 PM PDT 24
Peak memory 255960 kb
Host smart-d7990655-5e2e-4983-b087-8f127a73970c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47061
8679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.470618679
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1054271479
Short name T636
Test name
Test status
Simulation time 118338212 ps
CPU time 9.87 seconds
Started Aug 06 05:29:07 PM PDT 24
Finished Aug 06 05:29:17 PM PDT 24
Peak memory 247844 kb
Host smart-0a9ba764-4acd-4199-8689-67fbcfc9ea0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10542
71479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1054271479
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3733910450
Short name T258
Test name
Test status
Simulation time 284796825 ps
CPU time 9.46 seconds
Started Aug 06 05:29:06 PM PDT 24
Finished Aug 06 05:29:16 PM PDT 24
Peak memory 247980 kb
Host smart-b7e1b94b-eb93-4250-8601-b94927350f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37339
10450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3733910450
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3639137891
Short name T396
Test name
Test status
Simulation time 136282180 ps
CPU time 8.77 seconds
Started Aug 06 05:29:10 PM PDT 24
Finished Aug 06 05:29:19 PM PDT 24
Peak memory 251376 kb
Host smart-2b70ed81-a8ec-4a2b-8b4e-03aa2482046d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36391
37891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3639137891
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1014955329
Short name T534
Test name
Test status
Simulation time 5669465793 ps
CPU time 142.32 seconds
Started Aug 06 05:29:09 PM PDT 24
Finished Aug 06 05:31:31 PM PDT 24
Peak memory 256640 kb
Host smart-814c33b6-2260-45fd-8fd1-fdafa08b6091
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014955329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1014955329
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.217468486
Short name T688
Test name
Test status
Simulation time 26728035264 ps
CPU time 1600.32 seconds
Started Aug 06 05:29:14 PM PDT 24
Finished Aug 06 05:55:54 PM PDT 24
Peak memory 273092 kb
Host smart-3b47dbd5-e82e-455e-bec5-a00b24ef0529
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217468486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.217468486
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2620740882
Short name T588
Test name
Test status
Simulation time 145849433 ps
CPU time 13.86 seconds
Started Aug 06 05:29:10 PM PDT 24
Finished Aug 06 05:29:24 PM PDT 24
Peak memory 255964 kb
Host smart-9bd73ff7-3ffe-43b9-9298-c07b31c0e00d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26207
40882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2620740882
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1067986590
Short name T591
Test name
Test status
Simulation time 1187778052 ps
CPU time 19.85 seconds
Started Aug 06 05:29:14 PM PDT 24
Finished Aug 06 05:29:33 PM PDT 24
Peak memory 256016 kb
Host smart-a4ec32d6-b5da-4881-ace4-4aefef89dcb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10679
86590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1067986590
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2812392849
Short name T531
Test name
Test status
Simulation time 47124560686 ps
CPU time 994.25 seconds
Started Aug 06 05:29:14 PM PDT 24
Finished Aug 06 05:45:48 PM PDT 24
Peak memory 272676 kb
Host smart-ebd3396c-1900-4c9e-828b-29702451fd67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812392849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2812392849
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2451911526
Short name T653
Test name
Test status
Simulation time 15635471796 ps
CPU time 343.34 seconds
Started Aug 06 05:29:17 PM PDT 24
Finished Aug 06 05:35:00 PM PDT 24
Peak memory 247404 kb
Host smart-71384dd9-e23f-4198-9fa0-b7dfa1686b90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451911526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2451911526
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2138970157
Short name T382
Test name
Test status
Simulation time 952368469 ps
CPU time 40.08 seconds
Started Aug 06 05:29:08 PM PDT 24
Finished Aug 06 05:29:48 PM PDT 24
Peak memory 255872 kb
Host smart-b9a37455-bb35-4791-9f7e-9b2b5568a8f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21389
70157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2138970157
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1531788896
Short name T433
Test name
Test status
Simulation time 2831000182 ps
CPU time 45.79 seconds
Started Aug 06 05:29:09 PM PDT 24
Finished Aug 06 05:29:54 PM PDT 24
Peak memory 255888 kb
Host smart-9142e323-4b20-4b64-9487-1c2bc3055fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15317
88896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1531788896
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1496968601
Short name T278
Test name
Test status
Simulation time 479234983 ps
CPU time 21.3 seconds
Started Aug 06 05:29:14 PM PDT 24
Finished Aug 06 05:29:36 PM PDT 24
Peak memory 256556 kb
Host smart-1fbccefa-1ce4-4203-832d-240eb45c0d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14969
68601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1496968601
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2675175399
Short name T58
Test name
Test status
Simulation time 1180971898 ps
CPU time 47.64 seconds
Started Aug 06 05:29:09 PM PDT 24
Finished Aug 06 05:29:57 PM PDT 24
Peak memory 256440 kb
Host smart-6436d1e9-0c67-4ce6-9968-aecf249521e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26751
75399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2675175399
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1236882142
Short name T685
Test name
Test status
Simulation time 63336614617 ps
CPU time 1946.76 seconds
Started Aug 06 05:29:14 PM PDT 24
Finished Aug 06 06:01:41 PM PDT 24
Peak memory 273064 kb
Host smart-00c907af-a84c-4dc8-ad6c-a53349dd99ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236882142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1236882142
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1843693802
Short name T282
Test name
Test status
Simulation time 9288862134 ps
CPU time 127.88 seconds
Started Aug 06 05:29:15 PM PDT 24
Finished Aug 06 05:31:23 PM PDT 24
Peak memory 256304 kb
Host smart-3d03b733-2ad4-4236-899b-4e3f4fe99f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18436
93802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1843693802
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2985627102
Short name T659
Test name
Test status
Simulation time 305175844 ps
CPU time 29.97 seconds
Started Aug 06 05:29:18 PM PDT 24
Finished Aug 06 05:29:48 PM PDT 24
Peak memory 248456 kb
Host smart-6674fa6d-9fef-441a-9415-b6f6991b3b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29856
27102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2985627102
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.4047773851
Short name T415
Test name
Test status
Simulation time 51393388221 ps
CPU time 1069.74 seconds
Started Aug 06 05:29:10 PM PDT 24
Finished Aug 06 05:47:00 PM PDT 24
Peak memory 289156 kb
Host smart-dbaf2263-5c8d-4110-bd92-8ca0c54002b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047773851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.4047773851
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1087505905
Short name T317
Test name
Test status
Simulation time 11876022582 ps
CPU time 457.1 seconds
Started Aug 06 05:29:15 PM PDT 24
Finished Aug 06 05:36:52 PM PDT 24
Peak memory 255584 kb
Host smart-d8e40693-6324-4a29-a19e-74bb5dc3af4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087505905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1087505905
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3513836688
Short name T547
Test name
Test status
Simulation time 1102693694 ps
CPU time 27.49 seconds
Started Aug 06 05:29:18 PM PDT 24
Finished Aug 06 05:29:45 PM PDT 24
Peak memory 248448 kb
Host smart-ae21f730-43ee-409b-addf-e44fd47d0de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35138
36688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3513836688
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2690236797
Short name T84
Test name
Test status
Simulation time 1429145896 ps
CPU time 37.9 seconds
Started Aug 06 05:29:13 PM PDT 24
Finished Aug 06 05:29:51 PM PDT 24
Peak memory 248128 kb
Host smart-1f68dacc-c5db-43f7-8be6-a3dbbe41c412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26902
36797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2690236797
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2113768761
Short name T80
Test name
Test status
Simulation time 166247726 ps
CPU time 16.34 seconds
Started Aug 06 05:29:14 PM PDT 24
Finished Aug 06 05:29:30 PM PDT 24
Peak memory 248428 kb
Host smart-7714ce5f-f2d9-4567-bc6d-0a7cfed6d230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21137
68761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2113768761
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3918615023
Short name T522
Test name
Test status
Simulation time 84214109497 ps
CPU time 3169.11 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 06:21:55 PM PDT 24
Peak memory 288164 kb
Host smart-a890b58d-68ef-4bb8-b108-69c59d6e25bc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918615023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3918615023
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2487669922
Short name T68
Test name
Test status
Simulation time 133961047274 ps
CPU time 2227.67 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 06:06:13 PM PDT 24
Peak memory 287920 kb
Host smart-925a5eb7-ea79-4692-99dd-7c974feb3ba5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487669922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2487669922
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.605901564
Short name T245
Test name
Test status
Simulation time 5486502960 ps
CPU time 116.37 seconds
Started Aug 06 05:29:07 PM PDT 24
Finished Aug 06 05:31:03 PM PDT 24
Peak memory 256364 kb
Host smart-7ae91041-c56e-4c57-97a4-b314e5f7cb21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60590
1564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.605901564
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3737827223
Short name T499
Test name
Test status
Simulation time 1995681773 ps
CPU time 67.23 seconds
Started Aug 06 05:29:02 PM PDT 24
Finished Aug 06 05:30:10 PM PDT 24
Peak memory 255960 kb
Host smart-d91c7bf1-6e72-4b2e-9556-7ade2500a988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37378
27223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3737827223
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1967962362
Short name T286
Test name
Test status
Simulation time 85008976099 ps
CPU time 2402.22 seconds
Started Aug 06 05:29:03 PM PDT 24
Finished Aug 06 06:09:06 PM PDT 24
Peak memory 288976 kb
Host smart-c0e6ead1-8d6f-48ff-81b1-8a2c5f93a2eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967962362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1967962362
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2412980800
Short name T677
Test name
Test status
Simulation time 177268348157 ps
CPU time 1318.55 seconds
Started Aug 06 05:29:04 PM PDT 24
Finished Aug 06 05:51:03 PM PDT 24
Peak memory 272764 kb
Host smart-d2d884cc-6c7b-4019-b805-700e9d3673c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412980800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2412980800
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2667582923
Short name T324
Test name
Test status
Simulation time 13363920611 ps
CPU time 542.71 seconds
Started Aug 06 05:29:09 PM PDT 24
Finished Aug 06 05:38:12 PM PDT 24
Peak memory 255716 kb
Host smart-1e1b9f7a-8dc1-40f8-a24c-bafb80db6bed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667582923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2667582923
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1925047865
Short name T597
Test name
Test status
Simulation time 1393313954 ps
CPU time 32.48 seconds
Started Aug 06 05:29:03 PM PDT 24
Finished Aug 06 05:29:36 PM PDT 24
Peak memory 248376 kb
Host smart-52ddf42f-4f9d-4627-8c42-abf3179cfbd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19250
47865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1925047865
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2933991633
Short name T525
Test name
Test status
Simulation time 534639127 ps
CPU time 35.75 seconds
Started Aug 06 05:29:04 PM PDT 24
Finished Aug 06 05:29:39 PM PDT 24
Peak memory 256000 kb
Host smart-9d62200a-8b88-4f6d-8198-78bba545374d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29339
91633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2933991633
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.827751009
Short name T223
Test name
Test status
Simulation time 4926064863 ps
CPU time 39.44 seconds
Started Aug 06 05:29:04 PM PDT 24
Finished Aug 06 05:29:43 PM PDT 24
Peak memory 248536 kb
Host smart-02fe2571-8059-4bfb-9005-78fbeba954be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82775
1009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.827751009
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.516865474
Short name T490
Test name
Test status
Simulation time 1031500027 ps
CPU time 59.4 seconds
Started Aug 06 05:29:04 PM PDT 24
Finished Aug 06 05:30:03 PM PDT 24
Peak memory 256520 kb
Host smart-67e46e0e-00cf-442d-bf12-d9b1531ccad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51686
5474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.516865474
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.4045721041
Short name T461
Test name
Test status
Simulation time 216213140322 ps
CPU time 6553.71 seconds
Started Aug 06 05:29:10 PM PDT 24
Finished Aug 06 07:18:25 PM PDT 24
Peak memory 354348 kb
Host smart-80b1dcb8-a7c6-4705-9590-1cb592cf9e09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045721041 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.4045721041
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3793868312
Short name T430
Test name
Test status
Simulation time 16791369151 ps
CPU time 881.66 seconds
Started Aug 06 05:29:06 PM PDT 24
Finished Aug 06 05:43:48 PM PDT 24
Peak memory 272444 kb
Host smart-6f0e1212-d68f-4bba-8b55-823347191a0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793868312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3793868312
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3100560006
Short name T611
Test name
Test status
Simulation time 794826471 ps
CPU time 18.1 seconds
Started Aug 06 05:29:04 PM PDT 24
Finished Aug 06 05:29:22 PM PDT 24
Peak memory 256184 kb
Host smart-40793f6a-c4ac-4a88-a77c-7228cf81046e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31005
60006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3100560006
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.352334654
Short name T606
Test name
Test status
Simulation time 1678917873 ps
CPU time 35.13 seconds
Started Aug 06 05:29:10 PM PDT 24
Finished Aug 06 05:29:45 PM PDT 24
Peak memory 255172 kb
Host smart-7b76e536-1f14-45ec-a3d5-5b430a4c7502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35233
4654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.352334654
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.565085992
Short name T338
Test name
Test status
Simulation time 76870763858 ps
CPU time 1475.72 seconds
Started Aug 06 05:29:09 PM PDT 24
Finished Aug 06 05:53:46 PM PDT 24
Peak memory 288872 kb
Host smart-d0b2c61a-162c-4104-849a-2f3e2e480403
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565085992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.565085992
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2505814885
Short name T370
Test name
Test status
Simulation time 42127947822 ps
CPU time 1301.33 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 05:50:47 PM PDT 24
Peak memory 286960 kb
Host smart-282d032f-73c0-4569-aba0-c17fd095d115
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505814885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2505814885
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2998161542
Short name T599
Test name
Test status
Simulation time 24373334415 ps
CPU time 539.95 seconds
Started Aug 06 05:29:05 PM PDT 24
Finished Aug 06 05:38:05 PM PDT 24
Peak memory 248540 kb
Host smart-e592e3ae-7964-4d68-918b-ab63e06e708e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998161542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2998161542
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1124123500
Short name T373
Test name
Test status
Simulation time 615243037 ps
CPU time 15.89 seconds
Started Aug 06 05:29:04 PM PDT 24
Finished Aug 06 05:29:20 PM PDT 24
Peak memory 255964 kb
Host smart-fc57f8e7-45db-41ab-a6c9-0118dad2701c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11241
23500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1124123500
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2271261913
Short name T357
Test name
Test status
Simulation time 8088769290 ps
CPU time 36.86 seconds
Started Aug 06 05:29:03 PM PDT 24
Finished Aug 06 05:29:40 PM PDT 24
Peak memory 248320 kb
Host smart-a77b9472-ae84-490b-90e6-81cb208c0fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22712
61913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2271261913
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.18267560
Short name T412
Test name
Test status
Simulation time 3809628797 ps
CPU time 59.57 seconds
Started Aug 06 05:29:08 PM PDT 24
Finished Aug 06 05:30:07 PM PDT 24
Peak memory 256772 kb
Host smart-58075e79-442b-431c-98dc-6433ac87a174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18267
560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.18267560
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3105600232
Short name T548
Test name
Test status
Simulation time 29217612648 ps
CPU time 1617.82 seconds
Started Aug 06 05:29:07 PM PDT 24
Finished Aug 06 05:56:05 PM PDT 24
Peak memory 272656 kb
Host smart-cd0ace7f-613d-4131-9a47-3f4cbae6cf7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105600232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3105600232
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3943170378
Short name T609
Test name
Test status
Simulation time 3403655077 ps
CPU time 155.74 seconds
Started Aug 06 05:29:07 PM PDT 24
Finished Aug 06 05:31:43 PM PDT 24
Peak memory 251756 kb
Host smart-ca776ec6-8489-460e-9a76-4a86cf0c5fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39431
70378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3943170378
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.734455684
Short name T645
Test name
Test status
Simulation time 101519235 ps
CPU time 4.59 seconds
Started Aug 06 05:29:07 PM PDT 24
Finished Aug 06 05:29:12 PM PDT 24
Peak memory 240172 kb
Host smart-23c2e71a-c190-4d35-9e66-a7e9532f1ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73445
5684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.734455684
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1138658953
Short name T177
Test name
Test status
Simulation time 58706838988 ps
CPU time 1333.03 seconds
Started Aug 06 05:29:12 PM PDT 24
Finished Aug 06 05:51:26 PM PDT 24
Peak memory 281124 kb
Host smart-24559c2d-0cbe-44c8-869b-fd7639ef0255
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138658953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1138658953
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.638303045
Short name T280
Test name
Test status
Simulation time 33901136517 ps
CPU time 2429.73 seconds
Started Aug 06 05:29:10 PM PDT 24
Finished Aug 06 06:09:40 PM PDT 24
Peak memory 288520 kb
Host smart-d172150f-7d9e-45e6-902b-a91b30cfd43f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638303045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.638303045
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.4161196628
Short name T319
Test name
Test status
Simulation time 8998243133 ps
CPU time 99.34 seconds
Started Aug 06 05:29:11 PM PDT 24
Finished Aug 06 05:30:50 PM PDT 24
Peak memory 248416 kb
Host smart-83fe5e57-90a0-4ea5-97ff-af79d2dbfe64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161196628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.4161196628
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1873922823
Short name T646
Test name
Test status
Simulation time 1537470205 ps
CPU time 29.7 seconds
Started Aug 06 05:29:07 PM PDT 24
Finished Aug 06 05:29:36 PM PDT 24
Peak memory 255680 kb
Host smart-bf87a054-af00-457b-bf34-fdddeb3c8f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18739
22823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1873922823
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3493003268
Short name T270
Test name
Test status
Simulation time 784337570 ps
CPU time 59.48 seconds
Started Aug 06 05:29:10 PM PDT 24
Finished Aug 06 05:30:10 PM PDT 24
Peak memory 248380 kb
Host smart-9301d4a2-1fc8-431f-bebd-c2b6cb1e11aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34930
03268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3493003268
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3906489720
Short name T594
Test name
Test status
Simulation time 841436152 ps
CPU time 14.68 seconds
Started Aug 06 05:29:07 PM PDT 24
Finished Aug 06 05:29:22 PM PDT 24
Peak memory 253684 kb
Host smart-12f84c94-184b-4601-83d7-a0f54a97f989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39064
89720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3906489720
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.101975216
Short name T253
Test name
Test status
Simulation time 19684240784 ps
CPU time 1765.94 seconds
Started Aug 06 05:29:11 PM PDT 24
Finished Aug 06 05:58:37 PM PDT 24
Peak memory 303604 kb
Host smart-366866cd-b048-4c77-8e38-577153c13337
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101975216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.101975216
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.1546921421
Short name T170
Test name
Test status
Simulation time 438753954121 ps
CPU time 4033.37 seconds
Started Aug 06 05:29:13 PM PDT 24
Finished Aug 06 06:36:27 PM PDT 24
Peak memory 313772 kb
Host smart-e911f346-cdc1-455e-bf2e-e46e009d2c81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546921421 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.1546921421
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1145650945
Short name T647
Test name
Test status
Simulation time 37558839899 ps
CPU time 1291.72 seconds
Started Aug 06 05:29:09 PM PDT 24
Finished Aug 06 05:50:41 PM PDT 24
Peak memory 273052 kb
Host smart-e4fe1e20-8d19-4111-99d5-068f9dd9b58c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145650945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1145650945
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3427780452
Short name T563
Test name
Test status
Simulation time 1085603427 ps
CPU time 78.86 seconds
Started Aug 06 05:29:10 PM PDT 24
Finished Aug 06 05:30:29 PM PDT 24
Peak memory 255960 kb
Host smart-6bf4e6ed-c7c7-4243-81f6-cf6cf3facd87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34277
80452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3427780452
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1881121340
Short name T419
Test name
Test status
Simulation time 3299047329 ps
CPU time 32.66 seconds
Started Aug 06 05:29:13 PM PDT 24
Finished Aug 06 05:29:45 PM PDT 24
Peak memory 256116 kb
Host smart-a86e1f33-d38a-422a-bec5-690f3b540e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18811
21340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1881121340
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1017235282
Short name T345
Test name
Test status
Simulation time 28140445939 ps
CPU time 1575.11 seconds
Started Aug 06 05:29:14 PM PDT 24
Finished Aug 06 05:55:29 PM PDT 24
Peak memory 283448 kb
Host smart-78cfa280-0c09-459c-a62b-4f59aa68bccd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017235282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1017235282
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2657805000
Short name T17
Test name
Test status
Simulation time 7283019544 ps
CPU time 742.78 seconds
Started Aug 06 05:29:18 PM PDT 24
Finished Aug 06 05:41:41 PM PDT 24
Peak memory 272284 kb
Host smart-c8a552f2-0f11-4f8d-800a-94b15cf6ff2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657805000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2657805000
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1366919238
Short name T306
Test name
Test status
Simulation time 26464521894 ps
CPU time 272.66 seconds
Started Aug 06 05:29:09 PM PDT 24
Finished Aug 06 05:33:42 PM PDT 24
Peak memory 247476 kb
Host smart-279251b8-864b-4748-bf0c-5daaeeb4b045
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366919238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1366919238
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2695871826
Short name T371
Test name
Test status
Simulation time 84379401 ps
CPU time 7.21 seconds
Started Aug 06 05:29:10 PM PDT 24
Finished Aug 06 05:29:18 PM PDT 24
Peak memory 248460 kb
Host smart-9d236902-17b0-4365-a23f-fe2efbf39ced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26958
71826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2695871826
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2069916390
Short name T464
Test name
Test status
Simulation time 605395151 ps
CPU time 19.64 seconds
Started Aug 06 05:29:09 PM PDT 24
Finished Aug 06 05:29:29 PM PDT 24
Peak memory 248020 kb
Host smart-f2aaab56-e90b-431b-966c-f092bd2b18f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20699
16390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2069916390
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3642112100
Short name T656
Test name
Test status
Simulation time 624674566 ps
CPU time 19.03 seconds
Started Aug 06 05:29:14 PM PDT 24
Finished Aug 06 05:29:33 PM PDT 24
Peak memory 255648 kb
Host smart-f6c61de8-d9ac-4a93-8bb3-2d191ca8f6b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36421
12100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3642112100
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1944737061
Short name T379
Test name
Test status
Simulation time 17117002 ps
CPU time 2.9 seconds
Started Aug 06 05:29:10 PM PDT 24
Finished Aug 06 05:29:13 PM PDT 24
Peak memory 250448 kb
Host smart-4fa28ed3-caad-4af8-896a-e7ec5a76dcac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19447
37061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1944737061
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3421290239
Short name T83
Test name
Test status
Simulation time 39476492884 ps
CPU time 1192.38 seconds
Started Aug 06 05:29:14 PM PDT 24
Finished Aug 06 05:49:07 PM PDT 24
Peak memory 287720 kb
Host smart-17eaeb70-5638-49a2-af40-6ea47b6e95fd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421290239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3421290239
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2187434660
Short name T43
Test name
Test status
Simulation time 29790058297 ps
CPU time 1007.85 seconds
Started Aug 06 05:29:24 PM PDT 24
Finished Aug 06 05:46:13 PM PDT 24
Peak memory 289208 kb
Host smart-a4add5a3-9174-4289-9a66-b70c514108bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187434660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2187434660
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2476880471
Short name T502
Test name
Test status
Simulation time 18020821317 ps
CPU time 270.39 seconds
Started Aug 06 05:29:18 PM PDT 24
Finished Aug 06 05:33:49 PM PDT 24
Peak memory 256140 kb
Host smart-b642ac06-2807-4e7b-a4e4-04959491b8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24768
80471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2476880471
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.768009206
Short name T112
Test name
Test status
Simulation time 711228182 ps
CPU time 16.26 seconds
Started Aug 06 05:29:19 PM PDT 24
Finished Aug 06 05:29:36 PM PDT 24
Peak memory 255288 kb
Host smart-b4c73ad2-065d-4f75-ac6c-bb5208266a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76800
9206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.768009206
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.747337508
Short name T553
Test name
Test status
Simulation time 35350620193 ps
CPU time 1440.09 seconds
Started Aug 06 05:29:25 PM PDT 24
Finished Aug 06 05:53:25 PM PDT 24
Peak memory 289536 kb
Host smart-f052006c-a42a-4854-9738-67d6b94e4f37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747337508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.747337508
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2593509282
Short name T361
Test name
Test status
Simulation time 21522600169 ps
CPU time 729.63 seconds
Started Aug 06 05:29:19 PM PDT 24
Finished Aug 06 05:41:28 PM PDT 24
Peak memory 272988 kb
Host smart-14c0d644-c413-49b9-abd8-84b72f09605d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593509282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2593509282
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.4188852157
Short name T323
Test name
Test status
Simulation time 10554836351 ps
CPU time 443.13 seconds
Started Aug 06 05:29:17 PM PDT 24
Finished Aug 06 05:36:41 PM PDT 24
Peak memory 248392 kb
Host smart-d7e6ec7c-16e8-4b03-8204-8cce4215adfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188852157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.4188852157
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3093435779
Short name T450
Test name
Test status
Simulation time 323319243 ps
CPU time 40.83 seconds
Started Aug 06 05:29:20 PM PDT 24
Finished Aug 06 05:30:01 PM PDT 24
Peak memory 247728 kb
Host smart-97c597bb-df54-4cfe-845b-2dc88b21496a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30934
35779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3093435779
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.367780947
Short name T22
Test name
Test status
Simulation time 693568038 ps
CPU time 20.74 seconds
Started Aug 06 05:29:26 PM PDT 24
Finished Aug 06 05:29:47 PM PDT 24
Peak memory 255688 kb
Host smart-2de343c2-eaf2-4211-aa6d-58f008733aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36778
0947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.367780947
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.594482814
Short name T544
Test name
Test status
Simulation time 4753488954 ps
CPU time 69.13 seconds
Started Aug 06 05:29:18 PM PDT 24
Finished Aug 06 05:30:27 PM PDT 24
Peak memory 255752 kb
Host smart-22bbbb8c-e537-436e-a9fb-3aaaeb9f098b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59448
2814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.594482814
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.6285183
Short name T291
Test name
Test status
Simulation time 432061122785 ps
CPU time 3673.41 seconds
Started Aug 06 05:29:26 PM PDT 24
Finished Aug 06 06:30:40 PM PDT 24
Peak memory 298152 kb
Host smart-6f22a7ae-d57d-409e-93c4-8020653ac026
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6285183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handl
er_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handl
er_stress_all.6285183
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2393667624
Short name T666
Test name
Test status
Simulation time 58308990969 ps
CPU time 3061.29 seconds
Started Aug 06 05:29:25 PM PDT 24
Finished Aug 06 06:20:26 PM PDT 24
Peak memory 288988 kb
Host smart-b9c70093-d866-41f7-b993-7adf9b2266be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393667624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2393667624
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.871924991
Short name T694
Test name
Test status
Simulation time 9035663462 ps
CPU time 305.6 seconds
Started Aug 06 05:29:27 PM PDT 24
Finished Aug 06 05:34:33 PM PDT 24
Peak memory 251640 kb
Host smart-ab197752-be0d-461c-8f42-72ba504b42a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87192
4991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.871924991
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2014842911
Short name T113
Test name
Test status
Simulation time 429422147 ps
CPU time 31.26 seconds
Started Aug 06 05:29:25 PM PDT 24
Finished Aug 06 05:29:56 PM PDT 24
Peak memory 255356 kb
Host smart-e703485b-bec0-4142-ad0e-ae16f352d6cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20148
42911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2014842911
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3335438495
Short name T303
Test name
Test status
Simulation time 11745349459 ps
CPU time 1017.23 seconds
Started Aug 06 05:29:27 PM PDT 24
Finished Aug 06 05:46:24 PM PDT 24
Peak memory 273092 kb
Host smart-1c2691d5-c72b-4e05-8721-af053b40be77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335438495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3335438495
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2508240961
Short name T21
Test name
Test status
Simulation time 69076258142 ps
CPU time 1323.12 seconds
Started Aug 06 05:29:24 PM PDT 24
Finished Aug 06 05:51:27 PM PDT 24
Peak memory 288484 kb
Host smart-573f3408-1b38-4e34-a8e7-35407f34e384
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508240961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2508240961
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1502906874
Short name T311
Test name
Test status
Simulation time 75495871999 ps
CPU time 339.08 seconds
Started Aug 06 05:29:27 PM PDT 24
Finished Aug 06 05:35:06 PM PDT 24
Peak memory 248436 kb
Host smart-9c369e17-3fbd-4c99-800c-b861ed32d8bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502906874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1502906874
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1235765710
Short name T432
Test name
Test status
Simulation time 233429935 ps
CPU time 6.09 seconds
Started Aug 06 05:29:25 PM PDT 24
Finished Aug 06 05:29:31 PM PDT 24
Peak memory 248412 kb
Host smart-094956b8-e0a3-412b-a665-581c4fdec652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12357
65710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1235765710
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1136207802
Short name T520
Test name
Test status
Simulation time 309491584 ps
CPU time 26.5 seconds
Started Aug 06 05:29:26 PM PDT 24
Finished Aug 06 05:29:53 PM PDT 24
Peak memory 256140 kb
Host smart-c8c6a03a-bb34-44d0-a091-28e288b01b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11362
07802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1136207802
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1116721853
Short name T622
Test name
Test status
Simulation time 455177513 ps
CPU time 27.43 seconds
Started Aug 06 05:29:25 PM PDT 24
Finished Aug 06 05:29:53 PM PDT 24
Peak memory 256212 kb
Host smart-a2870b9a-7081-4a7f-b568-7d95bceb2f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11167
21853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1116721853
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.238579991
Short name T284
Test name
Test status
Simulation time 152845640391 ps
CPU time 2392.53 seconds
Started Aug 06 05:29:25 PM PDT 24
Finished Aug 06 06:09:18 PM PDT 24
Peak memory 289260 kb
Host smart-08db8e7f-232f-43ac-b01c-7ef1c0b93a4a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238579991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.238579991
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3441995820
Short name T545
Test name
Test status
Simulation time 52122106085 ps
CPU time 2239.24 seconds
Started Aug 06 05:29:26 PM PDT 24
Finished Aug 06 06:06:46 PM PDT 24
Peak memory 288708 kb
Host smart-30f57a8a-5ff8-4424-ad2a-fd56293f329b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441995820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3441995820
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2078953812
Short name T675
Test name
Test status
Simulation time 1597622432 ps
CPU time 191.33 seconds
Started Aug 06 05:29:23 PM PDT 24
Finished Aug 06 05:32:34 PM PDT 24
Peak memory 255688 kb
Host smart-90d4abbf-e7cc-47a1-975f-70d6c9108653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20789
53812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2078953812
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1567121276
Short name T384
Test name
Test status
Simulation time 228697820 ps
CPU time 13.27 seconds
Started Aug 06 05:29:19 PM PDT 24
Finished Aug 06 05:29:32 PM PDT 24
Peak memory 255736 kb
Host smart-26e5202e-825f-4a16-81ed-20c0224d54d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15671
21276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1567121276
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1162461550
Short name T612
Test name
Test status
Simulation time 78665362844 ps
CPU time 1620.11 seconds
Started Aug 06 05:29:20 PM PDT 24
Finished Aug 06 05:56:20 PM PDT 24
Peak memory 273080 kb
Host smart-47ec02bf-5589-419c-ac71-541c3c6be340
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162461550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1162461550
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3323012811
Short name T314
Test name
Test status
Simulation time 24468239506 ps
CPU time 469.13 seconds
Started Aug 06 05:29:27 PM PDT 24
Finished Aug 06 05:37:16 PM PDT 24
Peak memory 248584 kb
Host smart-72d6ff31-f8f4-48e1-a5fd-c661682bab34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323012811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3323012811
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3926991533
Short name T551
Test name
Test status
Simulation time 1608708003 ps
CPU time 38.44 seconds
Started Aug 06 05:29:21 PM PDT 24
Finished Aug 06 05:29:59 PM PDT 24
Peak memory 255696 kb
Host smart-13591309-89e8-4b66-aa17-0103e9a36df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39269
91533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3926991533
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2452636160
Short name T292
Test name
Test status
Simulation time 1677563375 ps
CPU time 53.26 seconds
Started Aug 06 05:29:26 PM PDT 24
Finished Aug 06 05:30:19 PM PDT 24
Peak memory 256120 kb
Host smart-4a1aae1d-afcc-44a2-9acb-1a111a0e6310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24526
36160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2452636160
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3529669670
Short name T75
Test name
Test status
Simulation time 3260935962 ps
CPU time 52.83 seconds
Started Aug 06 05:29:26 PM PDT 24
Finished Aug 06 05:30:19 PM PDT 24
Peak memory 256008 kb
Host smart-44fd387b-7585-4565-91c7-40b5f0fc3125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35296
69670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3529669670
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1618047857
Short name T2
Test name
Test status
Simulation time 1152353307 ps
CPU time 23.33 seconds
Started Aug 06 05:29:27 PM PDT 24
Finished Aug 06 05:29:50 PM PDT 24
Peak memory 255816 kb
Host smart-37d48089-d7ce-4298-af46-79b5911db86d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16180
47857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1618047857
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2283784637
Short name T472
Test name
Test status
Simulation time 120976363 ps
CPU time 14.28 seconds
Started Aug 06 05:29:29 PM PDT 24
Finished Aug 06 05:29:43 PM PDT 24
Peak memory 248496 kb
Host smart-0cf5b46b-c9db-4232-acb4-fb863c415db6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283784637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2283784637
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3639668294
Short name T207
Test name
Test status
Simulation time 37986404 ps
CPU time 3.92 seconds
Started Aug 06 05:28:14 PM PDT 24
Finished Aug 06 05:28:18 PM PDT 24
Peak memory 248604 kb
Host smart-c2861f7c-d914-4efc-95fb-865836160b45
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3639668294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3639668294
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.939200066
Short name T661
Test name
Test status
Simulation time 36132700728 ps
CPU time 2243.88 seconds
Started Aug 06 05:28:05 PM PDT 24
Finished Aug 06 06:05:29 PM PDT 24
Peak memory 286380 kb
Host smart-8a4c2e71-8665-4dcc-b988-9f2a41caf2d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939200066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.939200066
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1950435917
Short name T1
Test name
Test status
Simulation time 158715247 ps
CPU time 9.22 seconds
Started Aug 06 05:28:13 PM PDT 24
Finished Aug 06 05:28:23 PM PDT 24
Peak memory 248428 kb
Host smart-beb89054-8573-4b0d-9ce4-c139d97fda4a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1950435917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1950435917
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1755661270
Short name T108
Test name
Test status
Simulation time 2020915568 ps
CPU time 121.33 seconds
Started Aug 06 05:28:14 PM PDT 24
Finished Aug 06 05:30:16 PM PDT 24
Peak memory 256168 kb
Host smart-decc7f38-18dc-4a2b-9bb1-22d98cab95b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17556
61270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1755661270
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1293767690
Short name T517
Test name
Test status
Simulation time 2291152398 ps
CPU time 34.62 seconds
Started Aug 06 05:28:14 PM PDT 24
Finished Aug 06 05:28:48 PM PDT 24
Peak memory 256620 kb
Host smart-f0767873-3b40-44ab-8e62-57bdb0384bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12937
67690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1293767690
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.367739653
Short name T638
Test name
Test status
Simulation time 69655610672 ps
CPU time 1531.92 seconds
Started Aug 06 05:28:07 PM PDT 24
Finished Aug 06 05:53:39 PM PDT 24
Peak memory 273164 kb
Host smart-674917a2-e9b8-4a5b-a8eb-1b6486663a58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367739653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.367739653
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2191693566
Short name T560
Test name
Test status
Simulation time 244222409886 ps
CPU time 2100.35 seconds
Started Aug 06 05:28:12 PM PDT 24
Finished Aug 06 06:03:13 PM PDT 24
Peak memory 281384 kb
Host smart-edbe879d-9603-4bf3-b560-3fe73d4ff36b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191693566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2191693566
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2350213936
Short name T663
Test name
Test status
Simulation time 205392411923 ps
CPU time 493.72 seconds
Started Aug 06 05:28:13 PM PDT 24
Finished Aug 06 05:36:27 PM PDT 24
Peak memory 248536 kb
Host smart-3b8c7444-0093-4c3c-8289-278478a82943
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350213936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2350213936
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1951217227
Short name T679
Test name
Test status
Simulation time 266229671 ps
CPU time 19.59 seconds
Started Aug 06 05:28:03 PM PDT 24
Finished Aug 06 05:28:23 PM PDT 24
Peak memory 248464 kb
Host smart-9862c24e-66a5-4378-a233-75f908bce3cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19512
17227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1951217227
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1153843035
Short name T369
Test name
Test status
Simulation time 2230567900 ps
CPU time 37.13 seconds
Started Aug 06 05:28:30 PM PDT 24
Finished Aug 06 05:29:07 PM PDT 24
Peak memory 255864 kb
Host smart-b167c05c-fca7-404a-9aab-b400959c7ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11538
43035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1153843035
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3971587609
Short name T33
Test name
Test status
Simulation time 915785535 ps
CPU time 13.12 seconds
Started Aug 06 05:28:08 PM PDT 24
Finished Aug 06 05:28:21 PM PDT 24
Peak memory 270552 kb
Host smart-4a1f553d-1c7e-4ba0-b147-daedc24c8143
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3971587609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3971587609
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3175744663
Short name T652
Test name
Test status
Simulation time 996083899 ps
CPU time 17.25 seconds
Started Aug 06 05:28:13 PM PDT 24
Finished Aug 06 05:28:30 PM PDT 24
Peak memory 255388 kb
Host smart-a33fff01-7bcd-4487-9663-518a182d2d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31757
44663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3175744663
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1356294756
Short name T621
Test name
Test status
Simulation time 1030352894 ps
CPU time 57.89 seconds
Started Aug 06 05:28:06 PM PDT 24
Finished Aug 06 05:29:04 PM PDT 24
Peak memory 255968 kb
Host smart-4c8e8120-1616-4478-b777-4be6fc8a9071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13562
94756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1356294756
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.319829406
Short name T295
Test name
Test status
Simulation time 88175257980 ps
CPU time 2686.69 seconds
Started Aug 06 05:28:14 PM PDT 24
Finished Aug 06 06:13:01 PM PDT 24
Peak memory 289492 kb
Host smart-0bd6838f-9f16-48a7-af26-bf47ca28f7ed
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319829406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.319829406
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.1176546666
Short name T263
Test name
Test status
Simulation time 14370197688 ps
CPU time 949.15 seconds
Started Aug 06 05:28:15 PM PDT 24
Finished Aug 06 05:44:04 PM PDT 24
Peak memory 271356 kb
Host smart-790c4419-4abb-4a8c-8116-6255ee6e4aad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176546666 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.1176546666
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1209194739
Short name T35
Test name
Test status
Simulation time 6759153802 ps
CPU time 20.28 seconds
Started Aug 06 05:29:24 PM PDT 24
Finished Aug 06 05:29:45 PM PDT 24
Peak memory 255784 kb
Host smart-724fc2be-f1d7-42e2-9cfa-ab15b95964de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12091
94739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1209194739
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3524274805
Short name T457
Test name
Test status
Simulation time 330109427 ps
CPU time 17.97 seconds
Started Aug 06 05:30:15 PM PDT 24
Finished Aug 06 05:30:34 PM PDT 24
Peak memory 256624 kb
Host smart-43f15f18-bc4a-44ec-932d-7186056f0bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35242
74805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3524274805
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2806486548
Short name T6
Test name
Test status
Simulation time 6174574148 ps
CPU time 702.14 seconds
Started Aug 06 05:29:29 PM PDT 24
Finished Aug 06 05:41:11 PM PDT 24
Peak memory 272440 kb
Host smart-6f1a95ee-f4c8-490d-8e4b-0bc89409fc0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806486548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2806486548
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2258552272
Short name T95
Test name
Test status
Simulation time 35689229879 ps
CPU time 2621.68 seconds
Started Aug 06 05:29:24 PM PDT 24
Finished Aug 06 06:13:06 PM PDT 24
Peak memory 289120 kb
Host smart-8659e5f3-a98f-41bd-837e-7f586a7d97d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258552272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2258552272
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.4039948464
Short name T332
Test name
Test status
Simulation time 49095128264 ps
CPU time 490.98 seconds
Started Aug 06 05:29:26 PM PDT 24
Finished Aug 06 05:37:37 PM PDT 24
Peak memory 248352 kb
Host smart-85b17d77-4ba1-40c0-a474-4b56a87261f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039948464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.4039948464
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1808093006
Short name T440
Test name
Test status
Simulation time 190357178 ps
CPU time 19.53 seconds
Started Aug 06 05:29:29 PM PDT 24
Finished Aug 06 05:29:48 PM PDT 24
Peak memory 255972 kb
Host smart-22798059-1371-444a-834a-0313ce35c95f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18080
93006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1808093006
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3756499962
Short name T358
Test name
Test status
Simulation time 91595318 ps
CPU time 8.74 seconds
Started Aug 06 05:29:29 PM PDT 24
Finished Aug 06 05:29:38 PM PDT 24
Peak memory 252028 kb
Host smart-337b787c-dddd-4ba3-aba1-97cb3e77351b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37564
99962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3756499962
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.126906728
Short name T402
Test name
Test status
Simulation time 172411470 ps
CPU time 20.17 seconds
Started Aug 06 05:29:28 PM PDT 24
Finished Aug 06 05:29:48 PM PDT 24
Peak memory 248428 kb
Host smart-ec30efdb-209f-4faa-98ac-1807432e94d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12690
6728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.126906728
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3832502389
Short name T36
Test name
Test status
Simulation time 2078570791 ps
CPU time 10.92 seconds
Started Aug 06 05:29:26 PM PDT 24
Finished Aug 06 05:29:37 PM PDT 24
Peak memory 248412 kb
Host smart-85f810e2-7526-410c-9b88-722f03bfc6b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38325
02389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3832502389
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2535816492
Short name T274
Test name
Test status
Simulation time 224682261335 ps
CPU time 3171.55 seconds
Started Aug 06 05:29:21 PM PDT 24
Finished Aug 06 06:22:13 PM PDT 24
Peak memory 287772 kb
Host smart-c35a2a86-f7bc-47fc-8602-edd2f8d0a3f7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535816492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2535816492
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1036484132
Short name T648
Test name
Test status
Simulation time 188800481719 ps
CPU time 2378.35 seconds
Started Aug 06 05:29:19 PM PDT 24
Finished Aug 06 06:08:57 PM PDT 24
Peak memory 288428 kb
Host smart-3cd02240-d1e1-4e56-ba4c-a607d3789587
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036484132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1036484132
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3356964472
Short name T56
Test name
Test status
Simulation time 1292315623 ps
CPU time 64.67 seconds
Started Aug 06 05:29:25 PM PDT 24
Finished Aug 06 05:30:29 PM PDT 24
Peak memory 249436 kb
Host smart-ddad89de-f070-4299-9fec-4745fb426a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33569
64472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3356964472
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2503488366
Short name T428
Test name
Test status
Simulation time 777923850 ps
CPU time 43.85 seconds
Started Aug 06 05:29:20 PM PDT 24
Finished Aug 06 05:30:03 PM PDT 24
Peak memory 248424 kb
Host smart-6931bb65-c841-4a68-98c0-a1b958967317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25034
88366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2503488366
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2010204874
Short name T218
Test name
Test status
Simulation time 56609071281 ps
CPU time 1197.66 seconds
Started Aug 06 05:29:19 PM PDT 24
Finished Aug 06 05:49:17 PM PDT 24
Peak memory 288508 kb
Host smart-d7e248fb-d1c7-49cf-af02-f1051481e590
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010204874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2010204874
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2250411568
Short name T635
Test name
Test status
Simulation time 6602883887 ps
CPU time 102.37 seconds
Started Aug 06 05:29:20 PM PDT 24
Finished Aug 06 05:31:02 PM PDT 24
Peak memory 248580 kb
Host smart-50dfd45a-9969-4c3c-aab0-21467ca9d571
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250411568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2250411568
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.66896548
Short name T633
Test name
Test status
Simulation time 191331641 ps
CPU time 4.88 seconds
Started Aug 06 05:29:25 PM PDT 24
Finished Aug 06 05:29:30 PM PDT 24
Peak memory 240176 kb
Host smart-8ee4a6d8-6251-4e64-87fa-2420c554d048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66896
548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.66896548
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1432544407
Short name T300
Test name
Test status
Simulation time 172211320 ps
CPU time 11.55 seconds
Started Aug 06 05:29:25 PM PDT 24
Finished Aug 06 05:29:36 PM PDT 24
Peak memory 254064 kb
Host smart-b60e8081-162f-4e4d-8672-597eac7bdbab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14325
44407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1432544407
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.751280064
Short name T627
Test name
Test status
Simulation time 48412291 ps
CPU time 7.72 seconds
Started Aug 06 05:29:20 PM PDT 24
Finished Aug 06 05:29:27 PM PDT 24
Peak memory 252524 kb
Host smart-12016306-3159-4231-9c7a-26eb3e412f5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75128
0064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.751280064
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.631229121
Short name T391
Test name
Test status
Simulation time 3572970109 ps
CPU time 47.96 seconds
Started Aug 06 05:29:21 PM PDT 24
Finished Aug 06 05:30:09 PM PDT 24
Peak memory 254696 kb
Host smart-153726b0-3b13-44c5-90e7-e09d23e34c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63122
9121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.631229121
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2597553065
Short name T592
Test name
Test status
Simulation time 18577833572 ps
CPU time 1918.1 seconds
Started Aug 06 05:29:25 PM PDT 24
Finished Aug 06 06:01:23 PM PDT 24
Peak memory 305104 kb
Host smart-dd37e3b7-23eb-490c-b17c-963eae0f8408
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597553065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2597553065
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.648806919
Short name T87
Test name
Test status
Simulation time 231000217700 ps
CPU time 4097.32 seconds
Started Aug 06 05:29:26 PM PDT 24
Finished Aug 06 06:37:44 PM PDT 24
Peak memory 303820 kb
Host smart-44bcb03e-a52a-4578-a047-9aad805551bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648806919 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.648806919
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.732579401
Short name T42
Test name
Test status
Simulation time 81703184350 ps
CPU time 1206.15 seconds
Started Aug 06 05:29:39 PM PDT 24
Finished Aug 06 05:49:45 PM PDT 24
Peak memory 272976 kb
Host smart-9c07a2df-d924-4839-8fce-2d7fd438629f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732579401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.732579401
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.573444562
Short name T690
Test name
Test status
Simulation time 190505233 ps
CPU time 14.47 seconds
Started Aug 06 05:29:34 PM PDT 24
Finished Aug 06 05:29:49 PM PDT 24
Peak memory 254072 kb
Host smart-cf944c69-de6a-44a7-ac45-398f9b179d4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57344
4562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.573444562
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2906876423
Short name T604
Test name
Test status
Simulation time 5497510361 ps
CPU time 43.12 seconds
Started Aug 06 05:29:36 PM PDT 24
Finished Aug 06 05:30:19 PM PDT 24
Peak memory 255100 kb
Host smart-67d44c20-9296-48b6-85ed-66e4c2ae1d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29068
76423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2906876423
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3959617853
Short name T602
Test name
Test status
Simulation time 38213483218 ps
CPU time 2160.21 seconds
Started Aug 06 05:29:37 PM PDT 24
Finished Aug 06 06:05:37 PM PDT 24
Peak memory 273032 kb
Host smart-80402a94-9878-47bd-ae83-a40a69b60aec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959617853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3959617853
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.4262155844
Short name T231
Test name
Test status
Simulation time 25255284450 ps
CPU time 1161.46 seconds
Started Aug 06 05:29:39 PM PDT 24
Finished Aug 06 05:49:01 PM PDT 24
Peak memory 289080 kb
Host smart-afaffbf0-6184-4563-84a0-ed74bc93513b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262155844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.4262155844
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1174205567
Short name T620
Test name
Test status
Simulation time 19708019167 ps
CPU time 400.42 seconds
Started Aug 06 05:29:37 PM PDT 24
Finished Aug 06 05:36:17 PM PDT 24
Peak memory 256320 kb
Host smart-961a791d-03c4-47e2-bfb5-3daad9fb4851
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174205567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1174205567
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.763517572
Short name T639
Test name
Test status
Simulation time 1064552318 ps
CPU time 22.2 seconds
Started Aug 06 05:29:36 PM PDT 24
Finished Aug 06 05:29:58 PM PDT 24
Peak memory 248432 kb
Host smart-7d03467c-daad-4d52-85bd-c07e4795c09e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76351
7572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.763517572
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1813607029
Short name T228
Test name
Test status
Simulation time 1449130596 ps
CPU time 55.76 seconds
Started Aug 06 05:29:37 PM PDT 24
Finished Aug 06 05:30:32 PM PDT 24
Peak memory 256076 kb
Host smart-8b499ac8-cc36-4030-a3f4-235320f104a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18136
07029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1813607029
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2039500652
Short name T363
Test name
Test status
Simulation time 740941321 ps
CPU time 37.92 seconds
Started Aug 06 05:29:27 PM PDT 24
Finished Aug 06 05:30:05 PM PDT 24
Peak memory 256236 kb
Host smart-2bc75e1f-2ec9-4ac8-bb73-93870efda94b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20395
00652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2039500652
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.81171849
Short name T25
Test name
Test status
Simulation time 19832928085 ps
CPU time 1961.7 seconds
Started Aug 06 05:29:38 PM PDT 24
Finished Aug 06 06:02:20 PM PDT 24
Peak memory 303772 kb
Host smart-9f400c12-938f-4639-a3a3-0898b95eec00
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81171849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_hand
ler_stress_all.81171849
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2172366359
Short name T193
Test name
Test status
Simulation time 80471306553 ps
CPU time 1252.85 seconds
Started Aug 06 05:29:35 PM PDT 24
Finished Aug 06 05:50:28 PM PDT 24
Peak memory 272620 kb
Host smart-bdba3a2c-7209-49f3-b6fa-3efe61517ed6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172366359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2172366359
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2782768168
Short name T530
Test name
Test status
Simulation time 4314115301 ps
CPU time 121.68 seconds
Started Aug 06 05:29:42 PM PDT 24
Finished Aug 06 05:31:44 PM PDT 24
Peak memory 255852 kb
Host smart-809c577c-695b-4e95-8267-fc6ca638128c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27827
68168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2782768168
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3024442816
Short name T585
Test name
Test status
Simulation time 1587996403 ps
CPU time 24.41 seconds
Started Aug 06 05:29:36 PM PDT 24
Finished Aug 06 05:30:01 PM PDT 24
Peak memory 248372 kb
Host smart-0c138fb7-98a7-485d-b21e-a8b61c8ee507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30244
42816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3024442816
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2191608969
Short name T340
Test name
Test status
Simulation time 120164315431 ps
CPU time 1782.94 seconds
Started Aug 06 05:29:35 PM PDT 24
Finished Aug 06 05:59:18 PM PDT 24
Peak memory 272388 kb
Host smart-6ff18a89-ec9b-4b7b-9c18-b5e06c835320
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191608969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2191608969
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.4021508710
Short name T630
Test name
Test status
Simulation time 20817048574 ps
CPU time 470.97 seconds
Started Aug 06 05:29:35 PM PDT 24
Finished Aug 06 05:37:26 PM PDT 24
Peak memory 248344 kb
Host smart-d55f74dc-f876-49a9-9563-4ff8b49164a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021508710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.4021508710
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2586782439
Short name T276
Test name
Test status
Simulation time 2886953561 ps
CPU time 46.61 seconds
Started Aug 06 05:29:35 PM PDT 24
Finished Aug 06 05:30:22 PM PDT 24
Peak memory 256428 kb
Host smart-66c820b6-7d0b-492b-9a17-76db0a9b858e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25867
82439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2586782439
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1310247162
Short name T542
Test name
Test status
Simulation time 3247882695 ps
CPU time 56.51 seconds
Started Aug 06 05:29:37 PM PDT 24
Finished Aug 06 05:30:34 PM PDT 24
Peak memory 248280 kb
Host smart-b0eb656a-db34-4cd8-93d4-35549124ccb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13102
47162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1310247162
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1390726454
Short name T251
Test name
Test status
Simulation time 715072623 ps
CPU time 42.28 seconds
Started Aug 06 05:29:41 PM PDT 24
Finished Aug 06 05:30:23 PM PDT 24
Peak memory 256028 kb
Host smart-e1dd1b32-d3d5-4ff8-8afc-0ddf15be31c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13907
26454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1390726454
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2161170859
Short name T441
Test name
Test status
Simulation time 2795067509 ps
CPU time 45.9 seconds
Started Aug 06 05:29:40 PM PDT 24
Finished Aug 06 05:30:26 PM PDT 24
Peak memory 256060 kb
Host smart-e7fc475b-6fcf-4b02-b495-25de712bfdfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21611
70859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2161170859
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1247231113
Short name T41
Test name
Test status
Simulation time 3547006722 ps
CPU time 175.43 seconds
Started Aug 06 05:29:40 PM PDT 24
Finished Aug 06 05:32:35 PM PDT 24
Peak memory 256756 kb
Host smart-dc103529-aeae-4529-8ff3-9a6a3728eb56
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247231113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1247231113
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3641231806
Short name T247
Test name
Test status
Simulation time 97716445301 ps
CPU time 6272 seconds
Started Aug 06 05:29:40 PM PDT 24
Finished Aug 06 07:14:13 PM PDT 24
Peak memory 355104 kb
Host smart-13e76427-5d8a-4dcf-a0ce-6519571d7508
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641231806 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3641231806
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.714007861
Short name T31
Test name
Test status
Simulation time 9296462554 ps
CPU time 810.45 seconds
Started Aug 06 05:29:36 PM PDT 24
Finished Aug 06 05:43:06 PM PDT 24
Peak memory 267012 kb
Host smart-dd370ef1-312c-4e82-880c-0041fbb9b187
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714007861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.714007861
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1211618988
Short name T519
Test name
Test status
Simulation time 26840153956 ps
CPU time 122.17 seconds
Started Aug 06 05:29:35 PM PDT 24
Finished Aug 06 05:31:38 PM PDT 24
Peak memory 256020 kb
Host smart-aa10a8c0-bf0d-4a16-aecb-abfdf63760b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12116
18988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1211618988
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1576958646
Short name T219
Test name
Test status
Simulation time 364179693 ps
CPU time 14.26 seconds
Started Aug 06 05:29:42 PM PDT 24
Finished Aug 06 05:29:57 PM PDT 24
Peak memory 247864 kb
Host smart-1c3fede5-bde0-4691-bc91-c7e1f60077da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15769
58646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1576958646
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2088192970
Short name T689
Test name
Test status
Simulation time 38425059226 ps
CPU time 2080.32 seconds
Started Aug 06 05:29:37 PM PDT 24
Finished Aug 06 06:04:17 PM PDT 24
Peak memory 272864 kb
Host smart-50442b76-cbec-44ab-97ae-e18e1b0fb806
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088192970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2088192970
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1331012238
Short name T236
Test name
Test status
Simulation time 32864506244 ps
CPU time 1230.16 seconds
Started Aug 06 05:29:35 PM PDT 24
Finished Aug 06 05:50:06 PM PDT 24
Peak memory 282228 kb
Host smart-d24b70b2-f918-47ee-903f-75691c0a85fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331012238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1331012238
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.232864306
Short name T308
Test name
Test status
Simulation time 16965779124 ps
CPU time 176.31 seconds
Started Aug 06 05:29:37 PM PDT 24
Finished Aug 06 05:32:33 PM PDT 24
Peak memory 248412 kb
Host smart-636db7f9-9934-4ae5-82e9-85d2be71e3fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232864306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.232864306
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.926207646
Short name T279
Test name
Test status
Simulation time 2288664529 ps
CPU time 38.35 seconds
Started Aug 06 05:29:36 PM PDT 24
Finished Aug 06 05:30:14 PM PDT 24
Peak memory 256508 kb
Host smart-6c6c3b50-8076-49ca-91f2-17d10c15ecb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92620
7646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.926207646
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3597116315
Short name T50
Test name
Test status
Simulation time 1798123783 ps
CPU time 40.95 seconds
Started Aug 06 05:29:36 PM PDT 24
Finished Aug 06 05:30:17 PM PDT 24
Peak memory 256168 kb
Host smart-619d9bb1-ea30-48db-89cf-01a09f41c527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35971
16315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3597116315
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.4064922086
Short name T600
Test name
Test status
Simulation time 461088347 ps
CPU time 30.88 seconds
Started Aug 06 05:29:36 PM PDT 24
Finished Aug 06 05:30:07 PM PDT 24
Peak memory 255604 kb
Host smart-7f07b820-42f5-480c-b099-4049d0558bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40649
22086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.4064922086
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.291677411
Short name T194
Test name
Test status
Simulation time 1060699625 ps
CPU time 65.91 seconds
Started Aug 06 05:29:35 PM PDT 24
Finished Aug 06 05:30:41 PM PDT 24
Peak memory 256628 kb
Host smart-29cca8b4-439d-4b18-a0dc-eed7f8bba599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29167
7411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.291677411
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2051145143
Short name T359
Test name
Test status
Simulation time 2520592108 ps
CPU time 119.75 seconds
Started Aug 06 05:29:43 PM PDT 24
Finished Aug 06 05:31:42 PM PDT 24
Peak memory 256772 kb
Host smart-be32dde5-0ae9-4bc2-b30f-ab2a4e683694
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051145143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2051145143
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1407558270
Short name T503
Test name
Test status
Simulation time 38914273298 ps
CPU time 1070.5 seconds
Started Aug 06 05:29:53 PM PDT 24
Finished Aug 06 05:47:43 PM PDT 24
Peak memory 271732 kb
Host smart-0fbee68f-8cc0-4795-9c8c-4d73c742b8bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407558270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1407558270
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1708363989
Short name T614
Test name
Test status
Simulation time 9550287615 ps
CPU time 159.4 seconds
Started Aug 06 05:29:55 PM PDT 24
Finished Aug 06 05:32:35 PM PDT 24
Peak memory 250580 kb
Host smart-68528ac1-ed08-48cb-94b4-b94b816070ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17083
63989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1708363989
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2134274364
Short name T475
Test name
Test status
Simulation time 206507523 ps
CPU time 19.99 seconds
Started Aug 06 05:29:57 PM PDT 24
Finished Aug 06 05:30:17 PM PDT 24
Peak memory 247836 kb
Host smart-7001b514-f513-4da3-909c-9ef81e9af84f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21342
74364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2134274364
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3976687625
Short name T608
Test name
Test status
Simulation time 81481274659 ps
CPU time 1302.08 seconds
Started Aug 06 05:29:57 PM PDT 24
Finished Aug 06 05:51:39 PM PDT 24
Peak memory 273056 kb
Host smart-50dc47cf-9571-4cec-b6b2-fb9f1488eb9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976687625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3976687625
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.4276103205
Short name T78
Test name
Test status
Simulation time 9285953378 ps
CPU time 862.67 seconds
Started Aug 06 05:29:51 PM PDT 24
Finished Aug 06 05:44:14 PM PDT 24
Peak memory 288772 kb
Host smart-58c76fe4-258e-4360-b196-b8ecca0348c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276103205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.4276103205
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.4188000169
Short name T232
Test name
Test status
Simulation time 299681736 ps
CPU time 24.91 seconds
Started Aug 06 05:29:57 PM PDT 24
Finished Aug 06 05:30:22 PM PDT 24
Peak memory 255764 kb
Host smart-f8692812-9e68-40fc-b035-d6934ce5b8eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41880
00169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.4188000169
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.933254978
Short name T92
Test name
Test status
Simulation time 79644830 ps
CPU time 6.51 seconds
Started Aug 06 05:29:48 PM PDT 24
Finished Aug 06 05:29:55 PM PDT 24
Peak memory 239664 kb
Host smart-a4966ea5-ab1e-4773-b670-4b18443d8475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93325
4978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.933254978
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2050068151
Short name T71
Test name
Test status
Simulation time 322436110 ps
CPU time 24.92 seconds
Started Aug 06 05:29:44 PM PDT 24
Finished Aug 06 05:30:09 PM PDT 24
Peak memory 247812 kb
Host smart-497dfebb-9091-458a-924a-e436637d0ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20500
68151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2050068151
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.4168315711
Short name T417
Test name
Test status
Simulation time 1401185767 ps
CPU time 38.02 seconds
Started Aug 06 05:29:44 PM PDT 24
Finished Aug 06 05:30:23 PM PDT 24
Peak memory 256592 kb
Host smart-679432ec-d880-422f-a9df-510fd5902717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41683
15711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.4168315711
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3419367026
Short name T272
Test name
Test status
Simulation time 9451012135 ps
CPU time 1045.99 seconds
Started Aug 06 05:29:45 PM PDT 24
Finished Aug 06 05:47:11 PM PDT 24
Peak memory 287680 kb
Host smart-4210f606-c17b-43bd-b0c1-83e8544e2ccc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419367026 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3419367026
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2231955995
Short name T88
Test name
Test status
Simulation time 31221075896 ps
CPU time 2376.69 seconds
Started Aug 06 05:30:03 PM PDT 24
Finished Aug 06 06:09:40 PM PDT 24
Peak memory 288648 kb
Host smart-4b25ce1e-6c50-4497-8911-0cb273c8d90b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231955995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2231955995
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1279341621
Short name T568
Test name
Test status
Simulation time 12733999574 ps
CPU time 197.72 seconds
Started Aug 06 05:29:45 PM PDT 24
Finished Aug 06 05:33:03 PM PDT 24
Peak memory 256312 kb
Host smart-1664dfc9-65b5-44af-982f-3d8da1983ad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12793
41621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1279341621
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2057463352
Short name T510
Test name
Test status
Simulation time 684952441 ps
CPU time 13.61 seconds
Started Aug 06 05:29:54 PM PDT 24
Finished Aug 06 05:30:07 PM PDT 24
Peak memory 248156 kb
Host smart-687c48eb-04be-4d86-9d90-e4c31fd125d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20574
63352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2057463352
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3514117538
Short name T556
Test name
Test status
Simulation time 126740450789 ps
CPU time 1639.46 seconds
Started Aug 06 05:29:43 PM PDT 24
Finished Aug 06 05:57:02 PM PDT 24
Peak memory 271816 kb
Host smart-90ca50dc-3dcc-47e6-be26-76507e75f22c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514117538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3514117538
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2710218506
Short name T448
Test name
Test status
Simulation time 64777290065 ps
CPU time 2063.31 seconds
Started Aug 06 05:29:53 PM PDT 24
Finished Aug 06 06:04:16 PM PDT 24
Peak memory 289024 kb
Host smart-5e8e66ef-e5eb-4b0c-93bd-2ff614fee150
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710218506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2710218506
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2486528567
Short name T492
Test name
Test status
Simulation time 841935092 ps
CPU time 34.33 seconds
Started Aug 06 05:29:48 PM PDT 24
Finished Aug 06 05:30:22 PM PDT 24
Peak memory 256048 kb
Host smart-1c34f5b2-5d45-47be-bced-873af24e0be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24865
28567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2486528567
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.268907044
Short name T504
Test name
Test status
Simulation time 6753915673 ps
CPU time 54.22 seconds
Started Aug 06 05:29:47 PM PDT 24
Finished Aug 06 05:30:41 PM PDT 24
Peak memory 248448 kb
Host smart-28ab9b2f-d618-4a2a-adfd-c49a585f1cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26890
7044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.268907044
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.770571993
Short name T459
Test name
Test status
Simulation time 938349403 ps
CPU time 21.73 seconds
Started Aug 06 05:29:52 PM PDT 24
Finished Aug 06 05:30:14 PM PDT 24
Peak memory 255948 kb
Host smart-22525aeb-99bd-470d-9fe5-cca31423d0e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77057
1993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.770571993
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1021292086
Short name T634
Test name
Test status
Simulation time 820580320 ps
CPU time 51.04 seconds
Started Aug 06 05:29:42 PM PDT 24
Finished Aug 06 05:30:33 PM PDT 24
Peak memory 256600 kb
Host smart-a7b9bafb-a0b1-44ee-9aa9-a6c09f64daed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10212
92086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1021292086
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.4256119318
Short name T590
Test name
Test status
Simulation time 20530448973 ps
CPU time 1769.76 seconds
Started Aug 06 05:29:44 PM PDT 24
Finished Aug 06 05:59:14 PM PDT 24
Peak memory 305852 kb
Host smart-a08f658c-e22b-48d6-9930-0c6641d01fa2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256119318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.4256119318
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2704593736
Short name T678
Test name
Test status
Simulation time 74030197037 ps
CPU time 1992.46 seconds
Started Aug 06 05:29:44 PM PDT 24
Finished Aug 06 06:02:56 PM PDT 24
Peak memory 273132 kb
Host smart-1aa83499-51f3-4cf8-bc2b-2b35fc63973c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704593736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2704593736
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1192111291
Short name T511
Test name
Test status
Simulation time 5537240379 ps
CPU time 85.89 seconds
Started Aug 06 05:29:52 PM PDT 24
Finished Aug 06 05:31:18 PM PDT 24
Peak memory 256308 kb
Host smart-84528584-e1c2-44d6-95dd-ac13d2b4bea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11921
11291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1192111291
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1833328368
Short name T73
Test name
Test status
Simulation time 4153333382 ps
CPU time 59.31 seconds
Started Aug 06 05:29:45 PM PDT 24
Finished Aug 06 05:30:44 PM PDT 24
Peak memory 256688 kb
Host smart-39b94234-62e7-48fa-9b23-87bc77a2f058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18333
28368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1833328368
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.732457175
Short name T336
Test name
Test status
Simulation time 48247408962 ps
CPU time 2423.33 seconds
Started Aug 06 05:29:56 PM PDT 24
Finished Aug 06 06:10:20 PM PDT 24
Peak memory 286992 kb
Host smart-78b10a08-729f-4c11-a726-1b18283f117f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732457175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.732457175
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2199395893
Short name T494
Test name
Test status
Simulation time 38166569043 ps
CPU time 962.29 seconds
Started Aug 06 05:30:09 PM PDT 24
Finished Aug 06 05:46:12 PM PDT 24
Peak memory 273172 kb
Host smart-3c010f1d-93f4-44aa-952f-7902b7e8ec47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199395893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2199395893
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2351529619
Short name T380
Test name
Test status
Simulation time 95642521 ps
CPU time 9.21 seconds
Started Aug 06 05:29:47 PM PDT 24
Finished Aug 06 05:29:56 PM PDT 24
Peak memory 248428 kb
Host smart-2c582a92-6d83-42d4-80a4-08c52fbf0289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23515
29619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2351529619
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2279082963
Short name T296
Test name
Test status
Simulation time 570655983 ps
CPU time 40.32 seconds
Started Aug 06 05:29:43 PM PDT 24
Finished Aug 06 05:30:24 PM PDT 24
Peak memory 255944 kb
Host smart-a5521a1c-75ef-42df-880e-2cbf361b64cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22790
82963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2279082963
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3724897183
Short name T416
Test name
Test status
Simulation time 97048387 ps
CPU time 8.58 seconds
Started Aug 06 05:29:44 PM PDT 24
Finished Aug 06 05:29:53 PM PDT 24
Peak memory 254212 kb
Host smart-c5f74765-6b0d-48ac-877b-4151264192c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37248
97183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3724897183
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2780565102
Short name T541
Test name
Test status
Simulation time 2604333415 ps
CPU time 29.18 seconds
Started Aug 06 05:29:44 PM PDT 24
Finished Aug 06 05:30:13 PM PDT 24
Peak memory 256432 kb
Host smart-a655f4cf-4d71-491e-862b-cb428f114297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27805
65102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2780565102
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3092263815
Short name T411
Test name
Test status
Simulation time 12980057150 ps
CPU time 1290.06 seconds
Started Aug 06 05:29:44 PM PDT 24
Finished Aug 06 05:51:14 PM PDT 24
Peak memory 289196 kb
Host smart-b98c37ca-ba15-48a8-8840-f00dd83e1e51
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092263815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3092263815
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.4145595808
Short name T171
Test name
Test status
Simulation time 58122781750 ps
CPU time 3126 seconds
Started Aug 06 05:29:53 PM PDT 24
Finished Aug 06 06:21:59 PM PDT 24
Peak memory 305924 kb
Host smart-912c87bb-7945-4426-a445-ce229f73ad1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145595808 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.4145595808
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2685963300
Short name T486
Test name
Test status
Simulation time 59222478568 ps
CPU time 1056.63 seconds
Started Aug 06 05:30:01 PM PDT 24
Finished Aug 06 05:47:38 PM PDT 24
Peak memory 271804 kb
Host smart-f9e1e53d-9a74-47cf-b345-3ed4f2bacb10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685963300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2685963300
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.4007878681
Short name T554
Test name
Test status
Simulation time 118139458 ps
CPU time 6.04 seconds
Started Aug 06 05:30:01 PM PDT 24
Finished Aug 06 05:30:07 PM PDT 24
Peak memory 250588 kb
Host smart-c324028f-850b-478b-aa22-ae0847af5c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40078
78681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.4007878681
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.462297995
Short name T436
Test name
Test status
Simulation time 761240330 ps
CPU time 50.47 seconds
Started Aug 06 05:30:14 PM PDT 24
Finished Aug 06 05:31:05 PM PDT 24
Peak memory 256524 kb
Host smart-0f7452c7-2eea-4b2e-81de-6671aaa200e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46229
7995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.462297995
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3222570842
Short name T339
Test name
Test status
Simulation time 80060860384 ps
CPU time 1240.34 seconds
Started Aug 06 05:30:04 PM PDT 24
Finished Aug 06 05:50:45 PM PDT 24
Peak memory 272884 kb
Host smart-9afe8c43-55dd-4a0f-bc1d-f3e458773b07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222570842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3222570842
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.4111434382
Short name T533
Test name
Test status
Simulation time 37260518947 ps
CPU time 758.89 seconds
Started Aug 06 05:30:00 PM PDT 24
Finished Aug 06 05:42:39 PM PDT 24
Peak memory 270996 kb
Host smart-9d3307d3-8e54-415d-b540-8dfc2a5d5672
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111434382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.4111434382
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2091772966
Short name T683
Test name
Test status
Simulation time 10110508178 ps
CPU time 196.59 seconds
Started Aug 06 05:30:14 PM PDT 24
Finished Aug 06 05:33:31 PM PDT 24
Peak memory 248444 kb
Host smart-fc52c5b5-2736-47c2-967e-18b385de2761
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091772966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2091772966
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2260229483
Short name T513
Test name
Test status
Simulation time 956376891 ps
CPU time 19.85 seconds
Started Aug 06 05:29:56 PM PDT 24
Finished Aug 06 05:30:16 PM PDT 24
Peak memory 248480 kb
Host smart-f1a4a95d-41bf-43ac-aa3c-2a26c24b37ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22602
29483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2260229483
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3448920372
Short name T387
Test name
Test status
Simulation time 134377079 ps
CPU time 8.36 seconds
Started Aug 06 05:30:01 PM PDT 24
Finished Aug 06 05:30:09 PM PDT 24
Peak memory 251492 kb
Host smart-7080b5fd-c2c1-4a35-9622-ed693670c6c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34489
20372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3448920372
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3129100079
Short name T589
Test name
Test status
Simulation time 2264251604 ps
CPU time 33.88 seconds
Started Aug 06 05:29:45 PM PDT 24
Finished Aug 06 05:30:19 PM PDT 24
Peak memory 248428 kb
Host smart-812b0f62-e52d-4901-a4d9-313d5461d038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31291
00079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3129100079
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3392164653
Short name T644
Test name
Test status
Simulation time 164474879117 ps
CPU time 2364.51 seconds
Started Aug 06 05:30:14 PM PDT 24
Finished Aug 06 06:09:39 PM PDT 24
Peak memory 285316 kb
Host smart-770dff77-99a7-41c1-921d-4c536b785d11
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392164653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3392164653
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2682325729
Short name T268
Test name
Test status
Simulation time 121610222710 ps
CPU time 3234.01 seconds
Started Aug 06 05:30:01 PM PDT 24
Finished Aug 06 06:23:56 PM PDT 24
Peak memory 331608 kb
Host smart-1e62bd21-17b3-4066-af9c-ceac991fec8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682325729 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2682325729
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1454353974
Short name T619
Test name
Test status
Simulation time 132697816776 ps
CPU time 1718.33 seconds
Started Aug 06 05:30:02 PM PDT 24
Finished Aug 06 05:58:41 PM PDT 24
Peak memory 289160 kb
Host smart-db40ef5e-8f10-42e9-95f8-dd197c247e7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454353974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1454353974
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2994397021
Short name T418
Test name
Test status
Simulation time 32994573818 ps
CPU time 221.29 seconds
Started Aug 06 05:30:01 PM PDT 24
Finished Aug 06 05:33:42 PM PDT 24
Peak memory 256344 kb
Host smart-40cb8345-47d9-4463-b09e-b6106172e8e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29943
97021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2994397021
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.4107052148
Short name T582
Test name
Test status
Simulation time 52183556 ps
CPU time 6.42 seconds
Started Aug 06 05:30:01 PM PDT 24
Finished Aug 06 05:30:07 PM PDT 24
Peak memory 248408 kb
Host smart-648ab0f2-0744-4d96-949e-5342a72791d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41070
52148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.4107052148
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2843858989
Short name T650
Test name
Test status
Simulation time 28515087115 ps
CPU time 1062.37 seconds
Started Aug 06 05:30:01 PM PDT 24
Finished Aug 06 05:47:44 PM PDT 24
Peak memory 285100 kb
Host smart-25acc3f3-fba1-441b-bbca-3b7609abd200
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843858989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2843858989
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1369696535
Short name T576
Test name
Test status
Simulation time 79648507899 ps
CPU time 1854.6 seconds
Started Aug 06 05:30:00 PM PDT 24
Finished Aug 06 06:00:55 PM PDT 24
Peak memory 272340 kb
Host smart-eaa3048f-852d-4d0b-a460-0e969cc578d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369696535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1369696535
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3788241373
Short name T96
Test name
Test status
Simulation time 7496568699 ps
CPU time 135.17 seconds
Started Aug 06 05:30:00 PM PDT 24
Finished Aug 06 05:32:16 PM PDT 24
Peak memory 248560 kb
Host smart-a6146dba-538d-4a90-aedf-742906727f7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788241373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3788241373
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1536219501
Short name T655
Test name
Test status
Simulation time 585226126 ps
CPU time 16.09 seconds
Started Aug 06 05:30:00 PM PDT 24
Finished Aug 06 05:30:17 PM PDT 24
Peak memory 255916 kb
Host smart-6d1cceb5-a615-4a02-aaeb-fc32c285d6a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15362
19501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1536219501
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1223898790
Short name T389
Test name
Test status
Simulation time 791914985 ps
CPU time 45.74 seconds
Started Aug 06 05:30:00 PM PDT 24
Finished Aug 06 05:30:45 PM PDT 24
Peak memory 248016 kb
Host smart-08532a1a-1a15-4e9c-9cdb-e3e710face1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12238
98790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1223898790
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.865978015
Short name T261
Test name
Test status
Simulation time 605257883 ps
CPU time 41.59 seconds
Started Aug 06 05:30:00 PM PDT 24
Finished Aug 06 05:30:41 PM PDT 24
Peak memory 255672 kb
Host smart-fa9606a6-dd2b-488d-9c82-1b3c319d2d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86597
8015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.865978015
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.4193610984
Short name T624
Test name
Test status
Simulation time 2151761335 ps
CPU time 30.6 seconds
Started Aug 06 05:30:00 PM PDT 24
Finished Aug 06 05:30:30 PM PDT 24
Peak memory 256640 kb
Host smart-e0064548-8eb2-4094-81d4-5494f929cc38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41936
10984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.4193610984
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1291604001
Short name T211
Test name
Test status
Simulation time 372025560 ps
CPU time 3.84 seconds
Started Aug 06 05:28:13 PM PDT 24
Finished Aug 06 05:28:17 PM PDT 24
Peak memory 248544 kb
Host smart-d291becf-ec20-4a44-bf9e-943ea0f33751
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1291604001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1291604001
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2567739048
Short name T422
Test name
Test status
Simulation time 51433271351 ps
CPU time 3030.54 seconds
Started Aug 06 05:28:08 PM PDT 24
Finished Aug 06 06:18:39 PM PDT 24
Peak memory 289520 kb
Host smart-2290b922-aef9-4788-92fb-af381eb7811f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567739048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2567739048
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3517692741
Short name T674
Test name
Test status
Simulation time 933707687 ps
CPU time 37.39 seconds
Started Aug 06 05:28:17 PM PDT 24
Finished Aug 06 05:28:54 PM PDT 24
Peak memory 248416 kb
Host smart-83e665b1-c6d3-46a4-9a40-c85d8600a20b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3517692741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3517692741
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3268030590
Short name T660
Test name
Test status
Simulation time 1650649391 ps
CPU time 50.79 seconds
Started Aug 06 05:28:08 PM PDT 24
Finished Aug 06 05:28:59 PM PDT 24
Peak memory 256200 kb
Host smart-3ef492ca-0661-4495-b11a-eec580d5786a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32680
30590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3268030590
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2197364919
Short name T625
Test name
Test status
Simulation time 964455688 ps
CPU time 57.44 seconds
Started Aug 06 05:28:13 PM PDT 24
Finished Aug 06 05:29:10 PM PDT 24
Peak memory 256520 kb
Host smart-c704a3c4-61cf-454a-bbd6-4bc17ab27f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21973
64919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2197364919
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1710150355
Short name T302
Test name
Test status
Simulation time 57798920486 ps
CPU time 1604.91 seconds
Started Aug 06 05:28:18 PM PDT 24
Finished Aug 06 05:55:03 PM PDT 24
Peak memory 272304 kb
Host smart-8799648d-ea70-4436-8365-a6d71088b5d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710150355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1710150355
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1628005032
Short name T235
Test name
Test status
Simulation time 28431550327 ps
CPU time 1456.71 seconds
Started Aug 06 05:28:13 PM PDT 24
Finished Aug 06 05:52:30 PM PDT 24
Peak memory 289136 kb
Host smart-3ba936cb-fded-4a21-9277-f2c280d4987d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628005032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1628005032
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3211071755
Short name T233
Test name
Test status
Simulation time 6809220944 ps
CPU time 231.86 seconds
Started Aug 06 05:28:13 PM PDT 24
Finished Aug 06 05:32:05 PM PDT 24
Peak memory 248452 kb
Host smart-e52c3668-3e12-4aa1-b188-1ee5b2b62aeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211071755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3211071755
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.17316556
Short name T579
Test name
Test status
Simulation time 8753672743 ps
CPU time 61.16 seconds
Started Aug 06 05:28:07 PM PDT 24
Finished Aug 06 05:29:08 PM PDT 24
Peak memory 256032 kb
Host smart-3ea68f7f-b133-4550-bbde-8953a18c4eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17316
556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.17316556
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2120795350
Short name T488
Test name
Test status
Simulation time 751687983 ps
CPU time 40.81 seconds
Started Aug 06 05:28:19 PM PDT 24
Finished Aug 06 05:29:00 PM PDT 24
Peak memory 247536 kb
Host smart-823a4a47-8668-4e69-9912-e272a6b3dc7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21207
95350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2120795350
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2758548657
Short name T9
Test name
Test status
Simulation time 852751196 ps
CPU time 12.74 seconds
Started Aug 06 05:28:13 PM PDT 24
Finished Aug 06 05:28:26 PM PDT 24
Peak memory 270308 kb
Host smart-a18467be-8403-4f55-b271-daf00c437c2d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2758548657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2758548657
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.63302507
Short name T91
Test name
Test status
Simulation time 1082586800 ps
CPU time 15.72 seconds
Started Aug 06 05:28:18 PM PDT 24
Finished Aug 06 05:28:34 PM PDT 24
Peak memory 256064 kb
Host smart-2e292323-41d6-4e41-ac78-90acd74a4565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63302
507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.63302507
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.4288526836
Short name T362
Test name
Test status
Simulation time 3462178048 ps
CPU time 43.3 seconds
Started Aug 06 05:28:14 PM PDT 24
Finished Aug 06 05:28:58 PM PDT 24
Peak memory 256584 kb
Host smart-f2e13cf6-bfa5-4fdb-b3e2-600ef3d68f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42885
26836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.4288526836
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2618943800
Short name T256
Test name
Test status
Simulation time 42093947991 ps
CPU time 1239.27 seconds
Started Aug 06 05:28:18 PM PDT 24
Finished Aug 06 05:48:57 PM PDT 24
Peak memory 288816 kb
Host smart-517341c7-0122-480b-ae0b-a6a94ec5ff1e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618943800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2618943800
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2088979533
Short name T285
Test name
Test status
Simulation time 122686234641 ps
CPU time 1645.54 seconds
Started Aug 06 05:30:01 PM PDT 24
Finished Aug 06 05:57:27 PM PDT 24
Peak memory 289340 kb
Host smart-f64d7bf9-77ed-47a1-acd2-595b6deacca3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088979533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2088979533
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2878458516
Short name T60
Test name
Test status
Simulation time 436105240 ps
CPU time 25.79 seconds
Started Aug 06 05:30:14 PM PDT 24
Finished Aug 06 05:30:40 PM PDT 24
Peak memory 256068 kb
Host smart-bcd1ae29-4177-413a-9f65-c99f657cffca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28784
58516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2878458516
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1084895310
Short name T442
Test name
Test status
Simulation time 638779845 ps
CPU time 25.48 seconds
Started Aug 06 05:30:02 PM PDT 24
Finished Aug 06 05:30:27 PM PDT 24
Peak memory 247888 kb
Host smart-4eff4c31-6397-4546-ab12-2dfc3957fe3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10848
95310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1084895310
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2815241910
Short name T687
Test name
Test status
Simulation time 102617532308 ps
CPU time 1503.21 seconds
Started Aug 06 05:30:01 PM PDT 24
Finished Aug 06 05:55:04 PM PDT 24
Peak memory 284384 kb
Host smart-dc8a54fa-300e-4059-86af-4e2b65f8d2b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815241910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2815241910
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3390292831
Short name T581
Test name
Test status
Simulation time 25810283894 ps
CPU time 268.69 seconds
Started Aug 06 05:30:01 PM PDT 24
Finished Aug 06 05:34:30 PM PDT 24
Peak memory 255484 kb
Host smart-c46f5ad9-5cf2-471e-b53d-c05e58d2ec1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390292831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3390292831
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.331748283
Short name T196
Test name
Test status
Simulation time 1165231365 ps
CPU time 27.77 seconds
Started Aug 06 05:30:03 PM PDT 24
Finished Aug 06 05:30:31 PM PDT 24
Peak memory 255896 kb
Host smart-8b7287a6-671a-424c-9b76-4e83a4f25430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33174
8283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.331748283
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.596959507
Short name T178
Test name
Test status
Simulation time 8098807705 ps
CPU time 65.11 seconds
Started Aug 06 05:30:01 PM PDT 24
Finished Aug 06 05:31:07 PM PDT 24
Peak memory 248564 kb
Host smart-ec7a6a88-6db7-4e31-811b-386025269f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59695
9507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.596959507
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2764876843
Short name T465
Test name
Test status
Simulation time 615851848 ps
CPU time 22.11 seconds
Started Aug 06 05:30:02 PM PDT 24
Finished Aug 06 05:30:25 PM PDT 24
Peak memory 248424 kb
Host smart-992d4843-c28a-40be-a15a-1c50baccf2f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27648
76843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2764876843
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2072447912
Short name T290
Test name
Test status
Simulation time 137909170203 ps
CPU time 1960.13 seconds
Started Aug 06 05:30:03 PM PDT 24
Finished Aug 06 06:02:43 PM PDT 24
Peak memory 285732 kb
Host smart-266856ec-593c-4b4c-8d07-da3fa748a9a8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072447912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2072447912
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2506685347
Short name T94
Test name
Test status
Simulation time 77326356442 ps
CPU time 2361.73 seconds
Started Aug 06 05:30:22 PM PDT 24
Finished Aug 06 06:09:44 PM PDT 24
Peak memory 289160 kb
Host smart-78eecd0a-a96a-42ee-bd76-8be3bfb58ffb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506685347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2506685347
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1542848297
Short name T244
Test name
Test status
Simulation time 10666449678 ps
CPU time 307.75 seconds
Started Aug 06 05:30:02 PM PDT 24
Finished Aug 06 05:35:10 PM PDT 24
Peak memory 256808 kb
Host smart-441bac95-7013-4e50-bec4-14462b91e25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15428
48297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1542848297
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3306476464
Short name T70
Test name
Test status
Simulation time 1832863115 ps
CPU time 52.67 seconds
Started Aug 06 05:30:04 PM PDT 24
Finished Aug 06 05:30:57 PM PDT 24
Peak memory 248368 kb
Host smart-ee2833fe-8e66-4045-ac90-96270d69a9c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33064
76464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3306476464
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.4033047441
Short name T341
Test name
Test status
Simulation time 7663175112 ps
CPU time 664.45 seconds
Started Aug 06 05:30:19 PM PDT 24
Finished Aug 06 05:41:24 PM PDT 24
Peak memory 272792 kb
Host smart-8d84e21d-9205-480c-9617-28084980a050
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033047441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.4033047441
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2183085503
Short name T393
Test name
Test status
Simulation time 35197793417 ps
CPU time 1109.76 seconds
Started Aug 06 05:30:20 PM PDT 24
Finished Aug 06 05:48:50 PM PDT 24
Peak memory 264612 kb
Host smart-1942db55-6da0-446d-b89a-f786238fd6ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183085503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2183085503
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.882934315
Short name T331
Test name
Test status
Simulation time 51754014631 ps
CPU time 239.94 seconds
Started Aug 06 05:30:20 PM PDT 24
Finished Aug 06 05:34:21 PM PDT 24
Peak memory 247592 kb
Host smart-1d4443d3-be99-424a-b5cc-14c0a7159b68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882934315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.882934315
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2917527195
Short name T628
Test name
Test status
Simulation time 793852460 ps
CPU time 53.96 seconds
Started Aug 06 05:30:02 PM PDT 24
Finished Aug 06 05:30:56 PM PDT 24
Peak memory 248472 kb
Host smart-f103841b-61a2-4672-8e66-c96d237cdd5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29175
27195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2917527195
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3891753548
Short name T100
Test name
Test status
Simulation time 311806576 ps
CPU time 28.75 seconds
Started Aug 06 05:30:02 PM PDT 24
Finished Aug 06 05:30:31 PM PDT 24
Peak memory 255660 kb
Host smart-e337adaf-41eb-4b8f-82c2-1c4984a7153b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38917
53548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3891753548
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2374101563
Short name T626
Test name
Test status
Simulation time 1789761954 ps
CPU time 57.79 seconds
Started Aug 06 05:30:01 PM PDT 24
Finished Aug 06 05:30:58 PM PDT 24
Peak memory 256068 kb
Host smart-fc179ccd-629c-4cdb-967e-1ecc3c56e840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23741
01563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2374101563
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2427699280
Short name T618
Test name
Test status
Simulation time 606440695505 ps
CPU time 2348.77 seconds
Started Aug 06 05:30:22 PM PDT 24
Finished Aug 06 06:09:31 PM PDT 24
Peak memory 281340 kb
Host smart-193bb5b8-7326-45f5-be4c-0718de38a481
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427699280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2427699280
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3173158694
Short name T580
Test name
Test status
Simulation time 176052900212 ps
CPU time 2455.17 seconds
Started Aug 06 05:30:21 PM PDT 24
Finished Aug 06 06:11:17 PM PDT 24
Peak memory 282744 kb
Host smart-8c2763fb-4f9f-4a20-996f-72856f071656
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173158694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3173158694
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2143586323
Short name T383
Test name
Test status
Simulation time 2835632093 ps
CPU time 101.53 seconds
Started Aug 06 05:30:20 PM PDT 24
Finished Aug 06 05:32:01 PM PDT 24
Peak memory 256204 kb
Host smart-47a6d5a3-991c-45b3-b21a-efb9c586e14f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21435
86323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2143586323
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1233867356
Short name T601
Test name
Test status
Simulation time 438680088 ps
CPU time 37.08 seconds
Started Aug 06 05:30:25 PM PDT 24
Finished Aug 06 05:31:02 PM PDT 24
Peak memory 256572 kb
Host smart-1ab77c6a-e93a-4103-a32b-effafc8aefdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12338
67356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1233867356
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.253956178
Short name T304
Test name
Test status
Simulation time 17721003024 ps
CPU time 982.51 seconds
Started Aug 06 05:30:23 PM PDT 24
Finished Aug 06 05:46:46 PM PDT 24
Peak memory 273072 kb
Host smart-aec47a53-9e40-40cc-95cf-1e44cca76fb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253956178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.253956178
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3515563537
Short name T288
Test name
Test status
Simulation time 56010217552 ps
CPU time 1642.35 seconds
Started Aug 06 05:30:21 PM PDT 24
Finished Aug 06 05:57:44 PM PDT 24
Peak memory 273032 kb
Host smart-01be6209-9e94-45cb-bd22-e7f263d5ae54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515563537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3515563537
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1146457091
Short name T623
Test name
Test status
Simulation time 13515061193 ps
CPU time 286.3 seconds
Started Aug 06 05:30:21 PM PDT 24
Finished Aug 06 05:35:08 PM PDT 24
Peak memory 248588 kb
Host smart-bd64a4d5-3d16-4312-a93d-d2bde092ad25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146457091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1146457091
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3916546532
Short name T469
Test name
Test status
Simulation time 524153537 ps
CPU time 30.73 seconds
Started Aug 06 05:30:21 PM PDT 24
Finished Aug 06 05:30:52 PM PDT 24
Peak memory 255860 kb
Host smart-342b3a7e-701e-4ffb-816f-be9cb7f18906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39165
46532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3916546532
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1571408284
Short name T437
Test name
Test status
Simulation time 1557595962 ps
CPU time 27.29 seconds
Started Aug 06 05:30:19 PM PDT 24
Finished Aug 06 05:30:47 PM PDT 24
Peak memory 247948 kb
Host smart-61ba4d4d-f6ae-4066-8714-6f7af909a255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15714
08284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1571408284
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3873409857
Short name T250
Test name
Test status
Simulation time 4078277235 ps
CPU time 61.43 seconds
Started Aug 06 05:30:19 PM PDT 24
Finished Aug 06 05:31:21 PM PDT 24
Peak memory 256772 kb
Host smart-00b3849b-3d16-4ca4-a519-2339de9c9b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38734
09857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3873409857
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.322691528
Short name T447
Test name
Test status
Simulation time 1423631269 ps
CPU time 20.59 seconds
Started Aug 06 05:30:20 PM PDT 24
Finished Aug 06 05:30:41 PM PDT 24
Peak memory 255576 kb
Host smart-d9aa9fba-95b0-481c-a734-5cee683f087b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32269
1528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.322691528
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2413824892
Short name T500
Test name
Test status
Simulation time 67234130427 ps
CPU time 1415.78 seconds
Started Aug 06 05:30:23 PM PDT 24
Finished Aug 06 05:53:59 PM PDT 24
Peak memory 288636 kb
Host smart-07f1d14c-616d-45ee-ab89-0130a45d3f4d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413824892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2413824892
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.2993320718
Short name T696
Test name
Test status
Simulation time 89656071582 ps
CPU time 7917.77 seconds
Started Aug 06 05:30:21 PM PDT 24
Finished Aug 06 07:42:19 PM PDT 24
Peak memory 338636 kb
Host smart-12b431c4-dd1b-46aa-bea7-d9118ed3c777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993320718 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.2993320718
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1218713652
Short name T81
Test name
Test status
Simulation time 60466807218 ps
CPU time 1447.86 seconds
Started Aug 06 05:30:20 PM PDT 24
Finished Aug 06 05:54:28 PM PDT 24
Peak memory 287196 kb
Host smart-a66ca897-c7a9-46d3-848a-57e15facb2eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218713652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1218713652
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2238353497
Short name T431
Test name
Test status
Simulation time 13031483756 ps
CPU time 206.09 seconds
Started Aug 06 05:30:19 PM PDT 24
Finished Aug 06 05:33:46 PM PDT 24
Peak memory 256576 kb
Host smart-a331ef10-3d80-442d-8ade-84ebbe91c01c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22383
53497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2238353497
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3221635058
Short name T454
Test name
Test status
Simulation time 130663901 ps
CPU time 5.84 seconds
Started Aug 06 05:30:19 PM PDT 24
Finished Aug 06 05:30:25 PM PDT 24
Peak memory 239668 kb
Host smart-f8ad5642-f8e7-4da2-b190-d641f92018e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32216
35058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3221635058
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3213869860
Short name T38
Test name
Test status
Simulation time 40403867010 ps
CPU time 2520.73 seconds
Started Aug 06 05:30:20 PM PDT 24
Finished Aug 06 06:12:22 PM PDT 24
Peak memory 288628 kb
Host smart-df8d5472-7ead-4a88-ab6d-a6c0a1eaedf6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213869860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3213869860
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2039913706
Short name T466
Test name
Test status
Simulation time 47720008817 ps
CPU time 2911.99 seconds
Started Aug 06 05:30:22 PM PDT 24
Finished Aug 06 06:18:55 PM PDT 24
Peak memory 288540 kb
Host smart-67d3c867-a4d6-471f-9770-610a7a943647
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039913706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2039913706
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2139332295
Short name T642
Test name
Test status
Simulation time 19959554976 ps
CPU time 211.06 seconds
Started Aug 06 05:30:22 PM PDT 24
Finished Aug 06 05:33:53 PM PDT 24
Peak memory 248536 kb
Host smart-b826f904-924b-4035-8ce5-28010d0997ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139332295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2139332295
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2818406450
Short name T671
Test name
Test status
Simulation time 38056191 ps
CPU time 3.57 seconds
Started Aug 06 05:30:23 PM PDT 24
Finished Aug 06 05:30:27 PM PDT 24
Peak memory 248440 kb
Host smart-58ea3e8d-e8b6-4ba6-a506-bf1ecd811917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28184
06450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2818406450
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1911374272
Short name T408
Test name
Test status
Simulation time 127294585 ps
CPU time 5.47 seconds
Started Aug 06 05:30:20 PM PDT 24
Finished Aug 06 05:30:26 PM PDT 24
Peak memory 239756 kb
Host smart-06b1e8c8-43cc-4d01-8790-3d4197456703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19113
74272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1911374272
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1923517609
Short name T444
Test name
Test status
Simulation time 398285025 ps
CPU time 15.94 seconds
Started Aug 06 05:30:38 PM PDT 24
Finished Aug 06 05:30:54 PM PDT 24
Peak memory 248500 kb
Host smart-617fc8f9-6090-4926-9145-3e00b1558e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19235
17609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1923517609
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2923581174
Short name T662
Test name
Test status
Simulation time 3226310993 ps
CPU time 50.5 seconds
Started Aug 06 05:30:21 PM PDT 24
Finished Aug 06 05:31:11 PM PDT 24
Peak memory 256796 kb
Host smart-35d0cb92-0c9c-4d58-9a5a-21112731896f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29235
81174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2923581174
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.2966440031
Short name T445
Test name
Test status
Simulation time 261102898651 ps
CPU time 4958.82 seconds
Started Aug 06 05:30:24 PM PDT 24
Finished Aug 06 06:53:03 PM PDT 24
Peak memory 338508 kb
Host smart-f351ade2-3ef7-4fb3-a2d7-9dced2cd6c18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966440031 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.2966440031
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3893446047
Short name T607
Test name
Test status
Simulation time 3654558777 ps
CPU time 208.3 seconds
Started Aug 06 05:30:22 PM PDT 24
Finished Aug 06 05:33:50 PM PDT 24
Peak memory 256672 kb
Host smart-779e1de2-3cce-43b3-ac45-b5db5387ae35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38934
46047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3893446047
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1273289911
Short name T374
Test name
Test status
Simulation time 4929729342 ps
CPU time 38.84 seconds
Started Aug 06 05:30:22 PM PDT 24
Finished Aug 06 05:31:01 PM PDT 24
Peak memory 248016 kb
Host smart-c15b0d95-0da5-4563-9258-e6b44df8429a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12732
89911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1273289911
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1040575750
Short name T523
Test name
Test status
Simulation time 8842838324 ps
CPU time 747.91 seconds
Started Aug 06 05:30:35 PM PDT 24
Finished Aug 06 05:43:03 PM PDT 24
Peak memory 272892 kb
Host smart-d9a9de54-6fe2-47eb-a4bc-d411fd96eb15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040575750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1040575750
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1042113651
Short name T439
Test name
Test status
Simulation time 37859493122 ps
CPU time 2276.25 seconds
Started Aug 06 05:30:36 PM PDT 24
Finished Aug 06 06:08:33 PM PDT 24
Peak memory 289496 kb
Host smart-9470fea1-85bd-4ade-8639-b22bb478bb80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042113651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1042113651
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.997278194
Short name T673
Test name
Test status
Simulation time 7920805984 ps
CPU time 316.13 seconds
Started Aug 06 05:30:41 PM PDT 24
Finished Aug 06 05:35:57 PM PDT 24
Peak memory 248328 kb
Host smart-031abdb0-252e-4bf3-8d03-49c9fbb2742a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997278194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.997278194
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3707014999
Short name T438
Test name
Test status
Simulation time 901383899 ps
CPU time 19.79 seconds
Started Aug 06 05:30:22 PM PDT 24
Finished Aug 06 05:30:42 PM PDT 24
Peak memory 248452 kb
Host smart-9c900651-d19e-4128-a0e3-8e6e0068be56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37070
14999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3707014999
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1160632862
Short name T67
Test name
Test status
Simulation time 2887977228 ps
CPU time 20.32 seconds
Started Aug 06 05:30:20 PM PDT 24
Finished Aug 06 05:30:40 PM PDT 24
Peak memory 256108 kb
Host smart-dcd4a419-9b64-4ace-9545-6d33156e7ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11606
32862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1160632862
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.398764678
Short name T267
Test name
Test status
Simulation time 510911530 ps
CPU time 35.91 seconds
Started Aug 06 05:30:38 PM PDT 24
Finished Aug 06 05:31:14 PM PDT 24
Peak memory 248004 kb
Host smart-bf6edd1a-38eb-43bd-81ca-a23b8cd1bf3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39876
4678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.398764678
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2003230740
Short name T409
Test name
Test status
Simulation time 331866574 ps
CPU time 30.19 seconds
Started Aug 06 05:30:19 PM PDT 24
Finished Aug 06 05:30:49 PM PDT 24
Peak memory 256648 kb
Host smart-2795b730-4a66-4fdc-962f-f59e29be7198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20032
30740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2003230740
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3404856483
Short name T271
Test name
Test status
Simulation time 79078440184 ps
CPU time 1259.77 seconds
Started Aug 06 05:30:38 PM PDT 24
Finished Aug 06 05:51:38 PM PDT 24
Peak memory 273120 kb
Host smart-85f4ce56-d514-4df6-a4d5-e7bc4d0fb0c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404856483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3404856483
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1918014401
Short name T410
Test name
Test status
Simulation time 5004050575 ps
CPU time 65.17 seconds
Started Aug 06 05:30:38 PM PDT 24
Finished Aug 06 05:31:44 PM PDT 24
Peak memory 249576 kb
Host smart-c25fd288-3ae2-4c78-bc94-0a97d6ee2ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19180
14401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1918014401
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3424158005
Short name T658
Test name
Test status
Simulation time 902948019 ps
CPU time 27.29 seconds
Started Aug 06 05:30:36 PM PDT 24
Finished Aug 06 05:31:04 PM PDT 24
Peak memory 256520 kb
Host smart-28d070d4-5649-4566-aaf1-c1386ab426f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34241
58005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3424158005
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2710427211
Short name T567
Test name
Test status
Simulation time 142664362066 ps
CPU time 2168.21 seconds
Started Aug 06 05:30:35 PM PDT 24
Finished Aug 06 06:06:43 PM PDT 24
Peak memory 288472 kb
Host smart-7b139137-2929-429b-911a-5dcee1eec8f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710427211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2710427211
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.984922254
Short name T664
Test name
Test status
Simulation time 110353939384 ps
CPU time 3152.05 seconds
Started Aug 06 05:30:37 PM PDT 24
Finished Aug 06 06:23:10 PM PDT 24
Peak memory 288876 kb
Host smart-8b3c225e-bdf0-42a7-9406-1e168b55c0d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984922254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.984922254
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2878786590
Short name T329
Test name
Test status
Simulation time 18868576305 ps
CPU time 423.79 seconds
Started Aug 06 05:30:37 PM PDT 24
Finished Aug 06 05:37:41 PM PDT 24
Peak memory 248516 kb
Host smart-14dfcd5a-856e-45ae-ab9a-6b8a37cd5584
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878786590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2878786590
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3686425322
Short name T637
Test name
Test status
Simulation time 592508363 ps
CPU time 34.53 seconds
Started Aug 06 05:30:37 PM PDT 24
Finished Aug 06 05:31:12 PM PDT 24
Peak memory 248500 kb
Host smart-c58d0d82-dd55-47d9-b12b-d5feeada6b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36864
25322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3686425322
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3092795505
Short name T498
Test name
Test status
Simulation time 4820531829 ps
CPU time 24.84 seconds
Started Aug 06 05:30:38 PM PDT 24
Finished Aug 06 05:31:03 PM PDT 24
Peak memory 248164 kb
Host smart-ab5f05ca-c2d9-4714-a881-25f21472afa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30927
95505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3092795505
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1642676839
Short name T47
Test name
Test status
Simulation time 183493377 ps
CPU time 31.03 seconds
Started Aug 06 05:30:35 PM PDT 24
Finished Aug 06 05:31:06 PM PDT 24
Peak memory 247976 kb
Host smart-aafb7725-4158-4f06-81f1-6816490aace6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16426
76839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1642676839
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.574873445
Short name T616
Test name
Test status
Simulation time 549539061 ps
CPU time 14.33 seconds
Started Aug 06 05:30:36 PM PDT 24
Finished Aug 06 05:30:50 PM PDT 24
Peak memory 248424 kb
Host smart-ab0eaafe-1c23-4e8b-b50c-f5ad840774f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57487
3445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.574873445
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.4246032120
Short name T484
Test name
Test status
Simulation time 4585173367 ps
CPU time 150.94 seconds
Started Aug 06 05:30:35 PM PDT 24
Finished Aug 06 05:33:06 PM PDT 24
Peak memory 252772 kb
Host smart-0a944f47-80a7-40e5-9765-426938149228
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246032120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.4246032120
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1482163544
Short name T406
Test name
Test status
Simulation time 22716823047 ps
CPU time 1400.21 seconds
Started Aug 06 05:30:39 PM PDT 24
Finished Aug 06 05:54:00 PM PDT 24
Peak memory 273044 kb
Host smart-b1c51e2c-09f4-43d4-9406-159002c14a6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482163544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1482163544
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.768617966
Short name T571
Test name
Test status
Simulation time 843237322 ps
CPU time 7.41 seconds
Started Aug 06 05:30:37 PM PDT 24
Finished Aug 06 05:30:45 PM PDT 24
Peak memory 247884 kb
Host smart-738bf080-dca1-4553-adc1-b38eb6294298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76861
7966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.768617966
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1127129081
Short name T425
Test name
Test status
Simulation time 10224589677 ps
CPU time 1189.18 seconds
Started Aug 06 05:30:37 PM PDT 24
Finished Aug 06 05:50:26 PM PDT 24
Peak memory 288600 kb
Host smart-e43f407e-e622-4852-b14a-8c567a2b0b07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127129081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1127129081
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1971087764
Short name T398
Test name
Test status
Simulation time 532600100 ps
CPU time 32.22 seconds
Started Aug 06 05:30:36 PM PDT 24
Finished Aug 06 05:31:09 PM PDT 24
Peak memory 255868 kb
Host smart-ffc94faa-fe82-451a-b078-62611f5d1982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19710
87764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1971087764
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3193647655
Short name T474
Test name
Test status
Simulation time 174210018 ps
CPU time 4.73 seconds
Started Aug 06 05:30:34 PM PDT 24
Finished Aug 06 05:30:39 PM PDT 24
Peak memory 239564 kb
Host smart-eba6331b-71c9-48f1-a7ed-8851bf70bbf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31936
47655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3193647655
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.983820914
Short name T224
Test name
Test status
Simulation time 57565180 ps
CPU time 6 seconds
Started Aug 06 05:30:42 PM PDT 24
Finished Aug 06 05:30:48 PM PDT 24
Peak memory 240152 kb
Host smart-42f5cc58-65a1-446d-97f3-7b8933825d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98382
0914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.983820914
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1342249491
Short name T372
Test name
Test status
Simulation time 11540578175 ps
CPU time 74.31 seconds
Started Aug 06 05:30:36 PM PDT 24
Finished Aug 06 05:31:50 PM PDT 24
Peak memory 256404 kb
Host smart-b4610628-4514-40db-9198-6d21ccfd9d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13422
49491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1342249491
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2273147389
Short name T255
Test name
Test status
Simulation time 41592083318 ps
CPU time 2729.75 seconds
Started Aug 06 05:30:36 PM PDT 24
Finished Aug 06 06:16:07 PM PDT 24
Peak memory 289300 kb
Host smart-7aa576dc-78ad-447c-815f-093685138aaa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273147389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2273147389
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3560324604
Short name T665
Test name
Test status
Simulation time 42667224194 ps
CPU time 2414.14 seconds
Started Aug 06 05:30:38 PM PDT 24
Finished Aug 06 06:10:53 PM PDT 24
Peak memory 281312 kb
Host smart-692b3360-1a8e-4539-97f8-08d0754df973
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560324604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3560324604
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2851422440
Short name T246
Test name
Test status
Simulation time 12007797211 ps
CPU time 342.19 seconds
Started Aug 06 05:30:38 PM PDT 24
Finished Aug 06 05:36:21 PM PDT 24
Peak memory 256740 kb
Host smart-6f1ce1e5-617f-448e-9a8f-97a00275a149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28514
22440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2851422440
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3108358044
Short name T699
Test name
Test status
Simulation time 1701606240 ps
CPU time 27.84 seconds
Started Aug 06 05:30:37 PM PDT 24
Finished Aug 06 05:31:05 PM PDT 24
Peak memory 248052 kb
Host smart-0b8c0c39-24db-492c-8756-09e9be811eb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31083
58044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3108358044
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.4272084105
Short name T343
Test name
Test status
Simulation time 10515869900 ps
CPU time 999.13 seconds
Started Aug 06 05:30:36 PM PDT 24
Finished Aug 06 05:47:15 PM PDT 24
Peak memory 273148 kb
Host smart-2ee24698-78b2-4e37-95f6-61f777a709ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272084105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.4272084105
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3118045146
Short name T54
Test name
Test status
Simulation time 58299259520 ps
CPU time 1701.32 seconds
Started Aug 06 05:30:37 PM PDT 24
Finished Aug 06 05:58:59 PM PDT 24
Peak memory 272680 kb
Host smart-8569b1bf-0f34-4102-9880-b231afcffc82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118045146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3118045146
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2846442669
Short name T330
Test name
Test status
Simulation time 18805382931 ps
CPU time 380.09 seconds
Started Aug 06 05:30:37 PM PDT 24
Finished Aug 06 05:36:57 PM PDT 24
Peak memory 248512 kb
Host smart-82512e6a-ef87-4970-8aa7-c04c39d7212d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846442669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2846442669
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.24689225
Short name T53
Test name
Test status
Simulation time 1394387993 ps
CPU time 13.44 seconds
Started Aug 06 05:30:37 PM PDT 24
Finished Aug 06 05:30:51 PM PDT 24
Peak memory 248332 kb
Host smart-0c232afb-5529-4216-bf9d-7683863e5e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24689
225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.24689225
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3780673797
Short name T552
Test name
Test status
Simulation time 1246787387 ps
CPU time 33.52 seconds
Started Aug 06 05:30:36 PM PDT 24
Finished Aug 06 05:31:09 PM PDT 24
Peak memory 247908 kb
Host smart-7cf61887-a73e-402c-bc27-970bf13e6393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37806
73797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3780673797
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.787161777
Short name T505
Test name
Test status
Simulation time 59319280 ps
CPU time 3.37 seconds
Started Aug 06 05:30:36 PM PDT 24
Finished Aug 06 05:30:40 PM PDT 24
Peak memory 239748 kb
Host smart-17c66970-f474-410e-b71a-4830002d1817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78716
1777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.787161777
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2969975841
Short name T420
Test name
Test status
Simulation time 783633690 ps
CPU time 29.67 seconds
Started Aug 06 05:30:42 PM PDT 24
Finished Aug 06 05:31:12 PM PDT 24
Peak memory 256592 kb
Host smart-8351b33e-8bfc-4800-b7c5-6380a67e6f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29699
75841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2969975841
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2538410901
Short name T37
Test name
Test status
Simulation time 4740518303 ps
CPU time 46.44 seconds
Started Aug 06 05:30:37 PM PDT 24
Finished Aug 06 05:31:24 PM PDT 24
Peak memory 255728 kb
Host smart-2b1158e7-53cf-41bf-98c0-1a095c135bb5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538410901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2538410901
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2948762242
Short name T613
Test name
Test status
Simulation time 30313283357 ps
CPU time 1262 seconds
Started Aug 06 05:30:36 PM PDT 24
Finished Aug 06 05:51:38 PM PDT 24
Peak memory 272792 kb
Host smart-cc43b4e7-bea2-4774-bc88-cfa0b278f775
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948762242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2948762242
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3035333477
Short name T512
Test name
Test status
Simulation time 2691971298 ps
CPU time 161.98 seconds
Started Aug 06 05:30:35 PM PDT 24
Finished Aug 06 05:33:17 PM PDT 24
Peak memory 256104 kb
Host smart-e9bb1e3e-c8c7-433d-a1ce-62c50b3d4e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30353
33477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3035333477
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.345751191
Short name T390
Test name
Test status
Simulation time 993470923 ps
CPU time 24.14 seconds
Started Aug 06 05:30:34 PM PDT 24
Finished Aug 06 05:30:58 PM PDT 24
Peak memory 256632 kb
Host smart-be368c89-a5d6-45ee-979e-5ce08cb514fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34575
1191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.345751191
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1981420102
Short name T593
Test name
Test status
Simulation time 183860934579 ps
CPU time 2830.96 seconds
Started Aug 06 05:30:37 PM PDT 24
Finished Aug 06 06:17:48 PM PDT 24
Peak memory 289568 kb
Host smart-7f2d5cd5-e2af-42d0-a058-d3c8f25bafe7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981420102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1981420102
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3098694741
Short name T79
Test name
Test status
Simulation time 7033696491 ps
CPU time 702.41 seconds
Started Aug 06 05:30:37 PM PDT 24
Finished Aug 06 05:42:20 PM PDT 24
Peak memory 265964 kb
Host smart-99c66237-af10-4126-ab57-87cc03d51079
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098694741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3098694741
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3946102719
Short name T316
Test name
Test status
Simulation time 10224625541 ps
CPU time 85.28 seconds
Started Aug 06 05:30:36 PM PDT 24
Finished Aug 06 05:32:01 PM PDT 24
Peak memory 248536 kb
Host smart-e1712544-9804-457d-90cf-c194ce5dedc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946102719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3946102719
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2846020657
Short name T76
Test name
Test status
Simulation time 1128870467 ps
CPU time 28.69 seconds
Started Aug 06 05:30:37 PM PDT 24
Finished Aug 06 05:31:06 PM PDT 24
Peak memory 255864 kb
Host smart-23af6b62-6698-49ce-9fb4-3011308fea37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28460
20657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2846020657
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3540121675
Short name T676
Test name
Test status
Simulation time 2012145511 ps
CPU time 58.61 seconds
Started Aug 06 05:30:38 PM PDT 24
Finished Aug 06 05:31:36 PM PDT 24
Peak memory 256176 kb
Host smart-87246fb0-6f93-41e7-9653-4cf171936e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35401
21675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3540121675
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3882101582
Short name T491
Test name
Test status
Simulation time 979585894 ps
CPU time 31.46 seconds
Started Aug 06 05:30:36 PM PDT 24
Finished Aug 06 05:31:08 PM PDT 24
Peak memory 247932 kb
Host smart-67d4ce67-0862-4bf8-9d3c-fd9472945b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38821
01582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3882101582
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.760696287
Short name T414
Test name
Test status
Simulation time 244844316 ps
CPU time 17.14 seconds
Started Aug 06 05:30:38 PM PDT 24
Finished Aug 06 05:30:56 PM PDT 24
Peak memory 254620 kb
Host smart-82d0450d-fe19-4b78-a691-ddd9d3457002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76069
6287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.760696287
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1331991968
Short name T190
Test name
Test status
Simulation time 93181712624 ps
CPU time 2930.53 seconds
Started Aug 06 05:30:37 PM PDT 24
Finished Aug 06 06:19:28 PM PDT 24
Peak memory 288752 kb
Host smart-1e243a15-0afb-4a7a-b690-97b5eb62fa0c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331991968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1331991968
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2006061104
Short name T103
Test name
Test status
Simulation time 73482751344 ps
CPU time 4512.4 seconds
Started Aug 06 05:30:36 PM PDT 24
Finished Aug 06 06:45:49 PM PDT 24
Peak memory 338092 kb
Host smart-bc714009-c8b9-467f-8b45-0f68a3e87ef3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006061104 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2006061104
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.222628911
Short name T478
Test name
Test status
Simulation time 50012840891 ps
CPU time 2755.4 seconds
Started Aug 06 05:30:49 PM PDT 24
Finished Aug 06 06:16:45 PM PDT 24
Peak memory 287424 kb
Host smart-f5790a99-1d53-4f9f-952c-3850c2bf291f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222628911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.222628911
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1647871658
Short name T537
Test name
Test status
Simulation time 3338744870 ps
CPU time 116.7 seconds
Started Aug 06 05:30:50 PM PDT 24
Finished Aug 06 05:32:46 PM PDT 24
Peak memory 255980 kb
Host smart-07ad2cb4-0886-42ce-866a-8d106d65387b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16478
71658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1647871658
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2663654402
Short name T643
Test name
Test status
Simulation time 38262712 ps
CPU time 4.6 seconds
Started Aug 06 05:30:50 PM PDT 24
Finished Aug 06 05:30:55 PM PDT 24
Peak memory 251040 kb
Host smart-fdcc5995-c4e7-44aa-807e-64cdfd9d5add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26636
54402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2663654402
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.946775706
Short name T313
Test name
Test status
Simulation time 79667788306 ps
CPU time 2267.08 seconds
Started Aug 06 05:30:53 PM PDT 24
Finished Aug 06 06:08:40 PM PDT 24
Peak memory 272412 kb
Host smart-2322a575-15b7-4f5a-907f-7758094d853f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946775706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.946775706
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.4036935482
Short name T565
Test name
Test status
Simulation time 93927038479 ps
CPU time 1704.07 seconds
Started Aug 06 05:30:51 PM PDT 24
Finished Aug 06 05:59:15 PM PDT 24
Peak memory 272988 kb
Host smart-70cb748c-2dff-4c89-9a4a-9f2e03d9a395
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036935482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.4036935482
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3893031358
Short name T328
Test name
Test status
Simulation time 56490571026 ps
CPU time 622.15 seconds
Started Aug 06 05:30:52 PM PDT 24
Finished Aug 06 05:41:14 PM PDT 24
Peak memory 255116 kb
Host smart-4453073b-f7ac-4264-b1ce-bbad11b5042c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893031358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3893031358
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3194606552
Short name T356
Test name
Test status
Simulation time 170567692 ps
CPU time 11.68 seconds
Started Aug 06 05:30:51 PM PDT 24
Finished Aug 06 05:31:03 PM PDT 24
Peak memory 248444 kb
Host smart-ab103531-c150-41b4-8b25-7a4568e7d545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31946
06552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3194606552
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3777752578
Short name T90
Test name
Test status
Simulation time 690662464 ps
CPU time 42.98 seconds
Started Aug 06 05:30:48 PM PDT 24
Finished Aug 06 05:31:31 PM PDT 24
Peak memory 248368 kb
Host smart-858b9391-6fe0-4597-b96e-93850f9796da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37777
52578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3777752578
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2035644999
Short name T307
Test name
Test status
Simulation time 511943138 ps
CPU time 14.04 seconds
Started Aug 06 05:30:51 PM PDT 24
Finished Aug 06 05:31:05 PM PDT 24
Peak memory 255760 kb
Host smart-23e9589e-99e8-4082-b883-3497e385de93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20356
44999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2035644999
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1597028131
Short name T684
Test name
Test status
Simulation time 7895670514 ps
CPU time 31.01 seconds
Started Aug 06 05:30:38 PM PDT 24
Finished Aug 06 05:31:09 PM PDT 24
Peak memory 248608 kb
Host smart-a2fa9878-71c8-4fc8-89e3-280c6b93106d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15970
28131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1597028131
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.67251310
Short name T559
Test name
Test status
Simulation time 603531050 ps
CPU time 17 seconds
Started Aug 06 05:30:54 PM PDT 24
Finished Aug 06 05:31:11 PM PDT 24
Peak memory 256516 kb
Host smart-a329c193-49cd-49c8-a721-859e3bbc38ce
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67251310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_hand
ler_stress_all.67251310
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.2362667380
Short name T39
Test name
Test status
Simulation time 173470122517 ps
CPU time 4877.24 seconds
Started Aug 06 05:30:51 PM PDT 24
Finished Aug 06 06:52:09 PM PDT 24
Peak memory 338088 kb
Host smart-d93c61fa-7b65-45ea-a067-f478bd949936
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362667380 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.2362667380
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2006234318
Short name T212
Test name
Test status
Simulation time 13719309 ps
CPU time 2.5 seconds
Started Aug 06 05:28:06 PM PDT 24
Finished Aug 06 05:28:09 PM PDT 24
Peak memory 248696 kb
Host smart-4e802ce0-ebaa-4a09-9379-e4c1a9df8518
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2006234318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2006234318
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.4125420571
Short name T89
Test name
Test status
Simulation time 37221947034 ps
CPU time 1305.56 seconds
Started Aug 06 05:28:08 PM PDT 24
Finished Aug 06 05:49:53 PM PDT 24
Peak memory 286204 kb
Host smart-063445ec-e258-4b3e-beff-ce60b3f1df8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125420571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.4125420571
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1529053637
Short name T377
Test name
Test status
Simulation time 3132059346 ps
CPU time 34.25 seconds
Started Aug 06 05:28:07 PM PDT 24
Finished Aug 06 05:28:41 PM PDT 24
Peak memory 248472 kb
Host smart-6d5e669d-2d06-4a53-ac9a-4b1911b931c3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1529053637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1529053637
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.975849702
Short name T569
Test name
Test status
Simulation time 13303028414 ps
CPU time 304.45 seconds
Started Aug 06 05:28:05 PM PDT 24
Finished Aug 06 05:33:10 PM PDT 24
Peak memory 251952 kb
Host smart-8c666ab8-03f7-43a4-86d6-0f70a4b35de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97584
9702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.975849702
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.64607143
Short name T672
Test name
Test status
Simulation time 3606377383 ps
CPU time 49.72 seconds
Started Aug 06 05:28:05 PM PDT 24
Finished Aug 06 05:28:55 PM PDT 24
Peak memory 248308 kb
Host smart-b1fd2ce4-12dd-4d1a-8a3e-1ab9f7b6646b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64607
143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.64607143
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1659049843
Short name T189
Test name
Test status
Simulation time 26069795200 ps
CPU time 1482.49 seconds
Started Aug 06 05:28:05 PM PDT 24
Finished Aug 06 05:52:47 PM PDT 24
Peak memory 288760 kb
Host smart-3f9a19e4-e26c-47dd-9617-b2eacbad3113
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659049843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1659049843
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.262149496
Short name T14
Test name
Test status
Simulation time 14715427068 ps
CPU time 1452.75 seconds
Started Aug 06 05:28:07 PM PDT 24
Finished Aug 06 05:52:20 PM PDT 24
Peak memory 288616 kb
Host smart-693e777c-f794-4732-8c4e-eef5ed05c5eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262149496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.262149496
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1897693808
Short name T495
Test name
Test status
Simulation time 18390521131 ps
CPU time 370.38 seconds
Started Aug 06 05:28:07 PM PDT 24
Finished Aug 06 05:34:17 PM PDT 24
Peak memory 248456 kb
Host smart-1806485c-5dba-4f8f-8805-734eaa0f304f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897693808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1897693808
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2418571924
Short name T63
Test name
Test status
Simulation time 350204236 ps
CPU time 20.94 seconds
Started Aug 06 05:28:08 PM PDT 24
Finished Aug 06 05:28:29 PM PDT 24
Peak memory 248368 kb
Host smart-515b636b-dcd2-4ecb-8a1b-d079556a712b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24185
71924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2418571924
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2490567253
Short name T181
Test name
Test status
Simulation time 1377377121 ps
CPU time 40.73 seconds
Started Aug 06 05:28:15 PM PDT 24
Finished Aug 06 05:28:56 PM PDT 24
Peak memory 248452 kb
Host smart-961d2c28-950b-4a14-bb13-05d957f26d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24905
67253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2490567253
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3061298662
Short name T426
Test name
Test status
Simulation time 3211957624 ps
CPU time 13.42 seconds
Started Aug 06 05:28:08 PM PDT 24
Finished Aug 06 05:28:21 PM PDT 24
Peak memory 248608 kb
Host smart-9f27131d-a55d-4ade-a09c-dcf8a7566a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30612
98662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3061298662
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1682389942
Short name T3
Test name
Test status
Simulation time 508336371 ps
CPU time 7.3 seconds
Started Aug 06 05:28:15 PM PDT 24
Finished Aug 06 05:28:22 PM PDT 24
Peak memory 251428 kb
Host smart-be50b7b4-175b-473c-828b-4d1b6aeb5e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16823
89942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1682389942
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3131669421
Short name T248
Test name
Test status
Simulation time 15163796986 ps
CPU time 1332.03 seconds
Started Aug 06 05:28:55 PM PDT 24
Finished Aug 06 05:51:07 PM PDT 24
Peak memory 285140 kb
Host smart-8bb9578e-fde3-4308-9d47-9045514a22de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131669421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3131669421
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.4187787303
Short name T213
Test name
Test status
Simulation time 60037233 ps
CPU time 3.01 seconds
Started Aug 06 05:28:20 PM PDT 24
Finished Aug 06 05:28:23 PM PDT 24
Peak memory 248676 kb
Host smart-98479354-3c0a-4a98-9a5e-5a2ae39bd48a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4187787303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.4187787303
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1920831076
Short name T468
Test name
Test status
Simulation time 113932446612 ps
CPU time 1929.6 seconds
Started Aug 06 05:28:08 PM PDT 24
Finished Aug 06 06:00:18 PM PDT 24
Peak memory 284344 kb
Host smart-0d321c19-6dbc-4a84-bca2-c1e42df20e8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920831076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1920831076
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2870890345
Short name T376
Test name
Test status
Simulation time 329369624 ps
CPU time 17.2 seconds
Started Aug 06 05:28:34 PM PDT 24
Finished Aug 06 05:28:51 PM PDT 24
Peak memory 248324 kb
Host smart-24dfd0b4-9601-4e75-a4fa-c3b2bef04c65
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2870890345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2870890345
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2119284936
Short name T572
Test name
Test status
Simulation time 4826002014 ps
CPU time 272.75 seconds
Started Aug 06 05:28:13 PM PDT 24
Finished Aug 06 05:32:46 PM PDT 24
Peak memory 256328 kb
Host smart-30461142-934e-4c90-a4b5-1c43a7ecaa05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21192
84936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2119284936
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3571730488
Short name T65
Test name
Test status
Simulation time 2258731296 ps
CPU time 38.01 seconds
Started Aug 06 05:28:13 PM PDT 24
Finished Aug 06 05:28:51 PM PDT 24
Peak memory 248476 kb
Host smart-f9211792-dbe9-4b26-9966-b98ad86d75af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35717
30488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3571730488
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.236508191
Short name T289
Test name
Test status
Simulation time 244085337185 ps
CPU time 1834.02 seconds
Started Aug 06 05:28:20 PM PDT 24
Finished Aug 06 05:58:54 PM PDT 24
Peak memory 273164 kb
Host smart-119a5769-4ae4-4a32-b98e-f85e73e015fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236508191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.236508191
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3626955158
Short name T456
Test name
Test status
Simulation time 394976866 ps
CPU time 16.66 seconds
Started Aug 06 05:28:13 PM PDT 24
Finished Aug 06 05:28:30 PM PDT 24
Peak memory 248500 kb
Host smart-92f899b7-f7b9-44cb-96b7-a1bcf32ee3bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36269
55158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3626955158
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3956402293
Short name T40
Test name
Test status
Simulation time 65755026 ps
CPU time 4.56 seconds
Started Aug 06 05:28:03 PM PDT 24
Finished Aug 06 05:28:08 PM PDT 24
Peak memory 240280 kb
Host smart-cf46db81-3d9e-4907-9072-794f32f921e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39564
02293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3956402293
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2789414127
Short name T230
Test name
Test status
Simulation time 1034080233 ps
CPU time 60.2 seconds
Started Aug 06 05:28:07 PM PDT 24
Finished Aug 06 05:29:07 PM PDT 24
Peak memory 256124 kb
Host smart-37278a53-9732-48a5-9159-9be0bba6bef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27894
14127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2789414127
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3601662093
Short name T229
Test name
Test status
Simulation time 670394854 ps
CPU time 44.6 seconds
Started Aug 06 05:28:13 PM PDT 24
Finished Aug 06 05:28:58 PM PDT 24
Peak memory 256256 kb
Host smart-96f71b22-5139-44b4-8c48-a1dae0865b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36016
62093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3601662093
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2206946398
Short name T203
Test name
Test status
Simulation time 181366245 ps
CPU time 3.9 seconds
Started Aug 06 05:28:21 PM PDT 24
Finished Aug 06 05:28:24 PM PDT 24
Peak memory 248556 kb
Host smart-afce4f8d-908a-4cfd-8828-3262bad933db
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2206946398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2206946398
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3350449530
Short name T629
Test name
Test status
Simulation time 80768968492 ps
CPU time 1858.56 seconds
Started Aug 06 05:28:22 PM PDT 24
Finished Aug 06 05:59:21 PM PDT 24
Peak memory 288280 kb
Host smart-695061e5-2123-4327-9ba1-9c3470f4ce13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350449530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3350449530
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1192629924
Short name T539
Test name
Test status
Simulation time 4293905129 ps
CPU time 44.03 seconds
Started Aug 06 05:28:21 PM PDT 24
Finished Aug 06 05:29:05 PM PDT 24
Peak memory 248348 kb
Host smart-91e29f64-1a49-4029-902e-ac2ba4466258
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1192629924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1192629924
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3645890703
Short name T686
Test name
Test status
Simulation time 522675598 ps
CPU time 43.76 seconds
Started Aug 06 05:28:25 PM PDT 24
Finished Aug 06 05:29:08 PM PDT 24
Peak memory 256108 kb
Host smart-7dc026b3-c66b-4332-b0a9-189b17b34aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36458
90703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3645890703
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3637082815
Short name T386
Test name
Test status
Simulation time 306687007 ps
CPU time 6.99 seconds
Started Aug 06 05:28:28 PM PDT 24
Finished Aug 06 05:28:35 PM PDT 24
Peak memory 247328 kb
Host smart-79479009-d161-4aec-8612-354741a56d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36370
82815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3637082815
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.4211012482
Short name T670
Test name
Test status
Simulation time 53136409261 ps
CPU time 3157.75 seconds
Started Aug 06 05:28:34 PM PDT 24
Finished Aug 06 06:21:13 PM PDT 24
Peak memory 288820 kb
Host smart-1249eac5-647c-4494-b8f5-6caddd6b2dd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211012482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.4211012482
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2989604814
Short name T451
Test name
Test status
Simulation time 13408448238 ps
CPU time 1021.83 seconds
Started Aug 06 05:28:24 PM PDT 24
Finished Aug 06 05:45:26 PM PDT 24
Peak memory 289316 kb
Host smart-b8bbe4ab-1c11-43d1-aec7-ea9e2b516ede
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989604814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2989604814
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2273105262
Short name T310
Test name
Test status
Simulation time 15175255260 ps
CPU time 618.73 seconds
Started Aug 06 05:28:21 PM PDT 24
Finished Aug 06 05:38:40 PM PDT 24
Peak memory 248400 kb
Host smart-82b90d93-c886-4ac1-8037-2e6ce8e1fc5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273105262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2273105262
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2409068118
Short name T12
Test name
Test status
Simulation time 1376323317 ps
CPU time 21.98 seconds
Started Aug 06 05:28:22 PM PDT 24
Finished Aug 06 05:28:44 PM PDT 24
Peak memory 255932 kb
Host smart-d1efa6ad-7f81-4ade-83a1-3a35505b4008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24090
68118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2409068118
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.316206232
Short name T107
Test name
Test status
Simulation time 97384288 ps
CPU time 16.78 seconds
Started Aug 06 05:28:35 PM PDT 24
Finished Aug 06 05:28:52 PM PDT 24
Peak memory 248152 kb
Host smart-40062d98-93fd-4f9e-acd1-ffcb2eefdcdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31620
6232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.316206232
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3773330034
Short name T365
Test name
Test status
Simulation time 984246651 ps
CPU time 55.97 seconds
Started Aug 06 05:28:20 PM PDT 24
Finished Aug 06 05:29:16 PM PDT 24
Peak memory 256304 kb
Host smart-497fbe5b-c530-43e1-874a-a4c98b29be5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37733
30034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3773330034
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2972026465
Short name T479
Test name
Test status
Simulation time 694703270 ps
CPU time 14.2 seconds
Started Aug 06 05:28:35 PM PDT 24
Finished Aug 06 05:28:49 PM PDT 24
Peak memory 256256 kb
Host smart-3591b844-0bb9-4e37-bca0-3b45575cd468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29720
26465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2972026465
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1109437756
Short name T4
Test name
Test status
Simulation time 11346575315 ps
CPU time 220.86 seconds
Started Aug 06 05:28:20 PM PDT 24
Finished Aug 06 05:32:01 PM PDT 24
Peak memory 256800 kb
Host smart-d76cb2a0-e172-4ad6-ab1f-ec1bd05b044a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109437756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1109437756
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1413178426
Short name T206
Test name
Test status
Simulation time 48903946 ps
CPU time 4.51 seconds
Started Aug 06 05:28:23 PM PDT 24
Finished Aug 06 05:28:28 PM PDT 24
Peak memory 248676 kb
Host smart-f54f117c-3c40-4ec4-bbbd-eedac5b87f68
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1413178426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1413178426
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3125865912
Short name T104
Test name
Test status
Simulation time 114291987734 ps
CPU time 1558.75 seconds
Started Aug 06 05:28:21 PM PDT 24
Finished Aug 06 05:54:20 PM PDT 24
Peak memory 273048 kb
Host smart-c0804dd9-0bb7-44fa-bb73-f6a230096fd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125865912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3125865912
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.885393648
Short name T392
Test name
Test status
Simulation time 147895834 ps
CPU time 9.07 seconds
Started Aug 06 05:28:34 PM PDT 24
Finished Aug 06 05:28:43 PM PDT 24
Peak memory 248396 kb
Host smart-f4078331-2ba8-424f-8399-ad559404d60c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=885393648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.885393648
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.4000772078
Short name T460
Test name
Test status
Simulation time 48128812667 ps
CPU time 257.96 seconds
Started Aug 06 05:28:21 PM PDT 24
Finished Aug 06 05:32:39 PM PDT 24
Peak memory 255876 kb
Host smart-00da96c8-9a0f-4f8c-b3bb-c996c3dbfba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40007
72078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.4000772078
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.1974526126
Short name T74
Test name
Test status
Simulation time 930823880 ps
CPU time 27.32 seconds
Started Aug 06 05:28:23 PM PDT 24
Finished Aug 06 05:28:50 PM PDT 24
Peak memory 248196 kb
Host smart-44eb3e4e-1aa7-4821-b908-50ad9eb0ea29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19745
26126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1974526126
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2777414121
Short name T301
Test name
Test status
Simulation time 105564783438 ps
CPU time 1705.8 seconds
Started Aug 06 05:28:23 PM PDT 24
Finished Aug 06 05:56:49 PM PDT 24
Peak memory 273056 kb
Host smart-9edc2bb9-0172-4d36-b5ba-61a92311d974
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777414121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2777414121
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.660072258
Short name T514
Test name
Test status
Simulation time 116020063579 ps
CPU time 1722.15 seconds
Started Aug 06 05:28:35 PM PDT 24
Finished Aug 06 05:57:18 PM PDT 24
Peak memory 286532 kb
Host smart-5e4cafa8-09cf-4ffc-8bab-fabec45dbddc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660072258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.660072258
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3173361818
Short name T97
Test name
Test status
Simulation time 8436257039 ps
CPU time 381.79 seconds
Started Aug 06 05:28:35 PM PDT 24
Finished Aug 06 05:34:57 PM PDT 24
Peak memory 248456 kb
Host smart-13b4aef1-faa8-4bbf-b94a-0cd398e6d905
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173361818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3173361818
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.646617283
Short name T191
Test name
Test status
Simulation time 308875069 ps
CPU time 10.69 seconds
Started Aug 06 05:28:35 PM PDT 24
Finished Aug 06 05:28:46 PM PDT 24
Peak memory 248480 kb
Host smart-3b8d4e99-c62d-464c-980c-fffe67dcc396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64661
7283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.646617283
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1081792220
Short name T57
Test name
Test status
Simulation time 50880669 ps
CPU time 3.21 seconds
Started Aug 06 05:28:27 PM PDT 24
Finished Aug 06 05:28:31 PM PDT 24
Peak memory 239600 kb
Host smart-3c5cc54e-c9a5-41f2-bf93-f16775355cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10817
92220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1081792220
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1814718988
Short name T66
Test name
Test status
Simulation time 766612829 ps
CPU time 47.46 seconds
Started Aug 06 05:28:37 PM PDT 24
Finished Aug 06 05:29:25 PM PDT 24
Peak memory 247964 kb
Host smart-01f066d3-59cf-4a42-b83c-ee34e7a334fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18147
18988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1814718988
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1532561462
Short name T562
Test name
Test status
Simulation time 136803789 ps
CPU time 4.12 seconds
Started Aug 06 05:28:28 PM PDT 24
Finished Aug 06 05:28:32 PM PDT 24
Peak memory 247880 kb
Host smart-9064966f-0744-45d0-9e51-cad5554d6285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15325
61462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1532561462
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2179331526
Short name T51
Test name
Test status
Simulation time 102381148859 ps
CPU time 3540.33 seconds
Started Aug 06 05:28:28 PM PDT 24
Finished Aug 06 06:27:29 PM PDT 24
Peak memory 297752 kb
Host smart-9dd6d58f-99b9-408c-ab56-dacb70b33435
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179331526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2179331526
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.214113813
Short name T209
Test name
Test status
Simulation time 57049973 ps
CPU time 2.42 seconds
Started Aug 06 05:28:22 PM PDT 24
Finished Aug 06 05:28:25 PM PDT 24
Peak memory 248672 kb
Host smart-3a3c0513-4fa2-4f0a-93b4-42641cfda51e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=214113813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.214113813
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3214095425
Short name T173
Test name
Test status
Simulation time 28239797901 ps
CPU time 1717.03 seconds
Started Aug 06 05:28:34 PM PDT 24
Finished Aug 06 05:57:12 PM PDT 24
Peak memory 272288 kb
Host smart-e695f657-42c5-46e1-931f-7534d906bb77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214095425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3214095425
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.328405671
Short name T421
Test name
Test status
Simulation time 1736345503 ps
CPU time 39.32 seconds
Started Aug 06 05:28:28 PM PDT 24
Finished Aug 06 05:29:07 PM PDT 24
Peak memory 247724 kb
Host smart-3176b588-1d1a-43db-81dc-ffdbe1729526
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=328405671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.328405671
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1536247827
Short name T407
Test name
Test status
Simulation time 2768621487 ps
CPU time 63.97 seconds
Started Aug 06 05:28:23 PM PDT 24
Finished Aug 06 05:29:27 PM PDT 24
Peak memory 255952 kb
Host smart-e5e797e1-4e91-44a8-bb00-babb964464cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15362
47827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1536247827
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3114999092
Short name T509
Test name
Test status
Simulation time 1228641616 ps
CPU time 23.11 seconds
Started Aug 06 05:28:23 PM PDT 24
Finished Aug 06 05:28:46 PM PDT 24
Peak memory 254840 kb
Host smart-8c42805f-2184-4398-8b36-f2a38221733f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31149
99092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3114999092
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3525027399
Short name T682
Test name
Test status
Simulation time 154912327887 ps
CPU time 1903.71 seconds
Started Aug 06 05:28:21 PM PDT 24
Finished Aug 06 06:00:05 PM PDT 24
Peak memory 286436 kb
Host smart-bc37b7b0-694c-421b-a04a-0d30efb258e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525027399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3525027399
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.127084952
Short name T226
Test name
Test status
Simulation time 27977555204 ps
CPU time 120.91 seconds
Started Aug 06 05:28:20 PM PDT 24
Finished Aug 06 05:30:21 PM PDT 24
Peak memory 248424 kb
Host smart-de4c936f-ff49-4db8-8eeb-b0efa1e98150
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127084952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.127084952
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2188512801
Short name T192
Test name
Test status
Simulation time 301718392 ps
CPU time 32.68 seconds
Started Aug 06 05:28:36 PM PDT 24
Finished Aug 06 05:29:09 PM PDT 24
Peak memory 255924 kb
Host smart-d3d35124-ae1f-481c-bc1d-5085826f2754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21885
12801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2188512801
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1273705487
Short name T693
Test name
Test status
Simulation time 606917680 ps
CPU time 19.87 seconds
Started Aug 06 05:28:36 PM PDT 24
Finished Aug 06 05:28:56 PM PDT 24
Peak memory 248392 kb
Host smart-6bdc23d2-fb72-44c4-a903-6c6a968ac7af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12737
05487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1273705487
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.644828282
Short name T680
Test name
Test status
Simulation time 583593837 ps
CPU time 15.87 seconds
Started Aug 06 05:28:34 PM PDT 24
Finished Aug 06 05:28:50 PM PDT 24
Peak memory 248756 kb
Host smart-502ecd97-ccc6-4db4-b0e1-dbf0e0ae0fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64482
8282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.644828282
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.836752793
Short name T489
Test name
Test status
Simulation time 79776217 ps
CPU time 7.77 seconds
Started Aug 06 05:28:21 PM PDT 24
Finished Aug 06 05:28:29 PM PDT 24
Peak memory 248456 kb
Host smart-9dc89fd3-dfe5-4abc-a0bf-c3f459c56301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83675
2793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.836752793
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.145101683
Short name T649
Test name
Test status
Simulation time 1241242813 ps
CPU time 14.44 seconds
Started Aug 06 05:28:37 PM PDT 24
Finished Aug 06 05:28:51 PM PDT 24
Peak memory 256568 kb
Host smart-ad8b6930-af00-46f0-9a16-cbf6d263670d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145101683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.145101683
Directory /workspace/9.alert_handler_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%