Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65962718	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32074468

1

T1

2997

T2

12854

T3

1743

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14675186	1			T1	2830		T2	4783		T3	1286
values[0x0]	40520276	1			T1	2788		T2	18188		T3	1993
values[0x1]	42841724	1			T1	2724		T2	18364		T3	2163

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56189946	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41847240

1

T1

3717

T2

16366

T3

2203

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	304890	1			T1	24		T3	16		T16	6
valid_sources[0x01]	298080	1			T1	27		T3	20		T16	3
valid_sources[0x02]	308720	1			T1	44		T3	24		T16	13
valid_sources[0x03]	736205	1			T1	32		T3	23		T16	5
valid_sources[0x04]	315705	1			T1	28		T3	25		T16	5
valid_sources[0x05]	303767	1			T1	36		T3	25		T16	5
valid_sources[0x06]	302582	1			T1	37		T3	24		T16	12
valid_sources[0x07]	298611	1			T1	28		T3	13		T16	10
valid_sources[0x08]	318023	1			T1	42		T3	19		T16	3
valid_sources[0x09]	302359	1			T1	26		T3	12		T16	12
valid_sources[0x0a]	555470	1			T1	38		T3	24		T16	5
valid_sources[0x0b]	296767	1			T1	26		T3	20		T16	9
valid_sources[0x0c]	315603	1			T1	30		T3	18		T16	4
valid_sources[0x0d]	327956	1			T1	25		T3	31		T16	1
valid_sources[0x0e]	308642	1			T1	41		T3	24		T16	2
valid_sources[0x0f]	302304	1			T1	39		T3	25		T16	15
valid_sources[0x10]	564312	1			T1	38		T3	16		T16	6
valid_sources[0x11]	572122	1			T1	28		T3	29		T16	10
valid_sources[0x12]	298535	1			T1	33		T3	19		T16	7
valid_sources[0x13]	653753	1			T1	38		T3	19		T16	5
valid_sources[0x14]	303700	1			T1	29		T3	22		T16	6
valid_sources[0x15]	730322	1			T1	41		T3	31		T7	427061
valid_sources[0x16]	932616	1			T1	34		T3	23		T16	4
valid_sources[0x17]	308309	1			T1	35		T3	29		T16	9
valid_sources[0x18]	306875	1			T1	29		T3	27		T16	17
valid_sources[0x19]	331329	1			T1	33		T3	22		T16	7
valid_sources[0x1a]	598863	1			T1	29		T3	9		T16	7
valid_sources[0x1b]	666913	1			T1	27		T3	24		T16	19
valid_sources[0x1c]	987292	1			T1	34		T3	24		T16	9
valid_sources[0x1d]	300626	1			T1	44		T3	25		T16	5
valid_sources[0x1e]	305896	1			T1	31		T3	15		T16	11
valid_sources[0x1f]	313254	1			T1	27		T3	21		T16	4
valid_sources[0x20]	302345	1			T1	33		T3	16		T16	9
valid_sources[0x21]	701867	1			T1	34		T3	22		T16	5
valid_sources[0x22]	310096	1			T1	32		T3	11		T16	18
valid_sources[0x23]	305259	1			T1	32		T3	17		T16	7
valid_sources[0x24]	307612	1			T1	32		T3	40		T16	6
valid_sources[0x25]	305281	1			T1	33		T3	22		T16	3
valid_sources[0x26]	306651	1			T1	35		T3	22		T16	9
valid_sources[0x27]	306514	1			T1	35		T3	23		T16	5
valid_sources[0x28]	315889	1			T1	35		T3	28		T16	8
valid_sources[0x29]	300965	1			T1	25		T3	24		T16	14
valid_sources[0x2a]	303423	1			T1	33		T3	19		T16	5
valid_sources[0x2b]	297618	1			T1	39		T3	10		T16	9
valid_sources[0x2c]	305981	1			T1	23		T3	25		T16	23
valid_sources[0x2d]	696384	1			T1	27		T3	15		T16	8
valid_sources[0x2e]	299916	1			T1	26		T3	18		T16	6
valid_sources[0x2f]	298049	1			T1	31		T3	18		T16	12
valid_sources[0x30]	303197	1			T1	44		T3	24		T16	8
valid_sources[0x31]	305863	1			T1	22		T3	17		T16	1
valid_sources[0x32]	313480	1			T1	32		T3	13		T16	10
valid_sources[0x33]	314255	1			T1	29		T3	17		T16	1
valid_sources[0x34]	817085	1			T1	28		T3	23		T16	13
valid_sources[0x35]	308758	1			T1	29		T3	12		T16	13
valid_sources[0x36]	305047	1			T1	36		T3	23		T16	5
valid_sources[0x37]	310129	1			T1	35		T3	33		T16	15
valid_sources[0x38]	299963	1			T1	39		T3	22		T16	10
valid_sources[0x39]	300025	1			T1	27		T3	15		T16	6
valid_sources[0x3a]	300478	1			T1	26		T3	21		T16	3
valid_sources[0x3b]	317724	1			T1	42		T3	40		T16	12
valid_sources[0x3c]	302167	1			T1	31		T3	38		T16	2
valid_sources[0x3d]	362735	1			T1	57		T3	19		T16	3
valid_sources[0x3e]	322206	1			T1	26		T3	19		T16	1
valid_sources[0x3f]	306429	1			T1	29		T3	17		T16	8
valid_sources[0x40]	297472	1			T1	37		T3	17		T16	7
valid_sources[0x41]	314104	1			T1	40		T3	22		T16	15
valid_sources[0x42]	310878	1			T1	31		T3	31		T16	9
valid_sources[0x43]	300812	1			T1	39		T3	21		T16	1
valid_sources[0x44]	834135	1			T1	34		T3	22		T16	11
valid_sources[0x45]	309211	1			T1	32		T3	32		T16	14
valid_sources[0x46]	313488	1			T1	28		T3	15		T16	7
valid_sources[0x47]	321610	1			T1	31		T3	15		T16	16
valid_sources[0x48]	301423	1			T1	33		T3	18		T16	4
valid_sources[0x49]	303047	1			T1	38		T3	26		T16	7
valid_sources[0x4a]	299413	1			T1	32		T3	19		T16	7
valid_sources[0x4b]	355307	1			T1	28		T3	12		T16	4
valid_sources[0x4c]	304697	1			T1	21		T3	13		T16	4
valid_sources[0x4d]	539419	1			T1	35		T3	19		T16	5
valid_sources[0x4e]	669412	1			T1	34		T3	21		T16	10
valid_sources[0x4f]	309253	1			T1	34		T3	21		T16	12
valid_sources[0x50]	322937	1			T1	33		T3	13		T16	11
valid_sources[0x51]	657511	1			T1	28		T3	20		T16	6
valid_sources[0x52]	554917	1			T1	33		T3	20		T16	19
valid_sources[0x53]	303358	1			T1	30		T3	20		T16	4
valid_sources[0x54]	1041710	1			T1	38		T3	24		T16	3
valid_sources[0x55]	314481	1			T1	34		T3	20		T16	13
valid_sources[0x56]	302281	1			T1	30		T3	21		T16	3
valid_sources[0x57]	646496	1			T1	32		T3	27		T16	8
valid_sources[0x58]	307267	1			T1	29		T3	14		T16	10
valid_sources[0x59]	343715	1			T1	29		T3	22		T16	7
valid_sources[0x5a]	304233	1			T1	25		T3	19		T16	2
valid_sources[0x5b]	638603	1			T1	26		T3	30		T16	3
valid_sources[0x5c]	309767	1			T1	45		T3	22		T16	7
valid_sources[0x5d]	315506	1			T1	36		T3	22		T16	10
valid_sources[0x5e]	306770	1			T1	39		T3	15		T16	6
valid_sources[0x5f]	603958	1			T1	26		T3	24		T16	2
valid_sources[0x60]	304022	1			T1	31		T3	11		T16	7
valid_sources[0x61]	307225	1			T1	36		T3	21		T16	8
valid_sources[0x62]	315076	1			T1	32		T3	21		T16	8
valid_sources[0x63]	529060	1			T1	25		T3	14		T16	6
valid_sources[0x64]	308324	1			T1	31		T3	20		T16	8
valid_sources[0x65]	308619	1			T1	21		T3	20		T16	10
valid_sources[0x66]	303698	1			T1	28		T3	21		T16	9
valid_sources[0x67]	298746	1			T1	27		T3	20		T16	8
valid_sources[0x68]	305263	1			T1	37		T3	22		T16	6
valid_sources[0x69]	303256	1			T1	40		T3	20		T16	6
valid_sources[0x6a]	315952	1			T1	21		T3	33		T16	5
valid_sources[0x6b]	327611	1			T1	32		T3	14		T16	2
valid_sources[0x6c]	299368	1			T1	24		T3	24		T16	9
valid_sources[0x6d]	307742	1			T1	34		T3	25		T16	7
valid_sources[0x6e]	300630	1			T1	40		T3	28		T16	5
valid_sources[0x6f]	681584	1			T1	29		T3	22		T16	4
valid_sources[0x70]	304785	1			T1	41		T3	20		T16	9
valid_sources[0x71]	310637	1			T1	26		T3	13		T16	18
valid_sources[0x72]	304161	1			T1	33		T3	21		T16	6
valid_sources[0x73]	704609	1			T1	31		T3	20		T16	6
valid_sources[0x74]	304765	1			T1	40		T3	17		T16	17
valid_sources[0x75]	301814	1			T1	36		T3	23		T16	2
valid_sources[0x76]	302251	1			T1	43		T3	32		T16	9
valid_sources[0x77]	310754	1			T1	32		T3	18		T16	4
valid_sources[0x78]	299681	1			T1	39		T3	18		T16	4
valid_sources[0x79]	632318	1			T1	40		T3	36		T16	12
valid_sources[0x7a]	1165223	1			T1	29		T3	12		T16	6
valid_sources[0x7b]	303704	1			T1	36		T3	20		T16	10
valid_sources[0x7c]	300998	1			T1	34		T3	28		T16	9
valid_sources[0x7d]	302627	1			T1	44		T3	14		T16	4
valid_sources[0x7e]	330488	1			T1	20		T3	29		T16	15
valid_sources[0x7f]	1033803	1			T1	30		T3	14		T16	3
valid_sources[0x80]	298600	1			T1	35		T3	25		T16	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7342918

1

T1

1417

T2

2417

T3

627

values[0x0]

all_enables

biggest_size

15584065

1

T1

997

T2

6720

T3

706

values[0x1]

all_enables

biggest_size

9147485

1

T1

583

T2

3717

T3

410