Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T36,T191
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15274	0	0
DisabledNoTrigBkwd_A	2147483647	845153	0	0
DisabledNoTrigFwd_A	2147483647	1598157449	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15274	0	0
T8	529467	0	0	0
T9	134512	0	0	0
T13	85245	0	0	0
T14	5408	1547	0	0
T15	25052	0	0	0
T20	213483	0	0	0
T21	239477	0	0	0
T23	217307	0	0	0
T24	136534	0	0	0
T25	6976	0	0	0
T36	0	797	0	0
T60	751972	0	0	0
T102	31354	0	0	0
T191	0	1073	0	0
T192	1467	360	0	0
T193	0	533	0	0
T194	0	755	0	0
T195	0	871	0	0
T196	0	1546	0	0
T197	893	183	0	0
T198	0	686	0	0
T199	0	476	0	0
T200	0	773	0	0
T201	0	637	0	0
T202	0	1071	0	0
T203	0	596	0	0
T204	0	609	0	0
T205	0	432	0	0
T206	0	1082	0	0
T207	0	442	0	0
T208	30711	0	0	0
T209	984048	0	0	0
T210	20599	0	0	0
T211	7996	0	0	0
T212	201928	0	0	0
T213	50285	0	0	0
T214	12085	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	845153	0	0
T1	86379	60	0	0
T2	1577280	234	0	0
T3	54531	40	0	0
T4	368708	720	0	0
T5	0	2977	0	0
T6	0	4	0	0
T7	1515951	814	0	0
T8	2117868	880	0	0
T9	538048	1529	0	0
T13	255735	75	0	0
T14	16224	24	0	0
T15	100208	4	0	0
T16	25704	11	0	0
T17	0	2	0	0
T20	213483	1477	0	0
T21	239477	811	0	0
T22	0	2120	0	0
T23	217307	66	0	0
T24	136534	131	0	0
T25	6976	0	0	0
T30	0	424	0	0
T43	0	2144	0	0
T44	30622	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1598157449	0	0
T1	115172	49568	0	0
T2	2103040	1591104	0	0
T3	72708	53890	0	0
T7	2021268	1047053	0	0
T8	2117868	1075426	0	0
T9	538048	67965	0	0
T13	340980	258642	0	0
T14	21632	14287	0	0
T15	100208	65237	0	0
T16	34272	26025	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T197,T198,T199
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	719324539	2427	0	0
DisabledNoTrigBkwd_A	719324539	218055	0	0
DisabledNoTrigFwd_A	719324539	384665928	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	2427	0	0
T60	751972	0	0	0
T102	31354	0	0	0
T197	893	183	0	0
T198	0	686	0	0
T199	0	476	0	0
T206	0	1082	0	0
T208	30711	0	0	0
T209	984048	0	0	0
T210	20599	0	0	0
T211	7996	0	0	0
T212	201928	0	0	0
T213	50285	0	0	0
T214	12085	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	218055	0	0
T1	28793	42	0	0
T2	525760	234	0	0
T3	18177	40	0	0
T7	505317	2	0	0
T8	529467	438	0	0
T9	134512	633	0	0
T13	85245	75	0	0
T14	5408	0	0	0
T15	25052	0	0	0
T16	8568	11	0	0
T20	0	4	0	0
T23	0	33	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	384665928	0	0
T1	28793	1582	0	0
T2	525760	26588	0	0
T3	18177	2467	0	0
T7	505317	503543	0	0
T8	529467	8829	0	0
T9	134512	11736	0	0
T13	85245	3135	0	0
T14	5408	3533	0	0
T15	25052	24977	0	0
T16	8568	582	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T7,T14

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T36,T191
1	1	Covered	T1,T7,T14

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T14

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	719324539	10105	0	0
DisabledNoTrigBkwd_A	719324539	181561	0	0
DisabledNoTrigFwd_A	719324539	401923053	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	10105	0	0
T8	529467	0	0	0
T9	134512	0	0	0
T13	85245	0	0	0
T14	5408	1547	0	0
T15	25052	0	0	0
T20	213483	0	0	0
T21	239477	0	0	0
T23	217307	0	0	0
T24	136534	0	0	0
T25	6976	0	0	0
T36	0	797	0	0
T191	0	1073	0	0
T193	0	533	0	0
T194	0	755	0	0
T196	0	1546	0	0
T200	0	773	0	0
T202	0	1071	0	0
T203	0	596	0	0
T204	0	609	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	181561	0	0
T1	28793	18	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T4	0	5	0	0
T5	0	2670	0	0
T7	505317	812	0	0
T8	529467	442	0	0
T9	134512	0	0	0
T13	85245	0	0	0
T14	5408	24	0	0
T15	25052	0	0	0
T16	8568	0	0	0
T20	0	1473	0	0
T21	0	811	0	0
T23	0	33	0	0
T24	0	131	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	401923053	0	0
T1	28793	14279	0	0
T2	525760	525692	0	0
T3	18177	17146	0	0
T7	505317	14703	0	0
T8	529467	8847	0	0
T9	134512	16521	0	0
T13	85245	85169	0	0
T14	5408	3563	0	0
T15	25052	7865	0	0
T16	8568	8481	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T7,T15

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T192,T201,T205
1	1	Covered	T1,T7,T15

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T15,T9

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	719324539	1871	0	0
DisabledNoTrigBkwd_A	719324539	231274	0	0
DisabledNoTrigFwd_A	719324539	413122226	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	1871	0	0
T49	108637	0	0	0
T71	400924	0	0	0
T72	510709	0	0	0
T101	221931	0	0	0
T192	1467	360	0	0
T193	2743	0	0	0
T201	0	637	0	0
T205	0	432	0	0
T207	0	442	0	0
T215	129187	0	0	0
T216	648965	0	0	0
T217	104182	0	0	0
T218	132694	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	231274	0	0
T4	368708	715	0	0
T5	0	307	0	0
T6	0	4	0	0
T8	529467	0	0	0
T9	134512	896	0	0
T15	25052	4	0	0
T17	0	2	0	0
T20	213483	0	0	0
T21	239477	0	0	0
T22	0	2120	0	0
T23	217307	0	0	0
T24	136534	0	0	0
T25	6976	0	0	0
T30	0	424	0	0
T43	0	2144	0	0
T44	30622	0	0	0
T63	0	551	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	413122226	0	0
T1	28793	26175	0	0
T2	525760	525692	0	0
T3	18177	17146	0	0
T7	505317	503636	0	0
T8	529467	528292	0	0
T9	134512	26336	0	0
T13	85245	85169	0	0
T14	5408	3586	0	0
T15	25052	10178	0	0
T16	8568	8481	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T195
1	1	Covered	T1,T2,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T15

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	719324539	871	0	0
DisabledNoTrigBkwd_A	719324539	214263	0	0
DisabledNoTrigFwd_A	719324539	398446242	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	871	0	0
T12	42059	0	0	0
T27	94577	0	0	0
T77	89529	0	0	0
T82	25646	0	0	0
T83	105083	0	0	0
T172	735676	0	0	0
T195	1660	871	0	0
T219	81186	0	0	0
T220	121673	0	0	0
T221	105808	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	214263	0	0
T1	28793	16	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T4	0	1123	0	0
T5	0	5614	0	0
T7	505317	1152	0	0
T8	529467	0	0	0
T9	134512	363	0	0
T13	85245	0	0	0
T14	5408	0	0	0
T15	25052	2	0	0
T16	8568	0	0	0
T22	0	2502	0	0
T30	0	1358	0	0
T43	0	2631	0	0
T63	0	283	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	398446242	0	0
T1	28793	7532	0	0
T2	525760	513132	0	0
T3	18177	17131	0	0
T7	505317	25171	0	0
T8	529467	529458	0	0
T9	134512	13372	0	0
T13	85245	85169	0	0
T14	5408	3605	0	0
T15	25052	22217	0	0
T16	8568	8481	0	0