Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T16
1	0	1	Covered	T2,T7,T16
1	1	0	Covered	T1,T15,T25
1	1	1	Covered	T1,T15,T25

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T25
0	1	Covered	T25,T4,T5
1	0	Covered	T5,T6,T26

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T15,T25
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T26

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T25
1	0	Covered	T27
1	1	Covered	T25,T4,T5

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T3,T7

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T2,T16,T8

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T9,T20

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T15,T25

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T15,T25
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T4,T28,T29
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T4,T30,T31
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T16,T5,T30
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T30,T32,T33
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T16,T13
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T15,T4
TimeoutSt->Phase0St	172	Covered	T25,T4,T5

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T15,T25
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T25,T4,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T15,T25
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T15,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T28,T29
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T30,T31
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T16,T5,T30
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T30,T32,T33
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T16,T13,T25
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	839	0	0
CheckAccumTrig0_A	2147483647	2444	0	0
CheckAccumTrig1_A	2147483647	106	0	0
CheckClr_A	2147483647	1164	0	0
CheckEn_A	2147483647	1261002683	0	0
CheckPhase0_A	2147483647	2802	0	0
CheckPhase1_A	2147483647	2757	0	0
CheckPhase2_A	2147483647	2702	0	0
CheckPhase3_A	2147483647	2651	0	0
CheckTimeout0_A	2147483647	3787	0	0
CheckTimeoutSt1_A	2147483647	471397	0	0
CheckTimeoutSt2_A	2147483647	3374	0	0
CheckTimeoutStTrig_A	2147483647	305	0	0
ErrorStAllEscAsserted_A	2147483647	4520	0	0
ErrorStIsTerminal_A	2147483647	3680	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	839	0	0
T10	82828	93	0	0
T11	0	262	0	0
T12	0	253	0	0
T18	2011856	0	0	0
T19	3834900	0	0	0
T34	0	119	0	0
T35	0	112	0	0
T36	7796	0	0	0
T37	146600	0	0	0
T38	263728	0	0	0
T39	18748	0	0	0
T40	108616	0	0	0
T41	564736	0	0	0
T42	903624	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2444	0	0
T1	86379	2	0	0
T2	1577280	1	0	0
T3	54531	1	0	0
T4	368708	3	0	0
T5	0	9	0	0
T6	0	1	0	0
T7	1515951	2	0	0
T8	2117868	2	0	0
T9	538048	2	0	0
T13	255735	2	0	0
T14	16224	1	0	0
T15	100208	1	0	0
T16	25704	3	0	0
T17	0	1	0	0
T20	213483	2	0	0
T21	239477	1	0	0
T22	0	2	0	0
T23	217307	2	0	0
T24	136534	1	0	0
T25	6976	0	0	0
T30	0	9	0	0
T43	0	1	0	0
T44	30622	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	106	0	0
T5	1702318	2	0	0
T6	2539497	2	0	0
T10	41414	0	0	0
T17	1567875	0	0	0
T18	502964	0	0	0
T19	958725	0	0	0
T22	486819	0	0	0
T26	1938600	2	0	0
T27	0	1	0	0
T30	1045716	0	0	0
T31	322068	0	0	0
T36	1949	0	0	0
T37	36650	0	0	0
T38	65932	0	0	0
T39	4687	0	0	0
T40	27154	0	0	0
T41	141184	0	0	0
T43	338442	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	16392	0	0	0
T63	1170216	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1164	0	0
T4	737416	2	0	0
T5	1702318	8	0	0
T6	1692998	1	0	0
T8	529467	0	0	0
T9	134512	0	0	0
T13	85245	1	0	0
T14	5408	0	0	0
T15	25052	0	0	0
T16	8568	2	0	0
T17	1045250	0	0	0
T20	213483	0	0	0
T21	239477	0	0	0
T22	324546	1	0	0
T23	217307	0	0	0
T24	136534	0	0	0
T25	13952	2	0	0
T26	0	5	0	0
T28	0	2	0	0
T29	0	1	0	0
T30	697144	7	0	0
T31	0	1	0	0
T32	0	3	0	0
T33	0	4	0	0
T38	0	1	0	0
T43	112814	0	0	0
T44	30622	0	0	0
T45	0	2	0	0
T46	0	8	0	0
T62	10928	0	0	0
T63	390072	1	0	0
T64	0	2	0	0
T65	0	2	0	0
T66	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1261002683	0	0
T1	115172	42675	0	0
T2	2103040	1591101	0	0
T3	72708	52002	0	0
T7	2021268	536154	0	0
T8	2117868	1075426	0	0
T9	538048	45470	0	0
T13	340980	258639	0	0
T14	21632	14287	0	0
T15	100208	42772	0	0
T16	34272	26022	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2802	0	0
T1	86379	2	0	0
T2	1577280	1	0	0
T3	54531	1	0	0
T4	368708	3	0	0
T5	0	5	0	0
T6	0	2	0	0
T7	1515951	2	0	0
T8	2117868	2	0	0
T9	538048	2	0	0
T13	255735	2	0	0
T14	16224	1	0	0
T15	100208	1	0	0
T16	25704	3	0	0
T17	0	1	0	0
T20	213483	2	0	0
T21	239477	1	0	0
T22	0	2	0	0
T23	217307	2	0	0
T24	136534	1	0	0
T25	6976	2	0	0
T30	0	10	0	0
T44	30622	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2757	0	0
T1	86379	2	0	0
T2	1577280	1	0	0
T3	54531	1	0	0
T4	368708	2	0	0
T5	0	5	0	0
T6	0	2	0	0
T7	1515951	2	0	0
T8	2117868	2	0	0
T9	538048	2	0	0
T13	255735	2	0	0
T14	16224	1	0	0
T15	100208	1	0	0
T16	25704	3	0	0
T17	0	1	0	0
T20	213483	2	0	0
T21	239477	1	0	0
T22	0	2	0	0
T23	217307	2	0	0
T24	136534	1	0	0
T25	6976	2	0	0
T30	0	9	0	0
T44	30622	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2702	0	0
T1	86379	2	0	0
T2	1577280	1	0	0
T3	54531	1	0	0
T4	368708	2	0	0
T5	0	5	0	0
T6	0	2	0	0
T7	1515951	2	0	0
T8	2117868	2	0	0
T9	538048	2	0	0
T13	255735	2	0	0
T14	16224	1	0	0
T15	100208	1	0	0
T16	25704	2	0	0
T17	0	1	0	0
T20	213483	2	0	0
T21	239477	1	0	0
T22	0	2	0	0
T23	217307	2	0	0
T24	136534	1	0	0
T25	6976	2	0	0
T30	0	8	0	0
T44	30622	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2651	0	0
T1	86379	2	0	0
T2	1577280	1	0	0
T3	54531	1	0	0
T4	368708	2	0	0
T5	0	5	0	0
T6	0	2	0	0
T7	1515951	2	0	0
T8	2117868	2	0	0
T9	538048	2	0	0
T13	255735	2	0	0
T14	16224	1	0	0
T15	100208	1	0	0
T16	25704	2	0	0
T17	0	1	0	0
T20	213483	2	0	0
T21	239477	1	0	0
T22	0	2	0	0
T23	217307	2	0	0
T24	136534	1	0	0
T25	6976	2	0	0
T30	0	7	0	0
T44	30622	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3787	0	0
T1	86379	4	0	0
T2	1577280	0	0	0
T3	54531	0	0	0
T4	368708	4	0	0
T5	851159	15	0	0
T6	846499	11	0	0
T7	1515951	0	0	0
T8	1588401	0	0	0
T9	403536	0	0	0
T13	255735	0	0	0
T14	16224	0	0	0
T15	75156	6	0	0
T16	25704	0	0	0
T17	522625	0	0	0
T22	162273	0	0	0
T25	0	2	0	0
T26	0	29	0	0
T29	0	1	0	0
T30	348572	28	0	0
T31	107356	1	0	0
T32	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T43	112814	0	0	0
T45	0	1	0	0
T46	0	30	0	0
T48	0	2	0	0
T62	5464	0	0	0
T63	390072	0	0	0
T67	0	3	0	0
T68	0	4	0	0
T69	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	471397	0	0
T1	86379	720	0	0
T2	1577280	0	0	0
T3	54531	0	0	0
T4	368708	236	0	0
T5	851159	2554	0	0
T6	846499	2769	0	0
T7	1515951	0	0	0
T8	1588401	0	0	0
T9	403536	0	0	0
T13	255735	0	0	0
T14	16224	0	0	0
T15	75156	2939	0	0
T16	25704	0	0	0
T17	522625	0	0	0
T22	162273	0	0	0
T25	0	26	0	0
T26	0	4334	0	0
T29	0	141	0	0
T30	348572	5279	0	0
T31	107356	71	0	0
T32	0	213	0	0
T37	0	1134	0	0
T38	0	83	0	0
T43	112814	0	0	0
T45	0	30	0	0
T46	0	3483	0	0
T48	0	477	0	0
T62	5464	0	0	0
T63	390072	0	0	0
T67	0	276	0	0
T68	0	383	0	0
T69	0	566	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3374	0	0
T1	86379	4	0	0
T2	1577280	0	0	0
T3	54531	0	0	0
T4	368708	2	0	0
T5	851159	8	0	0
T6	846499	9	0	0
T7	1515951	0	0	0
T8	1588401	0	0	0
T9	403536	0	0	0
T13	255735	0	0	0
T14	16224	0	0	0
T15	75156	6	0	0
T16	25704	0	0	0
T17	522625	0	0	0
T22	162273	0	0	0
T26	0	22	0	0
T29	0	1	0	0
T30	348572	20	0	0
T31	107356	1	0	0
T32	0	1	0	0
T38	0	1	0	0
T43	112814	0	0	0
T45	0	1	0	0
T46	0	51	0	0
T48	0	1	0	0
T50	0	2	0	0
T62	5464	0	0	0
T63	390072	0	0	0
T67	0	7	0	0
T68	0	3	0	0
T69	0	5	0	0
T70	0	4	0	0
T71	0	2	0	0
T72	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	305	0	0
T4	737416	2	0	0
T5	3404636	2	0	0
T6	3385996	0	0	0
T17	2090500	0	0	0
T21	239477	0	0	0
T22	649092	0	0	0
T25	6976	2	0	0
T26	969300	3	0	0
T30	1394288	6	0	0
T31	322068	0	0	0
T37	0	3	0	0
T43	338442	0	0	0
T44	30622	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	0	2	0	0
T55	0	4	0	0
T62	21856	0	0	0
T63	1170216	0	0	0
T67	0	1	0	0
T69	0	1	0	0
T71	0	5	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4520	0	0
T10	82828	649	0	0
T11	0	1276	0	0
T12	0	1321	0	0
T18	2011856	0	0	0
T19	3834900	0	0	0
T34	0	623	0	0
T35	0	651	0	0
T36	7796	0	0	0
T37	146600	0	0	0
T38	263728	0	0	0
T39	18748	0	0	0
T40	108616	0	0	0
T41	564736	0	0	0
T42	903624	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3680	0	0
T10	82828	529	0	0
T11	0	1036	0	0
T12	0	1081	0	0
T18	2011856	0	0	0
T19	3834900	0	0	0
T34	0	503	0	0
T35	0	531	0	0
T36	7796	0	0	0
T37	146600	0	0	0
T38	263728	0	0	0
T39	18748	0	0	0
T40	108616	0	0	0
T41	564736	0	0	0
T42	903624	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	115172	114872	0	0
T2	2103040	2102768	0	0
T3	72708	72344	0	0
T7	2021268	2021244	0	0
T8	2117868	2117832	0	0
T9	538048	538012	0	0
T13	340980	340676	0	0
T14	21632	21404	0	0
T15	100208	99908	0	0
T16	34272	33924	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	115172	114872	0	0
T2	2103040	2102768	0	0
T3	72708	72344	0	0
T7	2021268	2021244	0	0
T8	2117868	2117832	0	0
T9	538048	538012	0	0
T13	340980	340676	0	0
T14	21632	21404	0	0
T15	100208	99908	0	0
T16	34272	33924	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T16
1	0	1	Covered	T2,T16,T23
1	1	0	Covered	T15,T4,T5
1	1	1	Covered	T4,T5,T30

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T30
0	1	Covered	T4,T5,T30
1	0	Covered	T26,T46,T47

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T5,T30
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T46,T47

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T30
1	0	Not Covered
1	1	Covered	T4,T5,T30

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T16,T13
1	Covered	T1,T3,T7

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T2,T16,T8

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T9,T20

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T5,T30

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T4,T5,T30

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T4,T5,T30
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T28,T29,T71
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T26,T38,T80
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T16,T5,T81
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T47,T82,T83
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T16,T13,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T5,T30
TimeoutSt->Phase0St	172	Covered	T4,T5,T30

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T30
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T30
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T30
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T30
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T29,T71
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T38,T80
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T16,T5,T81
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T47,T82,T83
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T16,T13,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	719324539	191	0	0
CheckAccumTrig0_A	719324539	891	0	0
CheckAccumTrig1_A	719324539	37	0	0
CheckClr_A	719324539	446	0	0
CheckEn_A	719179341	275086736	0	0
CheckPhase0_A	719324539	993	0	0
CheckPhase1_A	719324539	978	0	0
CheckPhase2_A	719324539	957	0	0
CheckPhase3_A	719324539	932	0	0
CheckTimeout0_A	719324539	1418	0	0
CheckTimeoutSt1_A	719324539	170147	0	0
CheckTimeoutSt2_A	719324539	1292	0	0
CheckTimeoutStTrig_A	719324539	87	0	0
ErrorStAllEscAsserted_A	719324539	1090	0	0
ErrorStIsTerminal_A	719324539	880	0	0
EscStateOut_A	719178059	719107124	0	0
u_state_regs_A	719324539	719164917	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	191	0	0
T10	20707	18	0	0
T11	0	63	0	0
T12	0	65	0	0
T18	502964	0	0	0
T19	958725	0	0	0
T34	0	28	0	0
T35	0	17	0	0
T36	1949	0	0	0
T37	36650	0	0	0
T38	65932	0	0	0
T39	4687	0	0	0
T40	27154	0	0	0
T41	141184	0	0	0
T42	225906	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	891	0	0
T1	28793	1	0	0
T2	525760	1	0	0
T3	18177	1	0	0
T7	505317	1	0	0
T8	529467	1	0	0
T9	134512	1	0	0
T13	85245	2	0	0
T14	5408	0	0	0
T15	25052	0	0	0
T16	8568	3	0	0
T20	0	1	0	0
T23	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	37	0	0
T10	20707	0	0	0
T18	502964	0	0	0
T19	958725	0	0	0
T26	484650	1	0	0
T36	1949	0	0	0
T37	36650	0	0	0
T38	65932	0	0	0
T39	4687	0	0	0
T40	27154	0	0	0
T41	141184	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	446	0	0
T5	0	4	0	0
T8	529467	0	0	0
T9	134512	0	0	0
T13	85245	1	0	0
T14	5408	0	0	0
T15	25052	0	0	0
T16	8568	2	0	0
T20	213483	0	0	0
T23	217307	0	0	0
T24	136534	0	0	0
T25	6976	0	0	0
T26	0	4	0	0
T28	0	2	0	0
T30	0	2	0	0
T32	0	1	0	0
T38	0	1	0	0
T46	0	3	0	0
T65	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719179341	275086736	0	0
T1	28793	582	0	0
T2	525760	26588	0	0
T3	18177	582	0	0
T7	505317	3073	0	0
T8	529467	8829	0	0
T9	134512	5567	0	0
T13	85245	3135	0	0
T14	5408	3533	0	0
T15	25052	24976	0	0
T16	8568	582	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	993	0	0
T1	28793	1	0	0
T2	525760	1	0	0
T3	18177	1	0	0
T7	505317	1	0	0
T8	529467	1	0	0
T9	134512	1	0	0
T13	85245	2	0	0
T14	5408	0	0	0
T15	25052	0	0	0
T16	8568	3	0	0
T20	0	1	0	0
T23	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	978	0	0
T1	28793	1	0	0
T2	525760	1	0	0
T3	18177	1	0	0
T7	505317	1	0	0
T8	529467	1	0	0
T9	134512	1	0	0
T13	85245	2	0	0
T14	5408	0	0	0
T15	25052	0	0	0
T16	8568	3	0	0
T20	0	1	0	0
T23	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	957	0	0
T1	28793	1	0	0
T2	525760	1	0	0
T3	18177	1	0	0
T7	505317	1	0	0
T8	529467	1	0	0
T9	134512	1	0	0
T13	85245	2	0	0
T14	5408	0	0	0
T15	25052	0	0	0
T16	8568	2	0	0
T20	0	1	0	0
T23	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	932	0	0
T1	28793	1	0	0
T2	525760	1	0	0
T3	18177	1	0	0
T7	505317	1	0	0
T8	529467	1	0	0
T9	134512	1	0	0
T13	85245	2	0	0
T14	5408	0	0	0
T15	25052	0	0	0
T16	8568	2	0	0
T20	0	1	0	0
T23	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	1418	0	0
T4	368708	2	0	0
T5	851159	5	0	0
T6	846499	0	0	0
T17	522625	0	0	0
T22	162273	0	0	0
T26	0	6	0	0
T30	348572	17	0	0
T31	107356	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	112814	0	0	0
T45	0	1	0	0
T46	0	4	0	0
T62	5464	0	0	0
T63	390072	0	0	0
T67	0	2	0	0
T68	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	170147	0	0
T4	368708	126	0	0
T5	851159	919	0	0
T6	846499	0	0	0
T17	522625	0	0	0
T22	162273	0	0	0
T26	0	1278	0	0
T30	348572	4085	0	0
T31	107356	0	0	0
T37	0	306	0	0
T38	0	83	0	0
T43	112814	0	0	0
T45	0	30	0	0
T46	0	165	0	0
T62	5464	0	0	0
T63	390072	0	0	0
T67	0	160	0	0
T68	0	170	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	1292	0	0
T4	368708	1	0	0
T5	851159	4	0	0
T6	846499	0	0	0
T17	522625	0	0	0
T22	162273	0	0	0
T26	0	2	0	0
T30	348572	14	0	0
T31	107356	0	0	0
T38	0	1	0	0
T43	112814	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T62	5464	0	0	0
T63	390072	0	0	0
T67	0	2	0	0
T68	0	1	0	0
T70	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	87	0	0
T4	368708	1	0	0
T5	851159	1	0	0
T6	846499	0	0	0
T17	522625	0	0	0
T22	162273	0	0	0
T26	0	3	0	0
T30	348572	3	0	0
T31	107356	0	0	0
T37	0	1	0	0
T43	112814	0	0	0
T46	0	1	0	0
T62	5464	0	0	0
T63	390072	0	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	1090	0	0
T10	20707	154	0	0
T11	0	306	0	0
T12	0	339	0	0
T18	502964	0	0	0
T19	958725	0	0	0
T34	0	152	0	0
T35	0	139	0	0
T36	1949	0	0	0
T37	36650	0	0	0
T38	65932	0	0	0
T39	4687	0	0	0
T40	27154	0	0	0
T41	141184	0	0	0
T42	225906	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	880	0	0
T10	20707	124	0	0
T11	0	246	0	0
T12	0	279	0	0
T18	502964	0	0	0
T19	958725	0	0	0
T34	0	122	0	0
T35	0	109	0	0
T36	1949	0	0	0
T37	36650	0	0	0
T38	65932	0	0	0
T39	4687	0	0	0
T40	27154	0	0	0
T41	141184	0	0	0
T42	225906	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719178059	719107124	0	0
T1	28793	28718	0	0
T2	525760	525692	0	0
T3	18177	18086	0	0
T7	505317	505311	0	0
T8	529467	529458	0	0
T9	134512	134503	0	0
T13	85245	85169	0	0
T14	5408	5351	0	0
T15	25052	24977	0	0
T16	8568	8481	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	719164917	0	0
T1	28793	28718	0	0
T2	525760	525692	0	0
T3	18177	18086	0	0
T7	505317	505311	0	0
T8	529467	529458	0	0
T9	134512	134503	0	0
T13	85245	85169	0	0
T14	5408	5351	0	0
T15	25052	24977	0	0
T16	8568	8481	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T7,T14
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T14

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T14

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T15
1	0	1	Covered	T7,T14,T8
1	1	0	Covered	T15,T4,T5
1	1	1	Covered	T1,T15,T25

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T25
0	1	Covered	T25,T4,T30
1	0	Covered	T5,T6,T26

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T15,T25
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T26

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T25
1	0	Not Covered
1	1	Covered	T25,T4,T30

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T23
1	Covered	T14,T8,T24

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T14
1	Covered	T23,T20,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T14
1	Covered	T25,T5,T6

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T14,T8,T23
1	Covered	T1,T7,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T14,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T14,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T14,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T7,T14

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T7,T14
Phase1St	198	Covered	T1,T7,T14
Phase2St	215	Covered	T1,T7,T14
Phase3St	233	Covered	T1,T7,T14
TerminalSt	249	Covered	T1,T7,T14
TimeoutSt	159	Covered	T1,T15,T25

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T7,T14
IdleSt->TimeoutSt	159	Covered	T1,T15,T25
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T84,T61,T85
Phase0St->Phase1St	198	Covered	T1,T7,T14
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T4,T31,T86
Phase1St->Phase2St	215	Covered	T1,T7,T14
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T64,T52,T27
Phase2St->Phase3St	233	Covered	T1,T7,T14
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T87,T88,T89
Phase3St->TerminalSt	249	Covered	T1,T7,T14
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T25,T5,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T15,T5
TimeoutSt->Phase0St	172	Covered	T25,T4,T5

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T14
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T15,T25
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T25,T4,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T15,T25
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T15,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T84,T85,T90
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T7,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T7,T8
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T31,T86
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T7,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T7,T8
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T64,T52,T27
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T7,T14
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T7,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T87,T88,T89
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T7,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T7,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T25,T5,T26
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T7,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	719324539	240	0	0
CheckAccumTrig0_A	719324539	510	0	0
CheckAccumTrig1_A	719324539	26	0	0
CheckClr_A	719324539	242	0	0
CheckEn_A	719179341	345995402	0	0
CheckPhase0_A	719324539	605	0	0
CheckPhase1_A	719324539	593	0	0
CheckPhase2_A	719324539	583	0	0
CheckPhase3_A	719324539	574	0	0
CheckTimeout0_A	719324539	685	0	0
CheckTimeoutSt1_A	719324539	92393	0	0
CheckTimeoutSt2_A	719324539	578	0	0
CheckTimeoutStTrig_A	719324539	81	0	0
ErrorStAllEscAsserted_A	719324539	1114	0	0
ErrorStIsTerminal_A	719324539	904	0	0
EscStateOut_A	719178059	719107124	0	0
u_state_regs_A	719324539	719164917	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	240	0	0
T10	20707	22	0	0
T11	0	68	0	0
T12	0	75	0	0
T18	502964	0	0	0
T19	958725	0	0	0
T34	0	28	0	0
T35	0	47	0	0
T36	1949	0	0	0
T37	36650	0	0	0
T38	65932	0	0	0
T39	4687	0	0	0
T40	27154	0	0	0
T41	141184	0	0	0
T42	225906	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	510	0	0
T1	28793	1	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T4	0	1	0	0
T5	0	5	0	0
T7	505317	1	0	0
T8	529467	1	0	0
T9	134512	0	0	0
T13	85245	0	0	0
T14	5408	1	0	0
T15	25052	0	0	0
T16	8568	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	26	0	0
T5	851159	2	0	0
T6	846499	1	0	0
T17	522625	0	0	0
T22	162273	0	0	0
T26	484650	1	0	0
T27	0	1	0	0
T30	348572	0	0	0
T31	107356	0	0	0
T43	112814	0	0	0
T45	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T58	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	5464	0	0	0
T63	390072	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	242	0	0
T4	368708	1	0	0
T5	851159	4	0	0
T6	846499	0	0	0
T17	522625	0	0	0
T21	239477	0	0	0
T22	162273	0	0	0
T25	6976	2	0	0
T26	0	1	0	0
T29	0	1	0	0
T30	348572	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T44	30622	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T62	5464	0	0	0
T64	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719179341	345995402	0	0
T1	28793	8387	0	0
T2	525760	525691	0	0
T3	18177	17145	0	0
T7	505317	14703	0	0
T8	529467	8847	0	0
T9	134512	16521	0	0
T13	85245	85168	0	0
T14	5408	3563	0	0
T15	25052	7865	0	0
T16	8568	8480	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	605	0	0
T1	28793	1	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T4	0	2	0	0
T7	505317	1	0	0
T8	529467	1	0	0
T9	134512	0	0	0
T13	85245	0	0	0
T14	5408	1	0	0
T15	25052	0	0	0
T16	8568	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	593	0	0
T1	28793	1	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T4	0	1	0	0
T7	505317	1	0	0
T8	529467	1	0	0
T9	134512	0	0	0
T13	85245	0	0	0
T14	5408	1	0	0
T15	25052	0	0	0
T16	8568	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	583	0	0
T1	28793	1	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T4	0	1	0	0
T7	505317	1	0	0
T8	529467	1	0	0
T9	134512	0	0	0
T13	85245	0	0	0
T14	5408	1	0	0
T15	25052	0	0	0
T16	8568	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	574	0	0
T1	28793	1	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T4	0	1	0	0
T7	505317	1	0	0
T8	529467	1	0	0
T9	134512	0	0	0
T13	85245	0	0	0
T14	5408	1	0	0
T15	25052	0	0	0
T16	8568	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	685	0	0
T1	28793	1	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T4	0	1	0	0
T5	0	5	0	0
T6	0	2	0	0
T7	505317	0	0	0
T8	529467	0	0	0
T9	134512	0	0	0
T13	85245	0	0	0
T14	5408	0	0	0
T15	25052	6	0	0
T16	8568	0	0	0
T25	0	2	0	0
T26	0	9	0	0
T30	0	5	0	0
T31	0	1	0	0
T37	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	92393	0	0
T1	28793	231	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T4	0	59	0	0
T5	0	578	0	0
T6	0	52	0	0
T7	505317	0	0	0
T8	529467	0	0	0
T9	134512	0	0	0
T13	85245	0	0	0
T14	5408	0	0	0
T15	25052	2939	0	0
T16	8568	0	0	0
T25	0	26	0	0
T26	0	687	0	0
T30	0	553	0	0
T31	0	71	0	0
T37	0	149	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	578	0	0
T1	28793	1	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T5	0	3	0	0
T6	0	1	0	0
T7	505317	0	0	0
T8	529467	0	0	0
T9	134512	0	0	0
T13	85245	0	0	0
T14	5408	0	0	0
T15	25052	6	0	0
T16	8568	0	0	0
T26	0	8	0	0
T30	0	3	0	0
T31	0	1	0	0
T46	0	25	0	0
T67	0	5	0	0
T70	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	81	0	0
T4	368708	1	0	0
T5	851159	0	0	0
T6	846499	0	0	0
T17	522625	0	0	0
T21	239477	0	0	0
T22	162273	0	0	0
T25	6976	2	0	0
T30	348572	2	0	0
T37	0	1	0	0
T44	30622	0	0	0
T51	0	2	0	0
T55	0	2	0	0
T62	5464	0	0	0
T69	0	1	0	0
T71	0	3	0	0
T76	0	1	0	0
T79	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	1114	0	0
T10	20707	154	0	0
T11	0	316	0	0
T12	0	318	0	0
T18	502964	0	0	0
T19	958725	0	0	0
T34	0	150	0	0
T35	0	176	0	0
T36	1949	0	0	0
T37	36650	0	0	0
T38	65932	0	0	0
T39	4687	0	0	0
T40	27154	0	0	0
T41	141184	0	0	0
T42	225906	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	904	0	0
T10	20707	124	0	0
T11	0	256	0	0
T12	0	258	0	0
T18	502964	0	0	0
T19	958725	0	0	0
T34	0	120	0	0
T35	0	146	0	0
T36	1949	0	0	0
T37	36650	0	0	0
T38	65932	0	0	0
T39	4687	0	0	0
T40	27154	0	0	0
T41	141184	0	0	0
T42	225906	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719178059	719107124	0	0
T1	28793	28718	0	0
T2	525760	525692	0	0
T3	18177	18086	0	0
T7	505317	505311	0	0
T8	529467	529458	0	0
T9	134512	134503	0	0
T13	85245	85169	0	0
T14	5408	5351	0	0
T15	25052	24977	0	0
T16	8568	8481	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	719164917	0	0
T1	28793	28718	0	0
T2	525760	525692	0	0
T3	18177	18086	0	0
T7	505317	505311	0	0
T8	529467	529458	0	0
T9	134512	134503	0	0
T13	85245	85169	0	0
T14	5408	5351	0	0
T15	25052	24977	0	0
T16	8568	8481	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T7,T15
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T15

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T7,T15,T9

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T15
1	0	1	Covered	T7,T8,T9
1	1	0	Covered	T1,T25,T4
1	1	1	Covered	T1,T5,T6

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T5,T30,T37
1	0	Covered	T6,T46,T49

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T5,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T46,T49

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Not Covered
1	1	Covered	T5,T30,T37

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T15,T9,T4
1	Covered	T5,T6,T63

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T15,T9,T5
1	Covered	T4,T5,T30

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T15,T4,T5
1	Covered	T9,T5,T6

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T9,T4,T5
1	Covered	T15,T22,T30

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T9,T5,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T15,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T15,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T15,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T15,T9,T4
Phase1St	198	Covered	T15,T9,T4
Phase2St	215	Covered	T15,T9,T4
Phase3St	233	Covered	T15,T9,T4
TerminalSt	249	Covered	T15,T9,T4
TimeoutSt	159	Covered	T1,T5,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T15,T9,T4
IdleSt->TimeoutSt	159	Covered	T1,T5,T6
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T4,T29,T73
Phase0St->Phase1St	198	Covered	T15,T9,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T30,T91,T92
Phase1St->Phase2St	215	Covered	T15,T9,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T30,T33,T49
Phase2St->Phase3St	233	Covered	T15,T9,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T30,T32,T33
Phase3St->TerminalSt	249	Covered	T15,T9,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T5,T6,T22
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T6,T30
TimeoutSt->Phase0St	172	Covered	T5,T6,T30

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T15,T9
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T30
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T30
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T29,T73
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T15,T9,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T15,T9,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T30,T91,T92
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T15,T9,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T15,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T30,T33,T49
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T15,T9,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T15,T9,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T30,T32,T33
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T15,T9,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T15,T9,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T22,T30
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T15,T9,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	719324539	187	0	0
CheckAccumTrig0_A	719324539	510	0	0
CheckAccumTrig1_A	719324539	22	0	0
CheckClr_A	719324539	224	0	0
CheckEn_A	719179341	327072314	0	0
CheckPhase0_A	719324539	584	0	0
CheckPhase1_A	719324539	578	0	0
CheckPhase2_A	719324539	567	0	0
CheckPhase3_A	719324539	558	0	0
CheckTimeout0_A	719324539	1096	0	0
CheckTimeoutSt1_A	719324539	125161	0	0
CheckTimeoutSt2_A	719324539	1013	0	0
CheckTimeoutStTrig_A	719324539	61	0	0
ErrorStAllEscAsserted_A	719324539	1154	0	0
ErrorStIsTerminal_A	719324539	944	0	0
EscStateOut_A	719178059	719107124	0	0
u_state_regs_A	719324539	719164917	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	187	0	0
T10	20707	19	0	0
T11	0	65	0	0
T12	0	47	0	0
T18	502964	0	0	0
T19	958725	0	0	0
T34	0	31	0	0
T35	0	25	0	0
T36	1949	0	0	0
T37	36650	0	0	0
T38	65932	0	0	0
T39	4687	0	0	0
T40	27154	0	0	0
T41	141184	0	0	0
T42	225906	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	510	0	0
T4	368708	2	0	0
T5	0	4	0	0
T6	0	1	0	0
T8	529467	0	0	0
T9	134512	1	0	0
T15	25052	1	0	0
T17	0	1	0	0
T20	213483	0	0	0
T21	239477	0	0	0
T22	0	2	0	0
T23	217307	0	0	0
T24	136534	0	0	0
T25	6976	0	0	0
T30	0	9	0	0
T43	0	1	0	0
T44	30622	0	0	0
T63	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	22	0	0
T6	846499	1	0	0
T10	20707	0	0	0
T17	522625	0	0	0
T22	162273	0	0	0
T26	484650	0	0	0
T30	348572	0	0	0
T31	107356	0	0	0
T43	112814	0	0	0
T46	0	1	0	0
T49	0	1	0	0
T56	0	1	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	5464	0	0	0
T63	390072	0	0	0
T93	0	2	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	3	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	224	0	0
T4	368708	1	0	0
T5	851159	0	0	0
T6	846499	1	0	0
T17	522625	0	0	0
T22	162273	1	0	0
T30	348572	5	0	0
T31	107356	0	0	0
T32	0	1	0	0
T33	0	4	0	0
T43	112814	0	0	0
T46	0	3	0	0
T62	5464	0	0	0
T63	390072	1	0	0
T65	0	1	0	0
T66	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719179341	327072314	0	0
T1	28793	26174	0	0
T2	525760	525691	0	0
T3	18177	17145	0	0
T7	505317	503636	0	0
T8	529467	528292	0	0
T9	134512	22779	0	0
T13	85245	85168	0	0
T14	5408	3586	0	0
T15	25052	3423	0	0
T16	8568	8480	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	584	0	0
T4	368708	1	0	0
T5	0	5	0	0
T6	0	2	0	0
T8	529467	0	0	0
T9	134512	1	0	0
T15	25052	1	0	0
T17	0	1	0	0
T20	213483	0	0	0
T21	239477	0	0	0
T22	0	2	0	0
T23	217307	0	0	0
T24	136534	0	0	0
T25	6976	0	0	0
T30	0	10	0	0
T43	0	1	0	0
T44	30622	0	0	0
T63	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	578	0	0
T4	368708	1	0	0
T5	0	5	0	0
T6	0	2	0	0
T8	529467	0	0	0
T9	134512	1	0	0
T15	25052	1	0	0
T17	0	1	0	0
T20	213483	0	0	0
T21	239477	0	0	0
T22	0	2	0	0
T23	217307	0	0	0
T24	136534	0	0	0
T25	6976	0	0	0
T30	0	9	0	0
T43	0	1	0	0
T44	30622	0	0	0
T63	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	567	0	0
T4	368708	1	0	0
T5	0	5	0	0
T6	0	2	0	0
T8	529467	0	0	0
T9	134512	1	0	0
T15	25052	1	0	0
T17	0	1	0	0
T20	213483	0	0	0
T21	239477	0	0	0
T22	0	2	0	0
T23	217307	0	0	0
T24	136534	0	0	0
T25	6976	0	0	0
T30	0	8	0	0
T43	0	1	0	0
T44	30622	0	0	0
T63	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	558	0	0
T4	368708	1	0	0
T5	0	5	0	0
T6	0	2	0	0
T8	529467	0	0	0
T9	134512	1	0	0
T15	25052	1	0	0
T17	0	1	0	0
T20	213483	0	0	0
T21	239477	0	0	0
T22	0	2	0	0
T23	217307	0	0	0
T24	136534	0	0	0
T25	6976	0	0	0
T30	0	7	0	0
T43	0	1	0	0
T44	30622	0	0	0
T63	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	1096	0	0
T1	28793	1	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T5	0	1	0	0
T6	0	8	0	0
T7	505317	0	0	0
T8	529467	0	0	0
T9	134512	0	0	0
T13	85245	0	0	0
T14	5408	0	0	0
T15	25052	0	0	0
T16	8568	0	0	0
T30	0	4	0	0
T37	0	1	0	0
T46	0	3	0	0
T48	0	2	0	0
T67	0	1	0	0
T68	0	2	0	0
T69	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	125161	0	0
T1	28793	295	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T5	0	148	0	0
T6	0	2234	0	0
T7	505317	0	0	0
T8	529467	0	0	0
T9	134512	0	0	0
T13	85245	0	0	0
T14	5408	0	0	0
T15	25052	0	0	0
T16	8568	0	0	0
T30	0	511	0	0
T37	0	679	0	0
T46	0	461	0	0
T48	0	477	0	0
T67	0	116	0	0
T68	0	133	0	0
T69	0	566	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	1013	0	0
T1	28793	1	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T6	0	7	0	0
T7	505317	0	0	0
T8	529467	0	0	0
T9	134512	0	0	0
T13	85245	0	0	0
T14	5408	0	0	0
T15	25052	0	0	0
T16	8568	0	0	0
T30	0	3	0	0
T46	0	2	0	0
T48	0	1	0	0
T50	0	2	0	0
T68	0	2	0	0
T69	0	5	0	0
T71	0	2	0	0
T72	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	61	0	0
T5	851159	1	0	0
T6	846499	0	0	0
T17	522625	0	0	0
T22	162273	0	0	0
T26	484650	0	0	0
T30	348572	1	0	0
T31	107356	0	0	0
T37	0	1	0	0
T43	112814	0	0	0
T48	0	1	0	0
T55	0	2	0	0
T62	5464	0	0	0
T63	390072	0	0	0
T67	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	1154	0	0
T10	20707	156	0	0
T11	0	334	0	0
T12	0	338	0	0
T18	502964	0	0	0
T19	958725	0	0	0
T34	0	142	0	0
T35	0	184	0	0
T36	1949	0	0	0
T37	36650	0	0	0
T38	65932	0	0	0
T39	4687	0	0	0
T40	27154	0	0	0
T41	141184	0	0	0
T42	225906	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	944	0	0
T10	20707	126	0	0
T11	0	274	0	0
T12	0	278	0	0
T18	502964	0	0	0
T19	958725	0	0	0
T34	0	112	0	0
T35	0	154	0	0
T36	1949	0	0	0
T37	36650	0	0	0
T38	65932	0	0	0
T39	4687	0	0	0
T40	27154	0	0	0
T41	141184	0	0	0
T42	225906	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719178059	719107124	0	0
T1	28793	28718	0	0
T2	525760	525692	0	0
T3	18177	18086	0	0
T7	505317	505311	0	0
T8	529467	529458	0	0
T9	134512	134503	0	0
T13	85245	85169	0	0
T14	5408	5351	0	0
T15	25052	24977	0	0
T16	8568	8481	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	719164917	0	0
T1	28793	28718	0	0
T2	525760	525692	0	0
T3	18177	18086	0	0
T7	505317	505311	0	0
T8	529467	529458	0	0
T9	134512	134503	0	0
T13	85245	85169	0	0
T14	5408	5351	0	0
T15	25052	24977	0	0
T16	8568	8481	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T7,T15
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T15

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T15

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T15
1	0	1	Covered	T2,T7,T24
1	1	0	Covered	T15,T5,T6
1	1	1	Covered	T1,T4,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T5,T30,T26
1	0	Covered	T5,T30,T26

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T30,T26

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T27
1	1	Covered	T5,T30,T26

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T15,T9
1	Covered	T1,T5,T22

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T9
1	Covered	T7,T5,T30

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T4
1	Covered	T15,T9,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T15
1	Covered	T4,T5,T30

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T15,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T7,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T5,T22

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T7,T15
Phase1St	198	Covered	T1,T7,T15
Phase2St	215	Covered	T1,T7,T15
Phase3St	233	Covered	T1,T7,T15
TerminalSt	249	Covered	T1,T7,T15
TimeoutSt	159	Covered	T1,T4,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T7,T15
IdleSt->TimeoutSt	159	Covered	T1,T4,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T61,T97,T98
Phase0St->Phase1St	198	Covered	T1,T7,T15
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T48,T99,T100
Phase1St->Phase2St	215	Covered	T1,T7,T15
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T5,T101,T52
Phase2St->Phase3St	233	Covered	T1,T7,T15
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T60,T102,T61
Phase3St->TerminalSt	249	Covered	T1,T7,T15
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T5,T30
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T4,T5
TimeoutSt->Phase0St	172	Covered	T5,T30,T26

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T30,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T61,T97,T98
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T7,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T7,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T48,T99,T100
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T7,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T7,T15,T9
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T101,T52
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T7,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T7,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T60,T102,T61
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T7,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T7,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T5,T30
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T7,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	719324539	221	0	0
CheckAccumTrig0_A	719324539	533	0	0
CheckAccumTrig1_A	719324539	21	0	0
CheckClr_A	719324539	252	0	0
CheckEn_A	719179341	312848231	0	0
CheckPhase0_A	719324539	620	0	0
CheckPhase1_A	719324539	608	0	0
CheckPhase2_A	719324539	595	0	0
CheckPhase3_A	719324539	587	0	0
CheckTimeout0_A	719324539	588	0	0
CheckTimeoutSt1_A	719324539	83696	0	0
CheckTimeoutSt2_A	719324539	491	0	0
CheckTimeoutStTrig_A	719324539	76	0	0
ErrorStAllEscAsserted_A	719324539	1162	0	0
ErrorStIsTerminal_A	719324539	952	0	0
EscStateOut_A	719178059	719107124	0	0
u_state_regs_A	719324539	719164917	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	221	0	0
T10	20707	34	0	0
T11	0	66	0	0
T12	0	66	0	0
T18	502964	0	0	0
T19	958725	0	0	0
T34	0	32	0	0
T35	0	23	0	0
T36	1949	0	0	0
T37	36650	0	0	0
T38	65932	0	0	0
T39	4687	0	0	0
T40	27154	0	0	0
T41	141184	0	0	0
T42	225906	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	533	0	0
T1	28793	4	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T4	0	1	0	0
T5	0	6	0	0
T7	505317	1	0	0
T8	529467	0	0	0
T9	134512	1	0	0
T13	85245	0	0	0
T14	5408	0	0	0
T15	25052	1	0	0
T16	8568	0	0	0
T22	0	1	0	0
T30	0	6	0	0
T43	0	4	0	0
T63	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	21	0	0
T5	851159	1	0	0
T6	846499	0	0	0
T17	522625	0	0	0
T22	162273	0	0	0
T26	484650	1	0	0
T30	348572	1	0	0
T31	107356	0	0	0
T43	112814	0	0	0
T48	0	1	0	0
T53	0	1	0	0
T61	0	2	0	0
T62	5464	0	0	0
T63	390072	0	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	252	0	0
T1	28793	3	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T5	0	4	0	0
T7	505317	0	0	0
T8	529467	0	0	0
T9	134512	0	0	0
T13	85245	0	0	0
T14	5408	0	0	0
T15	25052	0	0	0
T16	8568	0	0	0
T26	0	3	0	0
T30	0	5	0	0
T43	0	3	0	0
T46	0	6	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	4	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719179341	312848231	0	0
T1	28793	7532	0	0
T2	525760	513131	0	0
T3	18177	17130	0	0
T7	505317	14742	0	0
T8	529467	529458	0	0
T9	134512	603	0	0
T13	85245	85168	0	0
T14	5408	3605	0	0
T15	25052	6508	0	0
T16	8568	8480	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	620	0	0
T1	28793	4	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T4	0	1	0	0
T5	0	9	0	0
T7	505317	1	0	0
T8	529467	0	0	0
T9	134512	1	0	0
T13	85245	0	0	0
T14	5408	0	0	0
T15	25052	1	0	0
T16	8568	0	0	0
T22	0	1	0	0
T30	0	8	0	0
T43	0	4	0	0
T63	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	608	0	0
T1	28793	4	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T4	0	1	0	0
T5	0	9	0	0
T7	505317	1	0	0
T8	529467	0	0	0
T9	134512	1	0	0
T13	85245	0	0	0
T14	5408	0	0	0
T15	25052	1	0	0
T16	8568	0	0	0
T22	0	1	0	0
T30	0	8	0	0
T43	0	4	0	0
T63	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	595	0	0
T1	28793	4	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T4	0	1	0	0
T5	0	8	0	0
T7	505317	1	0	0
T8	529467	0	0	0
T9	134512	1	0	0
T13	85245	0	0	0
T14	5408	0	0	0
T15	25052	1	0	0
T16	8568	0	0	0
T22	0	1	0	0
T30	0	8	0	0
T43	0	4	0	0
T63	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	587	0	0
T1	28793	4	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T4	0	1	0	0
T5	0	8	0	0
T7	505317	1	0	0
T8	529467	0	0	0
T9	134512	1	0	0
T13	85245	0	0	0
T14	5408	0	0	0
T15	25052	1	0	0
T16	8568	0	0	0
T22	0	1	0	0
T30	0	8	0	0
T43	0	4	0	0
T63	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	588	0	0
T1	28793	2	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T4	0	1	0	0
T5	0	4	0	0
T6	0	1	0	0
T7	505317	0	0	0
T8	529467	0	0	0
T9	134512	0	0	0
T13	85245	0	0	0
T14	5408	0	0	0
T15	25052	0	0	0
T16	8568	0	0	0
T26	0	14	0	0
T29	0	1	0	0
T30	0	2	0	0
T32	0	1	0	0
T46	0	23	0	0
T68	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	83696	0	0
T1	28793	194	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T4	0	51	0	0
T5	0	909	0	0
T6	0	483	0	0
T7	505317	0	0	0
T8	529467	0	0	0
T9	134512	0	0	0
T13	85245	0	0	0
T14	5408	0	0	0
T15	25052	0	0	0
T16	8568	0	0	0
T26	0	2369	0	0
T29	0	141	0	0
T30	0	130	0	0
T32	0	213	0	0
T46	0	2857	0	0
T68	0	80	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	491	0	0
T1	28793	2	0	0
T2	525760	0	0	0
T3	18177	0	0	0
T4	0	1	0	0
T5	0	1	0	0
T6	0	1	0	0
T7	505317	0	0	0
T8	529467	0	0	0
T9	134512	0	0	0
T13	85245	0	0	0
T14	5408	0	0	0
T15	25052	0	0	0
T16	8568	0	0	0
T26	0	12	0	0
T29	0	1	0	0
T32	0	1	0	0
T46	0	22	0	0
T110	0	4	0	0
T111	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	76	0	0
T5	851159	2	0	0
T6	846499	0	0	0
T17	522625	0	0	0
T22	162273	0	0	0
T26	484650	1	0	0
T30	348572	1	0	0
T31	107356	0	0	0
T43	112814	0	0	0
T46	0	1	0	0
T51	0	1	0	0
T62	5464	0	0	0
T63	390072	0	0	0
T68	0	1	0	0
T72	0	1	0	0
T75	0	1	0	0
T110	0	1	0	0
T112	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	1162	0	0
T10	20707	185	0	0
T11	0	320	0	0
T12	0	326	0	0
T18	502964	0	0	0
T19	958725	0	0	0
T34	0	179	0	0
T35	0	152	0	0
T36	1949	0	0	0
T37	36650	0	0	0
T38	65932	0	0	0
T39	4687	0	0	0
T40	27154	0	0	0
T41	141184	0	0	0
T42	225906	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	952	0	0
T10	20707	155	0	0
T11	0	260	0	0
T12	0	266	0	0
T18	502964	0	0	0
T19	958725	0	0	0
T34	0	149	0	0
T35	0	122	0	0
T36	1949	0	0	0
T37	36650	0	0	0
T38	65932	0	0	0
T39	4687	0	0	0
T40	27154	0	0	0
T41	141184	0	0	0
T42	225906	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719178059	719107124	0	0
T1	28793	28718	0	0
T2	525760	525692	0	0
T3	18177	18086	0	0
T7	505317	505311	0	0
T8	529467	529458	0	0
T9	134512	134503	0	0
T13	85245	85169	0	0
T14	5408	5351	0	0
T15	25052	24977	0	0
T16	8568	8481	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719324539	719164917	0	0
T1	28793	28718	0	0
T2	525760	525692	0	0
T3	18177	18086	0	0
T7	505317	505311	0	0
T8	529467	529458	0	0
T9	134512	134503	0	0
T13	85245	85169	0	0
T14	5408	5351	0	0
T15	25052	24977	0	0
T16	8568	8481	0	0