Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	76749	1			T3	1		T20	11		T5	6
class_i[0x1]	42384	1			T3	8		T13	2		T44	862
class_i[0x2]	75587	1			T20	2347		T46	37		T69	5
class_i[0x3]	60948	1			T1	12		T46	20		T16	244

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	65690	1			T3	3		T13	1		T20	902
alert[0x1]	63109	1			T1	7		T3	2		T13	1
alert[0x2]	63383	1			T1	5		T3	2		T20	1410
alert[0x3]	63486	1			T3	2		T20	45		T5	5

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

255396

1

T1

12

T3

2

T20

2358

esc_ping_fail

272

1

T3

7

T13

2

T16

4

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	65618	1			T3	2		T20	902		T44	8
esc_integrity_fail	alert[0x1]	63055	1			T1	7		T20	1		T44	10
esc_integrity_fail	alert[0x2]	63294	1			T1	5		T20	1410		T5	1
esc_integrity_fail	alert[0x3]	63429	1			T20	45		T5	5		T44	9
esc_ping_fail	alert[0x0]	72	1			T3	1		T13	1		T16	1
esc_ping_fail	alert[0x1]	54	1			T3	2		T13	1		T16	2
esc_ping_fail	alert[0x2]	89	1			T3	2		T15	1		T66	3
esc_ping_fail	alert[0x3]	57	1			T3	2		T16	1		T15	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	76664	1			T20	11		T5	6		T46	16
esc_integrity_fail	class_i[0x1]	42313	1			T3	2		T44	862		T16	111
esc_integrity_fail	class_i[0x2]	75529	1			T20	2347		T46	37		T69	5
esc_integrity_fail	class_i[0x3]	60890	1			T1	12		T46	20		T16	244
esc_ping_fail	class_i[0x0]	85	1			T3	1		T15	1		T229	7
esc_ping_fail	class_i[0x1]	71	1			T3	6		T13	2		T16	4
esc_ping_fail	class_i[0x2]	58	1			T15	1		T207	4		T304	10
esc_ping_fail	class_i[0x3]	58	1			T15	1		T302	8		T305	1