Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	694191115	0	0	627
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	694191115	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	694191115	694019659	0	0
tb.dut.CheckAccuCntDw	0	0	627	627	0	0
tb.dut.CheckEscCntDw	0	0	627	627	0	0
tb.dut.CheckNAlerts	0	0	627	627	0	0
tb.dut.CheckNClasses	0	0	627	627	0	0
tb.dut.CheckNEscSev	0	0	627	627	0	0
tb.dut.CrashdumpKnownO_A	0	0	694191115	694019659	0	0
tb.dut.EdnKnownO_A	0	0	694191115	694019659	0	0
tb.dut.EscPKnownO_A	0	0	694191115	694019659	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	694191115	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	694191115	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	694191115	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	694191115	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	694191115	80	0	0
tb.dut.IrqAKnownO_A	0	0	694191115	694019659	0	0
tb.dut.IrqBKnownO_A	0	0	694191115	694019659	0	0
tb.dut.IrqCKnownO_A	0	0	694191115	694019659	0	0
tb.dut.IrqDKnownO_A	0	0	694191115	694019659	0	0
tb.dut.TlAReadyKnownO_A	0	0	694191115	694019659	0	0
tb.dut.TlDValidKnownO_A	0	0	694191115	694019659	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	718259567	3726075	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	718259567	13852	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	718259567	12730	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	718259567	12721	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	718259567	12683	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	718259567	12620	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	718259567	12781	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	718259567	12572	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	718259567	14360	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	718259567	12760	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	718259567	12890	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	718259567	13492	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	718259567	12680	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	718259567	12657	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	718259567	12870	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	718259567	13001	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	718259567	12594	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	718259567	12605	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	718259567	13927	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	718259567	12814	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	718259567	12450	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	718259567	13870	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	718259567	12709	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	718259567	12609	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	718259567	13697	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	718259567	14070	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	718259567	12786	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	718259567	12904	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	718259567	12822	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	718259567	12697	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	718259567	12828	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	718259567	12616	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	718259567	12839	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	718259567	13930	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	718259567	12932	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	718259567	12749	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	718259567	12792	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	718259567	12858	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	718259567	12785	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	718259567	12834	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	718259567	13748	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	718259567	12795	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	718259567	12809	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	718259567	12856	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	718259567	12794	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	718259567	12941	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	718259567	12554	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	718259567	12985	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	718259567	13934	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	718259567	12923	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	718259567	13931	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	718259567	12615	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	718259567	12999	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	718259567	12810	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	718259567	12371	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	718259567	13582	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	718259567	14089	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	718259567	12722	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	718259567	12251	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	718259567	12599	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	718259567	13116	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	718259567	12828	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	718259567	12837	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	718259567	13937	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	718259567	14009	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	718259567	13909	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	718259567	13858	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	718259567	12850	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	718259567	12750	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	718259567	12730	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	718259567	24742	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	718259567	12857	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	718259567	12943	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	718259567	13758	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	718259567	12993	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	718259567	12821	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	718259567	12572	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	718259567	13734	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	718259567	14051	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	694191115	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	694191115	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	694191115	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	694191115	4896	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	694191115	218999	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	694191115	346246194	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	694191115	220	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	694191115	849	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	694191115	36	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	694191115	408	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	694058875	224249516	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	694191115	945	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	694191115	922	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	694191115	909	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	694191115	891	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	694191115	1182	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	694191115	112548	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	694191115	1069	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	694191115	74	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	694191115	1341	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	694191115	1101	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	694057524	693988317	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	627	627	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	694191115	694019659	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	694191115	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	694191115	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	694191115	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	694191115	2907	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	694191115	169373	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	694191115	405372064	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	694191115	198	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	694191115	462	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	694191115	26	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	694191115	204	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	694058875	315326743	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	694191115	534	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	694191115	526	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	694191115	519	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	694191115	505	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	694191115	1578	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	694191115	170619	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	694191115	1496	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	694191115	55	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	694191115	1264	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	694191115	1024	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	694057524	693988317	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	627	627	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	694191115	694019659	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	694191115	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	694191115	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	694191115	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	694191115	3051	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	694191115	195190	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	694191115	414648658	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	694191115	225	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	694191115	512	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	694191115	16	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	694191115	220	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	694058875	323792714	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	694191115	596	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	694191115	588	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	694191115	576	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	694191115	565	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	694191115	1009	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	694191115	139073	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	694191115	915	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	694191115	78	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	694191115	1305	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	694191115	1065	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	694057524	693988317	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	627	627	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	694191115	694019659	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	694191115	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	694191115	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	694191115	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	694191115	3550	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	694191115	213368	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	694191115	377732187	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	694191115	204	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	694191115	499	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	694191115	32	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	694191115	241	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	694058875	305301950	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	694191115	597	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	694191115	584	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	694191115	577	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	694191115	566	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	694191115	1013	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	694191115	128655	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	694191115	909	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	694191115	72	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	694191115	1234	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	694191115	994	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	694057524	693988317	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	627	627	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	694191115	694019659	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	718259567	144456428	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	718259567	717574016	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	718259567	717574016	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	718259567	188868794	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	718259567	717574016	0	0
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tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	832	832	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	832	832	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	832	832	0	0

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