Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	74	1			T16	3		T23	2		T24	2
class_index[0x1]	55	1			T20	2		T5	1		T16	2
class_index[0x2]	78	1			T5	1		T16	5		T70	1
class_index[0x3]	72	1			T20	2		T46	2		T16	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	105	1			T20	1		T5	1		T16	1
intr_timeout_cnt[1]	75	1			T16	3		T70	1		T65	1
intr_timeout_cnt[2]	19	1			T5	1		T46	1		T16	1
intr_timeout_cnt[3]	12	1			T24	1		T88	1		T240	1
intr_timeout_cnt[4]	14	1			T46	1		T78	1		T49	1
intr_timeout_cnt[5]	12	1			T20	1		T76	1		T82	1
intr_timeout_cnt[6]	12	1			T20	2		T84	1		T241	1
intr_timeout_cnt[7]	8	1			T87	2		T242	1		T243	1
intr_timeout_cnt[8]	10	1			T16	2		T23	1		T24	1
intr_timeout_cnt[9]	12	1			T16	5		T76	1		T117	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	32	1			T23	1		T81	1		T84	1
class_index[0x0]	intr_timeout_cnt[1]	17	1			T16	2		T54	1		T83	1
class_index[0x0]	intr_timeout_cnt[2]	3	1			T24	1		T244	1		T245	1
class_index[0x0]	intr_timeout_cnt[3]	4	1			T24	1		T246	1		T234	2
class_index[0x0]	intr_timeout_cnt[4]	2	1			T49	1		T240	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	7	1			T82	1		T241	1		T247	1
class_index[0x0]	intr_timeout_cnt[7]	3	1			T242	1		T248	1		T249	1
class_index[0x0]	intr_timeout_cnt[8]	4	1			T16	1		T23	1		T87	1
class_index[0x0]	intr_timeout_cnt[9]	2	1			T241	1		T250	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	15	1			T5	1		T84	1		T25	1
class_index[0x1]	intr_timeout_cnt[1]	14	1			T16	1		T65	1		T26	2
class_index[0x1]	intr_timeout_cnt[2]	1	1			T78	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[3]	3	1			T240	1		T251	2		-	-
class_index[0x1]	intr_timeout_cnt[4]	5	1			T252	1		T247	2		T244	1
class_index[0x1]	intr_timeout_cnt[5]	3	1			T76	1		T180	1		T247	1
class_index[0x1]	intr_timeout_cnt[6]	8	1			T20	2		T84	1		T253	2
class_index[0x1]	intr_timeout_cnt[8]	4	1			T16	1		T24	1		T254	1
class_index[0x1]	intr_timeout_cnt[9]	2	1			T26	1		T238	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	37	1			T54	2		T86	1		T26	2
class_index[0x2]	intr_timeout_cnt[1]	20	1			T70	1		T84	1		T56	2
class_index[0x2]	intr_timeout_cnt[2]	2	1			T5	1		T255	1		-	-
class_index[0x2]	intr_timeout_cnt[3]	1	1			T256	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[4]	3	1			T84	1		T257	1		T258	1
class_index[0x2]	intr_timeout_cnt[5]	1	1			T103	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	2	1			T241	1		T247	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	5	1			T87	2		T243	1		T254	1
class_index[0x2]	intr_timeout_cnt[9]	7	1			T16	5		T76	1		T117	1
class_index[0x3]	intr_timeout_cnt[0]	21	1			T20	1		T16	1		T24	2
class_index[0x3]	intr_timeout_cnt[1]	24	1			T82	1		T56	1		T26	1
class_index[0x3]	intr_timeout_cnt[2]	13	1			T46	1		T16	1		T23	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T88	1		T103	1		T251	2
class_index[0x3]	intr_timeout_cnt[4]	4	1			T46	1		T78	1		T247	1
class_index[0x3]	intr_timeout_cnt[5]	1	1			T20	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	2	1			T234	1		T259	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T244	1		T260	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T261	1		-	-		-	-