Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	358674	1			T1	1785		T2	1797		T3	35
all_values[1]	358674	1			T1	1785		T2	1797		T3	35
all_values[2]	358674	1			T1	1785		T2	1797		T3	35
all_values[3]	358674	1			T1	1785		T2	1797		T3	35

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

714683

1

T1

3637

T2

3726

T10

29

auto[1]

720013

1

T1

3503

T2

3462

T3

140

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

846807

1

T1

3595

T2

3699

T3

122

auto[1]

587889

1

T1

3545

T2

3489

T3

18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	103108	1			T1	469		T2	480		T10	4
all_values[0]	auto[0]	auto[1]	75119	1			T1	463		T2	427		T10	3
all_values[0]	auto[1]	auto[0]	104799	1			T1	432		T2	474		T3	34
all_values[0]	auto[1]	auto[1]	75648	1			T1	421		T2	416		T3	1
all_values[1]	auto[0]	auto[0]	107720	1			T1	465		T2	481		T10	11
all_values[1]	auto[0]	auto[1]	71528	1			T1	451		T2	456		T11	28
all_values[1]	auto[1]	auto[0]	108255	1			T1	439		T2	444		T3	28
all_values[1]	auto[1]	auto[1]	71171	1			T1	430		T2	416		T3	7
all_values[2]	auto[0]	auto[0]	104553	1			T1	454		T2	467		T10	2
all_values[2]	auto[0]	auto[1]	74199	1			T1	453		T2	465		T11	29
all_values[2]	auto[1]	auto[0]	105571	1			T1	441		T2	433		T3	34
all_values[2]	auto[1]	auto[1]	74351	1			T1	437		T2	432		T3	1
all_values[3]	auto[0]	auto[0]	105755	1			T1	442		T2	491		T10	9
all_values[3]	auto[0]	auto[1]	72701	1			T1	440		T2	459		T11	37
all_values[3]	auto[1]	auto[0]	107046	1			T1	453		T2	429		T3	26
all_values[3]	auto[1]	auto[1]	73172	1			T1	450		T2	418		T3	9