Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	358674	1			T1	1785		T2	1797		T3	35
all_pins[1]	358674	1			T1	1785		T2	1797		T3	35
all_pins[2]	358674	1			T1	1785		T2	1797		T3	35
all_pins[3]	358674	1			T1	1785		T2	1797		T3	35

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1140354	1			T1	5402		T2	5506		T3	122
values[0x1]	294342	1			T1	1738		T2	1682		T3	18
transitions[0x0=>0x1]	194834	1			T1	1102		T2	1089		T3	17
transitions[0x1=>0x0]	195082	1			T1	1103		T2	1089		T3	17

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	283026	1			T1	1364		T2	1381		T3	34
all_pins[0]	values[0x1]	75648	1			T1	421		T2	416		T3	1
all_pins[0]	transitions[0x0=>0x1]	74907	1			T1	420		T2	416		T3	1
all_pins[0]	transitions[0x1=>0x0]	72679	1			T1	450		T2	418		T3	9
all_pins[1]	values[0x0]	287503	1			T1	1355		T2	1381		T3	28
all_pins[1]	values[0x1]	71171	1			T1	430		T2	416		T3	7
all_pins[1]	transitions[0x0=>0x1]	38607	1			T1	231		T2	225		T3	6
all_pins[1]	transitions[0x1=>0x0]	43084	1			T1	222		T2	225		T10	3
all_pins[2]	values[0x0]	284323	1			T1	1348		T2	1365		T3	34
all_pins[2]	values[0x1]	74351	1			T1	437		T2	432		T3	1
all_pins[2]	transitions[0x0=>0x1]	41537	1			T1	223		T2	234		T3	1
all_pins[2]	transitions[0x1=>0x0]	38357	1			T1	216		T2	218		T3	7
all_pins[3]	values[0x0]	285502	1			T1	1335		T2	1379		T3	26
all_pins[3]	values[0x1]	73172	1			T1	450		T2	418		T3	9
all_pins[3]	transitions[0x0=>0x1]	39783	1			T1	228		T2	214		T3	9
all_pins[3]	transitions[0x1=>0x0]	40962	1			T1	215		T2	228		T3	1