Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	89886	1			T1	682		T2	1027		T5	1355
accum_cnt_1000	228528	1			T1	577		T2	1513		T11	83
accum_cnt_100	26145	1			T1	35		T2	77		T11	78
accum_cnt_50	65188	1			T1	27		T2	54		T10	2
accum_cnt_10	209944	1			T1	1323		T2	2749		T3	68
accum_cnt_0	402179	1			T1	1329		T2	16		T3	36

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	265496	1			T1	1323		T2	1359		T3	26
class_index[0x1]	265496	1			T1	1323		T2	1359		T3	26
class_index[0x2]	265496	1			T1	1323		T2	1359		T3	26
class_index[0x3]	265496	1			T1	1323		T2	1359		T3	26

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	22405	1			T6	488		T16	247		T24	251
class_index[0x0]	accum_cnt_1000	59526	1			T11	19		T5	78		T80	2
class_index[0x0]	accum_cnt_100	7408	1			T11	20		T5	49		T79	15
class_index[0x0]	accum_cnt_50	20002	1			T10	2		T11	20		T5	62
class_index[0x0]	accum_cnt_10	58336	1			T1	1319		T2	1355		T3	24
class_index[0x0]	accum_cnt_0	87487	1			T1	4		T2	4		T3	2
class_index[0x1]	accum_cnt_2000	21115	1			T2	485		T5	631		T14	396
class_index[0x1]	accum_cnt_1000	50206	1			T2	774		T11	18		T5	629
class_index[0x1]	accum_cnt_100	5775	1			T2	38		T11	22		T5	82
class_index[0x1]	accum_cnt_50	14692	1			T2	27		T11	17		T20	1
class_index[0x1]	accum_cnt_10	54782	1			T2	25		T3	19		T13	1
class_index[0x1]	accum_cnt_0	110664	1			T1	1323		T2	10		T3	7
class_index[0x2]	accum_cnt_2000	22725	1			T1	432		T17	654		T14	351
class_index[0x2]	accum_cnt_1000	58874	1			T1	389		T11	25		T20	3
class_index[0x2]	accum_cnt_100	6792	1			T1	23		T11	19		T22	21
class_index[0x2]	accum_cnt_50	13307	1			T1	14		T11	12		T22	17
class_index[0x2]	accum_cnt_10	54007	1			T2	1357		T3	25		T11	4
class_index[0x2]	accum_cnt_0	100117	1			T1	1		T2	2		T3	1
class_index[0x3]	accum_cnt_2000	23641	1			T1	250		T2	542		T5	724
class_index[0x3]	accum_cnt_1000	59922	1			T1	188		T2	739		T11	21
class_index[0x3]	accum_cnt_100	6170	1			T1	12		T2	39		T11	17
class_index[0x3]	accum_cnt_50	17187	1			T1	13		T2	27		T11	15
class_index[0x3]	accum_cnt_10	42819	1			T1	4		T2	12		T11	11
class_index[0x3]	accum_cnt_0	103911	1			T1	1		T3	26		T10	9