Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4536	1			T69	1		T16	72		T229	1
alert[0x1]	4960	1			T1	34		T3	1		T6	311
alert[0x2]	6751	1			T3	1		T6	123		T16	89
alert[0x3]	9512	1			T3	1		T46	2		T23	18
alert[0x4]	5983	1			T24	4		T15	1		T66	1
alert[0x5]	3251	1			T1	73		T3	1		T17	1
alert[0x6]	13111	1			T226	3		T78	3		T50	353
alert[0x7]	7128	1			T1	45		T17	3		T24	21
alert[0x8]	5487	1			T46	243		T16	633		T63	3
alert[0x9]	8020	1			T6	17		T23	90		T66	1
alert[0xa]	3575	1			T6	4		T23	1		T221	200
alert[0xb]	7566	1			T6	133		T16	705		T66	1
alert[0xc]	13374	1			T1	465		T6	100		T23	244
alert[0xd]	7718	1			T6	107		T23	2		T47	362
alert[0xe]	2477	1			T1	49		T23	23		T24	295
alert[0xf]	4909	1			T1	152		T13	1		T47	48
alert[0x10]	5520	1			T3	1		T23	134		T24	277
alert[0x11]	2123	1			T16	127		T23	2		T221	9
alert[0x12]	5609	1			T1	51		T6	653		T46	50
alert[0x13]	4313	1			T6	77		T16	36		T66	2
alert[0x14]	4641	1			T1	61		T229	1		T221	10
alert[0x15]	9619	1			T16	365		T23	1		T24	1
alert[0x16]	5367	1			T1	447		T46	399		T16	47
alert[0x17]	4149	1			T1	196		T6	8		T46	229
alert[0x18]	9656	1			T1	160		T6	293		T16	66
alert[0x19]	5651	1			T1	291		T50	400		T90	31
alert[0x1a]	3459	1			T1	601		T3	2		T6	139
alert[0x1b]	8183	1			T1	52		T46	497		T16	16
alert[0x1c]	7003	1			T6	530		T23	740		T47	280
alert[0x1d]	4997	1			T6	92		T46	53		T16	50
alert[0x1e]	5863	1			T3	1		T63	1		T76	5
alert[0x1f]	3442	1			T1	21		T46	188		T47	15
alert[0x20]	9312	1			T1	806		T24	124		T47	74
alert[0x21]	13620	1			T1	61		T5	2		T46	723
alert[0x22]	6798	1			T1	95		T6	265		T16	2
alert[0x23]	5455	1			T6	829		T47	72		T228	11
alert[0x24]	5457	1			T3	1		T6	17		T24	837
alert[0x25]	6200	1			T1	87		T6	21		T46	82
alert[0x26]	8181	1			T1	407		T5	4		T46	16
alert[0x27]	9311	1			T13	1		T23	3051		T229	1
alert[0x28]	5533	1			T6	82		T23	3		T15	1
alert[0x29]	3730	1			T6	84		T46	197		T16	252
alert[0x2a]	2938	1			T6	67		T23	48		T47	44
alert[0x2b]	7006	1			T1	11		T6	58		T16	14
alert[0x2c]	11779	1			T6	66		T16	42		T50	519
alert[0x2d]	20061	1			T3	1		T6	829		T75	1
alert[0x2e]	4683	1			T46	77		T23	34		T47	42
alert[0x2f]	9677	1			T1	90		T16	5		T23	2
alert[0x30]	9941	1			T1	227		T16	9		T23	11
alert[0x31]	4416	1			T1	8		T24	5		T66	1
alert[0x32]	12353	1			T1	513		T6	18		T46	2
alert[0x33]	3601	1			T1	94		T15	1		T66	1
alert[0x34]	6947	1			T1	272		T229	1		T221	285
alert[0x35]	2793	1			T1	32		T13	1		T6	21
alert[0x36]	9855	1			T46	11		T16	73		T47	1375
alert[0x37]	10264	1			T16	3		T24	29		T221	340
alert[0x38]	4507	1			T16	84		T66	1		T47	470
alert[0x39]	3644	1			T6	600		T16	15		T23	2
alert[0x3a]	6371	1			T1	304		T6	87		T23	1
alert[0x3b]	6155	1			T1	1194		T6	9		T24	58
alert[0x3c]	7497	1			T1	6		T6	95		T23	13
alert[0x3d]	9696	1			T46	85		T69	1		T229	1
alert[0x3e]	12438	1			T46	6		T16	209		T23	2
alert[0x3f]	2893	1			T1	4		T6	658		T75	1
alert[0x40]	4973	1			T24	85		T15	1		T66	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	118625	1			T13	1		T46	44		T69	1
class_i[0x1]	94504	1			T1	22		T13	2		T17	4
class_i[0x2]	77016	1			T1	23		T3	1		T46	2853
class_i[0x3]	155893	1			T1	6864		T3	9		T5	6

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

445356

1

T1

6909

T5

6

T17

4

alert_ping_fail

682

1

T3

10

T13

3

T15

7

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4527	1			T69	1		T16	72		T221	106
alert_integrity_fail	alert[0x1]	4955	1			T1	34		T6	311		T16	53
alert_integrity_fail	alert[0x2]	6737	1			T6	123		T16	89		T23	24
alert_integrity_fail	alert[0x3]	9498	1			T46	2		T23	18		T24	22
alert_integrity_fail	alert[0x4]	5971	1			T24	4		T28	6		T228	34
alert_integrity_fail	alert[0x5]	3239	1			T1	73		T17	1		T6	12
alert_integrity_fail	alert[0x6]	13100	1			T78	3		T50	353		T82	35
alert_integrity_fail	alert[0x7]	7111	1			T1	45		T17	3		T24	21
alert_integrity_fail	alert[0x8]	5476	1			T46	243		T16	633		T63	3
alert_integrity_fail	alert[0x9]	8009	1			T6	17		T23	90		T221	122
alert_integrity_fail	alert[0xa]	3566	1			T6	4		T23	1		T221	200
alert_integrity_fail	alert[0xb]	7554	1			T6	133		T16	705		T47	126
alert_integrity_fail	alert[0xc]	13360	1			T1	465		T6	100		T23	244
alert_integrity_fail	alert[0xd]	7710	1			T6	107		T23	2		T47	362
alert_integrity_fail	alert[0xe]	2468	1			T1	49		T23	23		T24	295
alert_integrity_fail	alert[0xf]	4891	1			T1	152		T47	48		T221	77
alert_integrity_fail	alert[0x10]	5509	1			T23	134		T24	277		T51	5
alert_integrity_fail	alert[0x11]	2112	1			T16	127		T23	2		T221	9
alert_integrity_fail	alert[0x12]	5595	1			T1	51		T6	653		T46	50
alert_integrity_fail	alert[0x13]	4299	1			T6	77		T16	36		T47	48
alert_integrity_fail	alert[0x14]	4629	1			T1	61		T221	10		T55	156
alert_integrity_fail	alert[0x15]	9602	1			T16	365		T23	1		T24	1
alert_integrity_fail	alert[0x16]	5357	1			T1	447		T46	399		T16	47
alert_integrity_fail	alert[0x17]	4138	1			T1	196		T6	8		T46	229
alert_integrity_fail	alert[0x18]	9642	1			T1	160		T6	293		T16	66
alert_integrity_fail	alert[0x19]	5643	1			T1	291		T50	400		T90	31
alert_integrity_fail	alert[0x1a]	3445	1			T1	601		T6	139		T46	98
alert_integrity_fail	alert[0x1b]	8177	1			T1	52		T46	497		T16	16
alert_integrity_fail	alert[0x1c]	6994	1			T6	530		T23	740		T47	280
alert_integrity_fail	alert[0x1d]	4992	1			T6	92		T46	53		T16	50
alert_integrity_fail	alert[0x1e]	5855	1			T63	1		T76	5		T228	70
alert_integrity_fail	alert[0x1f]	3432	1			T1	21		T46	188		T47	15
alert_integrity_fail	alert[0x20]	9302	1			T1	806		T24	124		T47	74
alert_integrity_fail	alert[0x21]	13610	1			T1	61		T5	2		T46	723
alert_integrity_fail	alert[0x22]	6782	1			T1	95		T6	265		T16	2
alert_integrity_fail	alert[0x23]	5444	1			T6	829		T47	72		T228	11
alert_integrity_fail	alert[0x24]	5450	1			T6	17		T24	837		T63	3
alert_integrity_fail	alert[0x25]	6193	1			T1	87		T6	21		T46	82
alert_integrity_fail	alert[0x26]	8164	1			T1	407		T5	4		T46	16
alert_integrity_fail	alert[0x27]	9298	1			T23	3051		T221	73		T78	1
alert_integrity_fail	alert[0x28]	5521	1			T6	82		T23	3		T90	82
alert_integrity_fail	alert[0x29]	3721	1			T6	84		T46	197		T16	252
alert_integrity_fail	alert[0x2a]	2928	1			T6	67		T23	48		T47	44
alert_integrity_fail	alert[0x2b]	6988	1			T1	11		T6	58		T16	14
alert_integrity_fail	alert[0x2c]	11770	1			T6	66		T16	42		T50	519
alert_integrity_fail	alert[0x2d]	20051	1			T6	829		T75	1		T93	37
alert_integrity_fail	alert[0x2e]	4675	1			T46	77		T23	34		T47	42
alert_integrity_fail	alert[0x2f]	9668	1			T1	90		T16	5		T23	2
alert_integrity_fail	alert[0x30]	9933	1			T1	227		T16	9		T23	11
alert_integrity_fail	alert[0x31]	4410	1			T1	8		T24	5		T221	396
alert_integrity_fail	alert[0x32]	12346	1			T1	513		T6	18		T46	2
alert_integrity_fail	alert[0x33]	3594	1			T1	94		T75	1		T228	5
alert_integrity_fail	alert[0x34]	6940	1			T1	272		T221	285		T280	1
alert_integrity_fail	alert[0x35]	2779	1			T1	32		T6	21		T46	1
alert_integrity_fail	alert[0x36]	9847	1			T46	11		T16	73		T47	1375
alert_integrity_fail	alert[0x37]	10252	1			T16	3		T24	29		T221	340
alert_integrity_fail	alert[0x38]	4499	1			T16	84		T47	470		T78	1
alert_integrity_fail	alert[0x39]	3632	1			T6	600		T16	15		T23	2
alert_integrity_fail	alert[0x3a]	6360	1			T1	304		T6	87		T23	1
alert_integrity_fail	alert[0x3b]	6144	1			T1	1194		T6	9		T24	58
alert_integrity_fail	alert[0x3c]	7488	1			T1	6		T6	95		T23	13
alert_integrity_fail	alert[0x3d]	9686	1			T46	85		T69	1		T75	1
alert_integrity_fail	alert[0x3e]	12431	1			T46	6		T16	209		T23	2
alert_integrity_fail	alert[0x3f]	2890	1			T1	4		T6	658		T75	1
alert_integrity_fail	alert[0x40]	4967	1			T24	85		T78	1		T52	5
alert_ping_fail	alert[0x0]	9	1			T229	1		T296	1		T297	1
alert_ping_fail	alert[0x1]	5	1			T3	1		T296	1		T298	2
alert_ping_fail	alert[0x2]	14	1			T3	1		T15	1		T229	1
alert_ping_fail	alert[0x3]	14	1			T3	1		T229	1		T296	1
alert_ping_fail	alert[0x4]	12	1			T15	1		T66	1		T296	1
alert_ping_fail	alert[0x5]	12	1			T3	1		T292	1		T297	1
alert_ping_fail	alert[0x6]	11	1			T226	3		T291	1		T299	1
alert_ping_fail	alert[0x7]	17	1			T15	1		T226	1		T300	1
alert_ping_fail	alert[0x8]	11	1			T207	2		T297	1		T291	2
alert_ping_fail	alert[0x9]	11	1			T66	1		T229	1		T301	1
alert_ping_fail	alert[0xa]	9	1			T292	1		T299	1		T302	1
alert_ping_fail	alert[0xb]	12	1			T66	1		T226	1		T303	1
alert_ping_fail	alert[0xc]	14	1			T300	1		T304	1		T218	1
alert_ping_fail	alert[0xd]	8	1			T304	1		T305	1		T298	1
alert_ping_fail	alert[0xe]	9	1			T229	1		T304	1		T302	1
alert_ping_fail	alert[0xf]	18	1			T13	1		T229	1		T226	1
alert_ping_fail	alert[0x10]	11	1			T3	1		T15	1		T226	1
alert_ping_fail	alert[0x11]	11	1			T296	1		T297	1		T306	1
alert_ping_fail	alert[0x12]	14	1			T297	2		T307	1		T304	1
alert_ping_fail	alert[0x13]	14	1			T66	2		T231	1		T308	2
alert_ping_fail	alert[0x14]	12	1			T229	1		T305	1		T303	1
alert_ping_fail	alert[0x15]	17	1			T292	2		T297	1		T309	1
alert_ping_fail	alert[0x16]	10	1			T296	1		T293	1		T297	1
alert_ping_fail	alert[0x17]	11	1			T226	1		T297	1		T308	1
alert_ping_fail	alert[0x18]	14	1			T207	1		T300	1		T304	1
alert_ping_fail	alert[0x19]	8	1			T296	1		T300	1		T303	1
alert_ping_fail	alert[0x1a]	14	1			T3	2		T226	1		T300	1
alert_ping_fail	alert[0x1b]	6	1			T229	2		T289	1		T309	1
alert_ping_fail	alert[0x1c]	9	1			T297	1		T301	1		T91	1
alert_ping_fail	alert[0x1d]	5	1			T289	1		T298	1		T91	1
alert_ping_fail	alert[0x1e]	8	1			T3	1		T207	1		T303	1
alert_ping_fail	alert[0x1f]	10	1			T296	1		T291	1		T305	1
alert_ping_fail	alert[0x20]	10	1			T226	1		T207	1		T291	1
alert_ping_fail	alert[0x21]	10	1			T229	1		T293	1		T301	1
alert_ping_fail	alert[0x22]	16	1			T297	1		T291	2		T301	1
alert_ping_fail	alert[0x23]	11	1			T207	1		T296	1		T300	1
alert_ping_fail	alert[0x24]	7	1			T3	1		T297	1		T289	1
alert_ping_fail	alert[0x25]	7	1			T66	1		T226	1		T305	1
alert_ping_fail	alert[0x26]	17	1			T66	3		T226	1		T207	1
alert_ping_fail	alert[0x27]	13	1			T13	1		T229	1		T207	1
alert_ping_fail	alert[0x28]	12	1			T15	1		T207	1		T293	1
alert_ping_fail	alert[0x29]	9	1			T229	2		T226	1		T302	1
alert_ping_fail	alert[0x2a]	10	1			T229	1		T226	1		T40	1
alert_ping_fail	alert[0x2b]	18	1			T218	1		T281	1		T310	2
alert_ping_fail	alert[0x2c]	9	1			T207	1		T301	1		T303	1
alert_ping_fail	alert[0x2d]	10	1			T3	1		T307	1		T299	2
alert_ping_fail	alert[0x2e]	8	1			T296	1		T289	1		T306	1
alert_ping_fail	alert[0x2f]	9	1			T307	1		T309	1		T311	1
alert_ping_fail	alert[0x30]	8	1			T207	1		T296	2		T289	1
alert_ping_fail	alert[0x31]	6	1			T66	1		T300	1		T218	1
alert_ping_fail	alert[0x32]	7	1			T302	1		T289	1		T40	1
alert_ping_fail	alert[0x33]	7	1			T15	1		T66	1		T305	1
alert_ping_fail	alert[0x34]	7	1			T229	1		T226	1		T305	1
alert_ping_fail	alert[0x35]	14	1			T13	1		T207	1		T296	1
alert_ping_fail	alert[0x36]	8	1			T296	1		T300	1		T297	1
alert_ping_fail	alert[0x37]	12	1			T226	1		T207	1		T301	1
alert_ping_fail	alert[0x38]	8	1			T66	1		T226	1		T300	1
alert_ping_fail	alert[0x39]	12	1			T308	1		T304	2		T218	1
alert_ping_fail	alert[0x3a]	11	1			T229	1		T207	1		T306	1
alert_ping_fail	alert[0x3b]	11	1			T296	1		T304	1		T289	1
alert_ping_fail	alert[0x3c]	9	1			T226	1		T304	1		T302	1
alert_ping_fail	alert[0x3d]	10	1			T229	1		T296	1		T304	1
alert_ping_fail	alert[0x3e]	7	1			T226	1		T300	1		T312	1
alert_ping_fail	alert[0x3f]	3	1			T296	1		T298	1		T313	1
alert_ping_fail	alert[0x40]	6	1			T15	1		T66	1		T229	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	118495	1			T46	44		T69	1		T16	5
alert_integrity_fail	class_i[0x1]	94363	1			T1	22		T17	4		T24	50
alert_integrity_fail	class_i[0x2]	76808	1			T1	23		T46	2853		T16	3319
alert_integrity_fail	class_i[0x3]	155690	1			T1	6864		T5	6		T6	6405
alert_ping_fail	class_i[0x0]	130	1			T13	1		T15	1		T226	17
alert_ping_fail	class_i[0x1]	141	1			T13	2		T229	1		T231	1
alert_ping_fail	class_i[0x2]	208	1			T3	1		T15	6		T66	13
alert_ping_fail	class_i[0x3]	203	1			T3	9		T229	1		T226	1