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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.24 99.99 98.69 97.09 100.00 100.00 99.38 99.56


Total test records in report: 832
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T769 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2528701831 Aug 08 05:15:52 PM PDT 24 Aug 08 05:15:53 PM PDT 24 21711599 ps
T770 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2001461469 Aug 08 05:15:56 PM PDT 24 Aug 08 05:15:58 PM PDT 24 33134921 ps
T151 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1040913030 Aug 08 05:15:55 PM PDT 24 Aug 08 05:25:11 PM PDT 24 8492330764 ps
T771 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1937858607 Aug 08 05:15:50 PM PDT 24 Aug 08 05:15:56 PM PDT 24 42596163 ps
T262 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2100962855 Aug 08 05:15:47 PM PDT 24 Aug 08 05:16:30 PM PDT 24 304451118 ps
T772 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.364460274 Aug 08 05:15:56 PM PDT 24 Aug 08 05:15:57 PM PDT 24 14019611 ps
T773 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1566688679 Aug 08 05:15:55 PM PDT 24 Aug 08 05:16:36 PM PDT 24 2077690585 ps
T774 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.4138519154 Aug 08 05:15:58 PM PDT 24 Aug 08 05:15:59 PM PDT 24 33067588 ps
T775 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1546641923 Aug 08 05:15:27 PM PDT 24 Aug 08 05:15:32 PM PDT 24 21105884 ps
T776 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1009984158 Aug 08 05:15:33 PM PDT 24 Aug 08 05:15:47 PM PDT 24 625457813 ps
T777 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2172914751 Aug 08 05:15:52 PM PDT 24 Aug 08 05:16:03 PM PDT 24 184848174 ps
T778 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3184645233 Aug 08 05:15:52 PM PDT 24 Aug 08 05:16:15 PM PDT 24 337711141 ps
T779 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2748358498 Aug 08 05:15:57 PM PDT 24 Aug 08 05:15:59 PM PDT 24 6513145 ps
T780 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2357431847 Aug 08 05:15:55 PM PDT 24 Aug 08 05:15:57 PM PDT 24 28647801 ps
T781 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.547925749 Aug 08 05:15:48 PM PDT 24 Aug 08 05:15:49 PM PDT 24 8979785 ps
T148 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3718122757 Aug 08 05:15:57 PM PDT 24 Aug 08 05:19:04 PM PDT 24 2831051360 ps
T171 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.532901477 Aug 08 05:15:46 PM PDT 24 Aug 08 05:16:38 PM PDT 24 1322196177 ps
T782 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1632671736 Aug 08 05:15:26 PM PDT 24 Aug 08 05:19:06 PM PDT 24 11404449827 ps
T153 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3957587187 Aug 08 05:15:51 PM PDT 24 Aug 08 05:18:44 PM PDT 24 2325620635 ps
T783 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1345862432 Aug 08 05:15:51 PM PDT 24 Aug 08 05:15:58 PM PDT 24 71156755 ps
T784 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3273162849 Aug 08 05:15:40 PM PDT 24 Aug 08 05:17:29 PM PDT 24 3354109288 ps
T145 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3732459671 Aug 08 05:15:27 PM PDT 24 Aug 08 05:32:47 PM PDT 24 54519888153 ps
T785 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3948642222 Aug 08 05:15:36 PM PDT 24 Aug 08 05:15:54 PM PDT 24 469202007 ps
T149 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3254475059 Aug 08 05:15:36 PM PDT 24 Aug 08 05:26:30 PM PDT 24 4889100116 ps
T786 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3848797033 Aug 08 05:15:40 PM PDT 24 Aug 08 05:18:09 PM PDT 24 8771312453 ps
T787 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1304408167 Aug 08 05:15:57 PM PDT 24 Aug 08 05:16:03 PM PDT 24 40183158 ps
T788 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.359548118 Aug 08 05:15:56 PM PDT 24 Aug 08 05:16:02 PM PDT 24 46515295 ps
T152 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3943037928 Aug 08 05:15:47 PM PDT 24 Aug 08 05:25:32 PM PDT 24 54045880636 ps
T789 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.4073127262 Aug 08 05:15:59 PM PDT 24 Aug 08 05:16:00 PM PDT 24 14033439 ps
T790 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1336392351 Aug 08 05:15:40 PM PDT 24 Aug 08 05:15:49 PM PDT 24 194501001 ps
T791 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1205663826 Aug 08 05:15:38 PM PDT 24 Aug 08 05:15:48 PM PDT 24 243601358 ps
T792 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2503020222 Aug 08 05:15:32 PM PDT 24 Aug 08 05:15:41 PM PDT 24 127488143 ps
T793 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1380101144 Aug 08 05:15:52 PM PDT 24 Aug 08 05:25:14 PM PDT 24 7815229425 ps
T166 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.4082451714 Aug 08 05:15:46 PM PDT 24 Aug 08 05:16:30 PM PDT 24 367298231 ps
T178 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.343683577 Aug 08 05:15:34 PM PDT 24 Aug 08 05:16:39 PM PDT 24 987703459 ps
T150 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2427851653 Aug 08 05:15:26 PM PDT 24 Aug 08 05:32:37 PM PDT 24 48158960345 ps
T794 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3985109816 Aug 08 05:16:05 PM PDT 24 Aug 08 05:24:10 PM PDT 24 6046838454 ps
T795 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.544898616 Aug 08 05:15:39 PM PDT 24 Aug 08 05:16:44 PM PDT 24 892173780 ps
T147 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3060913229 Aug 08 05:15:48 PM PDT 24 Aug 08 05:19:16 PM PDT 24 6572084535 ps
T796 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3006337425 Aug 08 05:15:22 PM PDT 24 Aug 08 05:19:19 PM PDT 24 12866901954 ps
T797 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1689628623 Aug 08 05:15:44 PM PDT 24 Aug 08 05:15:59 PM PDT 24 847004170 ps
T798 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.4120517216 Aug 08 05:16:00 PM PDT 24 Aug 08 05:16:01 PM PDT 24 10170932 ps
T799 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1131116473 Aug 08 05:15:56 PM PDT 24 Aug 08 05:16:19 PM PDT 24 669859572 ps
T800 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2247643287 Aug 08 05:16:01 PM PDT 24 Aug 08 05:16:02 PM PDT 24 8970213 ps
T801 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2265249995 Aug 08 05:15:53 PM PDT 24 Aug 08 05:16:33 PM PDT 24 1134973650 ps
T177 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2182842034 Aug 08 05:15:53 PM PDT 24 Aug 08 05:16:00 PM PDT 24 122382145 ps
T802 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3750857331 Aug 08 05:15:29 PM PDT 24 Aug 08 05:15:38 PM PDT 24 515170171 ps
T803 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2542729326 Aug 08 05:15:54 PM PDT 24 Aug 08 05:16:00 PM PDT 24 30821854 ps
T804 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1340749521 Aug 08 05:15:56 PM PDT 24 Aug 08 05:16:08 PM PDT 24 183496231 ps
T805 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2881844793 Aug 08 05:15:56 PM PDT 24 Aug 08 05:15:57 PM PDT 24 9772837 ps
T806 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.4139867493 Aug 08 05:15:58 PM PDT 24 Aug 08 05:16:08 PM PDT 24 275922986 ps
T164 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.65305847 Aug 08 05:15:59 PM PDT 24 Aug 08 05:16:46 PM PDT 24 351413145 ps
T172 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1104359084 Aug 08 05:15:46 PM PDT 24 Aug 08 05:15:49 PM PDT 24 74281842 ps
T807 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3291522852 Aug 08 05:15:56 PM PDT 24 Aug 08 05:15:57 PM PDT 24 25842233 ps
T808 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1541953430 Aug 08 05:15:46 PM PDT 24 Aug 08 05:15:48 PM PDT 24 43309922 ps
T809 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3158453703 Aug 08 05:15:30 PM PDT 24 Aug 08 05:15:55 PM PDT 24 172583947 ps
T810 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.4276999208 Aug 08 05:15:30 PM PDT 24 Aug 08 05:15:38 PM PDT 24 90509291 ps
T811 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2952159986 Aug 08 05:15:50 PM PDT 24 Aug 08 05:15:52 PM PDT 24 27578161 ps
T812 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1980768893 Aug 08 05:15:50 PM PDT 24 Aug 08 05:18:31 PM PDT 24 2554190309 ps
T813 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1697789198 Aug 08 05:16:02 PM PDT 24 Aug 08 05:16:11 PM PDT 24 198041108 ps
T814 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1899131259 Aug 08 05:15:33 PM PDT 24 Aug 08 05:20:01 PM PDT 24 5700363842 ps
T815 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1315126827 Aug 08 05:15:45 PM PDT 24 Aug 08 05:15:53 PM PDT 24 56156270 ps
T816 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2544052189 Aug 08 05:15:51 PM PDT 24 Aug 08 05:16:16 PM PDT 24 1431931519 ps
T817 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1207596429 Aug 08 05:15:53 PM PDT 24 Aug 08 05:15:54 PM PDT 24 8560276 ps
T818 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.16878150 Aug 08 05:15:44 PM PDT 24 Aug 08 05:15:50 PM PDT 24 163686530 ps
T819 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3245214753 Aug 08 05:15:51 PM PDT 24 Aug 08 05:16:03 PM PDT 24 128788346 ps
T820 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1759447300 Aug 08 05:15:58 PM PDT 24 Aug 08 05:15:59 PM PDT 24 24090449 ps
T821 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.194765921 Aug 08 05:15:51 PM PDT 24 Aug 08 05:15:57 PM PDT 24 262404440 ps
T822 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2137084859 Aug 08 05:15:54 PM PDT 24 Aug 08 05:16:02 PM PDT 24 188030672 ps
T823 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2812439291 Aug 08 05:15:47 PM PDT 24 Aug 08 05:15:51 PM PDT 24 40455686 ps
T167 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2237529636 Aug 08 05:15:46 PM PDT 24 Aug 08 05:15:50 PM PDT 24 94900654 ps
T824 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2635519521 Aug 08 05:15:35 PM PDT 24 Aug 08 05:15:41 PM PDT 24 64946003 ps
T825 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3975138710 Aug 08 05:15:58 PM PDT 24 Aug 08 05:16:23 PM PDT 24 484833338 ps
T826 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2773265976 Aug 08 05:15:46 PM PDT 24 Aug 08 05:17:32 PM PDT 24 3616771001 ps
T827 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2178120372 Aug 08 05:15:34 PM PDT 24 Aug 08 05:15:40 PM PDT 24 45790077 ps
T828 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3550796105 Aug 08 05:15:57 PM PDT 24 Aug 08 05:15:58 PM PDT 24 7765823 ps
T829 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2346018816 Aug 08 05:15:56 PM PDT 24 Aug 08 05:16:01 PM PDT 24 125980287 ps
T162 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1952340765 Aug 08 05:15:34 PM PDT 24 Aug 08 05:16:05 PM PDT 24 936647321 ps
T830 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.634534158 Aug 08 05:15:55 PM PDT 24 Aug 08 05:16:25 PM PDT 24 1623540232 ps
T831 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.371173918 Aug 08 05:15:47 PM PDT 24 Aug 08 05:16:01 PM PDT 24 1089404364 ps
T832 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2136427084 Aug 08 05:15:49 PM PDT 24 Aug 08 05:15:53 PM PDT 24 97325389 ps
T170 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2909943559 Aug 08 05:15:54 PM PDT 24 Aug 08 05:16:17 PM PDT 24 609051439 ps

Test location /workspace/coverage/default/13.alert_handler_entropy.772724923
Short name T1
Test name
Test status
Simulation time 20592908702 ps
CPU time 1267.87 seconds
Started Aug 08 04:30:02 PM PDT 24
Finished Aug 08 04:51:10 PM PDT 24
Peak memory 288860 kb
Host smart-b58348c4-5086-47e2-b7e4-76973657a5bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772724923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.772724923
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.3969663462
Short name T16
Test name
Test status
Simulation time 314595184852 ps
CPU time 5075.62 seconds
Started Aug 08 04:31:39 PM PDT 24
Finished Aug 08 05:56:15 PM PDT 24
Peak memory 305056 kb
Host smart-b8a1052d-6676-4a23-bfbf-2f0a78e7cb97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969663462 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.3969663462
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1818442102
Short name T9
Test name
Test status
Simulation time 229167082 ps
CPU time 12.91 seconds
Started Aug 08 04:29:44 PM PDT 24
Finished Aug 08 04:29:57 PM PDT 24
Peak memory 272940 kb
Host smart-649229dc-1143-44ba-a78b-a7a6923ac3e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1818442102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1818442102
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.247950513
Short name T5
Test name
Test status
Simulation time 115243801332 ps
CPU time 3541.37 seconds
Started Aug 08 04:31:30 PM PDT 24
Finished Aug 08 05:30:31 PM PDT 24
Peak memory 305552 kb
Host smart-7bd372d9-30a9-4990-b6fa-aced9a8ebd84
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247950513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.247950513
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2639705197
Short name T123
Test name
Test status
Simulation time 24704888851 ps
CPU time 921.92 seconds
Started Aug 08 05:15:43 PM PDT 24
Finished Aug 08 05:31:06 PM PDT 24
Peak memory 273640 kb
Host smart-0973c147-2012-4719-a010-be7b532920f3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639705197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2639705197
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.1538556142
Short name T24
Test name
Test status
Simulation time 122087579911 ps
CPU time 4909.1 seconds
Started Aug 08 04:30:39 PM PDT 24
Finished Aug 08 05:52:29 PM PDT 24
Peak memory 331980 kb
Host smart-a7ea883f-8e76-490e-84a2-3c1c5a208712
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538556142 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.1538556142
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3418360774
Short name T97
Test name
Test status
Simulation time 832062838602 ps
CPU time 2903.32 seconds
Started Aug 08 04:30:23 PM PDT 24
Finished Aug 08 05:18:46 PM PDT 24
Peak memory 288468 kb
Host smart-84c68f5f-06e4-4861-bb4d-7da35c5d8cc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418360774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3418360774
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2690928018
Short name T120
Test name
Test status
Simulation time 18339885323 ps
CPU time 687.2 seconds
Started Aug 08 05:15:29 PM PDT 24
Finished Aug 08 05:26:56 PM PDT 24
Peak memory 272424 kb
Host smart-491d6f04-a0b7-408a-913c-2c9186de7b4f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690928018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2690928018
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.5479311
Short name T96
Test name
Test status
Simulation time 24195375241 ps
CPU time 454.83 seconds
Started Aug 08 04:29:39 PM PDT 24
Finished Aug 08 04:37:14 PM PDT 24
Peak memory 255816 kb
Host smart-b1f6ac35-bc26-47e9-b951-1d12db07178d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5479311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handl
er_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handle
r_stress_all.5479311
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1480547363
Short name T292
Test name
Test status
Simulation time 100224566952 ps
CPU time 2731.1 seconds
Started Aug 08 04:29:20 PM PDT 24
Finished Aug 08 05:14:52 PM PDT 24
Peak memory 288500 kb
Host smart-065aa1a9-7a0b-4f58-98a4-caac01482ffd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480547363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1480547363
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.541337732
Short name T131
Test name
Test status
Simulation time 75854095022 ps
CPU time 1315.99 seconds
Started Aug 08 05:15:45 PM PDT 24
Finished Aug 08 05:37:41 PM PDT 24
Peak memory 272412 kb
Host smart-a2da775a-e433-4316-894e-fb033731e22a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541337732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.541337732
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1307673232
Short name T105
Test name
Test status
Simulation time 74598980399 ps
CPU time 2345.43 seconds
Started Aug 08 04:30:00 PM PDT 24
Finished Aug 08 05:09:06 PM PDT 24
Peak memory 288280 kb
Host smart-ccefc7e4-a151-4085-8b15-1ab5987afebd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307673232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1307673232
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3766170713
Short name T227
Test name
Test status
Simulation time 4725041859 ps
CPU time 48.71 seconds
Started Aug 08 04:29:59 PM PDT 24
Finished Aug 08 04:30:47 PM PDT 24
Peak memory 248140 kb
Host smart-a62e50ce-d678-4a6b-9247-cb7d55d938a5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3766170713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3766170713
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3730902132
Short name T119
Test name
Test status
Simulation time 3358208695 ps
CPU time 234.22 seconds
Started Aug 08 05:15:35 PM PDT 24
Finished Aug 08 05:19:30 PM PDT 24
Peak memory 273384 kb
Host smart-191fd510-69e9-4cfd-b429-caf4240fc9b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3730902132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3730902132
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3504913456
Short name T56
Test name
Test status
Simulation time 46109192080 ps
CPU time 2743.31 seconds
Started Aug 08 04:29:59 PM PDT 24
Finished Aug 08 05:15:42 PM PDT 24
Peak memory 288028 kb
Host smart-a169b0f9-6215-4817-99b7-627d667ef64d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504913456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3504913456
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.230136286
Short name T155
Test name
Test status
Simulation time 624408773 ps
CPU time 41.13 seconds
Started Aug 08 05:15:50 PM PDT 24
Finished Aug 08 05:16:31 PM PDT 24
Peak memory 237776 kb
Host smart-e6bf4bee-1af2-48fd-a301-0a0a4b4e474d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=230136286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.230136286
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3211352737
Short name T291
Test name
Test status
Simulation time 172568024402 ps
CPU time 2755.94 seconds
Started Aug 08 04:29:58 PM PDT 24
Finished Aug 08 05:15:55 PM PDT 24
Peak memory 288480 kb
Host smart-a9496244-14c1-44f3-9821-42530ad36134
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211352737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3211352737
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2548929241
Short name T134
Test name
Test status
Simulation time 5943855294 ps
CPU time 179.69 seconds
Started Aug 08 05:15:19 PM PDT 24
Finished Aug 08 05:18:19 PM PDT 24
Peak memory 265692 kb
Host smart-07d952a7-79a1-40e8-9974-4beee12a1989
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2548929241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2548929241
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2854210562
Short name T343
Test name
Test status
Simulation time 13123485 ps
CPU time 1.72 seconds
Started Aug 08 05:15:56 PM PDT 24
Finished Aug 08 05:15:58 PM PDT 24
Peak memory 237588 kb
Host smart-0169fd72-d90c-4e51-86da-0051ebb44994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2854210562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2854210562
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3036327975
Short name T229
Test name
Test status
Simulation time 22071918995 ps
CPU time 458.75 seconds
Started Aug 08 04:30:16 PM PDT 24
Finished Aug 08 04:37:55 PM PDT 24
Peak memory 247184 kb
Host smart-b820e462-614a-4fe2-af13-f529114d78a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036327975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3036327975
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1040913030
Short name T151
Test name
Test status
Simulation time 8492330764 ps
CPU time 554.96 seconds
Started Aug 08 05:15:55 PM PDT 24
Finished Aug 08 05:25:11 PM PDT 24
Peak memory 265576 kb
Host smart-03389a79-c216-4692-9001-54a9052041f3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040913030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1040913030
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3027721053
Short name T281
Test name
Test status
Simulation time 64602507227 ps
CPU time 2243.33 seconds
Started Aug 08 04:30:43 PM PDT 24
Finished Aug 08 05:08:07 PM PDT 24
Peak memory 286856 kb
Host smart-267d92df-abdb-4dab-a12e-e69337d9390e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027721053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3027721053
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3050443943
Short name T54
Test name
Test status
Simulation time 90687837998 ps
CPU time 2579.32 seconds
Started Aug 08 04:30:39 PM PDT 24
Finished Aug 08 05:13:39 PM PDT 24
Peak memory 304660 kb
Host smart-33011a17-c6b9-481a-973d-6e37a3df2cac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050443943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3050443943
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.407910889
Short name T141
Test name
Test status
Simulation time 1791409801 ps
CPU time 223.85 seconds
Started Aug 08 05:15:59 PM PDT 24
Finished Aug 08 05:19:43 PM PDT 24
Peak memory 272876 kb
Host smart-0a161eac-5c5f-4090-b6f3-df5d66b3ca41
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=407910889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.407910889
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3146832610
Short name T298
Test name
Test status
Simulation time 13619024624 ps
CPU time 545.44 seconds
Started Aug 08 04:29:58 PM PDT 24
Finished Aug 08 04:39:04 PM PDT 24
Peak memory 256352 kb
Host smart-e1fb757b-b13a-4182-bf34-43ac541de396
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146832610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3146832610
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3152591205
Short name T310
Test name
Test status
Simulation time 119550097353 ps
CPU time 1791.54 seconds
Started Aug 08 04:30:00 PM PDT 24
Finished Aug 08 04:59:52 PM PDT 24
Peak memory 272000 kb
Host smart-cbb971c6-c142-47a4-82de-748ea4a6a0c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152591205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3152591205
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2433050544
Short name T303
Test name
Test status
Simulation time 10114908547 ps
CPU time 425.1 seconds
Started Aug 08 04:31:30 PM PDT 24
Finished Aug 08 04:38:35 PM PDT 24
Peak memory 248184 kb
Host smart-fb728929-bf6c-4010-976b-c49b492d933c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433050544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2433050544
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2517706758
Short name T116
Test name
Test status
Simulation time 31529596355 ps
CPU time 1946.47 seconds
Started Aug 08 04:30:45 PM PDT 24
Finished Aug 08 05:03:11 PM PDT 24
Peak memory 286516 kb
Host smart-af16f2ed-6e36-449a-a108-fa865b1107c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517706758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2517706758
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4059483338
Short name T125
Test name
Test status
Simulation time 6633761928 ps
CPU time 655.9 seconds
Started Aug 08 05:15:52 PM PDT 24
Finished Aug 08 05:26:48 PM PDT 24
Peak memory 265564 kb
Host smart-960d7bef-ef27-45fa-8964-715e234da076
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059483338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.4059483338
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2728095754
Short name T247
Test name
Test status
Simulation time 155629806099 ps
CPU time 4320.46 seconds
Started Aug 08 04:29:30 PM PDT 24
Finished Aug 08 05:41:31 PM PDT 24
Peak memory 337840 kb
Host smart-4bef7102-ebfc-43d3-85c7-c7ada0f1bef2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728095754 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2728095754
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1614964536
Short name T146
Test name
Test status
Simulation time 1992340536 ps
CPU time 207.91 seconds
Started Aug 08 05:15:47 PM PDT 24
Finished Aug 08 05:19:15 PM PDT 24
Peak memory 271752 kb
Host smart-3929e0c6-0a27-4c3d-9f8a-3bfd37e2d17d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1614964536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1614964536
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3048068601
Short name T23
Test name
Test status
Simulation time 28547294411 ps
CPU time 977.27 seconds
Started Aug 08 04:30:52 PM PDT 24
Finished Aug 08 04:47:10 PM PDT 24
Peak memory 285792 kb
Host smart-224aad1e-2728-4180-999c-fbfec695b3f7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048068601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3048068601
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3718799986
Short name T297
Test name
Test status
Simulation time 9480204938 ps
CPU time 373.1 seconds
Started Aug 08 04:31:00 PM PDT 24
Finished Aug 08 04:37:13 PM PDT 24
Peak memory 248132 kb
Host smart-f75cd5ba-de8a-4878-a6bf-4c5aa60243cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718799986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3718799986
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.4126396838
Short name T103
Test name
Test status
Simulation time 38155118056 ps
CPU time 2221.69 seconds
Started Aug 08 04:30:32 PM PDT 24
Finished Aug 08 05:07:34 PM PDT 24
Peak memory 288764 kb
Host smart-e60757ac-8ac4-40c1-8c37-9ca42ed51ba4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126396838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.4126396838
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.4288137786
Short name T26
Test name
Test status
Simulation time 36812233145 ps
CPU time 2493.12 seconds
Started Aug 08 04:29:39 PM PDT 24
Finished Aug 08 05:11:13 PM PDT 24
Peak memory 289284 kb
Host smart-ce4b0685-db3e-479c-adc1-7fa12468a857
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288137786 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.4288137786
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.937223086
Short name T340
Test name
Test status
Simulation time 9875692 ps
CPU time 1.49 seconds
Started Aug 08 05:15:49 PM PDT 24
Finished Aug 08 05:15:51 PM PDT 24
Peak memory 237692 kb
Host smart-e4883e0f-969b-4ecd-9baf-1bd9fa0fbacb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=937223086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.937223086
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1925745875
Short name T300
Test name
Test status
Simulation time 7699282776 ps
CPU time 297.1 seconds
Started Aug 08 04:31:00 PM PDT 24
Finished Aug 08 04:35:57 PM PDT 24
Peak memory 248184 kb
Host smart-7dd586d5-0db7-42a5-a715-8c4ff151daa8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925745875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1925745875
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2405688135
Short name T327
Test name
Test status
Simulation time 49691378520 ps
CPU time 2236.6 seconds
Started Aug 08 04:29:41 PM PDT 24
Finished Aug 08 05:06:58 PM PDT 24
Peak memory 288596 kb
Host smart-72c54c0f-b406-4d3f-9667-ecdad00e454f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405688135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2405688135
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1615845904
Short name T182
Test name
Test status
Simulation time 35639613 ps
CPU time 5.6 seconds
Started Aug 08 05:15:42 PM PDT 24
Finished Aug 08 05:15:47 PM PDT 24
Peak memory 237548 kb
Host smart-12db3523-2dd8-43cc-8c55-4d99137ee0cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1615845904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1615845904
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3060913229
Short name T147
Test name
Test status
Simulation time 6572084535 ps
CPU time 207.53 seconds
Started Aug 08 05:15:48 PM PDT 24
Finished Aug 08 05:19:16 PM PDT 24
Peak memory 265616 kb
Host smart-692b72db-eb3b-4ecc-80b8-211c9b847ec0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3060913229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3060913229
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.929156304
Short name T318
Test name
Test status
Simulation time 7764741365 ps
CPU time 810.27 seconds
Started Aug 08 04:31:26 PM PDT 24
Finished Aug 08 04:44:56 PM PDT 24
Peak memory 272712 kb
Host smart-811d77fa-44ec-4b28-8ceb-46b6472fe99c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929156304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.929156304
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2182842034
Short name T177
Test name
Test status
Simulation time 122382145 ps
CPU time 6.94 seconds
Started Aug 08 05:15:53 PM PDT 24
Finished Aug 08 05:16:00 PM PDT 24
Peak memory 237948 kb
Host smart-d9cfb3b1-78ee-4815-a9bb-4503364a2dda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2182842034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2182842034
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.710560171
Short name T129
Test name
Test status
Simulation time 6678850134 ps
CPU time 100.28 seconds
Started Aug 08 05:15:29 PM PDT 24
Finished Aug 08 05:17:09 PM PDT 24
Peak memory 265532 kb
Host smart-12929f90-063e-4969-a34f-22cda4a3534d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=710560171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.710560171
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3325822495
Short name T78
Test name
Test status
Simulation time 18870170565 ps
CPU time 1415.09 seconds
Started Aug 08 04:30:33 PM PDT 24
Finished Aug 08 04:54:08 PM PDT 24
Peak memory 289196 kb
Host smart-352b0635-1af4-48c0-82e8-38149b011d46
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325822495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3325822495
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1621006407
Short name T15
Test name
Test status
Simulation time 59818032796 ps
CPU time 139.73 seconds
Started Aug 08 04:31:41 PM PDT 24
Finished Aug 08 04:34:01 PM PDT 24
Peak memory 248160 kb
Host smart-ac5d351a-ff07-4c80-a105-212da1cb5a34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621006407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1621006407
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3943037928
Short name T152
Test name
Test status
Simulation time 54045880636 ps
CPU time 585.21 seconds
Started Aug 08 05:15:47 PM PDT 24
Finished Aug 08 05:25:32 PM PDT 24
Peak memory 265536 kb
Host smart-1dbb7a22-ad84-4e4f-af01-fd67552febe2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943037928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3943037928
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3381685369
Short name T12
Test name
Test status
Simulation time 55829154 ps
CPU time 2.38 seconds
Started Aug 08 04:29:36 PM PDT 24
Finished Aug 08 04:29:38 PM PDT 24
Peak memory 248336 kb
Host smart-82719fe3-4f3b-40c7-98b9-d39ce538f0b6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3381685369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3381685369
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2810416112
Short name T202
Test name
Test status
Simulation time 26200283 ps
CPU time 3.12 seconds
Started Aug 08 04:29:44 PM PDT 24
Finished Aug 08 04:29:47 PM PDT 24
Peak memory 248368 kb
Host smart-d3ff816b-6f48-4157-9778-d6c77a916135
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2810416112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2810416112
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2331688317
Short name T189
Test name
Test status
Simulation time 73178524 ps
CPU time 3.37 seconds
Started Aug 08 04:29:41 PM PDT 24
Finished Aug 08 04:29:45 PM PDT 24
Peak memory 248384 kb
Host smart-5ea62eea-d6d3-48aa-ae4d-89dc157ea132
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2331688317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2331688317
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3020596051
Short name T193
Test name
Test status
Simulation time 36582578 ps
CPU time 3.82 seconds
Started Aug 08 04:30:01 PM PDT 24
Finished Aug 08 04:30:05 PM PDT 24
Peak memory 248388 kb
Host smart-d8b06377-61df-4a3b-b0da-f02b2ff7bf46
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3020596051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3020596051
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1664883552
Short name T338
Test name
Test status
Simulation time 15475472 ps
CPU time 1.34 seconds
Started Aug 08 05:15:47 PM PDT 24
Finished Aug 08 05:15:48 PM PDT 24
Peak memory 237592 kb
Host smart-167bd715-c77e-46a0-814d-9a0b9999f5f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1664883552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1664883552
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2253088434
Short name T253
Test name
Test status
Simulation time 807399828 ps
CPU time 58.83 seconds
Started Aug 08 04:30:01 PM PDT 24
Finished Aug 08 04:31:00 PM PDT 24
Peak memory 248904 kb
Host smart-7b606654-dbda-4641-808f-3fdaf361b0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22530
88434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2253088434
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.896023733
Short name T243
Test name
Test status
Simulation time 6374100281 ps
CPU time 391.81 seconds
Started Aug 08 04:30:11 PM PDT 24
Finished Aug 08 04:36:43 PM PDT 24
Peak memory 255872 kb
Host smart-5c691393-0732-43fd-a8bd-f905d172a73c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896023733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.896023733
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.2128073397
Short name T82
Test name
Test status
Simulation time 176774968097 ps
CPU time 8260.82 seconds
Started Aug 08 04:30:41 PM PDT 24
Finished Aug 08 06:48:23 PM PDT 24
Peak memory 330036 kb
Host smart-395d8245-c5e0-494f-88cf-007ece47c39a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128073397 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.2128073397
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2062537614
Short name T313
Test name
Test status
Simulation time 11858891809 ps
CPU time 442.54 seconds
Started Aug 08 04:30:38 PM PDT 24
Finished Aug 08 04:38:01 PM PDT 24
Peak memory 248188 kb
Host smart-7e4e1559-9431-4957-b679-49766beeb145
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062537614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2062537614
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1464988525
Short name T234
Test name
Test status
Simulation time 347938910927 ps
CPU time 5192.44 seconds
Started Aug 08 04:31:32 PM PDT 24
Finished Aug 08 05:58:05 PM PDT 24
Peak memory 304096 kb
Host smart-6b3ad980-5181-422f-9c08-2407ec36b5b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464988525 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1464988525
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3821302457
Short name T240
Test name
Test status
Simulation time 26511751263 ps
CPU time 1311.34 seconds
Started Aug 08 04:30:46 PM PDT 24
Finished Aug 08 04:52:37 PM PDT 24
Peak memory 289252 kb
Host smart-76a9af9e-a77b-4773-bd5f-2d4a6bc549c4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821302457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3821302457
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3859249220
Short name T277
Test name
Test status
Simulation time 167422241251 ps
CPU time 2349.61 seconds
Started Aug 08 04:31:37 PM PDT 24
Finished Aug 08 05:10:47 PM PDT 24
Peak memory 281024 kb
Host smart-df2cb14f-f59e-446c-9213-2e41723222dd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859249220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3859249220
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1695547952
Short name T91
Test name
Test status
Simulation time 50456456160 ps
CPU time 2617.03 seconds
Started Aug 08 04:31:50 PM PDT 24
Finished Aug 08 05:15:28 PM PDT 24
Peak memory 286940 kb
Host smart-0305d7a4-c5be-465d-a92b-da6c51ad3af8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695547952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1695547952
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2999186290
Short name T88
Test name
Test status
Simulation time 324443175896 ps
CPU time 1695.88 seconds
Started Aug 08 04:29:42 PM PDT 24
Finished Aug 08 04:57:58 PM PDT 24
Peak memory 288656 kb
Host smart-89978f2f-83d4-4da2-a317-9aaa7bc81fcf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999186290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2999186290
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.32022283
Short name T128
Test name
Test status
Simulation time 7838793625 ps
CPU time 301.56 seconds
Started Aug 08 05:15:54 PM PDT 24
Finished Aug 08 05:20:56 PM PDT 24
Peak memory 265648 kb
Host smart-0089470b-c00a-429c-adf2-9f5b49449249
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=32022283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_error
s.32022283
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3202242971
Short name T265
Test name
Test status
Simulation time 1508077176 ps
CPU time 36.47 seconds
Started Aug 08 04:29:21 PM PDT 24
Finished Aug 08 04:29:58 PM PDT 24
Peak memory 248292 kb
Host smart-bd4777f2-874f-49f6-b49c-f5698706970b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32022
42971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3202242971
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1756828019
Short name T256
Test name
Test status
Simulation time 4324073363 ps
CPU time 82.55 seconds
Started Aug 08 04:29:38 PM PDT 24
Finished Aug 08 04:31:01 PM PDT 24
Peak memory 249556 kb
Host smart-95d2000d-4766-4a8d-8766-8c5322a85f7e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756828019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1756828019
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3677618661
Short name T258
Test name
Test status
Simulation time 19369707926 ps
CPU time 140.9 seconds
Started Aug 08 04:29:59 PM PDT 24
Finished Aug 08 04:32:20 PM PDT 24
Peak memory 256368 kb
Host smart-fc199bd3-68a4-4ef0-8c48-5bac61c5c053
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677618661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3677618661
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.568531172
Short name T44
Test name
Test status
Simulation time 359944904 ps
CPU time 25.82 seconds
Started Aug 08 04:30:03 PM PDT 24
Finished Aug 08 04:30:28 PM PDT 24
Peak memory 247680 kb
Host smart-37599f0b-35c6-4f48-877c-132fe15bfbfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56853
1172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.568531172
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3102985976
Short name T250
Test name
Test status
Simulation time 232125665 ps
CPU time 27.48 seconds
Started Aug 08 04:30:13 PM PDT 24
Finished Aug 08 04:30:41 PM PDT 24
Peak memory 255908 kb
Host smart-ef588626-31a3-44b2-ad84-dd5ab11d0738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31029
85976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3102985976
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1431309917
Short name T242
Test name
Test status
Simulation time 2745366119 ps
CPU time 50.42 seconds
Started Aug 08 04:29:30 PM PDT 24
Finished Aug 08 04:30:21 PM PDT 24
Peak memory 248212 kb
Host smart-e6b4c10a-a955-4d65-9b1f-374583b2b712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14313
09917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1431309917
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3995222399
Short name T244
Test name
Test status
Simulation time 677809257 ps
CPU time 16.25 seconds
Started Aug 08 04:30:18 PM PDT 24
Finished Aug 08 04:30:34 PM PDT 24
Peak memory 255568 kb
Host smart-608b0e1c-e89f-4fce-98a4-f6565994a4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39952
22399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3995222399
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.967095418
Short name T336
Test name
Test status
Simulation time 51207568079 ps
CPU time 932.16 seconds
Started Aug 08 04:30:39 PM PDT 24
Finished Aug 08 04:46:12 PM PDT 24
Peak memory 272768 kb
Host smart-7cbe6101-85d3-44b7-82d3-a5d9d5e42c57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967095418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.967095418
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3282522377
Short name T20
Test name
Test status
Simulation time 1428459826 ps
CPU time 26.06 seconds
Started Aug 08 04:30:38 PM PDT 24
Finished Aug 08 04:31:04 PM PDT 24
Peak memory 255176 kb
Host smart-5a5b6d8f-fc01-4550-8c82-72f0b6f7b248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32825
22377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3282522377
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2847960593
Short name T290
Test name
Test status
Simulation time 315582992290 ps
CPU time 3252.88 seconds
Started Aug 08 04:31:11 PM PDT 24
Finished Aug 08 05:25:24 PM PDT 24
Peak memory 288792 kb
Host smart-b4cadea0-aa34-409f-9542-6e80f14a62e8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847960593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2847960593
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3087579033
Short name T261
Test name
Test status
Simulation time 559421401 ps
CPU time 31.92 seconds
Started Aug 08 04:31:12 PM PDT 24
Finished Aug 08 04:31:44 PM PDT 24
Peak memory 247528 kb
Host smart-ef949971-9479-42cb-b94a-e27faa3234d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30875
79033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3087579033
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.971423011
Short name T104
Test name
Test status
Simulation time 37945239629 ps
CPU time 2472.65 seconds
Started Aug 08 04:31:16 PM PDT 24
Finished Aug 08 05:12:29 PM PDT 24
Peak memory 304012 kb
Host smart-4f0fadd2-ab2c-4032-a88b-0aca3b17e6db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971423011 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.971423011
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.654037137
Short name T284
Test name
Test status
Simulation time 462736240810 ps
CPU time 1824.79 seconds
Started Aug 08 04:31:24 PM PDT 24
Finished Aug 08 05:01:50 PM PDT 24
Peak memory 272572 kb
Host smart-f13d9197-9de1-4a25-8949-86d39cd7f9af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654037137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.654037137
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1980768893
Short name T812
Test name
Test status
Simulation time 2554190309 ps
CPU time 160.73 seconds
Started Aug 08 05:15:50 PM PDT 24
Finished Aug 08 05:18:31 PM PDT 24
Peak memory 265484 kb
Host smart-03f2ecda-6fe0-4ba7-abfa-294bf39285ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1980768893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1980768893
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3490889751
Short name T160
Test name
Test status
Simulation time 234960680 ps
CPU time 6.2 seconds
Started Aug 08 05:15:51 PM PDT 24
Finished Aug 08 05:15:57 PM PDT 24
Peak memory 237768 kb
Host smart-0e0c9883-f931-499a-b30f-016a45eee610
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3490889751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3490889751
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.65305847
Short name T164
Test name
Test status
Simulation time 351413145 ps
CPU time 45.95 seconds
Started Aug 08 05:15:59 PM PDT 24
Finished Aug 08 05:16:46 PM PDT 24
Peak memory 240488 kb
Host smart-88a53688-943c-4f69-a763-d189be4b1d48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=65305847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.65305847
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.739125261
Short name T143
Test name
Test status
Simulation time 13286478207 ps
CPU time 318.05 seconds
Started Aug 08 05:15:39 PM PDT 24
Finished Aug 08 05:20:58 PM PDT 24
Peak memory 265520 kb
Host smart-abaa5dbc-aa78-47d7-a6e0-76a8a3193ba9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=739125261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.739125261
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.532901477
Short name T171
Test name
Test status
Simulation time 1322196177 ps
CPU time 51.14 seconds
Started Aug 08 05:15:46 PM PDT 24
Finished Aug 08 05:16:38 PM PDT 24
Peak memory 240532 kb
Host smart-d749fd0a-4b33-4b24-965b-3984420f42fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=532901477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.532901477
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2427851653
Short name T150
Test name
Test status
Simulation time 48158960345 ps
CPU time 1030.36 seconds
Started Aug 08 05:15:26 PM PDT 24
Finished Aug 08 05:32:37 PM PDT 24
Peak memory 265664 kb
Host smart-7c0df832-28f5-4802-9aa8-b718db5aa467
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427851653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2427851653
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1120284606
Short name T163
Test name
Test status
Simulation time 21976110 ps
CPU time 2.14 seconds
Started Aug 08 05:15:09 PM PDT 24
Finished Aug 08 05:15:12 PM PDT 24
Peak memory 238560 kb
Host smart-26aa6bcb-6a00-4cf0-899e-1b1a0daaa0c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1120284606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1120284606
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.4082451714
Short name T166
Test name
Test status
Simulation time 367298231 ps
CPU time 43.06 seconds
Started Aug 08 05:15:46 PM PDT 24
Finished Aug 08 05:16:30 PM PDT 24
Peak memory 240636 kb
Host smart-d32053c1-511a-41d2-89ab-bffe44d4e63f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4082451714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.4082451714
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1104359084
Short name T172
Test name
Test status
Simulation time 74281842 ps
CPU time 2.5 seconds
Started Aug 08 05:15:46 PM PDT 24
Finished Aug 08 05:15:49 PM PDT 24
Peak memory 237888 kb
Host smart-8e3f9612-4573-4c7e-9fc3-94fab5f5fa25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1104359084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1104359084
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2909943559
Short name T170
Test name
Test status
Simulation time 609051439 ps
CPU time 22.38 seconds
Started Aug 08 05:15:54 PM PDT 24
Finished Aug 08 05:16:17 PM PDT 24
Peak memory 248688 kb
Host smart-fe9b47a5-4fe0-4beb-99b7-54a231e5ef9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2909943559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2909943559
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2111774956
Short name T161
Test name
Test status
Simulation time 982038682 ps
CPU time 67.06 seconds
Started Aug 08 05:16:00 PM PDT 24
Finished Aug 08 05:17:07 PM PDT 24
Peak memory 246384 kb
Host smart-eb3d9f18-7494-4365-8af8-4ffb5ce80741
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2111774956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2111774956
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2929745695
Short name T165
Test name
Test status
Simulation time 114415415 ps
CPU time 3.05 seconds
Started Aug 08 05:15:56 PM PDT 24
Finished Aug 08 05:15:59 PM PDT 24
Peak memory 237624 kb
Host smart-8388eff3-6d99-4563-8caa-23a73390e40f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2929745695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2929745695
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3100135216
Short name T168
Test name
Test status
Simulation time 36386544 ps
CPU time 2.84 seconds
Started Aug 08 05:15:56 PM PDT 24
Finished Aug 08 05:15:59 PM PDT 24
Peak memory 237624 kb
Host smart-05cbf370-8b63-4853-86c4-a5dc86968dd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3100135216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3100135216
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3940767404
Short name T156
Test name
Test status
Simulation time 260268545 ps
CPU time 3.31 seconds
Started Aug 08 05:15:51 PM PDT 24
Finished Aug 08 05:15:55 PM PDT 24
Peak memory 237916 kb
Host smart-154a5ff0-aff3-4d3e-a8af-facdd4baeec4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3940767404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3940767404
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2237529636
Short name T167
Test name
Test status
Simulation time 94900654 ps
CPU time 4.06 seconds
Started Aug 08 05:15:46 PM PDT 24
Finished Aug 08 05:15:50 PM PDT 24
Peak memory 237656 kb
Host smart-d0fe497f-0391-4f8a-92ff-365838f7b1c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2237529636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2237529636
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3218334695
Short name T174
Test name
Test status
Simulation time 89690957 ps
CPU time 12.96 seconds
Started Aug 08 05:15:27 PM PDT 24
Finished Aug 08 05:15:40 PM PDT 24
Peak memory 245772 kb
Host smart-12663982-bd71-4c26-8a2d-b4521c446602
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3218334695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3218334695
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1952340765
Short name T162
Test name
Test status
Simulation time 936647321 ps
CPU time 31.8 seconds
Started Aug 08 05:15:34 PM PDT 24
Finished Aug 08 05:16:05 PM PDT 24
Peak memory 240492 kb
Host smart-dca765df-7b62-4722-8d0c-a423199a7f00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1952340765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1952340765
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3380762186
Short name T169
Test name
Test status
Simulation time 60602703 ps
CPU time 3.23 seconds
Started Aug 08 05:15:34 PM PDT 24
Finished Aug 08 05:15:38 PM PDT 24
Peak memory 237584 kb
Host smart-a5728d68-0580-4d8d-a172-31e70da5987a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3380762186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3380762186
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.343683577
Short name T178
Test name
Test status
Simulation time 987703459 ps
CPU time 64.84 seconds
Started Aug 08 05:15:34 PM PDT 24
Finished Aug 08 05:16:39 PM PDT 24
Peak memory 240636 kb
Host smart-005b57bb-a9e1-4083-9067-98d574756086
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=343683577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.343683577
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.4084228819
Short name T27
Test name
Test status
Simulation time 177108316984 ps
CPU time 4478.17 seconds
Started Aug 08 04:30:01 PM PDT 24
Finished Aug 08 05:44:40 PM PDT 24
Peak memory 353528 kb
Host smart-596665d7-96da-47ae-adc7-1c558f2b51b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084228819 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.4084228819
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3848797033
Short name T786
Test name
Test status
Simulation time 8771312453 ps
CPU time 149.04 seconds
Started Aug 08 05:15:40 PM PDT 24
Finished Aug 08 05:18:09 PM PDT 24
Peak memory 237740 kb
Host smart-f0670e17-64eb-475d-aefc-a8ea086a0183
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3848797033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3848797033
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3882766474
Short name T760
Test name
Test status
Simulation time 1670985108 ps
CPU time 109.59 seconds
Started Aug 08 05:15:22 PM PDT 24
Finished Aug 08 05:17:12 PM PDT 24
Peak memory 237556 kb
Host smart-eb218ce3-affd-40ba-bcd9-3e7955d053f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3882766474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3882766474
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2178120372
Short name T827
Test name
Test status
Simulation time 45790077 ps
CPU time 6.77 seconds
Started Aug 08 05:15:34 PM PDT 24
Finished Aug 08 05:15:40 PM PDT 24
Peak memory 249068 kb
Host smart-293db3be-5957-4b9c-b248-121b2a25db74
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2178120372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2178120372
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2749453774
Short name T747
Test name
Test status
Simulation time 1767106440 ps
CPU time 10.95 seconds
Started Aug 08 05:15:35 PM PDT 24
Finished Aug 08 05:15:47 PM PDT 24
Peak memory 255732 kb
Host smart-e76ccead-cd56-46fb-a4dc-16b37f694c8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749453774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2749453774
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1546641923
Short name T775
Test name
Test status
Simulation time 21105884 ps
CPU time 4.59 seconds
Started Aug 08 05:15:27 PM PDT 24
Finished Aug 08 05:15:32 PM PDT 24
Peak memory 237552 kb
Host smart-f381660c-539b-48ab-9a81-af5b38d80ad7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1546641923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1546641923
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2627311968
Short name T720
Test name
Test status
Simulation time 9287749 ps
CPU time 1.56 seconds
Started Aug 08 05:15:42 PM PDT 24
Finished Aug 08 05:15:44 PM PDT 24
Peak memory 237568 kb
Host smart-62431f63-ad01-4bbb-a634-4fb44472df1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2627311968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2627311968
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2693573303
Short name T133
Test name
Test status
Simulation time 1633655140 ps
CPU time 171.7 seconds
Started Aug 08 05:15:14 PM PDT 24
Finished Aug 08 05:18:06 PM PDT 24
Peak memory 273368 kb
Host smart-a72b7e86-335a-47ff-a1c1-5bcc8ac4a7fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2693573303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.2693573303
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3031751009
Short name T742
Test name
Test status
Simulation time 1151311328 ps
CPU time 16.45 seconds
Started Aug 08 05:15:18 PM PDT 24
Finished Aug 08 05:15:34 PM PDT 24
Peak memory 248744 kb
Host smart-74b89e30-9733-45bb-a182-09d8bc721556
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3031751009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3031751009
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3006337425
Short name T796
Test name
Test status
Simulation time 12866901954 ps
CPU time 236.85 seconds
Started Aug 08 05:15:22 PM PDT 24
Finished Aug 08 05:19:19 PM PDT 24
Peak memory 240736 kb
Host smart-bf31c70f-b89e-4259-b33a-1d9b2a08283b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3006337425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3006337425
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1632671736
Short name T782
Test name
Test status
Simulation time 11404449827 ps
CPU time 219.79 seconds
Started Aug 08 05:15:26 PM PDT 24
Finished Aug 08 05:19:06 PM PDT 24
Peak memory 237792 kb
Host smart-cc2bd051-1afc-4b9a-b1b4-683ab8fd4d2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1632671736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1632671736
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2542438756
Short name T724
Test name
Test status
Simulation time 790288149 ps
CPU time 10.38 seconds
Started Aug 08 05:15:35 PM PDT 24
Finished Aug 08 05:15:46 PM PDT 24
Peak memory 249220 kb
Host smart-2076323b-a155-4c89-bab3-0891529adabc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2542438756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2542438756
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1009984158
Short name T776
Test name
Test status
Simulation time 625457813 ps
CPU time 13.56 seconds
Started Aug 08 05:15:33 PM PDT 24
Finished Aug 08 05:15:47 PM PDT 24
Peak memory 252332 kb
Host smart-40d5365c-6888-4234-89d6-7b79c8eea387
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009984158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1009984158
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.4276999208
Short name T810
Test name
Test status
Simulation time 90509291 ps
CPU time 7.94 seconds
Started Aug 08 05:15:30 PM PDT 24
Finished Aug 08 05:15:38 PM PDT 24
Peak memory 240564 kb
Host smart-6c861034-e454-46bc-a250-ccd6267d38cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4276999208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.4276999208
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2541126154
Short name T346
Test name
Test status
Simulation time 13137021 ps
CPU time 1.69 seconds
Started Aug 08 05:15:29 PM PDT 24
Finished Aug 08 05:15:31 PM PDT 24
Peak memory 236756 kb
Host smart-53676757-fed2-46e1-98d2-2923d22318e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2541126154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2541126154
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1934496059
Short name T755
Test name
Test status
Simulation time 501495991 ps
CPU time 37.78 seconds
Started Aug 08 05:15:29 PM PDT 24
Finished Aug 08 05:16:07 PM PDT 24
Peak memory 245000 kb
Host smart-b8e75c67-ba44-4af3-a818-1fba5f5560b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1934496059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1934496059
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3732459671
Short name T145
Test name
Test status
Simulation time 54519888153 ps
CPU time 1039.87 seconds
Started Aug 08 05:15:27 PM PDT 24
Finished Aug 08 05:32:47 PM PDT 24
Peak memory 265520 kb
Host smart-247ebe62-c579-42ef-9b74-85f672f90ffd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732459671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3732459671
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2689555784
Short name T737
Test name
Test status
Simulation time 707283801 ps
CPU time 16.15 seconds
Started Aug 08 05:15:24 PM PDT 24
Finished Aug 08 05:15:40 PM PDT 24
Peak memory 251408 kb
Host smart-2fd6161e-d273-4b4e-b49c-675bd2f9cbec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2689555784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2689555784
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2445104623
Short name T744
Test name
Test status
Simulation time 105212105 ps
CPU time 8.04 seconds
Started Aug 08 05:15:50 PM PDT 24
Finished Aug 08 05:15:58 PM PDT 24
Peak memory 240580 kb
Host smart-1ef16f19-9d8a-4ed1-9358-8cf651ae1174
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445104623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2445104623
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1937858607
Short name T771
Test name
Test status
Simulation time 42596163 ps
CPU time 5.62 seconds
Started Aug 08 05:15:50 PM PDT 24
Finished Aug 08 05:15:56 PM PDT 24
Peak memory 240540 kb
Host smart-d9c412a9-5783-495c-beb9-c78e2a0604ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1937858607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1937858607
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3480176396
Short name T184
Test name
Test status
Simulation time 579670228 ps
CPU time 36.42 seconds
Started Aug 08 05:15:42 PM PDT 24
Finished Aug 08 05:16:19 PM PDT 24
Peak memory 245784 kb
Host smart-baafb23a-0305-4646-9046-8dd5f27766ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3480176396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3480176396
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2018563279
Short name T140
Test name
Test status
Simulation time 6476297727 ps
CPU time 454.42 seconds
Started Aug 08 05:15:54 PM PDT 24
Finished Aug 08 05:23:28 PM PDT 24
Peak memory 265520 kb
Host smart-011458ed-edfa-4734-8abb-c92fffbfcb8b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018563279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2018563279
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.4111693994
Short name T710
Test name
Test status
Simulation time 114260642 ps
CPU time 4.29 seconds
Started Aug 08 05:15:49 PM PDT 24
Finished Aug 08 05:15:53 PM PDT 24
Peak memory 252164 kb
Host smart-7ad7077d-101e-4d53-affa-70dc24439715
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4111693994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.4111693994
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2512221327
Short name T154
Test name
Test status
Simulation time 146319909 ps
CPU time 6.96 seconds
Started Aug 08 05:15:45 PM PDT 24
Finished Aug 08 05:15:52 PM PDT 24
Peak memory 237624 kb
Host smart-7a384ca0-a601-4eeb-ad09-38e503bb510f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2512221327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2512221327
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.78127008
Short name T349
Test name
Test status
Simulation time 98509000 ps
CPU time 7.39 seconds
Started Aug 08 05:15:48 PM PDT 24
Finished Aug 08 05:15:55 PM PDT 24
Peak memory 238752 kb
Host smart-9911659e-8685-418f-a5b0-2b82aef85d16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78127008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.alert_handler_csr_mem_rw_with_rand_reset.78127008
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2137084859
Short name T822
Test name
Test status
Simulation time 188030672 ps
CPU time 8.41 seconds
Started Aug 08 05:15:54 PM PDT 24
Finished Aug 08 05:16:02 PM PDT 24
Peak memory 237616 kb
Host smart-2d6ae0c3-e82e-4bd5-a878-5eedf309f377
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2137084859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2137084859
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.707205855
Short name T157
Test name
Test status
Simulation time 12715148 ps
CPU time 1.33 seconds
Started Aug 08 05:15:44 PM PDT 24
Finished Aug 08 05:15:45 PM PDT 24
Peak memory 236744 kb
Host smart-7de252e0-806d-4618-9b0b-ea5ba021f940
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=707205855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.707205855
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2544052189
Short name T816
Test name
Test status
Simulation time 1431931519 ps
CPU time 24.04 seconds
Started Aug 08 05:15:51 PM PDT 24
Finished Aug 08 05:16:16 PM PDT 24
Peak memory 245796 kb
Host smart-0205c2de-0eae-4771-af7f-6af4f76f4f95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2544052189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2544052189
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1874472767
Short name T130
Test name
Test status
Simulation time 51842804892 ps
CPU time 359.24 seconds
Started Aug 08 05:15:39 PM PDT 24
Finished Aug 08 05:21:39 PM PDT 24
Peak memory 265560 kb
Host smart-165ddf97-31a5-4f31-affa-8abdbfec9f0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1874472767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1874472767
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.4075240785
Short name T144
Test name
Test status
Simulation time 25875828444 ps
CPU time 554.99 seconds
Started Aug 08 05:15:46 PM PDT 24
Finished Aug 08 05:25:01 PM PDT 24
Peak memory 273784 kb
Host smart-ebaf0d2e-e9f3-4674-bd3b-4379da1de6c8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075240785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.4075240785
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.634534158
Short name T830
Test name
Test status
Simulation time 1623540232 ps
CPU time 29 seconds
Started Aug 08 05:15:55 PM PDT 24
Finished Aug 08 05:16:25 PM PDT 24
Peak memory 247832 kb
Host smart-f32d63eb-012d-4c3b-8228-5c60fe198a64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=634534158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.634534158
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1185748148
Short name T176
Test name
Test status
Simulation time 64032916 ps
CPU time 9.57 seconds
Started Aug 08 05:15:45 PM PDT 24
Finished Aug 08 05:15:55 PM PDT 24
Peak memory 256936 kb
Host smart-cd36c78e-22e5-464c-8115-350586e53ec7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185748148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1185748148
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.182008702
Short name T732
Test name
Test status
Simulation time 182725556 ps
CPU time 9.26 seconds
Started Aug 08 05:15:50 PM PDT 24
Finished Aug 08 05:16:00 PM PDT 24
Peak memory 240620 kb
Host smart-bec869cb-f18b-4227-a0b0-f47a2a7c1923
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=182008702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.182008702
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1541953430
Short name T808
Test name
Test status
Simulation time 43309922 ps
CPU time 1.4 seconds
Started Aug 08 05:15:46 PM PDT 24
Finished Aug 08 05:15:48 PM PDT 24
Peak memory 236820 kb
Host smart-cba298fe-5b2d-4e34-93e4-ae84b0061a46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1541953430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1541953430
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2821741004
Short name T743
Test name
Test status
Simulation time 313673913 ps
CPU time 18.62 seconds
Started Aug 08 05:15:42 PM PDT 24
Finished Aug 08 05:16:00 PM PDT 24
Peak memory 245012 kb
Host smart-a71af5a9-9771-4b3b-9dd3-8806f9709e06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2821741004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2821741004
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.779236279
Short name T121
Test name
Test status
Simulation time 19248337081 ps
CPU time 577.02 seconds
Started Aug 08 05:15:54 PM PDT 24
Finished Aug 08 05:25:31 PM PDT 24
Peak memory 265508 kb
Host smart-f12e0e5a-7987-4a12-afaf-500b6891aaee
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779236279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.779236279
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3184645233
Short name T778
Test name
Test status
Simulation time 337711141 ps
CPU time 22.69 seconds
Started Aug 08 05:15:52 PM PDT 24
Finished Aug 08 05:16:15 PM PDT 24
Peak memory 249984 kb
Host smart-bbaa1da7-5682-44fa-b19e-adf66172b321
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3184645233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3184645233
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.359548118
Short name T788
Test name
Test status
Simulation time 46515295 ps
CPU time 5.74 seconds
Started Aug 08 05:15:56 PM PDT 24
Finished Aug 08 05:16:02 PM PDT 24
Peak memory 248856 kb
Host smart-afa8b5c3-3cc2-461c-addd-81805911c2af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359548118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.359548118
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.4241625164
Short name T759
Test name
Test status
Simulation time 490855755 ps
CPU time 9.93 seconds
Started Aug 08 05:15:53 PM PDT 24
Finished Aug 08 05:16:03 PM PDT 24
Peak memory 237568 kb
Host smart-44283a8c-3921-4acd-8174-d65442f84deb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4241625164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.4241625164
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.4265190039
Short name T718
Test name
Test status
Simulation time 21044406 ps
CPU time 1.39 seconds
Started Aug 08 05:15:57 PM PDT 24
Finished Aug 08 05:15:58 PM PDT 24
Peak memory 237552 kb
Host smart-e9eb025d-323d-446d-a174-e337bae4aa06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4265190039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.4265190039
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3672203459
Short name T762
Test name
Test status
Simulation time 4307178697 ps
CPU time 45.74 seconds
Started Aug 08 05:15:55 PM PDT 24
Finished Aug 08 05:16:40 PM PDT 24
Peak memory 246032 kb
Host smart-fdf52614-92d6-46c7-b1d3-fd4de7c6e115
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3672203459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3672203459
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2773265976
Short name T826
Test name
Test status
Simulation time 3616771001 ps
CPU time 106.26 seconds
Started Aug 08 05:15:46 PM PDT 24
Finished Aug 08 05:17:32 PM PDT 24
Peak memory 268612 kb
Host smart-5a185baa-6b46-423a-915e-799b8776c887
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2773265976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2773265976
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1340749521
Short name T804
Test name
Test status
Simulation time 183496231 ps
CPU time 12.32 seconds
Started Aug 08 05:15:56 PM PDT 24
Finished Aug 08 05:16:08 PM PDT 24
Peak memory 248908 kb
Host smart-bf1d0eae-b69f-4ef7-a530-a7e7c0effbdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1340749521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1340749521
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.4110842799
Short name T725
Test name
Test status
Simulation time 239355215 ps
CPU time 5.85 seconds
Started Aug 08 05:16:07 PM PDT 24
Finished Aug 08 05:16:13 PM PDT 24
Peak memory 240384 kb
Host smart-2a78515a-ed51-4bf2-b371-04e0a0321671
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110842799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.4110842799
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2346018816
Short name T829
Test name
Test status
Simulation time 125980287 ps
CPU time 5.19 seconds
Started Aug 08 05:15:56 PM PDT 24
Finished Aug 08 05:16:01 PM PDT 24
Peak memory 236688 kb
Host smart-af78af71-0340-479f-9b42-9f8965afd66e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2346018816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2346018816
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2748358498
Short name T779
Test name
Test status
Simulation time 6513145 ps
CPU time 1.5 seconds
Started Aug 08 05:15:57 PM PDT 24
Finished Aug 08 05:15:59 PM PDT 24
Peak memory 237648 kb
Host smart-fd7d3608-df9c-4649-a05e-fcb8c8020f18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2748358498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2748358498
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.574742633
Short name T731
Test name
Test status
Simulation time 619393156 ps
CPU time 21.73 seconds
Started Aug 08 05:15:57 PM PDT 24
Finished Aug 08 05:16:18 PM PDT 24
Peak memory 244864 kb
Host smart-dcc01add-9262-462a-8cf4-5709c71282b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=574742633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.574742633
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.769414023
Short name T139
Test name
Test status
Simulation time 3195975146 ps
CPU time 99.15 seconds
Started Aug 08 05:15:57 PM PDT 24
Finished Aug 08 05:17:36 PM PDT 24
Peak memory 265592 kb
Host smart-1b9760e4-537f-4b3e-9107-5527073bb320
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=769414023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.769414023
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2355688905
Short name T137
Test name
Test status
Simulation time 8523559446 ps
CPU time 605.02 seconds
Started Aug 08 05:15:52 PM PDT 24
Finished Aug 08 05:25:57 PM PDT 24
Peak memory 265804 kb
Host smart-f022b93b-e6d4-4d5f-8665-075b601f18c6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355688905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2355688905
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1191962276
Short name T738
Test name
Test status
Simulation time 301513745 ps
CPU time 10.33 seconds
Started Aug 08 05:15:51 PM PDT 24
Finished Aug 08 05:16:01 PM PDT 24
Peak memory 248916 kb
Host smart-4a92f6bc-7e8a-4c49-8bbf-3782c91e8f9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1191962276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1191962276
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.194765921
Short name T821
Test name
Test status
Simulation time 262404440 ps
CPU time 5.81 seconds
Started Aug 08 05:15:51 PM PDT 24
Finished Aug 08 05:15:57 PM PDT 24
Peak memory 239780 kb
Host smart-c00843ef-8549-4811-a131-ca8ffc54abcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194765921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.194765921
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.65926356
Short name T348
Test name
Test status
Simulation time 64265183 ps
CPU time 5.73 seconds
Started Aug 08 05:15:57 PM PDT 24
Finished Aug 08 05:16:05 PM PDT 24
Peak memory 237572 kb
Host smart-2348995b-e0a5-43f3-9482-c20eedc02686
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=65926356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.65926356
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.80932953
Short name T344
Test name
Test status
Simulation time 21305407 ps
CPU time 1.42 seconds
Started Aug 08 05:15:51 PM PDT 24
Finished Aug 08 05:15:53 PM PDT 24
Peak memory 236676 kb
Host smart-e6854922-0466-4979-81e8-7d7d18c69d88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=80932953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.80932953
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3975138710
Short name T825
Test name
Test status
Simulation time 484833338 ps
CPU time 24.74 seconds
Started Aug 08 05:15:58 PM PDT 24
Finished Aug 08 05:16:23 PM PDT 24
Peak memory 248676 kb
Host smart-a84f5505-03a7-495d-bb11-a5e7ad43a12c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3975138710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3975138710
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3114389213
Short name T142
Test name
Test status
Simulation time 5193016681 ps
CPU time 679.73 seconds
Started Aug 08 05:15:49 PM PDT 24
Finished Aug 08 05:27:09 PM PDT 24
Peak memory 272940 kb
Host smart-a9f30535-2265-43da-b3c6-aa251e708e2f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114389213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3114389213
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2744392960
Short name T714
Test name
Test status
Simulation time 63357724 ps
CPU time 8.38 seconds
Started Aug 08 05:15:50 PM PDT 24
Finished Aug 08 05:15:59 PM PDT 24
Peak memory 247928 kb
Host smart-cc07c427-46ab-4d5d-8073-3b19e3faa4a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2744392960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2744392960
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2542729326
Short name T803
Test name
Test status
Simulation time 30821854 ps
CPU time 5.54 seconds
Started Aug 08 05:15:54 PM PDT 24
Finished Aug 08 05:16:00 PM PDT 24
Peak memory 240276 kb
Host smart-e5a63bee-4ef1-471b-aa33-d8bc0479e78a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542729326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2542729326
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1116547974
Short name T350
Test name
Test status
Simulation time 33730826 ps
CPU time 3.37 seconds
Started Aug 08 05:15:55 PM PDT 24
Finished Aug 08 05:15:58 PM PDT 24
Peak memory 237580 kb
Host smart-5008f6d6-e223-4836-9242-0e0398e715b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1116547974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1116547974
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.654166828
Short name T736
Test name
Test status
Simulation time 26994142 ps
CPU time 1.48 seconds
Started Aug 08 05:15:55 PM PDT 24
Finished Aug 08 05:15:57 PM PDT 24
Peak memory 236676 kb
Host smart-dfb9dfae-28ec-4adc-a89e-7fc91c620087
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=654166828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.654166828
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1131116473
Short name T799
Test name
Test status
Simulation time 669859572 ps
CPU time 22.41 seconds
Started Aug 08 05:15:56 PM PDT 24
Finished Aug 08 05:16:19 PM PDT 24
Peak memory 245804 kb
Host smart-3094ecb8-0cf4-4588-86e2-ba5534bcd44b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1131116473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1131116473
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1426785919
Short name T711
Test name
Test status
Simulation time 211180927 ps
CPU time 12.98 seconds
Started Aug 08 05:16:00 PM PDT 24
Finished Aug 08 05:16:13 PM PDT 24
Peak memory 248752 kb
Host smart-e914ca6e-dad8-4cf8-9b87-3efa7559b6a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1426785919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1426785919
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1697789198
Short name T813
Test name
Test status
Simulation time 198041108 ps
CPU time 8.9 seconds
Started Aug 08 05:16:02 PM PDT 24
Finished Aug 08 05:16:11 PM PDT 24
Peak memory 240684 kb
Host smart-0552814b-6958-4f3e-80ab-f31aec405ee9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697789198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1697789198
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3427525173
Short name T768
Test name
Test status
Simulation time 1066189834 ps
CPU time 9.66 seconds
Started Aug 08 05:15:57 PM PDT 24
Finished Aug 08 05:16:07 PM PDT 24
Peak memory 240532 kb
Host smart-b007533e-4b15-4744-a721-7cd716b71101
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3427525173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3427525173
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1314175493
Short name T722
Test name
Test status
Simulation time 7789712 ps
CPU time 1.42 seconds
Started Aug 08 05:15:57 PM PDT 24
Finished Aug 08 05:15:58 PM PDT 24
Peak memory 237608 kb
Host smart-679e35a9-5ed6-4e6f-ac97-4767f263523a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1314175493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1314175493
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1566688679
Short name T773
Test name
Test status
Simulation time 2077690585 ps
CPU time 40.97 seconds
Started Aug 08 05:15:55 PM PDT 24
Finished Aug 08 05:16:36 PM PDT 24
Peak memory 245884 kb
Host smart-1cdb7e47-1a49-460c-9a64-157692c4afd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1566688679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1566688679
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.508186878
Short name T126
Test name
Test status
Simulation time 8207533404 ps
CPU time 156.63 seconds
Started Aug 08 05:15:51 PM PDT 24
Finished Aug 08 05:18:28 PM PDT 24
Peak memory 265576 kb
Host smart-14296b6c-9ed7-4ee0-b6fe-429cae8a6f74
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=508186878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.508186878
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3985109816
Short name T794
Test name
Test status
Simulation time 6046838454 ps
CPU time 484.69 seconds
Started Aug 08 05:16:05 PM PDT 24
Finished Aug 08 05:24:10 PM PDT 24
Peak memory 265616 kb
Host smart-fecd259c-6d6d-4251-bf5c-b53d25a5a8cd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985109816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3985109816
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.4139867493
Short name T806
Test name
Test status
Simulation time 275922986 ps
CPU time 9.76 seconds
Started Aug 08 05:15:58 PM PDT 24
Finished Aug 08 05:16:08 PM PDT 24
Peak memory 248356 kb
Host smart-15ba9464-a9bd-4126-8b04-1e92420d589b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4139867493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.4139867493
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.130264127
Short name T347
Test name
Test status
Simulation time 651695386 ps
CPU time 7.22 seconds
Started Aug 08 05:15:53 PM PDT 24
Finished Aug 08 05:16:00 PM PDT 24
Peak memory 240548 kb
Host smart-eb0fd3cf-5fa4-4ad4-b6dc-3d795a70e6e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130264127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.130264127
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1960388981
Short name T765
Test name
Test status
Simulation time 65141849 ps
CPU time 3.46 seconds
Started Aug 08 05:15:51 PM PDT 24
Finished Aug 08 05:15:55 PM PDT 24
Peak memory 237692 kb
Host smart-785de394-fe20-469c-a92b-ee8bd9f2735f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1960388981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1960388981
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.4138519154
Short name T774
Test name
Test status
Simulation time 33067588 ps
CPU time 1.56 seconds
Started Aug 08 05:15:58 PM PDT 24
Finished Aug 08 05:15:59 PM PDT 24
Peak memory 236640 kb
Host smart-4ccfb2ba-8ea2-4218-802b-47fcd1dd5d72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4138519154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.4138519154
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.4052696266
Short name T729
Test name
Test status
Simulation time 359294809 ps
CPU time 12.6 seconds
Started Aug 08 05:15:54 PM PDT 24
Finished Aug 08 05:16:07 PM PDT 24
Peak memory 245804 kb
Host smart-66fd034b-da73-44d5-9e55-567fd11cc0ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4052696266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.4052696266
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.4045829346
Short name T138
Test name
Test status
Simulation time 15650450761 ps
CPU time 142.34 seconds
Started Aug 08 05:15:52 PM PDT 24
Finished Aug 08 05:18:14 PM PDT 24
Peak memory 265612 kb
Host smart-0f4f9b3e-c726-4d7b-95c5-071b1932a838
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4045829346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.4045829346
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.964775790
Short name T754
Test name
Test status
Simulation time 359686380 ps
CPU time 7.87 seconds
Started Aug 08 05:15:51 PM PDT 24
Finished Aug 08 05:15:59 PM PDT 24
Peak memory 248804 kb
Host smart-0535efd5-a9f4-4331-8660-23972d7e5b4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=964775790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.964775790
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.556894581
Short name T173
Test name
Test status
Simulation time 85728174 ps
CPU time 5.62 seconds
Started Aug 08 05:15:59 PM PDT 24
Finished Aug 08 05:16:05 PM PDT 24
Peak memory 239684 kb
Host smart-e65e8d9d-2536-4e08-8184-106628ef761b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556894581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.556894581
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3267585297
Short name T750
Test name
Test status
Simulation time 21530546 ps
CPU time 3.58 seconds
Started Aug 08 05:15:53 PM PDT 24
Finished Aug 08 05:15:57 PM PDT 24
Peak memory 240656 kb
Host smart-447f025c-8c23-462f-b88b-24ab2187aeed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3267585297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3267585297
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2265249995
Short name T801
Test name
Test status
Simulation time 1134973650 ps
CPU time 40.15 seconds
Started Aug 08 05:15:53 PM PDT 24
Finished Aug 08 05:16:33 PM PDT 24
Peak memory 245744 kb
Host smart-eb69ffa2-b9e4-4d35-9962-df321d8e7728
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2265249995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2265249995
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3718122757
Short name T148
Test name
Test status
Simulation time 2831051360 ps
CPU time 186.9 seconds
Started Aug 08 05:15:57 PM PDT 24
Finished Aug 08 05:19:04 PM PDT 24
Peak memory 265484 kb
Host smart-7843bb5e-2d7d-4def-877a-5ddcdded72df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3718122757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3718122757
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1380101144
Short name T793
Test name
Test status
Simulation time 7815229425 ps
CPU time 561.97 seconds
Started Aug 08 05:15:52 PM PDT 24
Finished Aug 08 05:25:14 PM PDT 24
Peak memory 265476 kb
Host smart-8dcc538b-1ebf-4c5c-a342-36ac07326fb0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380101144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1380101144
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3014868481
Short name T748
Test name
Test status
Simulation time 164122856 ps
CPU time 10.36 seconds
Started Aug 08 05:15:55 PM PDT 24
Finished Aug 08 05:16:05 PM PDT 24
Peak memory 252652 kb
Host smart-4b294632-a0e0-41d4-a3e2-e4507fb8ff3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3014868481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3014868481
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1562956017
Short name T183
Test name
Test status
Simulation time 1175145408 ps
CPU time 161.54 seconds
Started Aug 08 05:15:29 PM PDT 24
Finished Aug 08 05:18:10 PM PDT 24
Peak memory 240536 kb
Host smart-acb3ae02-2396-4f7f-ba7d-d57550a1a13f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1562956017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1562956017
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.785745006
Short name T175
Test name
Test status
Simulation time 61642735641 ps
CPU time 244.77 seconds
Started Aug 08 05:15:32 PM PDT 24
Finished Aug 08 05:19:37 PM PDT 24
Peak memory 236720 kb
Host smart-13d016c8-415d-4c77-a72b-bd5dacbfeceb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=785745006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.785745006
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1336392351
Short name T790
Test name
Test status
Simulation time 194501001 ps
CPU time 8.6 seconds
Started Aug 08 05:15:40 PM PDT 24
Finished Aug 08 05:15:49 PM PDT 24
Peak memory 249264 kb
Host smart-85e9912e-d4b1-4fd8-a338-5178ff644a02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1336392351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1336392351
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2635519521
Short name T824
Test name
Test status
Simulation time 64946003 ps
CPU time 5.94 seconds
Started Aug 08 05:15:35 PM PDT 24
Finished Aug 08 05:15:41 PM PDT 24
Peak memory 248836 kb
Host smart-31dcb830-33ca-404a-b61c-d26d0e9b6198
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635519521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2635519521
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3750857331
Short name T802
Test name
Test status
Simulation time 515170171 ps
CPU time 8.98 seconds
Started Aug 08 05:15:29 PM PDT 24
Finished Aug 08 05:15:38 PM PDT 24
Peak memory 237628 kb
Host smart-8dc9b2c3-3642-49ba-a650-fee44e6c156f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3750857331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3750857331
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3371488895
Short name T758
Test name
Test status
Simulation time 11720515 ps
CPU time 1.34 seconds
Started Aug 08 05:15:23 PM PDT 24
Finished Aug 08 05:15:24 PM PDT 24
Peak memory 237636 kb
Host smart-bf3a005a-cc93-4e88-9447-04445ddec32d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3371488895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3371488895
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3158453703
Short name T809
Test name
Test status
Simulation time 172583947 ps
CPU time 25.22 seconds
Started Aug 08 05:15:30 PM PDT 24
Finished Aug 08 05:15:55 PM PDT 24
Peak memory 245884 kb
Host smart-f9fb23df-f0c1-44ab-91ea-07a15177ef79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3158453703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3158453703
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2982636064
Short name T136
Test name
Test status
Simulation time 4644945107 ps
CPU time 645.33 seconds
Started Aug 08 05:15:21 PM PDT 24
Finished Aug 08 05:26:07 PM PDT 24
Peak memory 265556 kb
Host smart-4bd9d655-07f6-41cb-b4c6-3dab46961c9e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982636064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2982636064
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1201873488
Short name T766
Test name
Test status
Simulation time 109814714 ps
CPU time 8.93 seconds
Started Aug 08 05:15:39 PM PDT 24
Finished Aug 08 05:15:48 PM PDT 24
Peak memory 253496 kb
Host smart-9581e5f1-309d-43c7-87cb-ae7310166c93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1201873488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1201873488
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2357431847
Short name T780
Test name
Test status
Simulation time 28647801 ps
CPU time 1.56 seconds
Started Aug 08 05:15:55 PM PDT 24
Finished Aug 08 05:15:57 PM PDT 24
Peak memory 237704 kb
Host smart-4b702644-b122-471a-9992-70c3becd57b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2357431847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2357431847
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.364460274
Short name T772
Test name
Test status
Simulation time 14019611 ps
CPU time 1.31 seconds
Started Aug 08 05:15:56 PM PDT 24
Finished Aug 08 05:15:57 PM PDT 24
Peak memory 236756 kb
Host smart-7a60987d-2730-40c6-b219-d5b0ac4ffff5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=364460274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.364460274
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2952159986
Short name T811
Test name
Test status
Simulation time 27578161 ps
CPU time 1.53 seconds
Started Aug 08 05:15:50 PM PDT 24
Finished Aug 08 05:15:52 PM PDT 24
Peak memory 236692 kb
Host smart-2d979248-8f3f-4fc3-8213-9469ae0e97c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2952159986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2952159986
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1759447300
Short name T820
Test name
Test status
Simulation time 24090449 ps
CPU time 1.45 seconds
Started Aug 08 05:15:58 PM PDT 24
Finished Aug 08 05:15:59 PM PDT 24
Peak memory 237684 kb
Host smart-56732a8d-7635-4a96-b438-7e27b77728f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1759447300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1759447300
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3900837409
Short name T756
Test name
Test status
Simulation time 14245823 ps
CPU time 1.34 seconds
Started Aug 08 05:15:52 PM PDT 24
Finished Aug 08 05:15:54 PM PDT 24
Peak memory 237636 kb
Host smart-42ae1c82-e991-439b-9537-884c23a3707d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3900837409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3900837409
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.629169886
Short name T746
Test name
Test status
Simulation time 7983513 ps
CPU time 1.53 seconds
Started Aug 08 05:15:57 PM PDT 24
Finished Aug 08 05:15:59 PM PDT 24
Peak memory 236720 kb
Host smart-bc0fd813-af0c-494a-8124-be4650c598d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=629169886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.629169886
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3291522852
Short name T807
Test name
Test status
Simulation time 25842233 ps
CPU time 1.54 seconds
Started Aug 08 05:15:56 PM PDT 24
Finished Aug 08 05:15:57 PM PDT 24
Peak memory 236656 kb
Host smart-1e1cc490-45f3-4c7e-be40-a4919bd96790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3291522852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3291522852
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2001461469
Short name T770
Test name
Test status
Simulation time 33134921 ps
CPU time 1.38 seconds
Started Aug 08 05:15:56 PM PDT 24
Finished Aug 08 05:15:58 PM PDT 24
Peak memory 237484 kb
Host smart-9800c53d-6ac6-4394-90e0-31e4357261b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2001461469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2001461469
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2887519606
Short name T723
Test name
Test status
Simulation time 6387787 ps
CPU time 1.4 seconds
Started Aug 08 05:15:56 PM PDT 24
Finished Aug 08 05:15:58 PM PDT 24
Peak memory 237688 kb
Host smart-c51e9e49-acbb-4904-b654-a57016d2e19f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2887519606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2887519606
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.580057350
Short name T735
Test name
Test status
Simulation time 2332746647 ps
CPU time 76.1 seconds
Started Aug 08 05:15:46 PM PDT 24
Finished Aug 08 05:17:03 PM PDT 24
Peak memory 240704 kb
Host smart-41c8f29d-0981-4315-a594-0206b39ac3dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=580057350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.580057350
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3616504066
Short name T186
Test name
Test status
Simulation time 6530945030 ps
CPU time 177.47 seconds
Started Aug 08 05:15:55 PM PDT 24
Finished Aug 08 05:18:52 PM PDT 24
Peak memory 240656 kb
Host smart-daf32aea-8085-4cc0-be5a-b933a2e47924
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3616504066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3616504066
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1076952696
Short name T739
Test name
Test status
Simulation time 22072306 ps
CPU time 3.93 seconds
Started Aug 08 05:15:55 PM PDT 24
Finished Aug 08 05:15:59 PM PDT 24
Peak memory 248736 kb
Host smart-f1a95df5-4f76-435c-9a37-9a871993f677
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1076952696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1076952696
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.4282367659
Short name T767
Test name
Test status
Simulation time 1349026186 ps
CPU time 9.12 seconds
Started Aug 08 05:15:40 PM PDT 24
Finished Aug 08 05:15:50 PM PDT 24
Peak memory 239848 kb
Host smart-5b5fd85e-d7fe-47c7-b641-c2b336c35efb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282367659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.4282367659
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.4268209419
Short name T749
Test name
Test status
Simulation time 24915534 ps
CPU time 1.52 seconds
Started Aug 08 05:15:38 PM PDT 24
Finished Aug 08 05:15:40 PM PDT 24
Peak memory 237616 kb
Host smart-d48b0c18-9067-4554-b1c2-12b9317e57ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4268209419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.4268209419
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3802381446
Short name T717
Test name
Test status
Simulation time 5651862667 ps
CPU time 24.7 seconds
Started Aug 08 05:15:40 PM PDT 24
Finished Aug 08 05:16:05 PM PDT 24
Peak memory 248876 kb
Host smart-5a273c44-a1ba-4837-ae0d-36abd2b51968
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3802381446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3802381446
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2873163099
Short name T122
Test name
Test status
Simulation time 3988708498 ps
CPU time 172.99 seconds
Started Aug 08 05:15:26 PM PDT 24
Finished Aug 08 05:18:19 PM PDT 24
Peak memory 267556 kb
Host smart-c1685504-f3a4-4a16-be5c-0c2a3825ce75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2873163099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2873163099
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2503020222
Short name T792
Test name
Test status
Simulation time 127488143 ps
CPU time 8.32 seconds
Started Aug 08 05:15:32 PM PDT 24
Finished Aug 08 05:15:41 PM PDT 24
Peak memory 248556 kb
Host smart-1bcb5095-1b00-4919-a664-f933870928c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2503020222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2503020222
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1207596429
Short name T817
Test name
Test status
Simulation time 8560276 ps
CPU time 1.37 seconds
Started Aug 08 05:15:53 PM PDT 24
Finished Aug 08 05:15:54 PM PDT 24
Peak memory 236832 kb
Host smart-0688b4a9-ceff-460a-8ce4-0af5a69a07e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1207596429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1207596429
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2638197640
Short name T745
Test name
Test status
Simulation time 10257808 ps
CPU time 1.57 seconds
Started Aug 08 05:15:57 PM PDT 24
Finished Aug 08 05:15:58 PM PDT 24
Peak memory 236732 kb
Host smart-9691fd8b-5143-48ef-87fb-49ef4e472041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2638197640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2638197640
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2528701831
Short name T769
Test name
Test status
Simulation time 21711599 ps
CPU time 1.23 seconds
Started Aug 08 05:15:52 PM PDT 24
Finished Aug 08 05:15:53 PM PDT 24
Peak memory 237688 kb
Host smart-ee1f01f7-6bb2-4991-ad1b-f010de2884e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2528701831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2528701831
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2247643287
Short name T800
Test name
Test status
Simulation time 8970213 ps
CPU time 1.3 seconds
Started Aug 08 05:16:01 PM PDT 24
Finished Aug 08 05:16:02 PM PDT 24
Peak memory 235588 kb
Host smart-4bb33fc8-7cce-467e-aa1a-bc13e35ed30c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2247643287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2247643287
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1420588518
Short name T740
Test name
Test status
Simulation time 33164657 ps
CPU time 1.28 seconds
Started Aug 08 05:15:57 PM PDT 24
Finished Aug 08 05:15:59 PM PDT 24
Peak memory 237552 kb
Host smart-8d43cbfb-a7e4-468e-91f7-0f40c7da7e02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1420588518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1420588518
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3738476554
Short name T713
Test name
Test status
Simulation time 11050606 ps
CPU time 1.31 seconds
Started Aug 08 05:15:55 PM PDT 24
Finished Aug 08 05:15:56 PM PDT 24
Peak memory 235660 kb
Host smart-f76770d5-dd57-474c-a5ca-49e858d4f262
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3738476554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3738476554
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2881844793
Short name T805
Test name
Test status
Simulation time 9772837 ps
CPU time 1.57 seconds
Started Aug 08 05:15:56 PM PDT 24
Finished Aug 08 05:15:57 PM PDT 24
Peak memory 236632 kb
Host smart-efa02740-f111-4825-be6b-8cf56c7f0f5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2881844793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2881844793
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3231171887
Short name T158
Test name
Test status
Simulation time 22357377 ps
CPU time 2.16 seconds
Started Aug 08 05:15:53 PM PDT 24
Finished Aug 08 05:15:56 PM PDT 24
Peak memory 237616 kb
Host smart-714da565-94a7-42ff-bd3f-52ec5f8905f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3231171887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3231171887
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.4035501750
Short name T728
Test name
Test status
Simulation time 9632435 ps
CPU time 1.33 seconds
Started Aug 08 05:16:00 PM PDT 24
Finished Aug 08 05:16:01 PM PDT 24
Peak memory 237588 kb
Host smart-3d7f5c27-8a48-4661-91c2-8da9fe230d4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4035501750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.4035501750
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3550796105
Short name T828
Test name
Test status
Simulation time 7765823 ps
CPU time 1.42 seconds
Started Aug 08 05:15:57 PM PDT 24
Finished Aug 08 05:15:58 PM PDT 24
Peak memory 236712 kb
Host smart-19a6c56c-a28d-44de-bc29-1fb3ca651808
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3550796105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3550796105
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3273162849
Short name T784
Test name
Test status
Simulation time 3354109288 ps
CPU time 109.09 seconds
Started Aug 08 05:15:40 PM PDT 24
Finished Aug 08 05:17:29 PM PDT 24
Peak memory 237828 kb
Host smart-bd4a49b2-d537-4f13-94e3-2f437df18f4d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3273162849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3273162849
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1899131259
Short name T814
Test name
Test status
Simulation time 5700363842 ps
CPU time 268.07 seconds
Started Aug 08 05:15:33 PM PDT 24
Finished Aug 08 05:20:01 PM PDT 24
Peak memory 237692 kb
Host smart-c2f3174c-df35-4c7d-9e32-6e8f70107a78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1899131259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1899131259
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2812439291
Short name T823
Test name
Test status
Simulation time 40455686 ps
CPU time 3.64 seconds
Started Aug 08 05:15:47 PM PDT 24
Finished Aug 08 05:15:51 PM PDT 24
Peak memory 248696 kb
Host smart-f039b57d-9378-4ac6-aac1-fdc03dbf3ff1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2812439291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2812439291
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1315126827
Short name T815
Test name
Test status
Simulation time 56156270 ps
CPU time 7.83 seconds
Started Aug 08 05:15:45 PM PDT 24
Finished Aug 08 05:15:53 PM PDT 24
Peak memory 249928 kb
Host smart-30dcaebb-7121-4fa0-9504-2cda281586f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315126827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1315126827
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1291161132
Short name T741
Test name
Test status
Simulation time 98978260 ps
CPU time 8.26 seconds
Started Aug 08 05:15:48 PM PDT 24
Finished Aug 08 05:15:56 PM PDT 24
Peak memory 237680 kb
Host smart-3124dfcc-d664-4850-95cd-45818c0c627b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1291161132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1291161132
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.784565842
Short name T751
Test name
Test status
Simulation time 21849707 ps
CPU time 1.4 seconds
Started Aug 08 05:15:37 PM PDT 24
Finished Aug 08 05:15:38 PM PDT 24
Peak memory 237636 kb
Host smart-e1d5c046-cee6-48ca-b79b-b820e76f6027
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=784565842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.784565842
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2705074787
Short name T764
Test name
Test status
Simulation time 2588307479 ps
CPU time 48.95 seconds
Started Aug 08 05:15:41 PM PDT 24
Finished Aug 08 05:16:30 PM PDT 24
Peak memory 245948 kb
Host smart-b5651d79-b93f-41b6-b098-d4828bbef55c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2705074787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2705074787
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.912873653
Short name T127
Test name
Test status
Simulation time 1922112785 ps
CPU time 104.99 seconds
Started Aug 08 05:15:41 PM PDT 24
Finished Aug 08 05:17:26 PM PDT 24
Peak memory 265544 kb
Host smart-726e4826-57fc-4e47-bff5-bcd0758be2b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=912873653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.912873653
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1033615374
Short name T135
Test name
Test status
Simulation time 13720220876 ps
CPU time 535.85 seconds
Started Aug 08 05:15:35 PM PDT 24
Finished Aug 08 05:24:31 PM PDT 24
Peak memory 265556 kb
Host smart-c9e9079b-d378-426b-86f9-6f5c66630225
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033615374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1033615374
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3948642222
Short name T785
Test name
Test status
Simulation time 469202007 ps
CPU time 17.96 seconds
Started Aug 08 05:15:36 PM PDT 24
Finished Aug 08 05:15:54 PM PDT 24
Peak memory 248316 kb
Host smart-18926050-b2ab-46d4-9084-0ef6cdbc95ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3948642222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3948642222
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.544898616
Short name T795
Test name
Test status
Simulation time 892173780 ps
CPU time 65.05 seconds
Started Aug 08 05:15:39 PM PDT 24
Finished Aug 08 05:16:44 PM PDT 24
Peak memory 240460 kb
Host smart-4080f922-7f9c-46e5-b1f9-903d05a29c60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=544898616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.544898616
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.4120517216
Short name T798
Test name
Test status
Simulation time 10170932 ps
CPU time 1.73 seconds
Started Aug 08 05:16:00 PM PDT 24
Finished Aug 08 05:16:01 PM PDT 24
Peak memory 237588 kb
Host smart-4739cf68-2414-441e-9ed9-1421eb490b7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4120517216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.4120517216
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1781357347
Short name T159
Test name
Test status
Simulation time 13444840 ps
CPU time 1.36 seconds
Started Aug 08 05:15:59 PM PDT 24
Finished Aug 08 05:16:00 PM PDT 24
Peak memory 235624 kb
Host smart-ea99b860-bdf6-4315-b003-4f0819fcd366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1781357347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1781357347
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1749147691
Short name T342
Test name
Test status
Simulation time 12770786 ps
CPU time 1.51 seconds
Started Aug 08 05:15:52 PM PDT 24
Finished Aug 08 05:15:53 PM PDT 24
Peak memory 236824 kb
Host smart-9a18945b-9fbc-446a-baf1-9be32f201138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1749147691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1749147691
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.4073127262
Short name T789
Test name
Test status
Simulation time 14033439 ps
CPU time 1.34 seconds
Started Aug 08 05:15:59 PM PDT 24
Finished Aug 08 05:16:00 PM PDT 24
Peak memory 237652 kb
Host smart-b10853b3-d602-4cfd-9801-0b11b02157d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4073127262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.4073127262
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1076790838
Short name T236
Test name
Test status
Simulation time 10425088 ps
CPU time 1.65 seconds
Started Aug 08 05:15:59 PM PDT 24
Finished Aug 08 05:16:01 PM PDT 24
Peak memory 237624 kb
Host smart-8e3c6e28-8b6e-4d23-91c9-929a822107fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1076790838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1076790838
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.84376927
Short name T763
Test name
Test status
Simulation time 9538900 ps
CPU time 1.34 seconds
Started Aug 08 05:16:07 PM PDT 24
Finished Aug 08 05:16:09 PM PDT 24
Peak memory 237616 kb
Host smart-036b3470-6b2c-4852-b276-8ab895911d05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=84376927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.84376927
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.29926471
Short name T715
Test name
Test status
Simulation time 27023337 ps
CPU time 1.31 seconds
Started Aug 08 05:16:01 PM PDT 24
Finished Aug 08 05:16:02 PM PDT 24
Peak memory 237680 kb
Host smart-6363030f-8fd3-49ec-9825-b428aa890c0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=29926471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.29926471
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.4294150975
Short name T716
Test name
Test status
Simulation time 7330921 ps
CPU time 1.46 seconds
Started Aug 08 05:15:57 PM PDT 24
Finished Aug 08 05:15:59 PM PDT 24
Peak memory 236728 kb
Host smart-f31cab1f-642f-4497-923d-243a458f0063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4294150975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.4294150975
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1007400840
Short name T345
Test name
Test status
Simulation time 8210991 ps
CPU time 1.51 seconds
Started Aug 08 05:15:55 PM PDT 24
Finished Aug 08 05:15:56 PM PDT 24
Peak memory 235776 kb
Host smart-a110efd2-61f4-4902-bfe7-be2417b0153d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1007400840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1007400840
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.857135978
Short name T727
Test name
Test status
Simulation time 11392323 ps
CPU time 1.42 seconds
Started Aug 08 05:16:06 PM PDT 24
Finished Aug 08 05:16:08 PM PDT 24
Peak memory 237696 kb
Host smart-834ef6ff-575f-4dcf-ad36-a3a45e042137
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=857135978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.857135978
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2278625056
Short name T235
Test name
Test status
Simulation time 368444837 ps
CPU time 8.6 seconds
Started Aug 08 05:15:46 PM PDT 24
Finished Aug 08 05:15:55 PM PDT 24
Peak memory 239556 kb
Host smart-a5fa260f-c3a8-4ef5-b872-776a77fbc41d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278625056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2278625056
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.16878150
Short name T818
Test name
Test status
Simulation time 163686530 ps
CPU time 5.12 seconds
Started Aug 08 05:15:44 PM PDT 24
Finished Aug 08 05:15:50 PM PDT 24
Peak memory 236728 kb
Host smart-9d61935f-c46a-480a-b658-9e36308ba3d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=16878150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.16878150
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.701065872
Short name T712
Test name
Test status
Simulation time 7655907 ps
CPU time 1.27 seconds
Started Aug 08 05:15:41 PM PDT 24
Finished Aug 08 05:15:42 PM PDT 24
Peak memory 237700 kb
Host smart-269db761-b6d2-4687-8108-1ba54b8a8e74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=701065872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.701065872
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3882591475
Short name T761
Test name
Test status
Simulation time 171237854 ps
CPU time 22.77 seconds
Started Aug 08 05:15:47 PM PDT 24
Finished Aug 08 05:16:10 PM PDT 24
Peak memory 244896 kb
Host smart-5c38a088-4eed-4cbf-92f1-0cd7396454ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3882591475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3882591475
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.4027075488
Short name T132
Test name
Test status
Simulation time 17292865394 ps
CPU time 290.75 seconds
Started Aug 08 05:15:43 PM PDT 24
Finished Aug 08 05:20:34 PM PDT 24
Peak memory 265548 kb
Host smart-cb37c219-1746-44fa-8a96-2303f4a51033
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4027075488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.4027075488
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3803541875
Short name T124
Test name
Test status
Simulation time 20780012431 ps
CPU time 979.27 seconds
Started Aug 08 05:15:43 PM PDT 24
Finished Aug 08 05:32:02 PM PDT 24
Peak memory 266560 kb
Host smart-eb0cfd9f-fd6d-4185-91b2-85de5d00dcb3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803541875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3803541875
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.375848610
Short name T721
Test name
Test status
Simulation time 415162368 ps
CPU time 15.53 seconds
Started Aug 08 05:15:51 PM PDT 24
Finished Aug 08 05:16:06 PM PDT 24
Peak memory 254016 kb
Host smart-53d6c45b-3011-4a2a-a8ab-1cf7aa3c8c84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=375848610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.375848610
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1304408167
Short name T787
Test name
Test status
Simulation time 40183158 ps
CPU time 6.3 seconds
Started Aug 08 05:15:57 PM PDT 24
Finished Aug 08 05:16:03 PM PDT 24
Peak memory 248908 kb
Host smart-6d4aa1f3-0572-4100-8e98-8ad01e1b97d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304408167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1304408167
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2336866960
Short name T752
Test name
Test status
Simulation time 324222147 ps
CPU time 6.04 seconds
Started Aug 08 05:15:54 PM PDT 24
Finished Aug 08 05:16:01 PM PDT 24
Peak memory 237572 kb
Host smart-841588d4-4973-4d76-afe2-6395937afeb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2336866960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2336866960
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3612902014
Short name T726
Test name
Test status
Simulation time 10519051 ps
CPU time 1.44 seconds
Started Aug 08 05:15:52 PM PDT 24
Finished Aug 08 05:15:53 PM PDT 24
Peak memory 235812 kb
Host smart-3ff6634b-95c0-4a08-8b33-571b7994a6cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3612902014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3612902014
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3635595838
Short name T757
Test name
Test status
Simulation time 330702281 ps
CPU time 11.93 seconds
Started Aug 08 05:15:44 PM PDT 24
Finished Aug 08 05:15:56 PM PDT 24
Peak memory 240520 kb
Host smart-e9d694bf-7074-4aa8-8022-c7239b2bc44f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3635595838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3635595838
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3254475059
Short name T149
Test name
Test status
Simulation time 4889100116 ps
CPU time 653.71 seconds
Started Aug 08 05:15:36 PM PDT 24
Finished Aug 08 05:26:30 PM PDT 24
Peak memory 265604 kb
Host smart-a66258ee-66e3-427a-99c7-88eee3e5b141
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254475059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3254475059
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.371173918
Short name T831
Test name
Test status
Simulation time 1089404364 ps
CPU time 13.66 seconds
Started Aug 08 05:15:47 PM PDT 24
Finished Aug 08 05:16:01 PM PDT 24
Peak memory 254528 kb
Host smart-af0f0638-b36d-42d8-bac3-d8b9512ac29d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=371173918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.371173918
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2100962855
Short name T262
Test name
Test status
Simulation time 304451118 ps
CPU time 43.42 seconds
Started Aug 08 05:15:47 PM PDT 24
Finished Aug 08 05:16:30 PM PDT 24
Peak memory 240548 kb
Host smart-72b6497c-a088-4393-af69-e418bb1098f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2100962855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2100962855
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3245214753
Short name T819
Test name
Test status
Simulation time 128788346 ps
CPU time 11.18 seconds
Started Aug 08 05:15:51 PM PDT 24
Finished Aug 08 05:16:03 PM PDT 24
Peak memory 253684 kb
Host smart-a0a2c7f2-b7aa-4cc5-9b38-63d2d51cb6b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245214753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3245214753
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1345862432
Short name T783
Test name
Test status
Simulation time 71156755 ps
CPU time 6.31 seconds
Started Aug 08 05:15:51 PM PDT 24
Finished Aug 08 05:15:58 PM PDT 24
Peak memory 237572 kb
Host smart-babf5835-67d3-47a9-889d-8d02415ab929
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1345862432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1345862432
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3804196138
Short name T339
Test name
Test status
Simulation time 24929201 ps
CPU time 1.52 seconds
Started Aug 08 05:15:47 PM PDT 24
Finished Aug 08 05:15:49 PM PDT 24
Peak memory 237672 kb
Host smart-d78e561b-8e1c-417b-bc5c-940c1b867c91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3804196138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3804196138
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3499043864
Short name T734
Test name
Test status
Simulation time 178982919 ps
CPU time 26.17 seconds
Started Aug 08 05:15:47 PM PDT 24
Finished Aug 08 05:16:14 PM PDT 24
Peak memory 248824 kb
Host smart-e43e087c-73c5-437f-a00b-313a41baec59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3499043864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3499043864
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3957587187
Short name T153
Test name
Test status
Simulation time 2325620635 ps
CPU time 171.98 seconds
Started Aug 08 05:15:51 PM PDT 24
Finished Aug 08 05:18:44 PM PDT 24
Peak memory 265580 kb
Host smart-ab11166d-b76b-4ac6-b223-2b50ae4acf6a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3957587187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3957587187
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1689628623
Short name T797
Test name
Test status
Simulation time 847004170 ps
CPU time 14.58 seconds
Started Aug 08 05:15:44 PM PDT 24
Finished Aug 08 05:15:59 PM PDT 24
Peak memory 248888 kb
Host smart-91694fc0-eddb-4bea-8fe7-2d557b4b3e84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1689628623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1689628623
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2087582393
Short name T730
Test name
Test status
Simulation time 113589918 ps
CPU time 9.82 seconds
Started Aug 08 05:15:53 PM PDT 24
Finished Aug 08 05:16:03 PM PDT 24
Peak memory 253236 kb
Host smart-1835a950-2511-421f-b472-2cb4fcd5c3b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087582393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2087582393
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.67562151
Short name T733
Test name
Test status
Simulation time 34456460 ps
CPU time 5.42 seconds
Started Aug 08 05:15:43 PM PDT 24
Finished Aug 08 05:15:49 PM PDT 24
Peak memory 237540 kb
Host smart-6851a7d0-b2cf-4304-891e-6b2d0661b21a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=67562151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.67562151
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.828433028
Short name T341
Test name
Test status
Simulation time 67425082 ps
CPU time 1.38 seconds
Started Aug 08 05:15:48 PM PDT 24
Finished Aug 08 05:15:50 PM PDT 24
Peak memory 236676 kb
Host smart-0b6f2bb3-669f-4f8a-a544-2344491c123a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=828433028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.828433028
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2172914751
Short name T777
Test name
Test status
Simulation time 184848174 ps
CPU time 10.92 seconds
Started Aug 08 05:15:52 PM PDT 24
Finished Aug 08 05:16:03 PM PDT 24
Peak memory 244876 kb
Host smart-16fdc48a-3c15-46db-8fa2-12c8d72ce620
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2172914751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2172914751
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.4281345672
Short name T753
Test name
Test status
Simulation time 104147440 ps
CPU time 7.75 seconds
Started Aug 08 05:15:49 PM PDT 24
Finished Aug 08 05:15:57 PM PDT 24
Peak memory 249808 kb
Host smart-8ba4aa33-7965-4609-9304-ba923319336b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4281345672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.4281345672
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1205663826
Short name T791
Test name
Test status
Simulation time 243601358 ps
CPU time 9.08 seconds
Started Aug 08 05:15:38 PM PDT 24
Finished Aug 08 05:15:48 PM PDT 24
Peak memory 253352 kb
Host smart-6785be57-ec57-446b-9ad5-5819077f93e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205663826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1205663826
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2136427084
Short name T832
Test name
Test status
Simulation time 97325389 ps
CPU time 4.61 seconds
Started Aug 08 05:15:49 PM PDT 24
Finished Aug 08 05:15:53 PM PDT 24
Peak memory 240648 kb
Host smart-4f3508be-d096-41a9-8228-b57cb01c51e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2136427084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2136427084
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.547925749
Short name T781
Test name
Test status
Simulation time 8979785 ps
CPU time 1.4 seconds
Started Aug 08 05:15:48 PM PDT 24
Finished Aug 08 05:15:49 PM PDT 24
Peak memory 237628 kb
Host smart-ed063992-19f3-4966-9633-f9747ae9b653
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=547925749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.547925749
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1018054339
Short name T185
Test name
Test status
Simulation time 83641345 ps
CPU time 11.68 seconds
Started Aug 08 05:15:50 PM PDT 24
Finished Aug 08 05:16:02 PM PDT 24
Peak memory 244964 kb
Host smart-192fb01d-5819-40c8-b694-00dc799ccbcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1018054339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1018054339
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1908230
Short name T118
Test name
Test status
Simulation time 15083269591 ps
CPU time 558.58 seconds
Started Aug 08 05:15:49 PM PDT 24
Finished Aug 08 05:25:08 PM PDT 24
Peak memory 268784 kb
Host smart-4dd3fd63-0465-4eb9-b786-20dd436919cb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1908230
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1155435464
Short name T719
Test name
Test status
Simulation time 158700629 ps
CPU time 11.71 seconds
Started Aug 08 05:15:47 PM PDT 24
Finished Aug 08 05:15:59 PM PDT 24
Peak memory 249904 kb
Host smart-481a0720-5303-4d05-83d0-d17eab05737c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1155435464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1155435464
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.298260270
Short name T47
Test name
Test status
Simulation time 104507558013 ps
CPU time 1951.33 seconds
Started Aug 08 04:29:29 PM PDT 24
Finished Aug 08 05:02:01 PM PDT 24
Peak memory 288068 kb
Host smart-ccac6805-a1e4-4543-b760-f7f50d3973e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298260270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.298260270
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3322930230
Short name T454
Test name
Test status
Simulation time 3594980964 ps
CPU time 24.46 seconds
Started Aug 08 04:29:35 PM PDT 24
Finished Aug 08 04:30:00 PM PDT 24
Peak memory 248268 kb
Host smart-a0fca7dc-8444-4043-96d6-04f73795e60c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3322930230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3322930230
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1351902365
Short name T475
Test name
Test status
Simulation time 10451829373 ps
CPU time 129.7 seconds
Started Aug 08 04:29:21 PM PDT 24
Finished Aug 08 04:31:31 PM PDT 24
Peak memory 256372 kb
Host smart-c5e00522-491c-40c5-b4b0-37d22a02237f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13519
02365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1351902365
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1590852350
Short name T443
Test name
Test status
Simulation time 3322667490 ps
CPU time 56.56 seconds
Started Aug 08 04:29:41 PM PDT 24
Finished Aug 08 04:30:38 PM PDT 24
Peak memory 256192 kb
Host smart-1b085331-442d-4359-87cf-5b7430906bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15908
52350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1590852350
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3285471287
Short name T31
Test name
Test status
Simulation time 165018025371 ps
CPU time 2117.02 seconds
Started Aug 08 04:29:32 PM PDT 24
Finished Aug 08 05:04:49 PM PDT 24
Peak memory 288500 kb
Host smart-f565b458-6ea1-4769-9e7b-d17b4330558a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285471287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3285471287
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3687818326
Short name T309
Test name
Test status
Simulation time 45664804743 ps
CPU time 464.85 seconds
Started Aug 08 04:29:34 PM PDT 24
Finished Aug 08 04:37:19 PM PDT 24
Peak memory 247056 kb
Host smart-2fd33d41-9ded-4b17-91c1-ac120a64b0be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687818326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3687818326
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2764551310
Short name T406
Test name
Test status
Simulation time 952140634 ps
CPU time 52.66 seconds
Started Aug 08 04:29:27 PM PDT 24
Finished Aug 08 04:30:20 PM PDT 24
Peak memory 255700 kb
Host smart-3e5be478-5876-4ab2-8ba5-610cf804acd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27645
51310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2764551310
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1753625206
Short name T8
Test name
Test status
Simulation time 1548840267 ps
CPU time 20.9 seconds
Started Aug 08 04:29:37 PM PDT 24
Finished Aug 08 04:29:58 PM PDT 24
Peak memory 270012 kb
Host smart-1b96a2a3-b770-4575-b956-d7c4387065e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1753625206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1753625206
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.688253254
Short name T69
Test name
Test status
Simulation time 1209317283 ps
CPU time 33.75 seconds
Started Aug 08 04:29:26 PM PDT 24
Finished Aug 08 04:30:00 PM PDT 24
Peak memory 248120 kb
Host smart-a28553d0-01d9-40bf-af13-3edcbf37b7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68825
3254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.688253254
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2678139616
Short name T671
Test name
Test status
Simulation time 3696509269 ps
CPU time 38.14 seconds
Started Aug 08 04:29:21 PM PDT 24
Finished Aug 08 04:30:00 PM PDT 24
Peak memory 256348 kb
Host smart-c8e4e872-7135-45c0-b176-92a77290b7e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26781
39616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2678139616
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1653849822
Short name T607
Test name
Test status
Simulation time 83802105743 ps
CPU time 1840 seconds
Started Aug 08 04:29:39 PM PDT 24
Finished Aug 08 05:00:19 PM PDT 24
Peak memory 296972 kb
Host smart-3c92b46f-223b-40a5-8cc2-855467ff9c39
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653849822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1653849822
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.804790091
Short name T655
Test name
Test status
Simulation time 12453628271 ps
CPU time 700.93 seconds
Started Aug 08 04:29:29 PM PDT 24
Finished Aug 08 04:41:10 PM PDT 24
Peak memory 272716 kb
Host smart-84470182-9ae7-49b7-9a68-5423a0e4f596
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804790091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.804790091
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.970433850
Short name T362
Test name
Test status
Simulation time 7438229238 ps
CPU time 34.87 seconds
Started Aug 08 04:29:44 PM PDT 24
Finished Aug 08 04:30:19 PM PDT 24
Peak memory 248128 kb
Host smart-dd9974a3-6271-4f29-bd53-f6a69089ac10
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=970433850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.970433850
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3809069931
Short name T528
Test name
Test status
Simulation time 1913285238 ps
CPU time 34.61 seconds
Started Aug 08 04:29:45 PM PDT 24
Finished Aug 08 04:30:19 PM PDT 24
Peak memory 255924 kb
Host smart-5d7b9454-048a-4403-a558-30cecef0672f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38090
69931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3809069931
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.4150879947
Short name T670
Test name
Test status
Simulation time 186881147 ps
CPU time 10.47 seconds
Started Aug 08 04:29:37 PM PDT 24
Finished Aug 08 04:29:48 PM PDT 24
Peak memory 247768 kb
Host smart-16f4dac4-a11a-472c-981a-b205287e1bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41508
79947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.4150879947
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3930213360
Short name T214
Test name
Test status
Simulation time 8322111891 ps
CPU time 818.45 seconds
Started Aug 08 04:29:44 PM PDT 24
Finished Aug 08 04:43:23 PM PDT 24
Peak memory 272108 kb
Host smart-a355ef58-476e-43e4-ac4a-20d65640099f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930213360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3930213360
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1467680862
Short name T14
Test name
Test status
Simulation time 323711509466 ps
CPU time 1394.32 seconds
Started Aug 08 04:29:35 PM PDT 24
Finished Aug 08 04:52:50 PM PDT 24
Peak memory 272616 kb
Host smart-2d80b458-1a78-4522-ba67-0f5f4bccca59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467680862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1467680862
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.848990080
Short name T312
Test name
Test status
Simulation time 58510064959 ps
CPU time 341.53 seconds
Started Aug 08 04:29:38 PM PDT 24
Finished Aug 08 04:35:20 PM PDT 24
Peak memory 248060 kb
Host smart-8fa511af-ff81-48bc-8618-72f3c6d79f6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848990080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.848990080
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.4050267486
Short name T353
Test name
Test status
Simulation time 6202560674 ps
CPU time 35.55 seconds
Started Aug 08 04:29:40 PM PDT 24
Finished Aug 08 04:30:16 PM PDT 24
Peak memory 255656 kb
Host smart-9b861b05-2c59-4c2c-b94d-65d9f6d15906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40502
67486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.4050267486
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2063781446
Short name T402
Test name
Test status
Simulation time 175541894 ps
CPU time 10.42 seconds
Started Aug 08 04:29:46 PM PDT 24
Finished Aug 08 04:29:56 PM PDT 24
Peak memory 248220 kb
Host smart-044016fe-4d79-4a47-8afa-d7f81fdd22f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20637
81446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2063781446
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1359302651
Short name T274
Test name
Test status
Simulation time 90101494 ps
CPU time 7.3 seconds
Started Aug 08 04:29:30 PM PDT 24
Finished Aug 08 04:29:37 PM PDT 24
Peak memory 252936 kb
Host smart-06152874-bd3f-472f-b03f-489dc6809ae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13593
02651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1359302651
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.4216003885
Short name T574
Test name
Test status
Simulation time 114828474 ps
CPU time 8.12 seconds
Started Aug 08 04:29:42 PM PDT 24
Finished Aug 08 04:29:51 PM PDT 24
Peak memory 251328 kb
Host smart-47ffb131-1574-43bd-89e7-194eaa60dbcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42160
03885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.4216003885
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.4034684463
Short name T187
Test name
Test status
Simulation time 30953463 ps
CPU time 3.11 seconds
Started Aug 08 04:29:59 PM PDT 24
Finished Aug 08 04:30:02 PM PDT 24
Peak memory 248352 kb
Host smart-525c338d-1434-49ac-8951-1ce15900c353
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4034684463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.4034684463
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3021026957
Short name T108
Test name
Test status
Simulation time 140962658193 ps
CPU time 1600.05 seconds
Started Aug 08 04:30:03 PM PDT 24
Finished Aug 08 04:56:43 PM PDT 24
Peak memory 268700 kb
Host smart-da5ad8f4-21a4-4dbf-bdc6-b49b50dbef1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021026957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3021026957
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1711304
Short name T381
Test name
Test status
Simulation time 6345171224 ps
CPU time 33.8 seconds
Started Aug 08 04:30:06 PM PDT 24
Finished Aug 08 04:30:40 PM PDT 24
Peak memory 248172 kb
Host smart-cf019dd0-bf36-4c52-b883-3bda99bb3df7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1711304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1711304
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1866627192
Short name T379
Test name
Test status
Simulation time 1217277644 ps
CPU time 51.82 seconds
Started Aug 08 04:29:59 PM PDT 24
Finished Aug 08 04:30:51 PM PDT 24
Peak memory 255432 kb
Host smart-43a19bdf-04fa-40a1-9661-cdbc069ae2ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18666
27192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1866627192
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3773349598
Short name T662
Test name
Test status
Simulation time 1314209663 ps
CPU time 59.35 seconds
Started Aug 08 04:29:58 PM PDT 24
Finished Aug 08 04:30:58 PM PDT 24
Peak memory 248080 kb
Host smart-ed4233ba-bb15-41ae-b36b-d265c9b0421d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37733
49598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3773349598
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.3637365365
Short name T328
Test name
Test status
Simulation time 21612604118 ps
CPU time 951.29 seconds
Started Aug 08 04:30:00 PM PDT 24
Finished Aug 08 04:45:52 PM PDT 24
Peak memory 272056 kb
Host smart-d5513968-4a28-46ab-8c0e-c7b492d3da50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637365365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3637365365
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.514578079
Short name T544
Test name
Test status
Simulation time 6413940167 ps
CPU time 608.96 seconds
Started Aug 08 04:29:57 PM PDT 24
Finished Aug 08 04:40:06 PM PDT 24
Peak memory 272584 kb
Host smart-df816fc5-3a2f-405c-b21b-5d5ccebda6c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514578079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.514578079
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1103739911
Short name T289
Test name
Test status
Simulation time 12593517409 ps
CPU time 306.26 seconds
Started Aug 08 04:30:03 PM PDT 24
Finished Aug 08 04:35:09 PM PDT 24
Peak memory 248160 kb
Host smart-abb9f3fb-4de1-4d05-83fa-665fa1cd989e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103739911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1103739911
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1589876353
Short name T648
Test name
Test status
Simulation time 254555635 ps
CPU time 5.17 seconds
Started Aug 08 04:29:58 PM PDT 24
Finished Aug 08 04:30:03 PM PDT 24
Peak memory 239960 kb
Host smart-b0a411b1-939e-4b92-b94d-32cb08acab50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15898
76353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1589876353
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1892519769
Short name T81
Test name
Test status
Simulation time 751292982 ps
CPU time 43.68 seconds
Started Aug 08 04:30:02 PM PDT 24
Finished Aug 08 04:30:46 PM PDT 24
Peak memory 255708 kb
Host smart-6615ee0d-bc93-4117-b4d0-89020f7b955b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18925
19769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1892519769
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.202383878
Short name T111
Test name
Test status
Simulation time 607829952 ps
CPU time 22.93 seconds
Started Aug 08 04:29:58 PM PDT 24
Finished Aug 08 04:30:21 PM PDT 24
Peak memory 255872 kb
Host smart-1fd7a86e-519b-495b-a7ea-0dcc3b557a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20238
3878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.202383878
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2730824151
Short name T518
Test name
Test status
Simulation time 874891047 ps
CPU time 16.17 seconds
Started Aug 08 04:29:59 PM PDT 24
Finished Aug 08 04:30:16 PM PDT 24
Peak memory 254880 kb
Host smart-6c759874-9ac3-468d-9c69-fa3655e01a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27308
24151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2730824151
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3257090258
Short name T199
Test name
Test status
Simulation time 118023663 ps
CPU time 2.41 seconds
Started Aug 08 04:29:58 PM PDT 24
Finished Aug 08 04:30:00 PM PDT 24
Peak memory 248468 kb
Host smart-71393367-d419-4e72-b812-e96e0948aff5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3257090258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3257090258
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1787904560
Short name T591
Test name
Test status
Simulation time 44959810081 ps
CPU time 2546.15 seconds
Started Aug 08 04:30:00 PM PDT 24
Finished Aug 08 05:12:26 PM PDT 24
Peak memory 288944 kb
Host smart-58df4fed-4798-4c4d-8c17-2105ab1f7d7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787904560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1787904560
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3869650415
Short name T695
Test name
Test status
Simulation time 634185407 ps
CPU time 10.26 seconds
Started Aug 08 04:30:02 PM PDT 24
Finished Aug 08 04:30:12 PM PDT 24
Peak memory 248288 kb
Host smart-cc723200-77d7-42c0-b01f-12ba99232a87
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3869650415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3869650415
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1850298085
Short name T363
Test name
Test status
Simulation time 7001029530 ps
CPU time 63.19 seconds
Started Aug 08 04:30:02 PM PDT 24
Finished Aug 08 04:31:05 PM PDT 24
Peak memory 255644 kb
Host smart-f512655a-ebcb-4ddb-bdd2-d76e1122a5b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18502
98085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1850298085
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1058678765
Short name T425
Test name
Test status
Simulation time 1965670851 ps
CPU time 54.67 seconds
Started Aug 08 04:29:58 PM PDT 24
Finished Aug 08 04:30:53 PM PDT 24
Peak memory 248056 kb
Host smart-03bc069e-01a6-4369-980d-6dd2992eadaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10586
78765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1058678765
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.914792845
Short name T675
Test name
Test status
Simulation time 4482377336 ps
CPU time 203.76 seconds
Started Aug 08 04:30:01 PM PDT 24
Finished Aug 08 04:33:25 PM PDT 24
Peak memory 254504 kb
Host smart-ddc65927-1166-473b-a77a-179690279b2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914792845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.914792845
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1767996350
Short name T42
Test name
Test status
Simulation time 85801004 ps
CPU time 6.32 seconds
Started Aug 08 04:30:01 PM PDT 24
Finished Aug 08 04:30:07 PM PDT 24
Peak memory 248060 kb
Host smart-5d48267f-0b6e-436d-ab2f-ee6c6c1ec98f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17679
96350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1767996350
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.453261384
Short name T53
Test name
Test status
Simulation time 18719227887 ps
CPU time 53.73 seconds
Started Aug 08 04:30:00 PM PDT 24
Finished Aug 08 04:30:54 PM PDT 24
Peak memory 248288 kb
Host smart-e3e91768-9863-45ad-a00e-cb35f24768eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45326
1384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.453261384
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.4251177489
Short name T549
Test name
Test status
Simulation time 294338721 ps
CPU time 25.73 seconds
Started Aug 08 04:30:02 PM PDT 24
Finished Aug 08 04:30:28 PM PDT 24
Peak memory 248492 kb
Host smart-1c4b2395-74d8-48c3-ad7d-697ad0dbd5dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42511
77489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.4251177489
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3581564614
Short name T101
Test name
Test status
Simulation time 3263069720 ps
CPU time 11.61 seconds
Started Aug 08 04:30:02 PM PDT 24
Finished Aug 08 04:30:14 PM PDT 24
Peak memory 248172 kb
Host smart-1ddf9ec9-1fea-4d75-8111-8c29ad267454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35815
64614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3581564614
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.4084315237
Short name T613
Test name
Test status
Simulation time 84232702009 ps
CPU time 2151.89 seconds
Started Aug 08 04:29:58 PM PDT 24
Finished Aug 08 05:05:50 PM PDT 24
Peak memory 305720 kb
Host smart-1a8912cc-e480-40ab-a147-ced66182b157
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084315237 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.4084315237
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2940150377
Short name T198
Test name
Test status
Simulation time 130580965 ps
CPU time 3.5 seconds
Started Aug 08 04:30:01 PM PDT 24
Finished Aug 08 04:30:04 PM PDT 24
Peak memory 248268 kb
Host smart-2840b795-f863-4ec7-bf9a-61ec603281aa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2940150377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2940150377
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2071874629
Short name T50
Test name
Test status
Simulation time 12327547624 ps
CPU time 681.08 seconds
Started Aug 08 04:30:03 PM PDT 24
Finished Aug 08 04:41:24 PM PDT 24
Peak memory 272604 kb
Host smart-c2dfd43d-37b4-42c6-8df5-8c41989e6f0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071874629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2071874629
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2462160538
Short name T521
Test name
Test status
Simulation time 3040958824 ps
CPU time 16.64 seconds
Started Aug 08 04:30:03 PM PDT 24
Finished Aug 08 04:30:19 PM PDT 24
Peak memory 248216 kb
Host smart-88aa5ebc-ea85-4483-8b4a-509ba134afa0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2462160538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2462160538
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2643095215
Short name T639
Test name
Test status
Simulation time 4414091988 ps
CPU time 230.7 seconds
Started Aug 08 04:30:00 PM PDT 24
Finished Aug 08 04:33:51 PM PDT 24
Peak memory 255924 kb
Host smart-330f4611-a885-409d-bfea-306a5cf99ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26430
95215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2643095215
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2165668011
Short name T389
Test name
Test status
Simulation time 411842223 ps
CPU time 25.56 seconds
Started Aug 08 04:30:03 PM PDT 24
Finished Aug 08 04:30:29 PM PDT 24
Peak memory 248100 kb
Host smart-f234f227-fb83-4afd-8cec-fe5db307f714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21656
68011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2165668011
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.411479000
Short name T264
Test name
Test status
Simulation time 66871485192 ps
CPU time 939.67 seconds
Started Aug 08 04:30:00 PM PDT 24
Finished Aug 08 04:45:40 PM PDT 24
Peak memory 272820 kb
Host smart-9c98f0d6-98f0-487a-896d-a3fc9d169759
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411479000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.411479000
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2685094194
Short name T705
Test name
Test status
Simulation time 11839051426 ps
CPU time 394.79 seconds
Started Aug 08 04:29:57 PM PDT 24
Finished Aug 08 04:36:31 PM PDT 24
Peak memory 255672 kb
Host smart-2cd61866-05a4-4302-a1d9-7a7823c9eb68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685094194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2685094194
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3718757314
Short name T442
Test name
Test status
Simulation time 424357149 ps
CPU time 42.77 seconds
Started Aug 08 04:30:02 PM PDT 24
Finished Aug 08 04:30:45 PM PDT 24
Peak memory 256268 kb
Host smart-94506ada-bd0d-43dc-b922-d3c4b90dd785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37187
57314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3718757314
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.597432891
Short name T682
Test name
Test status
Simulation time 1064526448 ps
CPU time 15.82 seconds
Started Aug 08 04:30:00 PM PDT 24
Finished Aug 08 04:30:16 PM PDT 24
Peak memory 248244 kb
Host smart-53b4c64e-15b1-4553-a92f-897705a36886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59743
2891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.597432891
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1465345202
Short name T246
Test name
Test status
Simulation time 253972051 ps
CPU time 32.71 seconds
Started Aug 08 04:30:00 PM PDT 24
Finished Aug 08 04:30:33 PM PDT 24
Peak memory 255484 kb
Host smart-44a8d067-126f-4729-985a-2938ea912716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14653
45202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1465345202
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3885211871
Short name T709
Test name
Test status
Simulation time 853414623 ps
CPU time 22.1 seconds
Started Aug 08 04:29:58 PM PDT 24
Finished Aug 08 04:30:21 PM PDT 24
Peak memory 254860 kb
Host smart-08082ccb-898c-4ff5-9dd7-c931120f6272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38852
11871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3885211871
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3397159937
Short name T531
Test name
Test status
Simulation time 9599661925 ps
CPU time 178.81 seconds
Started Aug 08 04:30:00 PM PDT 24
Finished Aug 08 04:33:00 PM PDT 24
Peak memory 256220 kb
Host smart-3807ff78-ea42-49a9-a161-771b5d71b3d9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397159937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3397159937
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3164565647
Short name T237
Test name
Test status
Simulation time 1251145292 ps
CPU time 70.25 seconds
Started Aug 08 04:29:57 PM PDT 24
Finished Aug 08 04:31:08 PM PDT 24
Peak memory 249088 kb
Host smart-3e3d5872-73fb-4440-adca-1e2d18fac776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31645
65647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3164565647
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3770317118
Short name T561
Test name
Test status
Simulation time 530614183 ps
CPU time 39.34 seconds
Started Aug 08 04:30:00 PM PDT 24
Finished Aug 08 04:30:40 PM PDT 24
Peak memory 255724 kb
Host smart-d7bbbedb-db8a-4451-b155-36c3c0f9c838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37703
17118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3770317118
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3403151344
Short name T333
Test name
Test status
Simulation time 122558139759 ps
CPU time 1928.27 seconds
Started Aug 08 04:30:01 PM PDT 24
Finished Aug 08 05:02:09 PM PDT 24
Peak memory 280984 kb
Host smart-8fd8ded6-1b08-40dc-9bd1-1f07b3eca5dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403151344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3403151344
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.829771973
Short name T2
Test name
Test status
Simulation time 39742822840 ps
CPU time 2580.92 seconds
Started Aug 08 04:30:04 PM PDT 24
Finished Aug 08 05:13:05 PM PDT 24
Peak memory 288424 kb
Host smart-46dd1628-84c7-49aa-88ae-19424fb34a8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829771973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.829771973
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3061843532
Short name T690
Test name
Test status
Simulation time 16793202841 ps
CPU time 322.84 seconds
Started Aug 08 04:30:01 PM PDT 24
Finished Aug 08 04:35:24 PM PDT 24
Peak memory 247064 kb
Host smart-28ec79ce-a3c6-418e-8939-06b8c744f5a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061843532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3061843532
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2964530768
Short name T383
Test name
Test status
Simulation time 679239950 ps
CPU time 37.36 seconds
Started Aug 08 04:30:01 PM PDT 24
Finished Aug 08 04:30:38 PM PDT 24
Peak memory 255420 kb
Host smart-8e847621-df88-404d-aa14-29124fe9ab26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29645
30768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2964530768
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3857643728
Short name T419
Test name
Test status
Simulation time 207178705 ps
CPU time 5.12 seconds
Started Aug 08 04:29:57 PM PDT 24
Finished Aug 08 04:30:02 PM PDT 24
Peak memory 239572 kb
Host smart-bdb3e433-b3f3-4423-ba49-ead4dc5af734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38576
43728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3857643728
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1440135171
Short name T474
Test name
Test status
Simulation time 55796831 ps
CPU time 3.45 seconds
Started Aug 08 04:30:00 PM PDT 24
Finished Aug 08 04:30:04 PM PDT 24
Peak memory 249696 kb
Host smart-19f782d9-881a-4029-9afe-384649aa369c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14401
35171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1440135171
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.1602798125
Short name T25
Test name
Test status
Simulation time 71630581140 ps
CPU time 2531.92 seconds
Started Aug 08 04:30:02 PM PDT 24
Finished Aug 08 05:12:14 PM PDT 24
Peak memory 288656 kb
Host smart-80842e0b-d71e-462d-b74c-52e86f567594
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602798125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1602798125
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3115177238
Short name T179
Test name
Test status
Simulation time 233887389926 ps
CPU time 4276.15 seconds
Started Aug 08 04:30:02 PM PDT 24
Finished Aug 08 05:41:19 PM PDT 24
Peak memory 322096 kb
Host smart-bf237207-1b6c-49fb-8881-40666645e418
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115177238 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3115177238
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.502855681
Short name T190
Test name
Test status
Simulation time 14837556 ps
CPU time 2.85 seconds
Started Aug 08 04:30:23 PM PDT 24
Finished Aug 08 04:30:26 PM PDT 24
Peak memory 248476 kb
Host smart-8c732725-c7b8-422a-a3d4-9cc348b16d35
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=502855681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.502855681
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.291534190
Short name T372
Test name
Test status
Simulation time 41624212856 ps
CPU time 2628.15 seconds
Started Aug 08 04:30:01 PM PDT 24
Finished Aug 08 05:13:49 PM PDT 24
Peak memory 289072 kb
Host smart-2ea4023a-5176-436e-947d-626d115429e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291534190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.291534190
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2352607300
Short name T570
Test name
Test status
Simulation time 963306250 ps
CPU time 12.41 seconds
Started Aug 08 04:30:29 PM PDT 24
Finished Aug 08 04:30:42 PM PDT 24
Peak memory 248180 kb
Host smart-0231cb47-5a62-4e92-b72e-05c40b16ac78
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2352607300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2352607300
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1372699611
Short name T375
Test name
Test status
Simulation time 15379634373 ps
CPU time 131.32 seconds
Started Aug 08 04:30:03 PM PDT 24
Finished Aug 08 04:32:15 PM PDT 24
Peak memory 251364 kb
Host smart-33613a07-42c6-4bef-b1fe-55fa87ba2a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13726
99611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1372699611
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2754335465
Short name T527
Test name
Test status
Simulation time 6298505544 ps
CPU time 69.85 seconds
Started Aug 08 04:29:59 PM PDT 24
Finished Aug 08 04:31:09 PM PDT 24
Peak memory 248172 kb
Host smart-89224729-5503-47fa-862b-98577fac2ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27543
35465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2754335465
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1774771647
Short name T509
Test name
Test status
Simulation time 134697559368 ps
CPU time 2213.96 seconds
Started Aug 08 04:30:17 PM PDT 24
Finished Aug 08 05:07:11 PM PDT 24
Peak memory 284376 kb
Host smart-5979458d-5a22-4022-a268-2ba80468e026
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774771647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1774771647
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.648336238
Short name T660
Test name
Test status
Simulation time 50306667677 ps
CPU time 1187.81 seconds
Started Aug 08 04:30:19 PM PDT 24
Finished Aug 08 04:50:07 PM PDT 24
Peak memory 282204 kb
Host smart-dd838355-10cc-458c-b4ea-2d5092d5e0e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648336238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.648336238
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.273416744
Short name T301
Test name
Test status
Simulation time 20246845166 ps
CPU time 156.54 seconds
Started Aug 08 04:30:15 PM PDT 24
Finished Aug 08 04:32:52 PM PDT 24
Peak memory 248096 kb
Host smart-cfa018f3-1be0-4218-9ea2-9b9a99855ea0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273416744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.273416744
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3928817915
Short name T409
Test name
Test status
Simulation time 280873117 ps
CPU time 27.26 seconds
Started Aug 08 04:30:01 PM PDT 24
Finished Aug 08 04:30:28 PM PDT 24
Peak memory 255320 kb
Host smart-42f254fb-2d0d-4875-a2c2-d880d5d59b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39288
17915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3928817915
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1253403183
Short name T392
Test name
Test status
Simulation time 1928222414 ps
CPU time 35.42 seconds
Started Aug 08 04:30:03 PM PDT 24
Finished Aug 08 04:30:39 PM PDT 24
Peak memory 256336 kb
Host smart-82b7c157-35ff-4e6d-b3f1-069c2fe05c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12534
03183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1253403183
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2041392146
Short name T351
Test name
Test status
Simulation time 200708692 ps
CPU time 22.76 seconds
Started Aug 08 04:30:02 PM PDT 24
Finished Aug 08 04:30:25 PM PDT 24
Peak memory 256276 kb
Host smart-58bc2f29-4ee4-45d9-8188-1d13751c40e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20413
92146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2041392146
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.538621564
Short name T239
Test name
Test status
Simulation time 71236952877 ps
CPU time 1686.34 seconds
Started Aug 08 04:30:11 PM PDT 24
Finished Aug 08 04:58:17 PM PDT 24
Peak memory 302976 kb
Host smart-6e904315-f9ab-421d-b1d6-33d9ef98a9f0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538621564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.538621564
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1663359580
Short name T205
Test name
Test status
Simulation time 38835934 ps
CPU time 3.57 seconds
Started Aug 08 04:30:20 PM PDT 24
Finished Aug 08 04:30:23 PM PDT 24
Peak memory 248348 kb
Host smart-b86fe102-edf0-4aca-8752-8c44aa7caa7e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1663359580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1663359580
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3519513813
Short name T481
Test name
Test status
Simulation time 36336063458 ps
CPU time 1853.43 seconds
Started Aug 08 04:30:14 PM PDT 24
Finished Aug 08 05:01:08 PM PDT 24
Peak memory 288144 kb
Host smart-488cd8eb-d43e-4c65-8316-6c25f9e08756
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519513813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3519513813
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1081915345
Short name T674
Test name
Test status
Simulation time 186766881 ps
CPU time 11.54 seconds
Started Aug 08 04:30:09 PM PDT 24
Finished Aug 08 04:30:20 PM PDT 24
Peak memory 248172 kb
Host smart-c4e0ecff-aae4-4626-9023-634e6babf40d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1081915345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1081915345
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.61394926
Short name T530
Test name
Test status
Simulation time 2708268996 ps
CPU time 149.53 seconds
Started Aug 08 04:30:08 PM PDT 24
Finished Aug 08 04:32:37 PM PDT 24
Peak memory 256468 kb
Host smart-76c0cc6c-0930-40d3-96c6-210fc63c75a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61394
926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.61394926
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1695102146
Short name T391
Test name
Test status
Simulation time 196843272 ps
CPU time 7.98 seconds
Started Aug 08 04:30:20 PM PDT 24
Finished Aug 08 04:30:28 PM PDT 24
Peak memory 247780 kb
Host smart-8ac5234e-a69c-4da2-8f8d-a676e0f37587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16951
02146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1695102146
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.726302657
Short name T315
Test name
Test status
Simulation time 96941544011 ps
CPU time 1418.12 seconds
Started Aug 08 04:30:22 PM PDT 24
Finished Aug 08 04:54:01 PM PDT 24
Peak memory 271956 kb
Host smart-2e1a16ed-c4e9-458d-b1f4-b942f1e0efc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726302657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.726302657
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2242109394
Short name T697
Test name
Test status
Simulation time 95511002227 ps
CPU time 1661.46 seconds
Started Aug 08 04:30:19 PM PDT 24
Finished Aug 08 04:58:00 PM PDT 24
Peak memory 272808 kb
Host smart-d8ccd71b-01ca-4fd1-a279-72e0212b59d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242109394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2242109394
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.346779406
Short name T305
Test name
Test status
Simulation time 43685630994 ps
CPU time 429.98 seconds
Started Aug 08 04:30:10 PM PDT 24
Finished Aug 08 04:37:20 PM PDT 24
Peak memory 247956 kb
Host smart-06b6b5ee-25e5-4cbc-b5b6-2eb719870280
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346779406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.346779406
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.397933981
Short name T367
Test name
Test status
Simulation time 66707261 ps
CPU time 5.13 seconds
Started Aug 08 04:30:14 PM PDT 24
Finished Aug 08 04:30:19 PM PDT 24
Peak memory 248104 kb
Host smart-0b27d494-8866-4eb3-9d71-8b8e9527ba99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39793
3981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.397933981
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2338786295
Short name T496
Test name
Test status
Simulation time 659329761 ps
CPU time 38.36 seconds
Started Aug 08 04:30:08 PM PDT 24
Finished Aug 08 04:30:46 PM PDT 24
Peak memory 254920 kb
Host smart-f576a32f-79de-427d-900d-b5e4e9eb5fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23387
86295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2338786295
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.621925281
Short name T584
Test name
Test status
Simulation time 1342733088 ps
CPU time 35.99 seconds
Started Aug 08 04:30:10 PM PDT 24
Finished Aug 08 04:30:47 PM PDT 24
Peak memory 255836 kb
Host smart-90a83b3c-78bd-44d4-9219-118a2d81a870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62192
5281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.621925281
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3731202912
Short name T575
Test name
Test status
Simulation time 12379733914 ps
CPU time 1364.95 seconds
Started Aug 08 04:30:27 PM PDT 24
Finished Aug 08 04:53:12 PM PDT 24
Peak memory 288992 kb
Host smart-2c55aae8-d2da-4a63-a816-bf1620378dbb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731202912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3731202912
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3980869582
Short name T407
Test name
Test status
Simulation time 366652120730 ps
CPU time 2222.44 seconds
Started Aug 08 04:30:26 PM PDT 24
Finished Aug 08 05:07:28 PM PDT 24
Peak memory 289352 kb
Host smart-4831af59-c47e-4bb9-b86e-93e4ce55c9c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980869582 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3980869582
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3983522085
Short name T195
Test name
Test status
Simulation time 43762265 ps
CPU time 2.8 seconds
Started Aug 08 04:30:12 PM PDT 24
Finished Aug 08 04:30:15 PM PDT 24
Peak memory 248420 kb
Host smart-901d61e6-1343-41bd-8335-ac1022d9714f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3983522085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3983522085
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1337391780
Short name T563
Test name
Test status
Simulation time 40294879510 ps
CPU time 1164.46 seconds
Started Aug 08 04:30:17 PM PDT 24
Finished Aug 08 04:49:41 PM PDT 24
Peak memory 272296 kb
Host smart-e4a60e13-2b53-44dd-9c51-b8e141fa400f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337391780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1337391780
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3763799147
Short name T431
Test name
Test status
Simulation time 1465453513 ps
CPU time 31.4 seconds
Started Aug 08 04:30:23 PM PDT 24
Finished Aug 08 04:30:55 PM PDT 24
Peak memory 248208 kb
Host smart-88302366-76eb-421f-97c7-8609498aac40
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3763799147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3763799147
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.998992773
Short name T429
Test name
Test status
Simulation time 1406503910 ps
CPU time 15.53 seconds
Started Aug 08 04:30:11 PM PDT 24
Finished Aug 08 04:30:27 PM PDT 24
Peak memory 256264 kb
Host smart-b0b92ca1-6388-4fbb-be1a-448de66efd38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99899
2773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.998992773
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.713743275
Short name T689
Test name
Test status
Simulation time 363731231 ps
CPU time 26.12 seconds
Started Aug 08 04:30:20 PM PDT 24
Finished Aug 08 04:30:47 PM PDT 24
Peak memory 255688 kb
Host smart-8daa9088-d5ce-4b28-a0a9-69b928678d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71374
3275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.713743275
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.133760120
Short name T319
Test name
Test status
Simulation time 28289268053 ps
CPU time 1587.3 seconds
Started Aug 08 04:30:10 PM PDT 24
Finished Aug 08 04:56:38 PM PDT 24
Peak memory 272116 kb
Host smart-316d1c8b-3aa2-430b-a921-e28a1f7932c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133760120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.133760120
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2647445742
Short name T573
Test name
Test status
Simulation time 31455161723 ps
CPU time 818.32 seconds
Started Aug 08 04:30:07 PM PDT 24
Finished Aug 08 04:43:46 PM PDT 24
Peak memory 272360 kb
Host smart-04e4d696-a929-48ba-a50d-dfa01afa62dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647445742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2647445742
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1301459005
Short name T656
Test name
Test status
Simulation time 997024995 ps
CPU time 64.01 seconds
Started Aug 08 04:30:16 PM PDT 24
Finished Aug 08 04:31:20 PM PDT 24
Peak memory 255488 kb
Host smart-830db1be-1383-45a3-9036-c63f166faebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13014
59005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1301459005
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.302468024
Short name T486
Test name
Test status
Simulation time 100705387 ps
CPU time 4.51 seconds
Started Aug 08 04:30:12 PM PDT 24
Finished Aug 08 04:30:16 PM PDT 24
Peak memory 239480 kb
Host smart-315431b0-b366-4043-9de4-1b40876d136f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30246
8024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.302468024
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2217009449
Short name T626
Test name
Test status
Simulation time 493951323 ps
CPU time 17.87 seconds
Started Aug 08 04:30:16 PM PDT 24
Finished Aug 08 04:30:34 PM PDT 24
Peak memory 252868 kb
Host smart-8a0a5d5b-78cb-420e-bcc9-09caacc43629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22170
09449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2217009449
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.996585073
Short name T640
Test name
Test status
Simulation time 688467511 ps
CPU time 30.76 seconds
Started Aug 08 04:30:22 PM PDT 24
Finished Aug 08 04:30:53 PM PDT 24
Peak memory 256320 kb
Host smart-75c1575c-e8ac-4b55-86e9-d9bb1c5efb38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99658
5073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.996585073
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1057112264
Short name T507
Test name
Test status
Simulation time 46523889472 ps
CPU time 727.17 seconds
Started Aug 08 04:30:10 PM PDT 24
Finished Aug 08 04:42:17 PM PDT 24
Peak memory 272284 kb
Host smart-3f0a8f1a-9011-43e0-a606-c829b444c47d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057112264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1057112264
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.465417592
Short name T529
Test name
Test status
Simulation time 29907797036 ps
CPU time 3326.59 seconds
Started Aug 08 04:30:12 PM PDT 24
Finished Aug 08 05:25:39 PM PDT 24
Peak memory 322100 kb
Host smart-4fce8381-ca1e-4b53-a238-144cb8187b3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465417592 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.465417592
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2851674568
Short name T194
Test name
Test status
Simulation time 54304763 ps
CPU time 3.25 seconds
Started Aug 08 04:30:10 PM PDT 24
Finished Aug 08 04:30:14 PM PDT 24
Peak memory 248328 kb
Host smart-d9f7c073-2124-418c-80b3-9e7240f161c2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2851674568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2851674568
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3937233767
Short name T631
Test name
Test status
Simulation time 66209366490 ps
CPU time 1100.29 seconds
Started Aug 08 04:30:14 PM PDT 24
Finished Aug 08 04:48:35 PM PDT 24
Peak memory 272716 kb
Host smart-7fb3e403-3180-4e6b-8ac6-03b9a213d1ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937233767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3937233767
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3033073535
Short name T36
Test name
Test status
Simulation time 152241180 ps
CPU time 9.65 seconds
Started Aug 08 04:30:10 PM PDT 24
Finished Aug 08 04:30:19 PM PDT 24
Peak memory 248196 kb
Host smart-fa32afa0-3138-4339-9524-46f0d05787da
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3033073535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3033073535
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1741882217
Short name T22
Test name
Test status
Simulation time 2361550205 ps
CPU time 138.89 seconds
Started Aug 08 04:30:11 PM PDT 24
Finished Aug 08 04:32:30 PM PDT 24
Peak memory 256320 kb
Host smart-769d99df-c1a6-4d11-833e-41bb3ce8b9d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17418
82217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1741882217
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1659011834
Short name T380
Test name
Test status
Simulation time 7154297688 ps
CPU time 51.9 seconds
Started Aug 08 04:30:10 PM PDT 24
Finished Aug 08 04:31:02 PM PDT 24
Peak memory 248280 kb
Host smart-dd8b3eca-f1ac-448f-a261-deb5900e8dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16590
11834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1659011834
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1503331638
Short name T636
Test name
Test status
Simulation time 67049152960 ps
CPU time 1263.91 seconds
Started Aug 08 04:30:10 PM PDT 24
Finished Aug 08 04:51:14 PM PDT 24
Peak memory 288268 kb
Host smart-309f800c-273f-44bc-a040-57ef9896e249
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503331638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1503331638
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3563002270
Short name T497
Test name
Test status
Simulation time 49362471098 ps
CPU time 1455.23 seconds
Started Aug 08 04:30:09 PM PDT 24
Finished Aug 08 04:54:25 PM PDT 24
Peak memory 264660 kb
Host smart-d3f6cd4f-fb01-48b9-ba71-9a69c7d9e21d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563002270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3563002270
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.658297719
Short name T604
Test name
Test status
Simulation time 16136336469 ps
CPU time 323.34 seconds
Started Aug 08 04:30:16 PM PDT 24
Finished Aug 08 04:35:40 PM PDT 24
Peak memory 248192 kb
Host smart-77673f0e-33fd-4728-af34-9cf3524570a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658297719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.658297719
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.4226600324
Short name T29
Test name
Test status
Simulation time 1041933698 ps
CPU time 25.19 seconds
Started Aug 08 04:30:15 PM PDT 24
Finished Aug 08 04:30:40 PM PDT 24
Peak memory 255648 kb
Host smart-fb012889-a873-474d-8a98-5bd3d228f7b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42266
00324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.4226600324
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.4254143571
Short name T266
Test name
Test status
Simulation time 5352719751 ps
CPU time 41.52 seconds
Started Aug 08 04:30:13 PM PDT 24
Finished Aug 08 04:30:54 PM PDT 24
Peak memory 255696 kb
Host smart-eabaa219-94cf-4bf0-a5df-64b355a06bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42541
43571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.4254143571
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2737835192
Short name T676
Test name
Test status
Simulation time 538697615 ps
CPU time 29.84 seconds
Started Aug 08 04:30:09 PM PDT 24
Finished Aug 08 04:30:39 PM PDT 24
Peak memory 256412 kb
Host smart-ff88ceac-b884-4add-885b-dcfcdff78137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27378
35192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2737835192
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1920200463
Short name T410
Test name
Test status
Simulation time 1265481739 ps
CPU time 23.56 seconds
Started Aug 08 04:30:23 PM PDT 24
Finished Aug 08 04:30:47 PM PDT 24
Peak memory 255400 kb
Host smart-07c3dd1d-c7ce-4358-a121-04f3a5c1488f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19202
00463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1920200463
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2988103617
Short name T252
Test name
Test status
Simulation time 231305029826 ps
CPU time 2961.35 seconds
Started Aug 08 04:30:26 PM PDT 24
Finished Aug 08 05:19:47 PM PDT 24
Peak memory 297200 kb
Host smart-21ce6e17-296a-4a48-bac1-3263b34352ac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988103617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2988103617
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2632101914
Short name T203
Test name
Test status
Simulation time 165475337 ps
CPU time 4.18 seconds
Started Aug 08 04:30:34 PM PDT 24
Finished Aug 08 04:30:39 PM PDT 24
Peak memory 248468 kb
Host smart-d48e8c50-5948-40f0-9282-1eb021f9563c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2632101914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2632101914
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.4246716658
Short name T61
Test name
Test status
Simulation time 57766679415 ps
CPU time 2010.03 seconds
Started Aug 08 04:30:19 PM PDT 24
Finished Aug 08 05:03:49 PM PDT 24
Peak memory 284308 kb
Host smart-99032fbd-a6ff-4527-b21a-d4fc31f30494
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246716658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.4246716658
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3585311348
Short name T504
Test name
Test status
Simulation time 328268917 ps
CPU time 10.63 seconds
Started Aug 08 04:30:22 PM PDT 24
Finished Aug 08 04:30:33 PM PDT 24
Peak memory 248080 kb
Host smart-3b1b3424-11a5-4826-8b2b-d4918cadb873
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3585311348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3585311348
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3230592589
Short name T510
Test name
Test status
Simulation time 612649224 ps
CPU time 61.68 seconds
Started Aug 08 04:30:23 PM PDT 24
Finished Aug 08 04:31:24 PM PDT 24
Peak memory 255204 kb
Host smart-3bb979c5-11cc-421d-9a8f-b57ffc9f5f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32305
92589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3230592589
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3845448819
Short name T611
Test name
Test status
Simulation time 258030512 ps
CPU time 17.03 seconds
Started Aug 08 04:30:30 PM PDT 24
Finished Aug 08 04:30:47 PM PDT 24
Peak memory 247860 kb
Host smart-317914a9-f6b5-4c57-86c2-b50a63fbfe1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38454
48819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3845448819
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.623512263
Short name T638
Test name
Test status
Simulation time 33763955056 ps
CPU time 704.18 seconds
Started Aug 08 04:30:24 PM PDT 24
Finished Aug 08 04:42:08 PM PDT 24
Peak memory 272752 kb
Host smart-2b3ca332-20cd-4ced-94e7-28af39beaf30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623512263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.623512263
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.836788935
Short name T311
Test name
Test status
Simulation time 17508035188 ps
CPU time 162.3 seconds
Started Aug 08 04:30:26 PM PDT 24
Finished Aug 08 04:33:08 PM PDT 24
Peak memory 248008 kb
Host smart-378e110d-cdca-45f3-a6d3-8ca6e2167f6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836788935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.836788935
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2711604487
Short name T114
Test name
Test status
Simulation time 195611790 ps
CPU time 15.76 seconds
Started Aug 08 04:30:14 PM PDT 24
Finished Aug 08 04:30:30 PM PDT 24
Peak memory 255456 kb
Host smart-7558c362-a2a1-4d58-b843-0e5224112dc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27116
04487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2711604487
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1798841784
Short name T373
Test name
Test status
Simulation time 1719832413 ps
CPU time 27.36 seconds
Started Aug 08 04:30:19 PM PDT 24
Finished Aug 08 04:30:46 PM PDT 24
Peak memory 254584 kb
Host smart-e1e052eb-f7c3-448d-bb58-e1ce48765c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17988
41784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1798841784
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.3989857877
Short name T393
Test name
Test status
Simulation time 1608515049 ps
CPU time 43.11 seconds
Started Aug 08 04:30:16 PM PDT 24
Finished Aug 08 04:30:59 PM PDT 24
Peak memory 255928 kb
Host smart-7a782cd7-061c-46d8-b2b5-5903e3e4042d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39898
57877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3989857877
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3986387817
Short name T524
Test name
Test status
Simulation time 693414024 ps
CPU time 14 seconds
Started Aug 08 04:30:14 PM PDT 24
Finished Aug 08 04:30:28 PM PDT 24
Peak memory 254292 kb
Host smart-19665a49-29fc-40f8-a39b-0040ab88db47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39863
87817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3986387817
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2958649279
Short name T92
Test name
Test status
Simulation time 350096687065 ps
CPU time 8059.4 seconds
Started Aug 08 04:30:30 PM PDT 24
Finished Aug 08 06:44:50 PM PDT 24
Peak memory 354576 kb
Host smart-f19536a7-1fc9-4a62-8f87-2f3447b2ae87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958649279 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2958649279
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.896219524
Short name T192
Test name
Test status
Simulation time 100867593 ps
CPU time 4.25 seconds
Started Aug 08 04:30:18 PM PDT 24
Finished Aug 08 04:30:22 PM PDT 24
Peak memory 248380 kb
Host smart-629f4854-8eca-45ed-bc87-e43c0b848914
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=896219524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.896219524
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3991333987
Short name T75
Test name
Test status
Simulation time 205256042470 ps
CPU time 2977.04 seconds
Started Aug 08 04:30:27 PM PDT 24
Finished Aug 08 05:20:04 PM PDT 24
Peak memory 286720 kb
Host smart-55ee0c20-0460-45b8-96bd-bda09564ec2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991333987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3991333987
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1370938134
Short name T619
Test name
Test status
Simulation time 420924246 ps
CPU time 7.6 seconds
Started Aug 08 04:30:33 PM PDT 24
Finished Aug 08 04:30:41 PM PDT 24
Peak memory 248100 kb
Host smart-d3729b76-b4a3-4ef0-9b8b-9c2c5f6aa9b3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1370938134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1370938134
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1315687582
Short name T515
Test name
Test status
Simulation time 43687171430 ps
CPU time 173.76 seconds
Started Aug 08 04:30:34 PM PDT 24
Finished Aug 08 04:33:28 PM PDT 24
Peak memory 255788 kb
Host smart-39550d66-bee2-49d2-84e9-cfb4766f7257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13156
87582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1315687582
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2215304734
Short name T490
Test name
Test status
Simulation time 2428840565 ps
CPU time 40.64 seconds
Started Aug 08 04:30:32 PM PDT 24
Finished Aug 08 04:31:12 PM PDT 24
Peak memory 256144 kb
Host smart-0f7e6238-e166-4f94-bcdd-fcfb961f5555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22153
04734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2215304734
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2735944387
Short name T324
Test name
Test status
Simulation time 212984589965 ps
CPU time 917.22 seconds
Started Aug 08 04:30:24 PM PDT 24
Finished Aug 08 04:45:42 PM PDT 24
Peak memory 272532 kb
Host smart-6a27224f-b816-45b5-aeb2-add8a872eca7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735944387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2735944387
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1117995705
Short name T89
Test name
Test status
Simulation time 9403470171 ps
CPU time 852.67 seconds
Started Aug 08 04:30:14 PM PDT 24
Finished Aug 08 04:44:27 PM PDT 24
Peak memory 282436 kb
Host smart-00c2c0b7-61c0-42cb-ac1f-f71baa83027d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117995705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1117995705
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2403834734
Short name T627
Test name
Test status
Simulation time 36072207345 ps
CPU time 311.97 seconds
Started Aug 08 04:30:12 PM PDT 24
Finished Aug 08 04:35:24 PM PDT 24
Peak memory 248216 kb
Host smart-bf98f477-c3fa-4060-8dc4-3dadd1cbd41e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403834734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2403834734
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1532544911
Short name T603
Test name
Test status
Simulation time 4148101621 ps
CPU time 63.51 seconds
Started Aug 08 04:30:35 PM PDT 24
Finished Aug 08 04:31:39 PM PDT 24
Peak memory 256384 kb
Host smart-045d0218-1169-46b8-bf32-b6363fe8eebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15325
44911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1532544911
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.4279757381
Short name T282
Test name
Test status
Simulation time 875686957 ps
CPU time 60.35 seconds
Started Aug 08 04:30:09 PM PDT 24
Finished Aug 08 04:31:09 PM PDT 24
Peak memory 249244 kb
Host smart-22647895-44a3-42ad-b6f0-9ceda90a55ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42797
57381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.4279757381
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2224966587
Short name T612
Test name
Test status
Simulation time 170961124 ps
CPU time 7.13 seconds
Started Aug 08 04:30:32 PM PDT 24
Finished Aug 08 04:30:40 PM PDT 24
Peak memory 248224 kb
Host smart-3a2b897d-88d2-4b66-ae73-b4869ce15510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22249
66587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2224966587
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3253785481
Short name T269
Test name
Test status
Simulation time 588180299 ps
CPU time 43.95 seconds
Started Aug 08 04:30:30 PM PDT 24
Finished Aug 08 04:31:14 PM PDT 24
Peak memory 256000 kb
Host smart-dc873ff4-202f-412a-bd40-de469e5ca4e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32537
85481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3253785481
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.2245114083
Short name T233
Test name
Test status
Simulation time 129287678068 ps
CPU time 1513.42 seconds
Started Aug 08 04:30:28 PM PDT 24
Finished Aug 08 04:55:42 PM PDT 24
Peak memory 286584 kb
Host smart-07ae9086-2fbd-45ef-998f-803db9b50170
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245114083 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.2245114083
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1527876040
Short name T197
Test name
Test status
Simulation time 163808713 ps
CPU time 4 seconds
Started Aug 08 04:29:39 PM PDT 24
Finished Aug 08 04:29:43 PM PDT 24
Peak memory 248300 kb
Host smart-6c3650e9-91fe-4b4e-a37a-66a15b7cfd87
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1527876040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1527876040
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3229420438
Short name T473
Test name
Test status
Simulation time 72403559182 ps
CPU time 508.49 seconds
Started Aug 08 04:29:39 PM PDT 24
Finished Aug 08 04:38:08 PM PDT 24
Peak memory 272252 kb
Host smart-4916cb9e-0fc3-4989-8f01-83848587d149
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229420438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3229420438
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1846523399
Short name T567
Test name
Test status
Simulation time 1041910110 ps
CPU time 11.95 seconds
Started Aug 08 04:29:38 PM PDT 24
Finished Aug 08 04:29:50 PM PDT 24
Peak memory 248148 kb
Host smart-a256e65e-7409-4533-8ebc-d28236a01bdc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1846523399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1846523399
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1343096841
Short name T663
Test name
Test status
Simulation time 14696473702 ps
CPU time 261.66 seconds
Started Aug 08 04:29:33 PM PDT 24
Finished Aug 08 04:33:55 PM PDT 24
Peak memory 251296 kb
Host smart-c3b32373-f61b-4633-a3ca-5bf7e416db47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13430
96841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1343096841
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.328324286
Short name T447
Test name
Test status
Simulation time 122402087 ps
CPU time 11.21 seconds
Started Aug 08 04:29:29 PM PDT 24
Finished Aug 08 04:29:40 PM PDT 24
Peak memory 248024 kb
Host smart-284776b2-0f33-4508-9aac-560f8a431e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32832
4286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.328324286
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2818976068
Short name T211
Test name
Test status
Simulation time 332622849698 ps
CPU time 1579.6 seconds
Started Aug 08 04:29:37 PM PDT 24
Finished Aug 08 04:55:57 PM PDT 24
Peak memory 269720 kb
Host smart-7c66806a-ff73-47c9-ba92-179b047a8fbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818976068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2818976068
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3359120826
Short name T13
Test name
Test status
Simulation time 1077610780 ps
CPU time 48.71 seconds
Started Aug 08 04:29:41 PM PDT 24
Finished Aug 08 04:30:30 PM PDT 24
Peak memory 248156 kb
Host smart-0f5f31f8-8259-4cab-90bc-f3823b7217c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359120826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3359120826
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2724521168
Short name T359
Test name
Test status
Simulation time 319953214 ps
CPU time 30.65 seconds
Started Aug 08 04:29:27 PM PDT 24
Finished Aug 08 04:29:57 PM PDT 24
Peak memory 248176 kb
Host smart-09f8ad02-52c2-4df5-a85f-0503d21dc3c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27245
21168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2724521168
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.583808087
Short name T617
Test name
Test status
Simulation time 282051120 ps
CPU time 5.86 seconds
Started Aug 08 04:29:30 PM PDT 24
Finished Aug 08 04:29:36 PM PDT 24
Peak memory 239916 kb
Host smart-6df41500-3c1b-42d4-a51d-169ba72686e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58380
8087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.583808087
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2573057084
Short name T34
Test name
Test status
Simulation time 649249626 ps
CPU time 11.25 seconds
Started Aug 08 04:29:41 PM PDT 24
Finished Aug 08 04:29:52 PM PDT 24
Peak memory 266388 kb
Host smart-048186e6-38a8-4263-8efe-11c5eb930c49
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2573057084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2573057084
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3837399427
Short name T213
Test name
Test status
Simulation time 1950696406 ps
CPU time 49.09 seconds
Started Aug 08 04:29:36 PM PDT 24
Finished Aug 08 04:30:25 PM PDT 24
Peak memory 255540 kb
Host smart-a02b2b4c-8f40-466f-ae2f-b4dffa4990a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38373
99427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3837399427
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.677211443
Short name T52
Test name
Test status
Simulation time 7947473076 ps
CPU time 258.09 seconds
Started Aug 08 04:29:33 PM PDT 24
Finished Aug 08 04:33:52 PM PDT 24
Peak memory 256456 kb
Host smart-92b413c6-b880-4a58-9d53-689a14026b28
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677211443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.677211443
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.4063424681
Short name T629
Test name
Test status
Simulation time 26572823134 ps
CPU time 1476.05 seconds
Started Aug 08 04:30:36 PM PDT 24
Finished Aug 08 04:55:12 PM PDT 24
Peak memory 272444 kb
Host smart-9ee4e2c9-28bd-474e-b3ec-bfa197d819a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063424681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.4063424681
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2588948330
Short name T634
Test name
Test status
Simulation time 1706694331 ps
CPU time 127.3 seconds
Started Aug 08 04:30:37 PM PDT 24
Finished Aug 08 04:32:44 PM PDT 24
Peak memory 255888 kb
Host smart-edd2fe0b-075d-4885-9a56-ba927a73466a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25889
48330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2588948330
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3108807689
Short name T385
Test name
Test status
Simulation time 505321426 ps
CPU time 10.25 seconds
Started Aug 08 04:30:43 PM PDT 24
Finished Aug 08 04:30:53 PM PDT 24
Peak memory 251708 kb
Host smart-fb8775e8-4fce-4f16-b100-3cb6f6b76464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31088
07689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3108807689
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2545793186
Short name T334
Test name
Test status
Simulation time 84539501352 ps
CPU time 1382.03 seconds
Started Aug 08 04:30:28 PM PDT 24
Finished Aug 08 04:53:30 PM PDT 24
Peak memory 288536 kb
Host smart-913fe4d2-4dfb-4624-8a3a-6bcafb5a00fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545793186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2545793186
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2349207566
Short name T438
Test name
Test status
Simulation time 153168510835 ps
CPU time 2140.82 seconds
Started Aug 08 04:30:31 PM PDT 24
Finished Aug 08 05:06:12 PM PDT 24
Peak memory 272780 kb
Host smart-77b09213-3517-4713-8ff4-53ff3cc58ce3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349207566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2349207566
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.560998279
Short name T513
Test name
Test status
Simulation time 10871045140 ps
CPU time 225.25 seconds
Started Aug 08 04:30:36 PM PDT 24
Finished Aug 08 04:34:21 PM PDT 24
Peak memory 248028 kb
Host smart-ec40f596-fca6-4afe-8436-fd594a36373f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560998279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.560998279
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2669737059
Short name T79
Test name
Test status
Simulation time 1716571396 ps
CPU time 31.44 seconds
Started Aug 08 04:30:26 PM PDT 24
Finished Aug 08 04:30:58 PM PDT 24
Peak memory 248168 kb
Host smart-c47bd4bf-a1c1-4535-ad3e-0301d01a7f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26697
37059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2669737059
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1897453029
Short name T263
Test name
Test status
Simulation time 352197245 ps
CPU time 23.89 seconds
Started Aug 08 04:30:22 PM PDT 24
Finished Aug 08 04:30:46 PM PDT 24
Peak memory 255892 kb
Host smart-21c98958-24c4-48d5-adce-701e5b1becdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18974
53029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1897453029
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3064868317
Short name T487
Test name
Test status
Simulation time 692785095 ps
CPU time 44.44 seconds
Started Aug 08 04:30:41 PM PDT 24
Finished Aug 08 04:31:25 PM PDT 24
Peak memory 248500 kb
Host smart-4d1f2024-75d6-4352-b9df-bc79760098fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30648
68317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3064868317
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.4232665334
Short name T532
Test name
Test status
Simulation time 1482956566 ps
CPU time 55.68 seconds
Started Aug 08 04:30:17 PM PDT 24
Finished Aug 08 04:31:13 PM PDT 24
Peak memory 255328 kb
Host smart-31146f28-2158-4bf0-8487-272f074bfb1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42326
65334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.4232665334
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3120979156
Short name T485
Test name
Test status
Simulation time 83694650026 ps
CPU time 1780.13 seconds
Started Aug 08 04:30:32 PM PDT 24
Finished Aug 08 05:00:13 PM PDT 24
Peak memory 297388 kb
Host smart-97fc31d7-0772-4f08-8a28-e37aa74b98a9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120979156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3120979156
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2222263095
Short name T658
Test name
Test status
Simulation time 32957418643 ps
CPU time 950.14 seconds
Started Aug 08 04:30:40 PM PDT 24
Finished Aug 08 04:46:31 PM PDT 24
Peak memory 281052 kb
Host smart-c6e0b273-be2f-4514-9a48-98564694240c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222263095 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2222263095
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1836206499
Short name T622
Test name
Test status
Simulation time 19485787513 ps
CPU time 769.47 seconds
Started Aug 08 04:30:24 PM PDT 24
Finished Aug 08 04:43:13 PM PDT 24
Peak memory 272440 kb
Host smart-ce438dac-a65e-4caf-a681-1066fbc02139
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836206499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1836206499
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.848398510
Short name T457
Test name
Test status
Simulation time 20694896564 ps
CPU time 148.51 seconds
Started Aug 08 04:30:21 PM PDT 24
Finished Aug 08 04:32:50 PM PDT 24
Peak memory 255716 kb
Host smart-a12a83d0-4a76-42c9-b1a0-46e6ed4b8cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84839
8510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.848398510
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.392942267
Short name T653
Test name
Test status
Simulation time 50145950 ps
CPU time 6.33 seconds
Started Aug 08 04:30:26 PM PDT 24
Finished Aug 08 04:30:32 PM PDT 24
Peak memory 247628 kb
Host smart-68fd34ce-1f6c-4166-91f1-35b5b9d813f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39294
2267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.392942267
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1892834421
Short name T299
Test name
Test status
Simulation time 101300719176 ps
CPU time 1683.45 seconds
Started Aug 08 04:30:17 PM PDT 24
Finished Aug 08 04:58:21 PM PDT 24
Peak memory 272792 kb
Host smart-07642ddb-e85b-4ae3-94a5-17dbe6cf60ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892834421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1892834421
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3470874369
Short name T365
Test name
Test status
Simulation time 43373917494 ps
CPU time 1063.4 seconds
Started Aug 08 04:30:15 PM PDT 24
Finished Aug 08 04:47:59 PM PDT 24
Peak memory 282860 kb
Host smart-ea5917e1-0cfb-4306-94fa-c0d67a8dd393
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470874369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3470874369
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2288581214
Short name T597
Test name
Test status
Simulation time 9760707442 ps
CPU time 209.98 seconds
Started Aug 08 04:30:13 PM PDT 24
Finished Aug 08 04:33:43 PM PDT 24
Peak memory 248588 kb
Host smart-c037a66d-8f3f-44d7-9c14-9670ad635e65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288581214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2288581214
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1073060945
Short name T600
Test name
Test status
Simulation time 71631810 ps
CPU time 4.1 seconds
Started Aug 08 04:30:26 PM PDT 24
Finished Aug 08 04:30:30 PM PDT 24
Peak memory 248108 kb
Host smart-5be1045f-d3a0-4c43-b0ed-06eb8dd0db7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10730
60945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1073060945
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3061121818
Short name T678
Test name
Test status
Simulation time 595385845 ps
CPU time 21.08 seconds
Started Aug 08 04:30:32 PM PDT 24
Finished Aug 08 04:30:54 PM PDT 24
Peak memory 247716 kb
Host smart-7afc47b8-cbb5-46ae-a99e-910fbd8a83cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30611
21818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3061121818
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3632013659
Short name T401
Test name
Test status
Simulation time 1680625224 ps
CPU time 51.35 seconds
Started Aug 08 04:30:18 PM PDT 24
Finished Aug 08 04:31:09 PM PDT 24
Peak memory 256176 kb
Host smart-5d33ed4c-8c99-4abd-9eaf-ba8bb8e8ee07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36320
13659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3632013659
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.66966087
Short name T557
Test name
Test status
Simulation time 75535670652 ps
CPU time 1209.81 seconds
Started Aug 08 04:30:29 PM PDT 24
Finished Aug 08 04:50:39 PM PDT 24
Peak memory 264540 kb
Host smart-774fd9bb-963d-4eae-a179-22d46b459226
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66966087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_hand
ler_stress_all.66966087
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2412049736
Short name T534
Test name
Test status
Simulation time 83744458099 ps
CPU time 2834.72 seconds
Started Aug 08 04:30:34 PM PDT 24
Finished Aug 08 05:17:49 PM PDT 24
Peak memory 289136 kb
Host smart-68b1d4e9-1517-4e61-91f3-93c8a6ea9ba2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412049736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2412049736
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.469257920
Short name T644
Test name
Test status
Simulation time 339142075 ps
CPU time 13.6 seconds
Started Aug 08 04:30:17 PM PDT 24
Finished Aug 08 04:30:31 PM PDT 24
Peak memory 256176 kb
Host smart-684df113-913f-4761-b268-ae901d85f646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46925
7920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.469257920
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2151370298
Short name T585
Test name
Test status
Simulation time 1071914391 ps
CPU time 16.7 seconds
Started Aug 08 04:30:29 PM PDT 24
Finished Aug 08 04:30:46 PM PDT 24
Peak memory 247480 kb
Host smart-5458bb5d-f2e6-416e-8aae-7082d1f29445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21513
70298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2151370298
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.301598743
Short name T558
Test name
Test status
Simulation time 26960713504 ps
CPU time 1527.56 seconds
Started Aug 08 04:30:16 PM PDT 24
Finished Aug 08 04:55:44 PM PDT 24
Peak memory 272064 kb
Host smart-0e5ac5cd-ebc6-41a5-884a-5fee58844555
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301598743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.301598743
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2297268882
Short name T399
Test name
Test status
Simulation time 21080023892 ps
CPU time 1083.86 seconds
Started Aug 08 04:30:17 PM PDT 24
Finished Aug 08 04:48:21 PM PDT 24
Peak memory 272828 kb
Host smart-baf6e452-e780-4583-9b1f-8578555574b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297268882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2297268882
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2338042943
Short name T307
Test name
Test status
Simulation time 4144449463 ps
CPU time 91.88 seconds
Started Aug 08 04:30:32 PM PDT 24
Finished Aug 08 04:32:04 PM PDT 24
Peak memory 247180 kb
Host smart-00ab9bed-caa4-4393-ad37-9b221dd820d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338042943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2338042943
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1903484654
Short name T398
Test name
Test status
Simulation time 27501121 ps
CPU time 3.48 seconds
Started Aug 08 04:30:16 PM PDT 24
Finished Aug 08 04:30:20 PM PDT 24
Peak memory 248116 kb
Host smart-fb8cde09-4811-4998-ba2a-7417c3596650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19034
84654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1903484654
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3071214185
Short name T71
Test name
Test status
Simulation time 1182106878 ps
CPU time 34.49 seconds
Started Aug 08 04:30:23 PM PDT 24
Finished Aug 08 04:30:57 PM PDT 24
Peak memory 248132 kb
Host smart-8786d48c-882f-4c3f-b37e-81cf0bf84129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30712
14185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3071214185
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1346822233
Short name T688
Test name
Test status
Simulation time 1007097231 ps
CPU time 38.1 seconds
Started Aug 08 04:30:23 PM PDT 24
Finished Aug 08 04:31:01 PM PDT 24
Peak memory 248092 kb
Host smart-1f487c99-d3cd-4528-afdd-0e4d39887677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13468
22233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1346822233
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3335653488
Short name T224
Test name
Test status
Simulation time 2698763158 ps
CPU time 33.16 seconds
Started Aug 08 04:30:22 PM PDT 24
Finished Aug 08 04:30:55 PM PDT 24
Peak memory 256388 kb
Host smart-0a284c7d-1f5f-42ea-ab05-26a5b98834b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33356
53488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3335653488
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3706787589
Short name T484
Test name
Test status
Simulation time 859775348 ps
CPU time 30.57 seconds
Started Aug 08 04:30:23 PM PDT 24
Finished Aug 08 04:30:54 PM PDT 24
Peak memory 255992 kb
Host smart-2f492048-f88a-4495-938f-701f0ea4716a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706787589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3706787589
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2534345335
Short name T539
Test name
Test status
Simulation time 25623494776 ps
CPU time 1744.45 seconds
Started Aug 08 04:30:33 PM PDT 24
Finished Aug 08 04:59:38 PM PDT 24
Peak memory 288944 kb
Host smart-48974a44-9e48-405b-8e62-bdea4870fa3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534345335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2534345335
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2362569057
Short name T615
Test name
Test status
Simulation time 5378206716 ps
CPU time 141.06 seconds
Started Aug 08 04:30:32 PM PDT 24
Finished Aug 08 04:32:53 PM PDT 24
Peak memory 255904 kb
Host smart-194918f2-f97d-4b69-b94e-2a99d0702ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23625
69057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2362569057
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.182040712
Short name T83
Test name
Test status
Simulation time 1219594013 ps
CPU time 62.16 seconds
Started Aug 08 04:30:30 PM PDT 24
Finished Aug 08 04:31:32 PM PDT 24
Peak memory 247864 kb
Host smart-7a1faa2c-e713-47a4-83e6-c4fe74d687d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18204
0712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.182040712
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3570307929
Short name T316
Test name
Test status
Simulation time 13353448914 ps
CPU time 1234.21 seconds
Started Aug 08 04:30:35 PM PDT 24
Finished Aug 08 04:51:10 PM PDT 24
Peak memory 284904 kb
Host smart-1090f06d-4b10-459f-960b-a49e54b72249
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570307929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3570307929
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2726649840
Short name T387
Test name
Test status
Simulation time 25569725734 ps
CPU time 1607.38 seconds
Started Aug 08 04:30:35 PM PDT 24
Finished Aug 08 04:57:23 PM PDT 24
Peak memory 272844 kb
Host smart-bfcecec5-b9c8-49e1-9eab-417f0cfd061a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726649840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2726649840
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3625761290
Short name T664
Test name
Test status
Simulation time 111662816324 ps
CPU time 225.34 seconds
Started Aug 08 04:30:29 PM PDT 24
Finished Aug 08 04:34:15 PM PDT 24
Peak memory 248240 kb
Host smart-45e713b1-9d46-4d55-bc37-466ca1a7f4dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625761290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3625761290
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.4117437736
Short name T222
Test name
Test status
Simulation time 196649612 ps
CPU time 7.51 seconds
Started Aug 08 04:30:39 PM PDT 24
Finished Aug 08 04:30:47 PM PDT 24
Peak memory 248144 kb
Host smart-fe959805-e364-4438-89b5-a38557bfbc16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41174
37736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.4117437736
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2731948505
Short name T476
Test name
Test status
Simulation time 278165988 ps
CPU time 16.05 seconds
Started Aug 08 04:30:40 PM PDT 24
Finished Aug 08 04:30:56 PM PDT 24
Peak memory 248016 kb
Host smart-de6faa45-30a8-403a-a0c4-3dc78487a4b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27319
48505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2731948505
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1401588356
Short name T37
Test name
Test status
Simulation time 317531039 ps
CPU time 28.85 seconds
Started Aug 08 04:30:36 PM PDT 24
Finished Aug 08 04:31:05 PM PDT 24
Peak memory 256256 kb
Host smart-e93a2103-0e03-4e63-8ec4-bdbd09e39007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14015
88356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1401588356
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.168419050
Short name T369
Test name
Test status
Simulation time 300918605 ps
CPU time 17.56 seconds
Started Aug 08 04:30:17 PM PDT 24
Finished Aug 08 04:30:35 PM PDT 24
Peak memory 255980 kb
Host smart-798155e1-f2b7-444c-b76d-9c98dbfef737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16841
9050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.168419050
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.898953101
Short name T254
Test name
Test status
Simulation time 230345743638 ps
CPU time 3350.85 seconds
Started Aug 08 04:30:39 PM PDT 24
Finished Aug 08 05:26:31 PM PDT 24
Peak memory 288428 kb
Host smart-baa68c5c-9409-4ee4-b21c-34c6ac8341bf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898953101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.898953101
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1959255078
Short name T614
Test name
Test status
Simulation time 283323064021 ps
CPU time 3897.02 seconds
Started Aug 08 04:30:42 PM PDT 24
Finished Aug 08 05:35:40 PM PDT 24
Peak memory 330184 kb
Host smart-bc78a17a-1b09-4cb0-a8e1-51f498ade1ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959255078 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1959255078
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.656797559
Short name T43
Test name
Test status
Simulation time 262005098880 ps
CPU time 1707.32 seconds
Started Aug 08 04:30:41 PM PDT 24
Finished Aug 08 04:59:09 PM PDT 24
Peak memory 288500 kb
Host smart-4d40bfff-610e-4866-b0d7-de82c83c34dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656797559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.656797559
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.4131524652
Short name T649
Test name
Test status
Simulation time 3063815317 ps
CPU time 62.15 seconds
Started Aug 08 04:30:28 PM PDT 24
Finished Aug 08 04:31:30 PM PDT 24
Peak memory 255948 kb
Host smart-f3ebf9f3-90e7-4456-8b52-006b9713b74d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41315
24652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.4131524652
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1642539306
Short name T683
Test name
Test status
Simulation time 3285957215 ps
CPU time 35.2 seconds
Started Aug 08 04:30:32 PM PDT 24
Finished Aug 08 04:31:08 PM PDT 24
Peak memory 248180 kb
Host smart-aaf259a0-8faf-445f-8806-e15944156e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16425
39306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1642539306
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.91654379
Short name T322
Test name
Test status
Simulation time 168130131244 ps
CPU time 2345.11 seconds
Started Aug 08 04:30:30 PM PDT 24
Finished Aug 08 05:09:35 PM PDT 24
Peak memory 283224 kb
Host smart-a72fef87-4b53-4566-bf71-93c5b50612d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91654379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.91654379
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3938698296
Short name T459
Test name
Test status
Simulation time 41957559246 ps
CPU time 1333.71 seconds
Started Aug 08 04:30:29 PM PDT 24
Finished Aug 08 04:52:43 PM PDT 24
Peak memory 271652 kb
Host smart-edcaf8eb-d7ec-46c3-9591-144743783ab0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938698296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3938698296
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1443562737
Short name T609
Test name
Test status
Simulation time 16734678508 ps
CPU time 358.54 seconds
Started Aug 08 04:30:36 PM PDT 24
Finished Aug 08 04:36:35 PM PDT 24
Peak memory 248128 kb
Host smart-e1c962cb-0a68-4a7e-93b9-365db4d9b174
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443562737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1443562737
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2942786856
Short name T397
Test name
Test status
Simulation time 3043289316 ps
CPU time 44.09 seconds
Started Aug 08 04:30:35 PM PDT 24
Finished Aug 08 04:31:19 PM PDT 24
Peak memory 248132 kb
Host smart-f9788d37-b893-4d03-853f-01f3ebdff781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29427
86856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2942786856
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.263788436
Short name T700
Test name
Test status
Simulation time 718933884 ps
CPU time 18.52 seconds
Started Aug 08 04:30:39 PM PDT 24
Finished Aug 08 04:30:58 PM PDT 24
Peak memory 255536 kb
Host smart-b010e3af-4a2b-4c2f-9080-3c50d97dd5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26378
8436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.263788436
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.245246255
Short name T273
Test name
Test status
Simulation time 3898006064 ps
CPU time 44.9 seconds
Started Aug 08 04:30:35 PM PDT 24
Finished Aug 08 04:31:20 PM PDT 24
Peak memory 248032 kb
Host smart-4e8e657a-3bdc-4635-994a-0321f8e90596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24524
6255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.245246255
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2100793256
Short name T595
Test name
Test status
Simulation time 238167760 ps
CPU time 6.65 seconds
Started Aug 08 04:30:36 PM PDT 24
Finished Aug 08 04:30:42 PM PDT 24
Peak memory 254376 kb
Host smart-e883dfd0-84de-46ec-ab23-e2b835474f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21007
93256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2100793256
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.826587344
Short name T245
Test name
Test status
Simulation time 25919192789 ps
CPU time 1137.54 seconds
Started Aug 08 04:30:48 PM PDT 24
Finished Aug 08 04:49:45 PM PDT 24
Peak memory 287168 kb
Host smart-cfa14a07-926f-4d2a-b0e8-3b166de90043
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826587344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.826587344
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3045996800
Short name T551
Test name
Test status
Simulation time 7863790426 ps
CPU time 662.76 seconds
Started Aug 08 04:30:38 PM PDT 24
Finished Aug 08 04:41:41 PM PDT 24
Peak memory 271964 kb
Host smart-b30080b9-685a-4d5b-a1c9-bfc828ae957c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045996800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3045996800
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3830509837
Short name T483
Test name
Test status
Simulation time 10146594454 ps
CPU time 153.68 seconds
Started Aug 08 04:30:29 PM PDT 24
Finished Aug 08 04:33:03 PM PDT 24
Peak memory 255396 kb
Host smart-ed4a894b-de14-4107-9f9b-539f66279b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38305
09837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3830509837
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1650908971
Short name T668
Test name
Test status
Simulation time 1328440566 ps
CPU time 47.34 seconds
Started Aug 08 04:30:35 PM PDT 24
Finished Aug 08 04:31:23 PM PDT 24
Peak memory 248024 kb
Host smart-891e8a42-9231-4334-ae8e-41dac994c1e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16509
08971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1650908971
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1297933475
Short name T231
Test name
Test status
Simulation time 46750872328 ps
CPU time 1609.44 seconds
Started Aug 08 04:30:34 PM PDT 24
Finished Aug 08 04:57:24 PM PDT 24
Peak memory 280980 kb
Host smart-8fc71c70-92c7-4e02-8000-9dcbf4419591
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297933475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1297933475
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2953861187
Short name T110
Test name
Test status
Simulation time 37294597213 ps
CPU time 960.34 seconds
Started Aug 08 04:30:35 PM PDT 24
Finished Aug 08 04:46:35 PM PDT 24
Peak memory 288540 kb
Host smart-f1b8c3e9-1661-42bb-a9fb-ee30b74ae929
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953861187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2953861187
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1217557703
Short name T308
Test name
Test status
Simulation time 10988150399 ps
CPU time 218.41 seconds
Started Aug 08 04:30:35 PM PDT 24
Finished Aug 08 04:34:13 PM PDT 24
Peak memory 248152 kb
Host smart-528d83b1-dc97-48ae-85c2-a37b96d37a9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217557703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1217557703
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.481813068
Short name T377
Test name
Test status
Simulation time 1433753136 ps
CPU time 34.67 seconds
Started Aug 08 04:30:30 PM PDT 24
Finished Aug 08 04:31:05 PM PDT 24
Peak memory 248124 kb
Host smart-47950705-98f3-4696-af3b-8ff1390fd628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48181
3068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.481813068
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1798668202
Short name T680
Test name
Test status
Simulation time 127228784 ps
CPU time 4.99 seconds
Started Aug 08 04:30:35 PM PDT 24
Finished Aug 08 04:30:40 PM PDT 24
Peak memory 247796 kb
Host smart-574cad94-215c-4320-8f8d-6cce9eb2f7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17986
68202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1798668202
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3480643065
Short name T251
Test name
Test status
Simulation time 414116634 ps
CPU time 26.43 seconds
Started Aug 08 04:30:41 PM PDT 24
Finished Aug 08 04:31:07 PM PDT 24
Peak memory 254976 kb
Host smart-81d18b07-8e36-40bb-8e34-dd1bd8ace6e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34806
43065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3480643065
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.4200463113
Short name T275
Test name
Test status
Simulation time 287511276 ps
CPU time 23.58 seconds
Started Aug 08 04:30:38 PM PDT 24
Finished Aug 08 04:31:02 PM PDT 24
Peak memory 248172 kb
Host smart-c27f0fe7-6860-4bfb-b9f6-1bdb28801c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42004
63113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.4200463113
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.813431834
Short name T601
Test name
Test status
Simulation time 492660338527 ps
CPU time 2945.82 seconds
Started Aug 08 04:30:50 PM PDT 24
Finished Aug 08 05:19:56 PM PDT 24
Peak memory 288168 kb
Host smart-757e5afc-7be4-4a66-9acd-9a62f0e7760e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813431834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.813431834
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2866248406
Short name T587
Test name
Test status
Simulation time 15237032632 ps
CPU time 678.53 seconds
Started Aug 08 04:30:41 PM PDT 24
Finished Aug 08 04:42:00 PM PDT 24
Peak memory 266540 kb
Host smart-0df6ce36-063e-42be-8c96-e4aea36c9f62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866248406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2866248406
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1918651794
Short name T592
Test name
Test status
Simulation time 703012683 ps
CPU time 73.29 seconds
Started Aug 08 04:30:39 PM PDT 24
Finished Aug 08 04:31:52 PM PDT 24
Peak memory 255856 kb
Host smart-ce88bcef-240d-481e-a4f1-c005ea631ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19186
51794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1918651794
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1537950800
Short name T478
Test name
Test status
Simulation time 396457880 ps
CPU time 37.39 seconds
Started Aug 08 04:30:40 PM PDT 24
Finished Aug 08 04:31:18 PM PDT 24
Peak memory 247740 kb
Host smart-6aa38e9c-96af-4c10-9395-898a2c774268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15379
50800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1537950800
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3236305524
Short name T232
Test name
Test status
Simulation time 33436034126 ps
CPU time 1909.4 seconds
Started Aug 08 04:30:41 PM PDT 24
Finished Aug 08 05:02:30 PM PDT 24
Peak memory 272692 kb
Host smart-0e12d3ba-2edf-4cfd-8f3a-2393537f3c36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236305524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3236305524
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.201346102
Short name T413
Test name
Test status
Simulation time 125760556 ps
CPU time 6.39 seconds
Started Aug 08 04:30:39 PM PDT 24
Finished Aug 08 04:30:46 PM PDT 24
Peak memory 248108 kb
Host smart-b252003c-dfff-483d-ad92-c2cc7707209f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20134
6102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.201346102
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.466376776
Short name T647
Test name
Test status
Simulation time 1480855633 ps
CPU time 34.05 seconds
Started Aug 08 04:30:32 PM PDT 24
Finished Aug 08 04:31:06 PM PDT 24
Peak memory 255540 kb
Host smart-5ae9e66b-bf28-4bc5-bc53-eead6d56ede9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46637
6776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.466376776
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1318532494
Short name T87
Test name
Test status
Simulation time 1840824689 ps
CPU time 27.3 seconds
Started Aug 08 04:30:41 PM PDT 24
Finished Aug 08 04:31:09 PM PDT 24
Peak memory 248624 kb
Host smart-956acbeb-4bdd-4bb0-b129-21a3432fa424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13185
32494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1318532494
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2559100848
Short name T394
Test name
Test status
Simulation time 260481475 ps
CPU time 23.92 seconds
Started Aug 08 04:30:39 PM PDT 24
Finished Aug 08 04:31:03 PM PDT 24
Peak memory 255892 kb
Host smart-d0e25070-0aba-4275-9840-cd345b013ea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25591
00848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2559100848
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2701672552
Short name T55
Test name
Test status
Simulation time 37520637494 ps
CPU time 1871.14 seconds
Started Aug 08 04:30:40 PM PDT 24
Finished Aug 08 05:01:51 PM PDT 24
Peak memory 287768 kb
Host smart-2036cc96-9c94-402c-934e-030de67a9734
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701672552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2701672552
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.934429685
Short name T221
Test name
Test status
Simulation time 35331485207 ps
CPU time 2474.09 seconds
Started Aug 08 04:30:35 PM PDT 24
Finished Aug 08 05:11:50 PM PDT 24
Peak memory 289032 kb
Host smart-6747c8b2-ebb4-4562-9c75-46ec31161ae8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934429685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.934429685
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3679324798
Short name T424
Test name
Test status
Simulation time 4872990438 ps
CPU time 103.83 seconds
Started Aug 08 04:30:40 PM PDT 24
Finished Aug 08 04:32:24 PM PDT 24
Peak memory 256296 kb
Host smart-fe45931a-eb63-47ae-b7b4-138773db3385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36793
24798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3679324798
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1504635029
Short name T554
Test name
Test status
Simulation time 1278460073 ps
CPU time 51.93 seconds
Started Aug 08 04:30:31 PM PDT 24
Finished Aug 08 04:31:23 PM PDT 24
Peak memory 248204 kb
Host smart-2c1e8bb0-6b3c-4a28-98f5-7f36e9607e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15046
35029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1504635029
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2819927230
Short name T331
Test name
Test status
Simulation time 53201225679 ps
CPU time 1033.8 seconds
Started Aug 08 04:30:41 PM PDT 24
Finished Aug 08 04:47:55 PM PDT 24
Peak memory 272088 kb
Host smart-e86edece-f2f8-43e9-ae8f-737086e4914a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819927230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2819927230
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.4021886740
Short name T18
Test name
Test status
Simulation time 139380430416 ps
CPU time 2174.26 seconds
Started Aug 08 04:30:27 PM PDT 24
Finished Aug 08 05:06:42 PM PDT 24
Peak memory 285844 kb
Host smart-fa59930e-83e3-4f03-92ac-cc64ca5ecc91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021886740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.4021886740
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2385419560
Short name T296
Test name
Test status
Simulation time 68540959170 ps
CPU time 482.65 seconds
Started Aug 08 04:30:45 PM PDT 24
Finished Aug 08 04:38:48 PM PDT 24
Peak memory 248064 kb
Host smart-95177e9a-c794-4c93-a592-62a1ee1eb091
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385419560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2385419560
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.333567806
Short name T498
Test name
Test status
Simulation time 1223767456 ps
CPU time 42.03 seconds
Started Aug 08 04:30:30 PM PDT 24
Finished Aug 08 04:31:12 PM PDT 24
Peak memory 255724 kb
Host smart-6bc7e959-e4eb-476c-8bf3-342400affb59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33356
7806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.333567806
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2815032617
Short name T364
Test name
Test status
Simulation time 211757110 ps
CPU time 16.85 seconds
Started Aug 08 04:30:34 PM PDT 24
Finished Aug 08 04:30:51 PM PDT 24
Peak memory 255620 kb
Host smart-c53917a0-52c1-45e4-bdce-1e809c38f43a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28150
32617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2815032617
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2216884821
Short name T51
Test name
Test status
Simulation time 100811796 ps
CPU time 8.64 seconds
Started Aug 08 04:30:32 PM PDT 24
Finished Aug 08 04:30:41 PM PDT 24
Peak memory 248168 kb
Host smart-8848b068-a25d-4d0a-8645-ec73f422a19f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22168
84821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2216884821
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3856184595
Short name T559
Test name
Test status
Simulation time 748402644 ps
CPU time 36 seconds
Started Aug 08 04:30:39 PM PDT 24
Finished Aug 08 04:31:16 PM PDT 24
Peak memory 256084 kb
Host smart-85191516-7ad3-4a98-844e-7c269209c393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38561
84595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3856184595
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2468656379
Short name T641
Test name
Test status
Simulation time 65389520396 ps
CPU time 2567.58 seconds
Started Aug 08 04:30:45 PM PDT 24
Finished Aug 08 05:13:33 PM PDT 24
Peak memory 289236 kb
Host smart-dcf2b800-6697-4af5-b3cd-7ab7e280f37f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468656379 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2468656379
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1180619535
Short name T17
Test name
Test status
Simulation time 15115307903 ps
CPU time 1370.65 seconds
Started Aug 08 04:30:44 PM PDT 24
Finished Aug 08 04:53:34 PM PDT 24
Peak memory 288916 kb
Host smart-17cdabf1-0d98-47bd-8cb6-88c60ff22228
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180619535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1180619535
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.576038976
Short name T440
Test name
Test status
Simulation time 3026726814 ps
CPU time 87.2 seconds
Started Aug 08 04:30:41 PM PDT 24
Finished Aug 08 04:32:08 PM PDT 24
Peak memory 249192 kb
Host smart-edf50764-084c-4063-b67c-c488a1317991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57603
8976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.576038976
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1183443188
Short name T616
Test name
Test status
Simulation time 891616347 ps
CPU time 49.77 seconds
Started Aug 08 04:30:39 PM PDT 24
Finished Aug 08 04:31:29 PM PDT 24
Peak memory 256356 kb
Host smart-acd9efc9-2ff6-4694-8e13-7e81d0d0c588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11834
43188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1183443188
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3345594951
Short name T109
Test name
Test status
Simulation time 11462918637 ps
CPU time 905.11 seconds
Started Aug 08 04:30:43 PM PDT 24
Finished Aug 08 04:45:49 PM PDT 24
Peak memory 281416 kb
Host smart-d46e641c-2c33-4206-8f04-10d04928744b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345594951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3345594951
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1209134844
Short name T3
Test name
Test status
Simulation time 18985015428 ps
CPU time 181.14 seconds
Started Aug 08 04:30:42 PM PDT 24
Finished Aug 08 04:33:43 PM PDT 24
Peak memory 248192 kb
Host smart-2fab3115-6e33-4071-b76e-973752492afb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209134844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1209134844
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2243490752
Short name T361
Test name
Test status
Simulation time 1054336067 ps
CPU time 60.95 seconds
Started Aug 08 04:30:40 PM PDT 24
Finished Aug 08 04:31:41 PM PDT 24
Peak memory 248172 kb
Host smart-540b4722-ba6e-4965-acd5-961e25cb5fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22434
90752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2243490752
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.891062678
Short name T416
Test name
Test status
Simulation time 251578996 ps
CPU time 24.41 seconds
Started Aug 08 04:30:38 PM PDT 24
Finished Aug 08 04:31:03 PM PDT 24
Peak memory 247960 kb
Host smart-e1fc4a91-5238-49ee-a131-23419d8e705c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89106
2678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.891062678
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1317181159
Short name T500
Test name
Test status
Simulation time 917742267 ps
CPU time 18.06 seconds
Started Aug 08 04:30:40 PM PDT 24
Finished Aug 08 04:30:58 PM PDT 24
Peak memory 255880 kb
Host smart-dca15032-cbde-469f-a51e-92a2f42976b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13171
81159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1317181159
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.195813415
Short name T390
Test name
Test status
Simulation time 2014753233 ps
CPU time 60.44 seconds
Started Aug 08 04:30:40 PM PDT 24
Finished Aug 08 04:31:41 PM PDT 24
Peak memory 256352 kb
Host smart-02364593-e817-450c-9043-71ceaf7ccb83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19581
3415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.195813415
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.4014948706
Short name T68
Test name
Test status
Simulation time 6541070561 ps
CPU time 633.52 seconds
Started Aug 08 04:30:33 PM PDT 24
Finished Aug 08 04:41:06 PM PDT 24
Peak memory 266608 kb
Host smart-61db46b5-dde0-4767-a3e3-bd8b0e6158a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014948706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.4014948706
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3959872132
Short name T514
Test name
Test status
Simulation time 3120995806 ps
CPU time 69.3 seconds
Started Aug 08 04:31:41 PM PDT 24
Finished Aug 08 04:32:50 PM PDT 24
Peak memory 256104 kb
Host smart-c8426d2f-b19a-4c57-be6e-1e83b0d4ffc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39598
72132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3959872132
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.4063971703
Short name T403
Test name
Test status
Simulation time 624856020 ps
CPU time 10.22 seconds
Started Aug 08 04:30:42 PM PDT 24
Finished Aug 08 04:30:53 PM PDT 24
Peak memory 247688 kb
Host smart-0f51aefa-d787-4f99-9e52-ae3bc0468322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40639
71703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.4063971703
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.224748886
Short name T423
Test name
Test status
Simulation time 99348250388 ps
CPU time 1804.84 seconds
Started Aug 08 04:30:39 PM PDT 24
Finished Aug 08 05:00:44 PM PDT 24
Peak memory 282816 kb
Host smart-3a52a987-f26f-4bc3-804b-e6eea308fa5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224748886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.224748886
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.440820169
Short name T226
Test name
Test status
Simulation time 12946693334 ps
CPU time 486.34 seconds
Started Aug 08 04:30:44 PM PDT 24
Finished Aug 08 04:38:50 PM PDT 24
Peak memory 248192 kb
Host smart-32f2093f-0df9-4c56-a4b9-51d056651f85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440820169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.440820169
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.4261417009
Short name T371
Test name
Test status
Simulation time 129328779 ps
CPU time 7.74 seconds
Started Aug 08 04:31:43 PM PDT 24
Finished Aug 08 04:31:51 PM PDT 24
Peak memory 247912 kb
Host smart-e47396b0-e95f-40a9-b57d-a09ab66e4d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42614
17009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.4261417009
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3865082917
Short name T533
Test name
Test status
Simulation time 107568423 ps
CPU time 7.5 seconds
Started Aug 08 04:31:43 PM PDT 24
Finished Aug 08 04:31:51 PM PDT 24
Peak memory 249780 kb
Host smart-6c3b4596-5233-4746-aa6a-82eaae60e74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38650
82917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3865082917
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2906438532
Short name T206
Test name
Test status
Simulation time 258917622 ps
CPU time 4.95 seconds
Started Aug 08 04:31:48 PM PDT 24
Finished Aug 08 04:31:53 PM PDT 24
Peak memory 250200 kb
Host smart-bb770a58-4053-4881-8487-48d9476ccc7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29064
38532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2906438532
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3683297784
Short name T400
Test name
Test status
Simulation time 2907046267 ps
CPU time 104.66 seconds
Started Aug 08 04:30:35 PM PDT 24
Finished Aug 08 04:32:20 PM PDT 24
Peak memory 249532 kb
Host smart-cf55e4c9-c5cb-41bd-9977-f676b1e2e082
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683297784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3683297784
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1763762949
Short name T204
Test name
Test status
Simulation time 80352556 ps
CPU time 3.03 seconds
Started Aug 08 04:29:42 PM PDT 24
Finished Aug 08 04:29:46 PM PDT 24
Peak memory 248332 kb
Host smart-2c19034b-5aad-44f9-8437-e1130dfebe5d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1763762949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1763762949
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2456454401
Short name T669
Test name
Test status
Simulation time 143696664265 ps
CPU time 1860.78 seconds
Started Aug 08 04:29:38 PM PDT 24
Finished Aug 08 05:00:39 PM PDT 24
Peak memory 272728 kb
Host smart-86aeaad7-c2b2-421b-b3b7-09c3a5b94594
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456454401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2456454401
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3594504585
Short name T4
Test name
Test status
Simulation time 3082331066 ps
CPU time 15.78 seconds
Started Aug 08 04:29:41 PM PDT 24
Finished Aug 08 04:29:57 PM PDT 24
Peak memory 248248 kb
Host smart-aeecc8c8-d3be-4679-9981-900a7fc9e61f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3594504585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3594504585
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1447064774
Short name T368
Test name
Test status
Simulation time 467053228 ps
CPU time 29.82 seconds
Started Aug 08 04:29:37 PM PDT 24
Finished Aug 08 04:30:07 PM PDT 24
Peak memory 255916 kb
Host smart-78435fab-d46e-4271-9853-fe5b473ed7f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14470
64774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1447064774
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.205869547
Short name T216
Test name
Test status
Simulation time 1440008845 ps
CPU time 42 seconds
Started Aug 08 04:29:37 PM PDT 24
Finished Aug 08 04:30:19 PM PDT 24
Peak memory 247548 kb
Host smart-9e91d431-ca72-4549-841c-e9f2af9569b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20586
9547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.205869547
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3202662040
Short name T337
Test name
Test status
Simulation time 51465533738 ps
CPU time 976.19 seconds
Started Aug 08 04:29:49 PM PDT 24
Finished Aug 08 04:46:05 PM PDT 24
Peak memory 271988 kb
Host smart-cb492f98-9dd1-4668-9279-867dd2d16b98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202662040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3202662040
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2949160639
Short name T441
Test name
Test status
Simulation time 16266791121 ps
CPU time 720.11 seconds
Started Aug 08 04:29:45 PM PDT 24
Finished Aug 08 04:41:45 PM PDT 24
Peak memory 272584 kb
Host smart-f7db8884-38d3-4184-9307-dfbd89526855
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949160639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2949160639
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2588447555
Short name T599
Test name
Test status
Simulation time 13754207740 ps
CPU time 573.6 seconds
Started Aug 08 04:29:39 PM PDT 24
Finished Aug 08 04:39:13 PM PDT 24
Peak memory 248188 kb
Host smart-c1b76a8d-eba7-44a1-abf7-14ecefdf4977
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588447555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2588447555
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.3662345830
Short name T357
Test name
Test status
Simulation time 312451865 ps
CPU time 15.93 seconds
Started Aug 08 04:29:37 PM PDT 24
Finished Aug 08 04:29:53 PM PDT 24
Peak memory 255692 kb
Host smart-ba502ae6-6fdf-4778-89ff-c9d806f51026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36623
45830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3662345830
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2248972250
Short name T434
Test name
Test status
Simulation time 96439851 ps
CPU time 2.83 seconds
Started Aug 08 04:29:29 PM PDT 24
Finished Aug 08 04:29:32 PM PDT 24
Peak memory 239160 kb
Host smart-0ad0a0c9-a2ce-4333-b8fa-0976d2a5f417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22489
72250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2248972250
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1849851439
Short name T7
Test name
Test status
Simulation time 712644533 ps
CPU time 22.19 seconds
Started Aug 08 04:29:45 PM PDT 24
Finished Aug 08 04:30:07 PM PDT 24
Peak memory 275728 kb
Host smart-7bdf6fef-aa33-4782-955d-7e910092abbe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1849851439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1849851439
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3026304546
Short name T280
Test name
Test status
Simulation time 3872978165 ps
CPU time 49.97 seconds
Started Aug 08 04:29:38 PM PDT 24
Finished Aug 08 04:30:28 PM PDT 24
Peak memory 248748 kb
Host smart-172264f1-77ad-40e8-aa90-99bf4df7d479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30263
04546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3026304546
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2425939295
Short name T677
Test name
Test status
Simulation time 1004561772 ps
CPU time 25.44 seconds
Started Aug 08 04:29:37 PM PDT 24
Finished Aug 08 04:30:03 PM PDT 24
Peak memory 248528 kb
Host smart-083fa400-8825-4e84-b5a6-0f934357877f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24259
39295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2425939295
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2174198052
Short name T522
Test name
Test status
Simulation time 1314394636 ps
CPU time 125.29 seconds
Started Aug 08 04:29:45 PM PDT 24
Finished Aug 08 04:31:50 PM PDT 24
Peak memory 256260 kb
Host smart-7aab192d-0241-43d3-8995-73f393636fbf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174198052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2174198052
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.2363073511
Short name T618
Test name
Test status
Simulation time 95249656816 ps
CPU time 4163.04 seconds
Started Aug 08 04:29:42 PM PDT 24
Finished Aug 08 05:39:06 PM PDT 24
Peak memory 321796 kb
Host smart-26b392d0-da4e-4d67-931c-72a5a8040d09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363073511 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.2363073511
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3034218597
Short name T470
Test name
Test status
Simulation time 27537072127 ps
CPU time 1686.58 seconds
Started Aug 08 04:30:41 PM PDT 24
Finished Aug 08 04:58:48 PM PDT 24
Peak memory 272772 kb
Host smart-cdfd6cb7-0aa4-494a-8d16-c21d3482604c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034218597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3034218597
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1075493810
Short name T517
Test name
Test status
Simulation time 2248180331 ps
CPU time 131.78 seconds
Started Aug 08 04:30:46 PM PDT 24
Finished Aug 08 04:32:58 PM PDT 24
Peak memory 249208 kb
Host smart-f06f2cf3-ec70-49ca-94d7-014277b8fe7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10754
93810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1075493810
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1778832352
Short name T701
Test name
Test status
Simulation time 382488610 ps
CPU time 22.15 seconds
Started Aug 08 04:30:41 PM PDT 24
Finished Aug 08 04:31:04 PM PDT 24
Peak memory 248148 kb
Host smart-7e209012-e780-4ed1-be39-84edd758e3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17788
32352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1778832352
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1945134264
Short name T553
Test name
Test status
Simulation time 381479983410 ps
CPU time 1581.72 seconds
Started Aug 08 04:30:42 PM PDT 24
Finished Aug 08 04:57:04 PM PDT 24
Peak memory 272712 kb
Host smart-0d976cfc-027e-4380-8d53-06900a658b99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945134264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1945134264
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.4061564144
Short name T703
Test name
Test status
Simulation time 15119911635 ps
CPU time 1367.24 seconds
Started Aug 08 04:30:52 PM PDT 24
Finished Aug 08 04:53:39 PM PDT 24
Peak memory 287484 kb
Host smart-3efc09a9-c172-48b5-be5a-9bee4e7f97aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061564144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.4061564144
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.4187939822
Short name T706
Test name
Test status
Simulation time 5546162351 ps
CPU time 232.8 seconds
Started Aug 08 04:30:38 PM PDT 24
Finished Aug 08 04:34:31 PM PDT 24
Peak memory 248204 kb
Host smart-18ec40c8-46c3-4b96-bfd1-79f0f9a4b60d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187939822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.4187939822
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2840202970
Short name T448
Test name
Test status
Simulation time 87394141 ps
CPU time 7.57 seconds
Started Aug 08 04:30:34 PM PDT 24
Finished Aug 08 04:30:41 PM PDT 24
Peak memory 248108 kb
Host smart-6b5305c6-2ca5-4994-9bc1-2a68f0bd0006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28402
02970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2840202970
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.64669586
Short name T60
Test name
Test status
Simulation time 12722848052 ps
CPU time 58 seconds
Started Aug 08 04:30:46 PM PDT 24
Finished Aug 08 04:31:44 PM PDT 24
Peak memory 247860 kb
Host smart-0dc62c59-590b-4257-8649-a7e8f67a5141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64669
586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.64669586
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3595801016
Short name T556
Test name
Test status
Simulation time 296630460 ps
CPU time 32 seconds
Started Aug 08 04:30:44 PM PDT 24
Finished Aug 08 04:31:16 PM PDT 24
Peak memory 247704 kb
Host smart-108c6cd7-8108-4be9-85ca-3c6d77ba5930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35958
01016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3595801016
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3127349598
Short name T516
Test name
Test status
Simulation time 388339199 ps
CPU time 26.25 seconds
Started Aug 08 04:30:45 PM PDT 24
Finished Aug 08 04:31:11 PM PDT 24
Peak memory 256272 kb
Host smart-d0cd94b5-5d4b-4b0b-aef3-c08362039aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31273
49598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3127349598
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.4084543230
Short name T589
Test name
Test status
Simulation time 30388549985 ps
CPU time 141.68 seconds
Started Aug 08 04:31:47 PM PDT 24
Finished Aug 08 04:34:09 PM PDT 24
Peak memory 256200 kb
Host smart-5a2bca39-5e8c-430b-b71b-49cddad0eacc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084543230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.4084543230
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2348479400
Short name T57
Test name
Test status
Simulation time 29622770868 ps
CPU time 1868.63 seconds
Started Aug 08 04:30:46 PM PDT 24
Finished Aug 08 05:01:55 PM PDT 24
Peak memory 285904 kb
Host smart-c901074d-be2e-4da1-8fa5-1822d23e47fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348479400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2348479400
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3248003855
Short name T449
Test name
Test status
Simulation time 8865968556 ps
CPU time 146.51 seconds
Started Aug 08 04:31:48 PM PDT 24
Finished Aug 08 04:34:14 PM PDT 24
Peak memory 255664 kb
Host smart-fdbc6cd4-84ae-4ccf-b138-b7ab2caf575f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32480
03855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3248003855
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.509124787
Short name T446
Test name
Test status
Simulation time 216858999 ps
CPU time 25.76 seconds
Started Aug 08 04:30:43 PM PDT 24
Finished Aug 08 04:31:09 PM PDT 24
Peak memory 247688 kb
Host smart-367a1ed7-300f-4b40-83cc-cef81f56ae7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50912
4787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.509124787
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3689987865
Short name T320
Test name
Test status
Simulation time 19689131046 ps
CPU time 1630.49 seconds
Started Aug 08 04:30:44 PM PDT 24
Finished Aug 08 04:57:54 PM PDT 24
Peak memory 289064 kb
Host smart-94174746-32f9-426f-a9df-62619cb29af1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689987865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3689987865
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2067383616
Short name T461
Test name
Test status
Simulation time 42645903017 ps
CPU time 1319.77 seconds
Started Aug 08 04:30:45 PM PDT 24
Finished Aug 08 04:52:45 PM PDT 24
Peak memory 288000 kb
Host smart-a8279f70-50a0-40f2-96f9-e094297acdfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067383616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2067383616
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2723391827
Short name T465
Test name
Test status
Simulation time 8589394123 ps
CPU time 311.92 seconds
Started Aug 08 04:31:43 PM PDT 24
Finished Aug 08 04:36:55 PM PDT 24
Peak memory 254092 kb
Host smart-2cb90599-ecc2-4d53-b443-5f46fa40acbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723391827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2723391827
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.4250658333
Short name T580
Test name
Test status
Simulation time 413216419 ps
CPU time 8.37 seconds
Started Aug 08 04:31:41 PM PDT 24
Finished Aug 08 04:31:50 PM PDT 24
Peak memory 247916 kb
Host smart-2612e453-d6e5-432e-967d-80e6f57eced1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42506
58333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.4250658333
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.395939460
Short name T278
Test name
Test status
Simulation time 667692581 ps
CPU time 38.62 seconds
Started Aug 08 04:31:41 PM PDT 24
Finished Aug 08 04:32:20 PM PDT 24
Peak memory 255580 kb
Host smart-6819e0ae-b5c1-4b76-b7b6-2bbe327c976c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39593
9460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.395939460
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1824263024
Short name T414
Test name
Test status
Simulation time 522143511 ps
CPU time 10.91 seconds
Started Aug 08 04:31:41 PM PDT 24
Finished Aug 08 04:31:52 PM PDT 24
Peak memory 247472 kb
Host smart-0a1b4b6a-595e-4e7e-82aa-b788a193f072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18242
63024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1824263024
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2834031153
Short name T355
Test name
Test status
Simulation time 700604352 ps
CPU time 25.16 seconds
Started Aug 08 04:30:45 PM PDT 24
Finished Aug 08 04:31:11 PM PDT 24
Peak memory 255424 kb
Host smart-6d54cbf9-4092-42b1-9c20-8d3e7cd4e8da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28340
31153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2834031153
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.3099715138
Short name T95
Test name
Test status
Simulation time 280733224350 ps
CPU time 5648.24 seconds
Started Aug 08 04:30:53 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 321760 kb
Host smart-6c0db355-8176-4bf4-87c1-bdb2fc747c52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099715138 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.3099715138
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2542630129
Short name T686
Test name
Test status
Simulation time 15347287573 ps
CPU time 1240.42 seconds
Started Aug 08 04:30:46 PM PDT 24
Finished Aug 08 04:51:27 PM PDT 24
Peak memory 288276 kb
Host smart-6cd8771c-eac4-490f-9e61-a56e6658f68d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542630129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2542630129
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2263277778
Short name T582
Test name
Test status
Simulation time 699784376 ps
CPU time 17.27 seconds
Started Aug 08 04:30:47 PM PDT 24
Finished Aug 08 04:31:04 PM PDT 24
Peak memory 255348 kb
Host smart-6db0c71c-08d2-4504-b6b0-f262e9b73510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22632
77778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2263277778
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1724838482
Short name T665
Test name
Test status
Simulation time 808519097 ps
CPU time 16.56 seconds
Started Aug 08 04:30:45 PM PDT 24
Finished Aug 08 04:31:02 PM PDT 24
Peak memory 248096 kb
Host smart-836fd84b-02cd-4e81-879e-407ab9fa6da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17248
38482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1724838482
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3814711812
Short name T314
Test name
Test status
Simulation time 18590771915 ps
CPU time 760.91 seconds
Started Aug 08 04:30:49 PM PDT 24
Finished Aug 08 04:43:30 PM PDT 24
Peak memory 272732 kb
Host smart-955a392e-bd4b-4076-9725-2e5d0fc44606
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814711812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3814711812
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3911279977
Short name T523
Test name
Test status
Simulation time 121796138712 ps
CPU time 1966.39 seconds
Started Aug 08 04:30:45 PM PDT 24
Finished Aug 08 05:03:31 PM PDT 24
Peak memory 272700 kb
Host smart-cd03fb8e-b141-4611-ab1c-a74fa08b8f3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911279977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3911279977
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2344688307
Short name T583
Test name
Test status
Simulation time 23163712176 ps
CPU time 265.53 seconds
Started Aug 08 04:30:46 PM PDT 24
Finished Aug 08 04:35:11 PM PDT 24
Peak memory 255112 kb
Host smart-82ea3b40-d066-4de8-ab78-bb7f15b994d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344688307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2344688307
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.668250232
Short name T637
Test name
Test status
Simulation time 3029113696 ps
CPU time 24.51 seconds
Started Aug 08 04:30:45 PM PDT 24
Finished Aug 08 04:31:09 PM PDT 24
Peak memory 255812 kb
Host smart-aaa642bd-8774-4a56-a239-3f47bac492cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66825
0232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.668250232
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2880225203
Short name T436
Test name
Test status
Simulation time 9530470110 ps
CPU time 38.86 seconds
Started Aug 08 04:30:49 PM PDT 24
Finished Aug 08 04:31:28 PM PDT 24
Peak memory 247800 kb
Host smart-fdbd3e04-8b59-4c5d-871a-5dde6a6e25f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28802
25203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2880225203
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2855822808
Short name T620
Test name
Test status
Simulation time 442973058 ps
CPU time 29.29 seconds
Started Aug 08 04:30:56 PM PDT 24
Finished Aug 08 04:31:25 PM PDT 24
Peak memory 248712 kb
Host smart-2749b529-8d74-42f8-8f0c-4ec811f9d13b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28558
22808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2855822808
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.443962083
Short name T112
Test name
Test status
Simulation time 154876281 ps
CPU time 19.08 seconds
Started Aug 08 04:30:45 PM PDT 24
Finished Aug 08 04:31:05 PM PDT 24
Peak memory 255396 kb
Host smart-d1459d0c-a7c2-4151-86a9-b15a0bdff490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44396
2083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.443962083
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3843003824
Short name T519
Test name
Test status
Simulation time 37071520425 ps
CPU time 2063.9 seconds
Started Aug 08 04:30:50 PM PDT 24
Finished Aug 08 05:05:14 PM PDT 24
Peak memory 283112 kb
Host smart-dfe3f4b6-7502-4631-b19c-d34a30d038a9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843003824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3843003824
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3122935594
Short name T598
Test name
Test status
Simulation time 113580007217 ps
CPU time 682.87 seconds
Started Aug 08 04:30:45 PM PDT 24
Finished Aug 08 04:42:08 PM PDT 24
Peak memory 264660 kb
Host smart-8029bbd0-618f-4307-b715-6c0b315715a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122935594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3122935594
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.709577142
Short name T209
Test name
Test status
Simulation time 14103031443 ps
CPU time 265.18 seconds
Started Aug 08 04:30:45 PM PDT 24
Finished Aug 08 04:35:10 PM PDT 24
Peak memory 256416 kb
Host smart-dabf6781-b78a-4576-9c23-2cf395163b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70957
7142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.709577142
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2452657091
Short name T73
Test name
Test status
Simulation time 18372845894 ps
CPU time 59.46 seconds
Started Aug 08 04:30:47 PM PDT 24
Finished Aug 08 04:31:47 PM PDT 24
Peak memory 248196 kb
Host smart-b4392baf-ac33-440e-9c00-69eb10bb5f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24526
57091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2452657091
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2343777781
Short name T572
Test name
Test status
Simulation time 10016747072 ps
CPU time 918.56 seconds
Started Aug 08 04:30:53 PM PDT 24
Finished Aug 08 04:46:11 PM PDT 24
Peak memory 272728 kb
Host smart-d4663f81-ccff-470c-badd-055297ba97a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343777781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2343777781
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1121024681
Short name T64
Test name
Test status
Simulation time 5635965902 ps
CPU time 710.55 seconds
Started Aug 08 04:30:49 PM PDT 24
Finished Aug 08 04:42:40 PM PDT 24
Peak memory 272772 kb
Host smart-e981b70e-5dfa-4f3f-865d-796a8fa42a80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121024681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1121024681
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2622670977
Short name T302
Test name
Test status
Simulation time 31678661337 ps
CPU time 302.98 seconds
Started Aug 08 04:30:47 PM PDT 24
Finished Aug 08 04:35:50 PM PDT 24
Peak memory 248276 kb
Host smart-8721aa28-ac82-4e58-aded-dc1a0638a229
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622670977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2622670977
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1878021138
Short name T681
Test name
Test status
Simulation time 1075224737 ps
CPU time 64.7 seconds
Started Aug 08 04:30:50 PM PDT 24
Finished Aug 08 04:31:55 PM PDT 24
Peak memory 256396 kb
Host smart-24c1c0bf-a652-45d2-abe6-99181d1f47af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18780
21138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1878021138
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3439950323
Short name T113
Test name
Test status
Simulation time 3790252058 ps
CPU time 59 seconds
Started Aug 08 04:30:53 PM PDT 24
Finished Aug 08 04:31:52 PM PDT 24
Peak memory 255572 kb
Host smart-dedc1052-e9a1-4235-8452-8951e4130668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34399
50323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3439950323
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3362704177
Short name T70
Test name
Test status
Simulation time 1974548364 ps
CPU time 27.94 seconds
Started Aug 08 04:30:45 PM PDT 24
Finished Aug 08 04:31:13 PM PDT 24
Peak memory 247444 kb
Host smart-e70d114d-a839-4e7a-95ec-ebc5cd95b62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33627
04177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3362704177
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3886259464
Short name T694
Test name
Test status
Simulation time 138962814 ps
CPU time 8.58 seconds
Started Aug 08 04:30:45 PM PDT 24
Finished Aug 08 04:30:53 PM PDT 24
Peak memory 253408 kb
Host smart-aa40d458-1675-4a11-a2ca-b35f2480cc3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38862
59464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3886259464
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.1809301978
Short name T100
Test name
Test status
Simulation time 99694116772 ps
CPU time 2536.66 seconds
Started Aug 08 04:30:46 PM PDT 24
Finished Aug 08 05:13:03 PM PDT 24
Peak memory 321980 kb
Host smart-0ff8102d-5e71-47bc-a3c4-9c71dc12a956
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809301978 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.1809301978
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2987014649
Short name T635
Test name
Test status
Simulation time 44401123740 ps
CPU time 1451 seconds
Started Aug 08 04:30:45 PM PDT 24
Finished Aug 08 04:54:56 PM PDT 24
Peak memory 271648 kb
Host smart-e57986b8-4a43-4628-9bb1-9e39ddb5985b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987014649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2987014649
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1620077818
Short name T646
Test name
Test status
Simulation time 1177964933 ps
CPU time 5.25 seconds
Started Aug 08 04:30:48 PM PDT 24
Finished Aug 08 04:30:53 PM PDT 24
Peak memory 239292 kb
Host smart-0c797dad-78fd-42d7-919d-d32a465c616a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16200
77818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1620077818
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3163495999
Short name T508
Test name
Test status
Simulation time 514775736 ps
CPU time 20.82 seconds
Started Aug 08 04:30:47 PM PDT 24
Finished Aug 08 04:31:08 PM PDT 24
Peak memory 248160 kb
Host smart-ecfe1d9c-3b2b-4b3e-a3da-a88f947b7c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31634
95999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3163495999
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.45985290
Short name T294
Test name
Test status
Simulation time 16732750947 ps
CPU time 1115.37 seconds
Started Aug 08 04:30:45 PM PDT 24
Finished Aug 08 04:49:21 PM PDT 24
Peak memory 288144 kb
Host smart-b4d5f8ee-c5e6-40fe-b0ff-7e64e263a15f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45985290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.45985290
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.855416945
Short name T288
Test name
Test status
Simulation time 119273475776 ps
CPU time 1371.88 seconds
Started Aug 08 04:30:44 PM PDT 24
Finished Aug 08 04:53:36 PM PDT 24
Peak memory 272636 kb
Host smart-5f3cc8e7-465b-43f4-bfde-539011aee196
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855416945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.855416945
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3335541910
Short name T526
Test name
Test status
Simulation time 57639663502 ps
CPU time 502.46 seconds
Started Aug 08 04:30:48 PM PDT 24
Finished Aug 08 04:39:10 PM PDT 24
Peak memory 247240 kb
Host smart-f82be07d-2806-4b08-b42c-c01293c6f153
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335541910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3335541910
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1962460321
Short name T426
Test name
Test status
Simulation time 519949319 ps
CPU time 28.16 seconds
Started Aug 08 04:30:48 PM PDT 24
Finished Aug 08 04:31:16 PM PDT 24
Peak memory 248180 kb
Host smart-eff61b0a-cd42-43a3-803c-c0561c71d31a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19624
60321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1962460321
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1233850208
Short name T537
Test name
Test status
Simulation time 339564278 ps
CPU time 26.09 seconds
Started Aug 08 04:30:43 PM PDT 24
Finished Aug 08 04:31:09 PM PDT 24
Peak memory 248200 kb
Host smart-34336858-2d81-4488-bf2d-b02180afec0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12338
50208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1233850208
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1060107235
Short name T238
Test name
Test status
Simulation time 878147681 ps
CPU time 35.91 seconds
Started Aug 08 04:30:47 PM PDT 24
Finished Aug 08 04:31:23 PM PDT 24
Peak memory 248228 kb
Host smart-6e88c823-276f-405e-8c7f-cee21c85b0b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10601
07235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1060107235
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.345884637
Short name T652
Test name
Test status
Simulation time 592102312 ps
CPU time 10.34 seconds
Started Aug 08 04:30:49 PM PDT 24
Finished Aug 08 04:31:00 PM PDT 24
Peak memory 248644 kb
Host smart-4c4f3840-1317-49cf-8d8b-9c51fe502466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34588
4637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.345884637
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2281835101
Short name T6
Test name
Test status
Simulation time 15649161572 ps
CPU time 922.88 seconds
Started Aug 08 04:30:46 PM PDT 24
Finished Aug 08 04:46:09 PM PDT 24
Peak memory 280892 kb
Host smart-a24dda69-d8cc-4769-ae3c-fb4eac9a4e22
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281835101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2281835101
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.3580892401
Short name T181
Test name
Test status
Simulation time 66521049784 ps
CPU time 6270.19 seconds
Started Aug 08 04:30:48 PM PDT 24
Finished Aug 08 06:15:19 PM PDT 24
Peak memory 369820 kb
Host smart-5ab0b1c3-1440-4077-9352-6784d0805982
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580892401 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.3580892401
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.426531375
Short name T30
Test name
Test status
Simulation time 29671576444 ps
CPU time 2014.21 seconds
Started Aug 08 04:30:57 PM PDT 24
Finished Aug 08 05:04:32 PM PDT 24
Peak memory 286692 kb
Host smart-a11ff542-992a-42f7-a91c-e8f1e7aff97d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426531375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.426531375
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3259140089
Short name T684
Test name
Test status
Simulation time 30347873981 ps
CPU time 241.69 seconds
Started Aug 08 04:30:59 PM PDT 24
Finished Aug 08 04:35:01 PM PDT 24
Peak memory 256340 kb
Host smart-04d7b7e0-3d2b-4fe8-808d-677f0781573c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32591
40089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3259140089
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3829240442
Short name T65
Test name
Test status
Simulation time 798505909 ps
CPU time 15.47 seconds
Started Aug 08 04:31:01 PM PDT 24
Finished Aug 08 04:31:17 PM PDT 24
Peak memory 247780 kb
Host smart-27f0e843-6b99-43ed-9ea3-06fb57418353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38292
40442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3829240442
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1767268588
Short name T295
Test name
Test status
Simulation time 14527179253 ps
CPU time 1141.97 seconds
Started Aug 08 04:30:59 PM PDT 24
Finished Aug 08 04:50:01 PM PDT 24
Peak memory 272472 kb
Host smart-b22f1e89-2203-453d-9c20-c897bc67590d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767268588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1767268588
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2438389797
Short name T287
Test name
Test status
Simulation time 85904733783 ps
CPU time 655.38 seconds
Started Aug 08 04:31:01 PM PDT 24
Finished Aug 08 04:41:57 PM PDT 24
Peak memory 266668 kb
Host smart-cd0888c0-45a5-4721-9c68-ba696374040d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438389797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2438389797
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3759457510
Short name T625
Test name
Test status
Simulation time 1035358532 ps
CPU time 33.38 seconds
Started Aug 08 04:30:45 PM PDT 24
Finished Aug 08 04:31:19 PM PDT 24
Peak memory 248144 kb
Host smart-9fc82b9c-093e-4d7b-a997-33dbc8983baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37594
57510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3759457510
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2036699224
Short name T395
Test name
Test status
Simulation time 1378082226 ps
CPU time 20.89 seconds
Started Aug 08 04:30:59 PM PDT 24
Finished Aug 08 04:31:20 PM PDT 24
Peak memory 247748 kb
Host smart-70837b17-5ffb-4ab2-a385-3d3777cc44c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20366
99224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2036699224
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3956847096
Short name T360
Test name
Test status
Simulation time 341837422 ps
CPU time 34.75 seconds
Started Aug 08 04:30:58 PM PDT 24
Finished Aug 08 04:31:33 PM PDT 24
Peak memory 248212 kb
Host smart-85295b2e-e3d9-43cd-93aa-f3bee56bc0a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39568
47096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3956847096
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2713352852
Short name T543
Test name
Test status
Simulation time 681317167 ps
CPU time 31.67 seconds
Started Aug 08 04:30:44 PM PDT 24
Finished Aug 08 04:31:16 PM PDT 24
Peak memory 255384 kb
Host smart-5d5b5f02-17ed-43df-b439-11df18350c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27133
52852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2713352852
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2577124830
Short name T249
Test name
Test status
Simulation time 46275789181 ps
CPU time 2636.48 seconds
Started Aug 08 04:31:02 PM PDT 24
Finished Aug 08 05:14:59 PM PDT 24
Peak memory 289028 kb
Host smart-6cfcf561-cf87-4a06-89f0-1be9fa02b17b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577124830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2577124830
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1890768657
Short name T267
Test name
Test status
Simulation time 63447421995 ps
CPU time 1116.02 seconds
Started Aug 08 04:30:59 PM PDT 24
Finished Aug 08 04:49:35 PM PDT 24
Peak memory 285376 kb
Host smart-b44bdd8e-be1e-460b-9b8c-7c1f8c688541
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890768657 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1890768657
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2725660880
Short name T90
Test name
Test status
Simulation time 89089132775 ps
CPU time 2527.43 seconds
Started Aug 08 04:30:58 PM PDT 24
Finished Aug 08 05:13:06 PM PDT 24
Peak memory 285744 kb
Host smart-199d7511-4657-4865-8d0f-5bb20b967cf9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725660880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2725660880
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1134855910
Short name T596
Test name
Test status
Simulation time 1726904038 ps
CPU time 54.4 seconds
Started Aug 08 04:31:00 PM PDT 24
Finished Aug 08 04:31:55 PM PDT 24
Peak memory 255812 kb
Host smart-b6e3d982-1450-46d9-80fc-77a29ea42b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11348
55910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1134855910
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3190015833
Short name T452
Test name
Test status
Simulation time 850575892 ps
CPU time 56.9 seconds
Started Aug 08 04:30:58 PM PDT 24
Finished Aug 08 04:31:55 PM PDT 24
Peak memory 248084 kb
Host smart-a110c93d-fe16-4a68-b884-e9c26c19af5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31900
15833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3190015833
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1007670007
Short name T293
Test name
Test status
Simulation time 43803058270 ps
CPU time 2383.59 seconds
Started Aug 08 04:31:00 PM PDT 24
Finished Aug 08 05:10:44 PM PDT 24
Peak memory 288480 kb
Host smart-8c0dde36-a89f-446d-b5af-8dca1773f336
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007670007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1007670007
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3468145054
Short name T223
Test name
Test status
Simulation time 25727131076 ps
CPU time 1235.49 seconds
Started Aug 08 04:30:59 PM PDT 24
Finished Aug 08 04:51:35 PM PDT 24
Peak memory 268740 kb
Host smart-346eaac0-9536-4b5b-bb4b-bb44124ec008
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468145054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3468145054
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2691666634
Short name T548
Test name
Test status
Simulation time 451614571 ps
CPU time 9.9 seconds
Started Aug 08 04:30:59 PM PDT 24
Finished Aug 08 04:31:10 PM PDT 24
Peak memory 253072 kb
Host smart-717c641f-4ef9-4d4d-bce5-e616d79baa1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26916
66634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2691666634
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3986108288
Short name T210
Test name
Test status
Simulation time 965429810 ps
CPU time 63.61 seconds
Started Aug 08 04:30:58 PM PDT 24
Finished Aug 08 04:32:02 PM PDT 24
Peak memory 247556 kb
Host smart-ca19b630-c995-40c3-af35-687bc7dd9af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39861
08288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3986108288
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2588683194
Short name T49
Test name
Test status
Simulation time 2398915754 ps
CPU time 22.66 seconds
Started Aug 08 04:30:59 PM PDT 24
Finished Aug 08 04:31:22 PM PDT 24
Peak memory 255976 kb
Host smart-249173e0-94f5-4d2b-aa12-3634c91d4387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25886
83194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2588683194
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1663405719
Short name T412
Test name
Test status
Simulation time 1567206893 ps
CPU time 22.13 seconds
Started Aug 08 04:31:03 PM PDT 24
Finished Aug 08 04:31:26 PM PDT 24
Peak memory 256392 kb
Host smart-bd2a5bd3-c01c-4029-958d-643b0c6f8884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16634
05719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1663405719
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.85002844
Short name T463
Test name
Test status
Simulation time 88558404247 ps
CPU time 2290.48 seconds
Started Aug 08 04:30:59 PM PDT 24
Finished Aug 08 05:09:10 PM PDT 24
Peak memory 289200 kb
Host smart-60e182d4-7874-4e56-aa73-15cc42ccd17e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85002844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_hand
ler_stress_all.85002844
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2735539078
Short name T659
Test name
Test status
Simulation time 106936182546 ps
CPU time 1631.81 seconds
Started Aug 08 04:31:15 PM PDT 24
Finished Aug 08 04:58:27 PM PDT 24
Peak memory 272716 kb
Host smart-d578f13b-cc6a-4de3-83ad-f92773a3bf62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735539078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2735539078
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.787401872
Short name T279
Test name
Test status
Simulation time 3266648943 ps
CPU time 179.4 seconds
Started Aug 08 04:30:59 PM PDT 24
Finished Aug 08 04:33:59 PM PDT 24
Peak memory 255564 kb
Host smart-fa8f81da-6bf5-4c63-8749-1eda9aaead0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78740
1872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.787401872
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3238650939
Short name T569
Test name
Test status
Simulation time 54769004 ps
CPU time 5.31 seconds
Started Aug 08 04:31:02 PM PDT 24
Finished Aug 08 04:31:08 PM PDT 24
Peak memory 247672 kb
Host smart-a3de3ea5-17d9-4c55-9c3a-a8fc3f724ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32386
50939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3238650939
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3662568932
Short name T542
Test name
Test status
Simulation time 37208541100 ps
CPU time 1665.63 seconds
Started Aug 08 04:31:12 PM PDT 24
Finished Aug 08 04:58:58 PM PDT 24
Peak memory 272080 kb
Host smart-2e880393-a735-45dc-97f2-88b3855f8a4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662568932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3662568932
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1320836196
Short name T230
Test name
Test status
Simulation time 5356798549 ps
CPU time 571.11 seconds
Started Aug 08 04:31:13 PM PDT 24
Finished Aug 08 04:40:44 PM PDT 24
Peak memory 272236 kb
Host smart-309a014c-8f5e-4056-b3f0-c1c09ca961ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320836196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1320836196
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1879872239
Short name T503
Test name
Test status
Simulation time 35131294076 ps
CPU time 370.13 seconds
Started Aug 08 04:31:11 PM PDT 24
Finished Aug 08 04:37:22 PM PDT 24
Peak memory 248204 kb
Host smart-78650a98-81bc-4f0a-a934-af6d08dfd9a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879872239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1879872239
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2931004548
Short name T581
Test name
Test status
Simulation time 812994044 ps
CPU time 46.63 seconds
Started Aug 08 04:30:59 PM PDT 24
Finished Aug 08 04:31:46 PM PDT 24
Peak memory 256028 kb
Host smart-3b1a0ee2-3f79-40a1-b28d-24a1a93c3a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29310
04548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2931004548
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1130846552
Short name T437
Test name
Test status
Simulation time 50923415 ps
CPU time 2.69 seconds
Started Aug 08 04:31:03 PM PDT 24
Finished Aug 08 04:31:06 PM PDT 24
Peak memory 239348 kb
Host smart-85185ded-0ad8-42ee-b782-6c1b3afa554d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11308
46552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1130846552
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1661062997
Short name T547
Test name
Test status
Simulation time 1301122769 ps
CPU time 37.73 seconds
Started Aug 08 04:31:00 PM PDT 24
Finished Aug 08 04:31:38 PM PDT 24
Peak memory 248152 kb
Host smart-560d5176-8781-47da-8e63-de9a93afaa52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16610
62997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1661062997
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1230557684
Short name T432
Test name
Test status
Simulation time 72551939 ps
CPU time 5.51 seconds
Started Aug 08 04:30:58 PM PDT 24
Finished Aug 08 04:31:03 PM PDT 24
Peak memory 250284 kb
Host smart-3814c3f6-a683-441c-b51d-b87a23386899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12305
57684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1230557684
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2849278
Short name T84
Test name
Test status
Simulation time 178141454094 ps
CPU time 2498.62 seconds
Started Aug 08 04:32:22 PM PDT 24
Finished Aug 08 05:14:01 PM PDT 24
Peak memory 304500 kb
Host smart-ddc33ea7-11e3-4d39-a140-1c019eb444ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849278 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2849278
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.498289957
Short name T208
Test name
Test status
Simulation time 50199431812 ps
CPU time 2748.54 seconds
Started Aug 08 04:32:13 PM PDT 24
Finished Aug 08 05:18:02 PM PDT 24
Peak memory 287700 kb
Host smart-86a2d162-2040-4169-a5c0-8ab518c4cb6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498289957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.498289957
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3178994353
Short name T608
Test name
Test status
Simulation time 29658028 ps
CPU time 2.83 seconds
Started Aug 08 04:31:11 PM PDT 24
Finished Aug 08 04:31:14 PM PDT 24
Peak memory 239064 kb
Host smart-ca047c78-e26b-4b15-8c34-7afa342dcd58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31789
94353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3178994353
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3703121742
Short name T541
Test name
Test status
Simulation time 1163223483 ps
CPU time 23.99 seconds
Started Aug 08 04:31:11 PM PDT 24
Finished Aug 08 04:31:35 PM PDT 24
Peak memory 255872 kb
Host smart-c6d2e568-a9d2-4172-bcbf-366aee7c7345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37031
21742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3703121742
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.896750323
Short name T335
Test name
Test status
Simulation time 176506916636 ps
CPU time 2421.91 seconds
Started Aug 08 04:31:13 PM PDT 24
Finished Aug 08 05:11:35 PM PDT 24
Peak memory 272372 kb
Host smart-88a80d79-dad7-4064-8ba6-35978206ca06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896750323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.896750323
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2804454678
Short name T654
Test name
Test status
Simulation time 24551068923 ps
CPU time 906.12 seconds
Started Aug 08 04:32:21 PM PDT 24
Finished Aug 08 04:47:28 PM PDT 24
Peak memory 272460 kb
Host smart-c46b2a1f-f31f-4b77-ba94-b5449a8c4492
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804454678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2804454678
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.934708654
Short name T207
Test name
Test status
Simulation time 9645927830 ps
CPU time 378.29 seconds
Started Aug 08 04:31:13 PM PDT 24
Finished Aug 08 04:37:31 PM PDT 24
Peak memory 256368 kb
Host smart-01a334c8-ee6c-44ed-ae6a-1e2c55fccd41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934708654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.934708654
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2622772292
Short name T415
Test name
Test status
Simulation time 1476782211 ps
CPU time 55.23 seconds
Started Aug 08 04:31:12 PM PDT 24
Finished Aug 08 04:32:08 PM PDT 24
Peak memory 248564 kb
Host smart-bb5926ef-1ee4-4bff-bb3b-6419d5234af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26227
72292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2622772292
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.399615578
Short name T495
Test name
Test status
Simulation time 922564995 ps
CPU time 22.22 seconds
Started Aug 08 04:31:12 PM PDT 24
Finished Aug 08 04:31:35 PM PDT 24
Peak memory 247500 kb
Host smart-2036878e-fd96-4ccf-8f99-776c10df28a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39961
5578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.399615578
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1918696506
Short name T76
Test name
Test status
Simulation time 136631398 ps
CPU time 18.35 seconds
Started Aug 08 04:31:12 PM PDT 24
Finished Aug 08 04:31:31 PM PDT 24
Peak memory 247576 kb
Host smart-e6b6887c-c6a0-464f-a369-4e51d4d4c045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19186
96506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1918696506
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1999584282
Short name T480
Test name
Test status
Simulation time 430871494 ps
CPU time 7.72 seconds
Started Aug 08 04:31:12 PM PDT 24
Finished Aug 08 04:31:19 PM PDT 24
Peak memory 250972 kb
Host smart-fc0f4aef-06b1-4ab5-b439-59f66f0d7a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19995
84282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1999584282
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2758441639
Short name T428
Test name
Test status
Simulation time 161991926971 ps
CPU time 2682.97 seconds
Started Aug 08 04:31:14 PM PDT 24
Finished Aug 08 05:15:57 PM PDT 24
Peak memory 289024 kb
Host smart-a874fdca-fac9-45fc-bc93-5145717e189e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758441639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2758441639
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.404905467
Short name T180
Test name
Test status
Simulation time 26232921233 ps
CPU time 1434.63 seconds
Started Aug 08 04:31:14 PM PDT 24
Finished Aug 08 04:55:09 PM PDT 24
Peak memory 286900 kb
Host smart-42641a5b-50ee-4bd9-87e2-5c02db850b9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404905467 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.404905467
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2550623115
Short name T477
Test name
Test status
Simulation time 164909446762 ps
CPU time 2682.41 seconds
Started Aug 08 04:31:12 PM PDT 24
Finished Aug 08 05:15:54 PM PDT 24
Peak memory 280952 kb
Host smart-72f3690a-a70f-48aa-96aa-2f09fbfe61ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550623115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2550623115
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3079180167
Short name T645
Test name
Test status
Simulation time 975242998 ps
CPU time 81.54 seconds
Started Aug 08 04:31:13 PM PDT 24
Finished Aug 08 04:32:34 PM PDT 24
Peak memory 256244 kb
Host smart-8d8beddc-114c-4736-9153-1859bc5bd76b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30791
80167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3079180167
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.4251694806
Short name T376
Test name
Test status
Simulation time 1351443720 ps
CPU time 28.89 seconds
Started Aug 08 04:31:14 PM PDT 24
Finished Aug 08 04:31:43 PM PDT 24
Peak memory 248016 kb
Host smart-ba3a9034-bb1f-42f9-bcfa-746237ebc571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42516
94806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.4251694806
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2036081280
Short name T323
Test name
Test status
Simulation time 19372825470 ps
CPU time 1187.68 seconds
Started Aug 08 04:31:11 PM PDT 24
Finished Aug 08 04:50:59 PM PDT 24
Peak memory 271968 kb
Host smart-584b6e41-e434-4a81-9278-e546c96d4e4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036081280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2036081280
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2227812772
Short name T102
Test name
Test status
Simulation time 121087714571 ps
CPU time 1652.77 seconds
Started Aug 08 04:31:18 PM PDT 24
Finished Aug 08 04:58:51 PM PDT 24
Peak memory 284364 kb
Host smart-c272596d-b872-4153-9fd7-a765780fc4b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227812772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2227812772
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3951456611
Short name T657
Test name
Test status
Simulation time 63080170487 ps
CPU time 602.45 seconds
Started Aug 08 04:31:13 PM PDT 24
Finished Aug 08 04:41:16 PM PDT 24
Peak memory 256360 kb
Host smart-ff51c63e-c33d-42b1-8bf5-05019a0c19a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951456611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3951456611
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.4150399716
Short name T10
Test name
Test status
Simulation time 343806029 ps
CPU time 18.5 seconds
Started Aug 08 04:31:12 PM PDT 24
Finished Aug 08 04:31:31 PM PDT 24
Peak memory 255316 kb
Host smart-5844abf3-7e3e-4191-80ba-b72af400dfc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41503
99716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.4150399716
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.4133934885
Short name T469
Test name
Test status
Simulation time 1813429444 ps
CPU time 55.85 seconds
Started Aug 08 04:31:12 PM PDT 24
Finished Aug 08 04:32:09 PM PDT 24
Peak memory 255116 kb
Host smart-f47cb820-0413-49c8-8269-8ec6f8905f9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41339
34885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.4133934885
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.558069703
Short name T77
Test name
Test status
Simulation time 727298501 ps
CPU time 52.65 seconds
Started Aug 08 04:31:11 PM PDT 24
Finished Aug 08 04:32:04 PM PDT 24
Peak memory 255352 kb
Host smart-56b1a57b-416e-4cc7-abf3-2628de46dec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55806
9703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.558069703
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.326230867
Short name T408
Test name
Test status
Simulation time 1032722203883 ps
CPU time 3444.46 seconds
Started Aug 08 04:31:12 PM PDT 24
Finished Aug 08 05:28:37 PM PDT 24
Peak memory 297492 kb
Host smart-5d068a6e-937d-4a7f-ad2d-8459f7fcd2e7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326230867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_han
dler_stress_all.326230867
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3721949081
Short name T687
Test name
Test status
Simulation time 5598252553 ps
CPU time 783.02 seconds
Started Aug 08 04:29:50 PM PDT 24
Finished Aug 08 04:42:53 PM PDT 24
Peak memory 265552 kb
Host smart-707fb598-dec6-45e5-a43c-3837fab9d838
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721949081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3721949081
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2236477516
Short name T471
Test name
Test status
Simulation time 763219106 ps
CPU time 11.57 seconds
Started Aug 08 04:29:45 PM PDT 24
Finished Aug 08 04:29:56 PM PDT 24
Peak memory 248160 kb
Host smart-93913c8d-2db6-49aa-8ab3-4f1997b2b1ec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2236477516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2236477516
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.740024484
Short name T564
Test name
Test status
Simulation time 1159827110 ps
CPU time 27.41 seconds
Started Aug 08 04:29:53 PM PDT 24
Finished Aug 08 04:30:21 PM PDT 24
Peak memory 255900 kb
Host smart-c87872f7-a039-47b1-ad91-e14e83c0d92e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74002
4484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.740024484
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2353914945
Short name T494
Test name
Test status
Simulation time 705026860 ps
CPU time 40.97 seconds
Started Aug 08 04:29:42 PM PDT 24
Finished Aug 08 04:30:23 PM PDT 24
Peak memory 248084 kb
Host smart-6ee8a5c7-4e65-4811-88e9-ca1117c56bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23539
14945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2353914945
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1629614968
Short name T586
Test name
Test status
Simulation time 41867560220 ps
CPU time 2454.32 seconds
Started Aug 08 04:29:38 PM PDT 24
Finished Aug 08 05:10:33 PM PDT 24
Peak memory 272140 kb
Host smart-2312ab51-a996-4376-a726-2ce5b5dec22c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629614968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1629614968
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.454008009
Short name T67
Test name
Test status
Simulation time 100342954530 ps
CPU time 1548.6 seconds
Started Aug 08 04:29:38 PM PDT 24
Finished Aug 08 04:55:26 PM PDT 24
Peak memory 281728 kb
Host smart-288bfdbd-e402-4df1-b1df-44830d527fc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454008009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.454008009
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2022485460
Short name T306
Test name
Test status
Simulation time 24757433229 ps
CPU time 260.4 seconds
Started Aug 08 04:29:36 PM PDT 24
Finished Aug 08 04:33:56 PM PDT 24
Peak memory 247980 kb
Host smart-691370e0-bcc9-4b92-b90b-d445ddbd86bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022485460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2022485460
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3647892301
Short name T58
Test name
Test status
Simulation time 444704816 ps
CPU time 35.03 seconds
Started Aug 08 04:29:51 PM PDT 24
Finished Aug 08 04:30:26 PM PDT 24
Peak memory 248212 kb
Host smart-ce3c1f75-4102-4c5d-9eca-5904c7b65054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36478
92301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3647892301
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1125548330
Short name T98
Test name
Test status
Simulation time 271933631 ps
CPU time 9.12 seconds
Started Aug 08 04:29:51 PM PDT 24
Finished Aug 08 04:30:00 PM PDT 24
Peak memory 248100 kb
Host smart-cbf6b60a-52af-42a0-9923-d4fccf644059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11255
48330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1125548330
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2380827796
Short name T33
Test name
Test status
Simulation time 345119422 ps
CPU time 18.56 seconds
Started Aug 08 04:29:36 PM PDT 24
Finished Aug 08 04:29:55 PM PDT 24
Peak memory 272864 kb
Host smart-54257f74-08c8-48f4-aab8-21c256bf9f9f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2380827796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2380827796
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2968128414
Short name T220
Test name
Test status
Simulation time 225808173 ps
CPU time 22.63 seconds
Started Aug 08 04:29:44 PM PDT 24
Finished Aug 08 04:30:06 PM PDT 24
Peak memory 255672 kb
Host smart-35be27a2-febd-4e13-9065-3e42414014da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29681
28414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2968128414
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1543074692
Short name T643
Test name
Test status
Simulation time 927924511 ps
CPU time 36.37 seconds
Started Aug 08 04:29:40 PM PDT 24
Finished Aug 08 04:30:17 PM PDT 24
Peak memory 255708 kb
Host smart-170ce78f-31fe-4325-99dc-b496ed7e7452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15430
74692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1543074692
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3115344576
Short name T418
Test name
Test status
Simulation time 72439542287 ps
CPU time 1572.49 seconds
Started Aug 08 04:29:49 PM PDT 24
Finished Aug 08 04:56:02 PM PDT 24
Peak memory 305344 kb
Host smart-0bcbdf45-f82e-4e8b-a315-daf0ec45a905
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115344576 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3115344576
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3751675861
Short name T482
Test name
Test status
Simulation time 28736135460 ps
CPU time 1460.84 seconds
Started Aug 08 04:31:16 PM PDT 24
Finished Aug 08 04:55:37 PM PDT 24
Peak memory 272080 kb
Host smart-5de6584c-628e-45d2-b0ad-b6682472afb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751675861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3751675861
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3630885778
Short name T650
Test name
Test status
Simulation time 454499050 ps
CPU time 10.87 seconds
Started Aug 08 04:31:13 PM PDT 24
Finished Aug 08 04:31:24 PM PDT 24
Peak memory 255464 kb
Host smart-6e64982f-2e51-46d8-8b55-1985930c4865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36308
85778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3630885778
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.452543943
Short name T85
Test name
Test status
Simulation time 2555620525 ps
CPU time 46.13 seconds
Started Aug 08 04:31:12 PM PDT 24
Finished Aug 08 04:31:59 PM PDT 24
Peak memory 248140 kb
Host smart-f00e5364-9651-4b9e-8ffe-535bc4434587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45254
3943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.452543943
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2557665670
Short name T38
Test name
Test status
Simulation time 16698173541 ps
CPU time 834.03 seconds
Started Aug 08 04:31:12 PM PDT 24
Finished Aug 08 04:45:07 PM PDT 24
Peak memory 267836 kb
Host smart-876750a9-1085-4221-93c1-39cde57f7b22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557665670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2557665670
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2797599368
Short name T283
Test name
Test status
Simulation time 234621292063 ps
CPU time 3115.61 seconds
Started Aug 08 04:31:14 PM PDT 24
Finished Aug 08 05:23:09 PM PDT 24
Peak memory 288304 kb
Host smart-00b4d294-5b9b-4d73-8efa-f385e2524f9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797599368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2797599368
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1890381725
Short name T285
Test name
Test status
Simulation time 4547127917 ps
CPU time 161.5 seconds
Started Aug 08 04:32:22 PM PDT 24
Finished Aug 08 04:35:03 PM PDT 24
Peak memory 254724 kb
Host smart-0fecdcfc-367b-485c-8cac-a89d3c7c160e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890381725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1890381725
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.625473654
Short name T576
Test name
Test status
Simulation time 265768410 ps
CPU time 25.23 seconds
Started Aug 08 04:31:14 PM PDT 24
Finished Aug 08 04:31:40 PM PDT 24
Peak memory 248200 kb
Host smart-22eff9c7-9afa-424e-a70a-afb3c57241ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62547
3654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.625473654
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2457274210
Short name T606
Test name
Test status
Simulation time 846172484 ps
CPU time 12.75 seconds
Started Aug 08 04:31:12 PM PDT 24
Finished Aug 08 04:31:25 PM PDT 24
Peak memory 247668 kb
Host smart-8d2fd266-8fb9-4226-b70f-1d2eeefef310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24572
74210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2457274210
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3795787728
Short name T512
Test name
Test status
Simulation time 606727857 ps
CPU time 21.54 seconds
Started Aug 08 04:31:15 PM PDT 24
Finished Aug 08 04:31:37 PM PDT 24
Peak memory 248104 kb
Host smart-a29b5e9e-9c1a-41c3-b981-c677a3d37a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37957
87728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3795787728
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.119343808
Short name T420
Test name
Test status
Simulation time 968220461 ps
CPU time 22.17 seconds
Started Aug 08 04:31:15 PM PDT 24
Finished Aug 08 04:31:37 PM PDT 24
Peak memory 255412 kb
Host smart-50170ad2-d9f6-4ae9-9f5f-48445981fa82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11934
3808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.119343808
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2629801218
Short name T268
Test name
Test status
Simulation time 12241730438 ps
CPU time 1187.18 seconds
Started Aug 08 04:31:13 PM PDT 24
Finished Aug 08 04:51:00 PM PDT 24
Peak memory 285776 kb
Host smart-2c8d0f2f-411e-4bb7-ae03-d5bababb47de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629801218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2629801218
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.1808932989
Short name T255
Test name
Test status
Simulation time 177980015066 ps
CPU time 9473.86 seconds
Started Aug 08 04:31:12 PM PDT 24
Finished Aug 08 07:09:07 PM PDT 24
Peak memory 387496 kb
Host smart-05f7268f-920f-4fdc-ba29-b09c096a4703
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808932989 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.1808932989
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.444974933
Short name T535
Test name
Test status
Simulation time 39222067082 ps
CPU time 2390.02 seconds
Started Aug 08 04:31:14 PM PDT 24
Finished Aug 08 05:11:04 PM PDT 24
Peak memory 272608 kb
Host smart-c14cd748-1031-4a82-aefb-ac7600a80a08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444974933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.444974933
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1135259920
Short name T492
Test name
Test status
Simulation time 10055669136 ps
CPU time 140.33 seconds
Started Aug 08 04:31:11 PM PDT 24
Finished Aug 08 04:33:32 PM PDT 24
Peak memory 255724 kb
Host smart-213460b0-e445-4225-970c-50fc108e20e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11352
59920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1135259920
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1286014913
Short name T602
Test name
Test status
Simulation time 111620439 ps
CPU time 11.32 seconds
Started Aug 08 04:31:12 PM PDT 24
Finished Aug 08 04:31:24 PM PDT 24
Peak memory 255208 kb
Host smart-0c5cf9c7-767e-49db-8d35-5a1c82097fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12860
14913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1286014913
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1267112472
Short name T672
Test name
Test status
Simulation time 8946223122 ps
CPU time 863.05 seconds
Started Aug 08 04:31:15 PM PDT 24
Finished Aug 08 04:45:38 PM PDT 24
Peak memory 272156 kb
Host smart-857124f0-fac6-4355-bb1f-1ee47b1b37ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267112472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1267112472
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1074448799
Short name T72
Test name
Test status
Simulation time 15480795330 ps
CPU time 1275.44 seconds
Started Aug 08 04:31:15 PM PDT 24
Finished Aug 08 04:52:30 PM PDT 24
Peak memory 288200 kb
Host smart-824ccc6c-28e4-4bb9-bdbb-2d5a1463f313
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074448799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1074448799
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2696338431
Short name T661
Test name
Test status
Simulation time 4737687808 ps
CPU time 180.27 seconds
Started Aug 08 04:31:14 PM PDT 24
Finished Aug 08 04:34:15 PM PDT 24
Peak memory 248188 kb
Host smart-91be0180-0f1d-43b2-a0bf-c6d6e8f7e07f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696338431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2696338431
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3084875748
Short name T506
Test name
Test status
Simulation time 627120934 ps
CPU time 42.89 seconds
Started Aug 08 04:31:14 PM PDT 24
Finished Aug 08 04:31:57 PM PDT 24
Peak memory 256308 kb
Host smart-6f60b448-8738-468c-9770-cff96723b29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30848
75748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3084875748
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1281951607
Short name T545
Test name
Test status
Simulation time 349002780 ps
CPU time 23.04 seconds
Started Aug 08 04:31:12 PM PDT 24
Finished Aug 08 04:31:35 PM PDT 24
Peak memory 247768 kb
Host smart-12c57337-5809-4824-936a-9cd615a6af12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12819
51607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1281951607
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1791141256
Short name T411
Test name
Test status
Simulation time 318793749 ps
CPU time 7.85 seconds
Started Aug 08 04:31:15 PM PDT 24
Finished Aug 08 04:31:23 PM PDT 24
Peak memory 250272 kb
Host smart-8b02f0ea-86c3-48f0-9dac-59d8d0b7c080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17911
41256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1791141256
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1263011210
Short name T451
Test name
Test status
Simulation time 842747916 ps
CPU time 14.6 seconds
Started Aug 08 04:31:13 PM PDT 24
Finished Aug 08 04:31:28 PM PDT 24
Peak memory 254740 kb
Host smart-cb75fdcc-a21f-4c1a-95bf-3f004f91617c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12630
11210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1263011210
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.4277037641
Short name T94
Test name
Test status
Simulation time 409694960782 ps
CPU time 3297.51 seconds
Started Aug 08 04:31:14 PM PDT 24
Finished Aug 08 05:26:12 PM PDT 24
Peak memory 304884 kb
Host smart-0baf6993-4efd-4b1e-9193-f5a4b63a786f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277037641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.4277037641
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1304911071
Short name T11
Test name
Test status
Simulation time 5502512539 ps
CPU time 114.35 seconds
Started Aug 08 04:31:12 PM PDT 24
Finished Aug 08 04:33:07 PM PDT 24
Peak memory 255852 kb
Host smart-3ecf3d4b-46f2-432d-873d-ef61d11fe939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13049
11071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1304911071
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3377199589
Short name T384
Test name
Test status
Simulation time 604825312 ps
CPU time 34.02 seconds
Started Aug 08 04:31:14 PM PDT 24
Finished Aug 08 04:31:48 PM PDT 24
Peak memory 248152 kb
Host smart-48214040-031f-4233-95da-7758bf273769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33771
99589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3377199589
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2592930456
Short name T317
Test name
Test status
Simulation time 22822672010 ps
CPU time 1313.28 seconds
Started Aug 08 04:31:29 PM PDT 24
Finished Aug 08 04:53:22 PM PDT 24
Peak memory 272740 kb
Host smart-ca35e3de-5c6b-44c2-9212-21ac0033b251
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592930456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2592930456
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3334943307
Short name T488
Test name
Test status
Simulation time 65496290665 ps
CPU time 2321.77 seconds
Started Aug 08 04:31:25 PM PDT 24
Finished Aug 08 05:10:07 PM PDT 24
Peak memory 288272 kb
Host smart-337bb404-598a-43e5-b469-884e995395b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334943307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3334943307
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2741813122
Short name T632
Test name
Test status
Simulation time 2772140723 ps
CPU time 113.23 seconds
Started Aug 08 04:31:27 PM PDT 24
Finished Aug 08 04:33:20 PM PDT 24
Peak memory 248180 kb
Host smart-bbdeab54-c125-46fd-904a-a8188e73e71d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741813122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2741813122
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3510794848
Short name T48
Test name
Test status
Simulation time 534716593 ps
CPU time 35.27 seconds
Started Aug 08 04:31:15 PM PDT 24
Finished Aug 08 04:31:50 PM PDT 24
Peak memory 255376 kb
Host smart-942c964f-3a80-4a7b-b904-3db028d2ab6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35107
94848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3510794848
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1633702293
Short name T356
Test name
Test status
Simulation time 2332626780 ps
CPU time 79.21 seconds
Started Aug 08 04:31:16 PM PDT 24
Finished Aug 08 04:32:35 PM PDT 24
Peak memory 247208 kb
Host smart-d476d16a-eb18-4830-9fa0-988b19ea16e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16337
02293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1633702293
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.819437116
Short name T699
Test name
Test status
Simulation time 168821984 ps
CPU time 4.4 seconds
Started Aug 08 04:31:29 PM PDT 24
Finished Aug 08 04:31:33 PM PDT 24
Peak memory 247512 kb
Host smart-2295f05e-3780-45b3-81ae-857ddc8f3e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81943
7116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.819437116
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2517061774
Short name T382
Test name
Test status
Simulation time 1305078425 ps
CPU time 18.18 seconds
Started Aug 08 04:31:15 PM PDT 24
Finished Aug 08 04:31:33 PM PDT 24
Peak memory 248384 kb
Host smart-a876b66b-60a9-43d3-821f-c79fca9b97aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25170
61774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2517061774
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1316972647
Short name T450
Test name
Test status
Simulation time 179686103626 ps
CPU time 3082.07 seconds
Started Aug 08 04:31:24 PM PDT 24
Finished Aug 08 05:22:46 PM PDT 24
Peak memory 288872 kb
Host smart-a59be1ab-36d4-495f-a61b-e887e6cb5de0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316972647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1316972647
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.39880746
Short name T270
Test name
Test status
Simulation time 940324803322 ps
CPU time 2633.32 seconds
Started Aug 08 04:31:31 PM PDT 24
Finished Aug 08 05:15:24 PM PDT 24
Peak memory 280876 kb
Host smart-e3a6f7b1-327b-4f12-8a17-c0a48384a5cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39880746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.39880746
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3964483791
Short name T466
Test name
Test status
Simulation time 4112858245 ps
CPU time 288.76 seconds
Started Aug 08 04:31:29 PM PDT 24
Finished Aug 08 04:36:18 PM PDT 24
Peak memory 256432 kb
Host smart-9987fa24-edf3-4f0b-a6b4-03bcdaeb2959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39644
83791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3964483791
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3516292890
Short name T499
Test name
Test status
Simulation time 560407979 ps
CPU time 19.98 seconds
Started Aug 08 04:31:21 PM PDT 24
Finished Aug 08 04:31:41 PM PDT 24
Peak memory 247600 kb
Host smart-b5bd358c-3d84-4420-b42d-2a8c125d8d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35162
92890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3516292890
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3068133672
Short name T272
Test name
Test status
Simulation time 22590356828 ps
CPU time 1363.02 seconds
Started Aug 08 04:31:25 PM PDT 24
Finished Aug 08 04:54:08 PM PDT 24
Peak memory 272740 kb
Host smart-c4cbbf32-f5c5-41f0-97a3-3ac81817762b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068133672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3068133672
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.19347844
Short name T566
Test name
Test status
Simulation time 15619152476 ps
CPU time 1309.6 seconds
Started Aug 08 04:31:24 PM PDT 24
Finished Aug 08 04:53:14 PM PDT 24
Peak memory 286864 kb
Host smart-1bdf1038-450b-4dc6-817e-80c14e634f51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19347844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.19347844
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2051290268
Short name T562
Test name
Test status
Simulation time 42313418609 ps
CPU time 424.42 seconds
Started Aug 08 04:31:26 PM PDT 24
Finished Aug 08 04:38:30 PM PDT 24
Peak memory 247168 kb
Host smart-95184df1-4e08-49c7-97ed-f1a3a74505f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051290268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2051290268
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1581105299
Short name T472
Test name
Test status
Simulation time 905743412 ps
CPU time 52.53 seconds
Started Aug 08 04:31:25 PM PDT 24
Finished Aug 08 04:32:17 PM PDT 24
Peak memory 255648 kb
Host smart-f88f119e-5ab4-4a8b-8991-476e4607912d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15811
05299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1581105299
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.759667389
Short name T511
Test name
Test status
Simulation time 283612318 ps
CPU time 4.88 seconds
Started Aug 08 04:31:30 PM PDT 24
Finished Aug 08 04:31:34 PM PDT 24
Peak memory 239512 kb
Host smart-743c40a1-1747-4940-802d-b988cb59741a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75966
7389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.759667389
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2421297911
Short name T259
Test name
Test status
Simulation time 814389398 ps
CPU time 15 seconds
Started Aug 08 04:31:26 PM PDT 24
Finished Aug 08 04:31:41 PM PDT 24
Peak memory 247576 kb
Host smart-09c23139-fb96-4b72-b7d0-f06f249fb611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24212
97911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2421297911
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1692812587
Short name T623
Test name
Test status
Simulation time 447275369 ps
CPU time 26.3 seconds
Started Aug 08 04:31:25 PM PDT 24
Finished Aug 08 04:31:52 PM PDT 24
Peak memory 256352 kb
Host smart-246ac5c7-99c3-493d-a6c0-fcd876eada72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16928
12587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1692812587
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3875077713
Short name T460
Test name
Test status
Simulation time 44310657431 ps
CPU time 1452.46 seconds
Started Aug 08 04:31:25 PM PDT 24
Finished Aug 08 04:55:37 PM PDT 24
Peak memory 272332 kb
Host smart-153883b1-d424-48ad-8aac-290329932db8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875077713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3875077713
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2952107095
Short name T565
Test name
Test status
Simulation time 3774428364 ps
CPU time 54.79 seconds
Started Aug 08 04:31:26 PM PDT 24
Finished Aug 08 04:32:21 PM PDT 24
Peak memory 256340 kb
Host smart-372d1cf7-9450-473c-90cd-fdd57b9d729b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29521
07095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2952107095
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1041403085
Short name T673
Test name
Test status
Simulation time 1403367580 ps
CPU time 33.6 seconds
Started Aug 08 04:31:27 PM PDT 24
Finished Aug 08 04:32:01 PM PDT 24
Peak memory 248136 kb
Host smart-af963dfb-edda-47db-b989-7e61e959711b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10414
03085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1041403085
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2644379580
Short name T396
Test name
Test status
Simulation time 48837182923 ps
CPU time 2997.45 seconds
Started Aug 08 04:31:23 PM PDT 24
Finished Aug 08 05:21:21 PM PDT 24
Peak memory 287804 kb
Host smart-67839b58-2086-4b9a-9c9c-50936699b849
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644379580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2644379580
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.361576681
Short name T40
Test name
Test status
Simulation time 25016537121 ps
CPU time 245.26 seconds
Started Aug 08 04:31:25 PM PDT 24
Finished Aug 08 04:35:30 PM PDT 24
Peak memory 248192 kb
Host smart-f0f4b1f9-627f-4c6c-87e3-ee8d1660b408
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361576681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.361576681
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2302621310
Short name T693
Test name
Test status
Simulation time 2086161295 ps
CPU time 33.56 seconds
Started Aug 08 04:31:24 PM PDT 24
Finished Aug 08 04:31:57 PM PDT 24
Peak memory 255488 kb
Host smart-95641912-acea-4b20-8ac8-4022f53ba643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23026
21310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2302621310
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1378868693
Short name T468
Test name
Test status
Simulation time 773028041 ps
CPU time 42.81 seconds
Started Aug 08 04:31:24 PM PDT 24
Finished Aug 08 04:32:07 PM PDT 24
Peak memory 256484 kb
Host smart-6eab947e-46cc-4e57-8e78-4dd253f1fa0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13788
68693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1378868693
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2696895874
Short name T215
Test name
Test status
Simulation time 643851902 ps
CPU time 53.14 seconds
Started Aug 08 04:31:26 PM PDT 24
Finished Aug 08 04:32:19 PM PDT 24
Peak memory 248232 kb
Host smart-1df09531-520b-4f5f-8b83-d4350064b3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26968
95874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2696895874
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.4110060102
Short name T536
Test name
Test status
Simulation time 90653000 ps
CPU time 7.47 seconds
Started Aug 08 04:31:25 PM PDT 24
Finished Aug 08 04:31:32 PM PDT 24
Peak memory 248040 kb
Host smart-20302762-85a8-405b-b6a5-4772988ba1c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41100
60102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.4110060102
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1081407472
Short name T286
Test name
Test status
Simulation time 1257526928 ps
CPU time 106.98 seconds
Started Aug 08 04:31:25 PM PDT 24
Finished Aug 08 04:33:12 PM PDT 24
Peak memory 251148 kb
Host smart-bba4fd4e-d76e-4a09-a1dd-8e2aad1904e4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081407472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1081407472
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.608774160
Short name T241
Test name
Test status
Simulation time 65374055042 ps
CPU time 5735.37 seconds
Started Aug 08 04:31:29 PM PDT 24
Finished Aug 08 06:07:05 PM PDT 24
Peak memory 321420 kb
Host smart-fe014ba8-9b47-4989-aba5-4f8b0d124090
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608774160 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.608774160
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2044248642
Short name T99
Test name
Test status
Simulation time 42347338959 ps
CPU time 2284.6 seconds
Started Aug 08 04:31:25 PM PDT 24
Finished Aug 08 05:09:30 PM PDT 24
Peak memory 280932 kb
Host smart-4e6c319d-560c-4806-851a-95761e739ef3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044248642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2044248642
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.882973775
Short name T642
Test name
Test status
Simulation time 23502224520 ps
CPU time 182.43 seconds
Started Aug 08 04:31:29 PM PDT 24
Finished Aug 08 04:34:32 PM PDT 24
Peak memory 255488 kb
Host smart-f277036b-0a7d-4136-aed0-42158dec1d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88297
3775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.882973775
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2166693116
Short name T489
Test name
Test status
Simulation time 177389936 ps
CPU time 19.88 seconds
Started Aug 08 04:31:27 PM PDT 24
Finished Aug 08 04:31:47 PM PDT 24
Peak memory 255860 kb
Host smart-a2aba1c2-fec0-4665-adf7-6d1da4a4b5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21666
93116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2166693116
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3093591160
Short name T225
Test name
Test status
Simulation time 47952036805 ps
CPU time 945.79 seconds
Started Aug 08 04:31:24 PM PDT 24
Finished Aug 08 04:47:10 PM PDT 24
Peak memory 272492 kb
Host smart-6cd2540c-6323-474b-bbe7-aef5fe0e4025
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093591160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3093591160
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3475082051
Short name T19
Test name
Test status
Simulation time 5622677324 ps
CPU time 652.47 seconds
Started Aug 08 04:31:25 PM PDT 24
Finished Aug 08 04:42:18 PM PDT 24
Peak memory 272196 kb
Host smart-df3cd094-a856-4310-8af1-ca9a24c6a4ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475082051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3475082051
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1776298285
Short name T80
Test name
Test status
Simulation time 1308044822 ps
CPU time 76.27 seconds
Started Aug 08 04:31:24 PM PDT 24
Finished Aug 08 04:32:41 PM PDT 24
Peak memory 255568 kb
Host smart-c5bbd286-00ec-4a47-8c9a-f4bdd37e1c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17762
98285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1776298285
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3799028411
Short name T702
Test name
Test status
Simulation time 189757239 ps
CPU time 22.55 seconds
Started Aug 08 04:31:26 PM PDT 24
Finished Aug 08 04:31:48 PM PDT 24
Peak memory 247544 kb
Host smart-2e238fa7-b4fe-4f11-a19f-70aafad03f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37990
28411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3799028411
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.843204474
Short name T696
Test name
Test status
Simulation time 349539138 ps
CPU time 4.82 seconds
Started Aug 08 04:31:27 PM PDT 24
Finished Aug 08 04:31:32 PM PDT 24
Peak memory 248164 kb
Host smart-124b6e9b-a8ef-46c4-81cc-5f47edded102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84320
4474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.843204474
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1174690406
Short name T74
Test name
Test status
Simulation time 138178738 ps
CPU time 7.87 seconds
Started Aug 08 04:31:24 PM PDT 24
Finished Aug 08 04:31:32 PM PDT 24
Peak memory 253244 kb
Host smart-84f6e8d2-5d2f-4683-a05b-e6338c4a3136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11746
90406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1174690406
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.4095371634
Short name T257
Test name
Test status
Simulation time 55075748748 ps
CPU time 3073.8 seconds
Started Aug 08 04:31:41 PM PDT 24
Finished Aug 08 05:22:55 PM PDT 24
Peak memory 288236 kb
Host smart-b2c3d8e3-e991-44f6-bf1d-5ee51f32d61d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095371634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.4095371634
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2275400741
Short name T404
Test name
Test status
Simulation time 167956290905 ps
CPU time 2283.49 seconds
Started Aug 08 04:31:47 PM PDT 24
Finished Aug 08 05:09:51 PM PDT 24
Peak memory 285524 kb
Host smart-a44e203e-6a66-4e24-ad91-f3c592ed99c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275400741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2275400741
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1765256072
Short name T560
Test name
Test status
Simulation time 17306335239 ps
CPU time 258.84 seconds
Started Aug 08 04:31:38 PM PDT 24
Finished Aug 08 04:35:57 PM PDT 24
Peak memory 256340 kb
Host smart-71d9a4f9-5971-4906-8084-278ff6a18e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17652
56072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1765256072
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.817395752
Short name T41
Test name
Test status
Simulation time 1072682707 ps
CPU time 60.29 seconds
Started Aug 08 04:31:38 PM PDT 24
Finished Aug 08 04:32:38 PM PDT 24
Peak memory 256032 kb
Host smart-fc75c4c5-9d0b-4823-832a-b149112306b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81739
5752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.817395752
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1822510351
Short name T326
Test name
Test status
Simulation time 76297200868 ps
CPU time 2435.86 seconds
Started Aug 08 04:31:37 PM PDT 24
Finished Aug 08 05:12:14 PM PDT 24
Peak memory 288192 kb
Host smart-78ebe15e-0ea0-467b-ba29-8f1c0fd17dd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822510351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1822510351
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.863448993
Short name T692
Test name
Test status
Simulation time 30099466891 ps
CPU time 1985.37 seconds
Started Aug 08 04:31:38 PM PDT 24
Finished Aug 08 05:04:44 PM PDT 24
Peak memory 281008 kb
Host smart-bd310b1b-5fe0-4d0b-93bf-242be13d6dea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863448993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.863448993
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.4072292333
Short name T505
Test name
Test status
Simulation time 3674931528 ps
CPU time 150.44 seconds
Started Aug 08 04:31:40 PM PDT 24
Finished Aug 08 04:34:10 PM PDT 24
Peak memory 248184 kb
Host smart-ca2cb493-193f-47b2-8d77-1e04b476b137
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072292333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.4072292333
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1506314865
Short name T479
Test name
Test status
Simulation time 779232608 ps
CPU time 34.52 seconds
Started Aug 08 04:31:37 PM PDT 24
Finished Aug 08 04:32:12 PM PDT 24
Peak memory 255628 kb
Host smart-81a97819-bf28-4b8b-bfa1-c22cb22c5500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15063
14865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1506314865
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1578163050
Short name T358
Test name
Test status
Simulation time 36837850 ps
CPU time 4.71 seconds
Started Aug 08 04:31:38 PM PDT 24
Finished Aug 08 04:31:42 PM PDT 24
Peak memory 239308 kb
Host smart-0f98568c-1e39-4568-ace1-f2e439c01985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15781
63050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1578163050
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3453992609
Short name T444
Test name
Test status
Simulation time 286558532 ps
CPU time 9.87 seconds
Started Aug 08 04:31:37 PM PDT 24
Finished Aug 08 04:31:47 PM PDT 24
Peak memory 247760 kb
Host smart-eb148923-0dba-437b-8f14-12c45caec8dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34539
92609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3453992609
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2073610901
Short name T577
Test name
Test status
Simulation time 1308086824 ps
CPU time 78.35 seconds
Started Aug 08 04:31:38 PM PDT 24
Finished Aug 08 04:32:57 PM PDT 24
Peak memory 256288 kb
Host smart-32c17062-e27a-4265-a812-129dc8b7573c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20736
10901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2073610901
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.934278881
Short name T525
Test name
Test status
Simulation time 231934251869 ps
CPU time 1269.74 seconds
Started Aug 08 04:31:40 PM PDT 24
Finished Aug 08 04:52:50 PM PDT 24
Peak memory 288832 kb
Host smart-cff5ebc2-be13-4a11-9577-2a91d0246d97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934278881 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.934278881
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1086394582
Short name T28
Test name
Test status
Simulation time 73260961338 ps
CPU time 711.16 seconds
Started Aug 08 04:31:38 PM PDT 24
Finished Aug 08 04:43:29 PM PDT 24
Peak memory 266556 kb
Host smart-068fb021-568a-439c-aa8f-6d11211d37e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086394582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1086394582
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1122786655
Short name T366
Test name
Test status
Simulation time 1637467792 ps
CPU time 58.92 seconds
Started Aug 08 04:31:36 PM PDT 24
Finished Aug 08 04:32:35 PM PDT 24
Peak memory 255784 kb
Host smart-1d55a1bd-889a-4a04-8912-99a709d9279d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11227
86655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1122786655
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1437165816
Short name T427
Test name
Test status
Simulation time 667858150 ps
CPU time 26.97 seconds
Started Aug 08 04:31:37 PM PDT 24
Finished Aug 08 04:32:04 PM PDT 24
Peak memory 248076 kb
Host smart-a07796df-738d-40cb-bcc5-7e0520cba928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14371
65816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1437165816
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3825897664
Short name T329
Test name
Test status
Simulation time 252357122715 ps
CPU time 3540.53 seconds
Started Aug 08 04:31:38 PM PDT 24
Finished Aug 08 05:30:39 PM PDT 24
Peak memory 288328 kb
Host smart-008d3729-0456-4a58-b011-185792e56fbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825897664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3825897664
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.538239828
Short name T610
Test name
Test status
Simulation time 72574251339 ps
CPU time 998.66 seconds
Started Aug 08 04:31:47 PM PDT 24
Finished Aug 08 04:48:26 PM PDT 24
Peak memory 272396 kb
Host smart-a52691f6-d3a3-48bb-b567-94248fcb43db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538239828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.538239828
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.869903148
Short name T666
Test name
Test status
Simulation time 32506861091 ps
CPU time 319.89 seconds
Started Aug 08 04:31:38 PM PDT 24
Finished Aug 08 04:36:58 PM PDT 24
Peak memory 247096 kb
Host smart-561819c8-0562-462e-81b4-438f6ece22ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869903148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.869903148
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2764277175
Short name T354
Test name
Test status
Simulation time 512094927 ps
CPU time 9.59 seconds
Started Aug 08 04:31:37 PM PDT 24
Finished Aug 08 04:31:47 PM PDT 24
Peak memory 248216 kb
Host smart-4dbce1dc-ff83-4518-8ad1-04f3aad897c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27642
77175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2764277175
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1983911872
Short name T628
Test name
Test status
Simulation time 3220072174 ps
CPU time 34.47 seconds
Started Aug 08 04:31:40 PM PDT 24
Finished Aug 08 04:32:15 PM PDT 24
Peak memory 248624 kb
Host smart-dcb3da99-1cbe-4f5f-b000-5293ed044e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19839
11872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1983911872
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2955826374
Short name T458
Test name
Test status
Simulation time 387806778 ps
CPU time 31.44 seconds
Started Aug 08 04:31:38 PM PDT 24
Finished Aug 08 04:32:09 PM PDT 24
Peak memory 255664 kb
Host smart-0f9fb867-e4e9-4969-96c5-fe38f1c25109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29558
26374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2955826374
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.888702460
Short name T667
Test name
Test status
Simulation time 397390738 ps
CPU time 22.89 seconds
Started Aug 08 04:31:37 PM PDT 24
Finished Aug 08 04:32:00 PM PDT 24
Peak memory 256320 kb
Host smart-0af60561-1b31-4502-ac62-98697e0402b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88870
2460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.888702460
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1060640499
Short name T276
Test name
Test status
Simulation time 16297272004 ps
CPU time 862.12 seconds
Started Aug 08 04:31:38 PM PDT 24
Finished Aug 08 04:46:01 PM PDT 24
Peak memory 272796 kb
Host smart-cb953123-b1f1-4646-b235-43c277e0e219
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060640499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1060640499
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1235749092
Short name T228
Test name
Test status
Simulation time 32700658947 ps
CPU time 1853.82 seconds
Started Aug 08 04:31:45 PM PDT 24
Finished Aug 08 05:02:39 PM PDT 24
Peak memory 272428 kb
Host smart-d8be1712-22d7-4b3c-85e2-d8153461f104
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235749092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1235749092
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3861157788
Short name T538
Test name
Test status
Simulation time 469629131 ps
CPU time 8.99 seconds
Started Aug 08 04:31:47 PM PDT 24
Finished Aug 08 04:31:56 PM PDT 24
Peak memory 252500 kb
Host smart-c733d313-cfe0-4e10-a23e-28f5fc106a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38611
57788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3861157788
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.477974578
Short name T435
Test name
Test status
Simulation time 4971176660 ps
CPU time 33.18 seconds
Started Aug 08 04:31:38 PM PDT 24
Finished Aug 08 04:32:11 PM PDT 24
Peak memory 248176 kb
Host smart-1176d1f3-470c-41a9-bd4e-5b2a701a4e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47797
4578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.477974578
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.4188679958
Short name T621
Test name
Test status
Simulation time 131453231874 ps
CPU time 1746.97 seconds
Started Aug 08 04:31:38 PM PDT 24
Finished Aug 08 05:00:45 PM PDT 24
Peak memory 272216 kb
Host smart-b5787642-6b1e-4475-b41a-d330bc231fb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188679958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.4188679958
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2971590517
Short name T106
Test name
Test status
Simulation time 55932915448 ps
CPU time 901.23 seconds
Started Aug 08 04:31:38 PM PDT 24
Finished Aug 08 04:46:40 PM PDT 24
Peak memory 272844 kb
Host smart-b69393a1-a1ca-4e59-9604-328e8aa2642c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971590517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2971590517
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2146323670
Short name T579
Test name
Test status
Simulation time 1044218862 ps
CPU time 52.35 seconds
Started Aug 08 04:31:38 PM PDT 24
Finished Aug 08 04:32:30 PM PDT 24
Peak memory 248188 kb
Host smart-785071a4-a507-44a4-8185-7ba2e67355f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21463
23670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2146323670
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.647270553
Short name T35
Test name
Test status
Simulation time 1237467809 ps
CPU time 21.18 seconds
Started Aug 08 04:31:39 PM PDT 24
Finished Aug 08 04:32:00 PM PDT 24
Peak memory 247604 kb
Host smart-446e1e03-8256-4bfd-9cb1-5a36cb5f2371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64727
0553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.647270553
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.243051593
Short name T467
Test name
Test status
Simulation time 188123374 ps
CPU time 19.24 seconds
Started Aug 08 04:31:47 PM PDT 24
Finished Aug 08 04:32:06 PM PDT 24
Peak memory 248052 kb
Host smart-66c54edc-203c-4ab2-b65c-6c7ac164ced0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24305
1593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.243051593
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2081106657
Short name T45
Test name
Test status
Simulation time 503050972 ps
CPU time 22.62 seconds
Started Aug 08 04:31:38 PM PDT 24
Finished Aug 08 04:32:01 PM PDT 24
Peak memory 256392 kb
Host smart-7e9564df-e80d-4800-a074-067a16435ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20811
06657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2081106657
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1230695553
Short name T633
Test name
Test status
Simulation time 19603498612 ps
CPU time 1685.53 seconds
Started Aug 08 04:31:40 PM PDT 24
Finished Aug 08 04:59:46 PM PDT 24
Peak memory 305152 kb
Host smart-45d93026-229b-45c0-92d7-e6381e89425f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230695553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1230695553
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.456647570
Short name T651
Test name
Test status
Simulation time 52770840545 ps
CPU time 944.33 seconds
Started Aug 08 04:31:52 PM PDT 24
Finished Aug 08 04:47:36 PM PDT 24
Peak memory 272788 kb
Host smart-6e5aa0ff-3cfb-4cee-be18-748a1abab2cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456647570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.456647570
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.481394541
Short name T520
Test name
Test status
Simulation time 2211189559 ps
CPU time 123.28 seconds
Started Aug 08 04:31:50 PM PDT 24
Finished Aug 08 04:33:53 PM PDT 24
Peak memory 256368 kb
Host smart-acef9137-c7da-4784-8680-94cad19d9cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48139
4541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.481394541
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3850918843
Short name T86
Test name
Test status
Simulation time 666590343 ps
CPU time 43.42 seconds
Started Aug 08 04:31:51 PM PDT 24
Finished Aug 08 04:32:34 PM PDT 24
Peak memory 248168 kb
Host smart-bb941712-f80a-48e9-925b-03af54f33e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38509
18843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3850918843
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.955921039
Short name T464
Test name
Test status
Simulation time 20931419464 ps
CPU time 867.45 seconds
Started Aug 08 04:31:49 PM PDT 24
Finished Aug 08 04:46:16 PM PDT 24
Peak memory 272504 kb
Host smart-0851ef72-b9b3-4782-a5cf-618fc371189b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955921039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.955921039
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.184961327
Short name T218
Test name
Test status
Simulation time 13411264896 ps
CPU time 271.79 seconds
Started Aug 08 04:31:50 PM PDT 24
Finished Aug 08 04:36:22 PM PDT 24
Peak memory 247212 kb
Host smart-c20173c6-6353-4acc-92b4-fab2c5b741b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184961327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.184961327
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.556229261
Short name T493
Test name
Test status
Simulation time 1020620130 ps
CPU time 65.11 seconds
Started Aug 08 04:31:50 PM PDT 24
Finished Aug 08 04:32:55 PM PDT 24
Peak memory 255528 kb
Host smart-551c78cd-830c-48b1-950d-12c4150f1235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55622
9261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.556229261
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.70735742
Short name T679
Test name
Test status
Simulation time 883157619 ps
CPU time 13.52 seconds
Started Aug 08 04:31:51 PM PDT 24
Finished Aug 08 04:32:04 PM PDT 24
Peak memory 253516 kb
Host smart-9596e69d-430e-4ddd-b136-7c726b44c067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70735
742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.70735742
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2877049213
Short name T39
Test name
Test status
Simulation time 225399784 ps
CPU time 18.54 seconds
Started Aug 08 04:31:50 PM PDT 24
Finished Aug 08 04:32:08 PM PDT 24
Peak memory 247844 kb
Host smart-f543b104-c1e8-4696-98a3-9dfa11c33052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28770
49213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2877049213
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.2161761969
Short name T352
Test name
Test status
Simulation time 342124627 ps
CPU time 7.28 seconds
Started Aug 08 04:31:49 PM PDT 24
Finished Aug 08 04:31:56 PM PDT 24
Peak memory 251160 kb
Host smart-82262a38-978c-492f-98c6-734e67120a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21617
61969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2161761969
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3850006252
Short name T453
Test name
Test status
Simulation time 13166257654 ps
CPU time 1436.32 seconds
Started Aug 08 04:31:50 PM PDT 24
Finished Aug 08 04:55:46 PM PDT 24
Peak memory 289120 kb
Host smart-8643857f-8f5e-4ed7-89af-3accc2801de4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850006252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3850006252
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.840019021
Short name T502
Test name
Test status
Simulation time 16002698052 ps
CPU time 1790.11 seconds
Started Aug 08 04:31:51 PM PDT 24
Finished Aug 08 05:01:41 PM PDT 24
Peak memory 299448 kb
Host smart-e307965b-9130-492e-8fa5-bc084e3bffcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840019021 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.840019021
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.123223392
Short name T196
Test name
Test status
Simulation time 15941522 ps
CPU time 2.8 seconds
Started Aug 08 04:29:42 PM PDT 24
Finished Aug 08 04:29:45 PM PDT 24
Peak memory 248336 kb
Host smart-7e217f24-6ad5-46c6-872b-6933c427d4f1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=123223392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.123223392
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1019617636
Short name T578
Test name
Test status
Simulation time 53441431191 ps
CPU time 1366.38 seconds
Started Aug 08 04:29:39 PM PDT 24
Finished Aug 08 04:52:26 PM PDT 24
Peak memory 286432 kb
Host smart-13efad97-9f5d-4d05-b3c7-6b570e5f1504
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019617636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1019617636
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.342430962
Short name T370
Test name
Test status
Simulation time 415595944 ps
CPU time 8.06 seconds
Started Aug 08 04:29:43 PM PDT 24
Finished Aug 08 04:29:51 PM PDT 24
Peak memory 248540 kb
Host smart-f3800422-6742-4c73-8422-bc5dc9487817
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=342430962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.342430962
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3276883960
Short name T433
Test name
Test status
Simulation time 5485064901 ps
CPU time 81.37 seconds
Started Aug 08 04:29:40 PM PDT 24
Finished Aug 08 04:31:02 PM PDT 24
Peak memory 249124 kb
Host smart-73e08a9c-9fe5-45a4-b4e2-221162f448c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32768
83960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3276883960
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.4218270470
Short name T421
Test name
Test status
Simulation time 115894692 ps
CPU time 8.7 seconds
Started Aug 08 04:29:42 PM PDT 24
Finished Aug 08 04:29:51 PM PDT 24
Peak memory 247552 kb
Host smart-e85a6bac-4bec-4ade-ac2a-ab74aaced851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42182
70470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.4218270470
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2934884623
Short name T321
Test name
Test status
Simulation time 57124279265 ps
CPU time 3044.37 seconds
Started Aug 08 04:29:38 PM PDT 24
Finished Aug 08 05:20:23 PM PDT 24
Peak memory 287228 kb
Host smart-3a9e8c57-207b-4771-8620-263d24c832ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934884623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2934884623
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3375198111
Short name T219
Test name
Test status
Simulation time 89611818591 ps
CPU time 1560.16 seconds
Started Aug 08 04:29:44 PM PDT 24
Finished Aug 08 04:55:44 PM PDT 24
Peak memory 272104 kb
Host smart-05aa315f-8da2-46f3-b9b6-c3192a4c16fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375198111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3375198111
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.4114729695
Short name T304
Test name
Test status
Simulation time 26715447557 ps
CPU time 518.83 seconds
Started Aug 08 04:29:37 PM PDT 24
Finished Aug 08 04:38:16 PM PDT 24
Peak memory 248176 kb
Host smart-be4bbf5a-c933-42fa-a3fa-5b7f443d9451
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114729695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.4114729695
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1711124627
Short name T540
Test name
Test status
Simulation time 1625995383 ps
CPU time 33.36 seconds
Started Aug 08 04:29:49 PM PDT 24
Finished Aug 08 04:30:22 PM PDT 24
Peak memory 256228 kb
Host smart-645b7bd6-250e-4169-b393-49bc1ac530f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17111
24627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1711124627
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2473989960
Short name T462
Test name
Test status
Simulation time 507202414 ps
CPU time 29.86 seconds
Started Aug 08 04:29:37 PM PDT 24
Finished Aug 08 04:30:07 PM PDT 24
Peak memory 248204 kb
Host smart-d621d051-32c1-4bc2-8194-8b99b7b76c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24739
89960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2473989960
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3713922630
Short name T117
Test name
Test status
Simulation time 196877818 ps
CPU time 23.29 seconds
Started Aug 08 04:29:40 PM PDT 24
Finished Aug 08 04:30:04 PM PDT 24
Peak memory 248544 kb
Host smart-1e79b1d2-22a4-4692-8eb4-2aaef4be8f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37139
22630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3713922630
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1564262630
Short name T212
Test name
Test status
Simulation time 7071971964 ps
CPU time 44.38 seconds
Started Aug 08 04:29:54 PM PDT 24
Finished Aug 08 04:30:38 PM PDT 24
Peak memory 256312 kb
Host smart-2989f22b-c537-4e52-9495-8bc15005db4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15642
62630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1564262630
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.1439897294
Short name T63
Test name
Test status
Simulation time 102717273089 ps
CPU time 1672.16 seconds
Started Aug 08 04:29:41 PM PDT 24
Finished Aug 08 04:57:33 PM PDT 24
Peak memory 282812 kb
Host smart-47715cf2-030a-4f62-acf0-2afc11536841
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439897294 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.1439897294
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2248726682
Short name T191
Test name
Test status
Simulation time 143410649 ps
CPU time 3.32 seconds
Started Aug 08 04:29:45 PM PDT 24
Finished Aug 08 04:29:48 PM PDT 24
Peak memory 248324 kb
Host smart-c91fe972-1107-48ae-a185-6ca9efb439d7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2248726682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2248726682
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1370732911
Short name T630
Test name
Test status
Simulation time 11271314416 ps
CPU time 921.69 seconds
Started Aug 08 04:29:40 PM PDT 24
Finished Aug 08 04:45:01 PM PDT 24
Peak memory 285496 kb
Host smart-fffb049a-35f9-421b-8811-d77649e771a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370732911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1370732911
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.696986321
Short name T555
Test name
Test status
Simulation time 717157929 ps
CPU time 17.74 seconds
Started Aug 08 04:29:44 PM PDT 24
Finished Aug 08 04:30:02 PM PDT 24
Peak memory 248096 kb
Host smart-e3136bf6-2264-405c-bcdc-c29725fe2760
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=696986321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.696986321
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.4008272715
Short name T378
Test name
Test status
Simulation time 2126169442 ps
CPU time 108 seconds
Started Aug 08 04:29:39 PM PDT 24
Finished Aug 08 04:31:27 PM PDT 24
Peak memory 254352 kb
Host smart-401fc65f-6802-454a-ae9a-3b27e4fdfe72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40082
72715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.4008272715
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.168095445
Short name T593
Test name
Test status
Simulation time 643282820 ps
CPU time 25.47 seconds
Started Aug 08 04:29:47 PM PDT 24
Finished Aug 08 04:30:12 PM PDT 24
Peak memory 248108 kb
Host smart-c5797ae2-5277-46b2-87b6-51c523b544b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16809
5445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.168095445
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3603526824
Short name T590
Test name
Test status
Simulation time 36088503594 ps
CPU time 2044.39 seconds
Started Aug 08 04:29:41 PM PDT 24
Finished Aug 08 05:03:46 PM PDT 24
Peak memory 281000 kb
Host smart-1a2fc555-4d08-4431-b3ad-a431bd2d82d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603526824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3603526824
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.4091079149
Short name T66
Test name
Test status
Simulation time 19691626148 ps
CPU time 414.51 seconds
Started Aug 08 04:29:50 PM PDT 24
Finished Aug 08 04:36:44 PM PDT 24
Peak memory 248080 kb
Host smart-fd90b467-3b4e-4d1c-ab00-347deaad5e83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091079149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.4091079149
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2111193244
Short name T685
Test name
Test status
Simulation time 1781053619 ps
CPU time 42.73 seconds
Started Aug 08 04:29:48 PM PDT 24
Finished Aug 08 04:30:31 PM PDT 24
Peak memory 248564 kb
Host smart-8db952f1-bfec-4932-8ece-1b8548c789b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21111
93244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2111193244
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2476770782
Short name T708
Test name
Test status
Simulation time 258381369 ps
CPU time 13.66 seconds
Started Aug 08 04:29:39 PM PDT 24
Finished Aug 08 04:29:53 PM PDT 24
Peak memory 254768 kb
Host smart-dfc0a3fc-a0a8-407f-be97-7ff10014fdf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24767
70782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2476770782
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.3152759592
Short name T260
Test name
Test status
Simulation time 744313796 ps
CPU time 23.93 seconds
Started Aug 08 04:29:38 PM PDT 24
Finished Aug 08 04:30:02 PM PDT 24
Peak memory 248096 kb
Host smart-df014afa-12fd-4d26-99e4-06e848142b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31527
59592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3152759592
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2454750153
Short name T445
Test name
Test status
Simulation time 789668940 ps
CPU time 47.87 seconds
Started Aug 08 04:29:41 PM PDT 24
Finished Aug 08 04:30:29 PM PDT 24
Peak memory 255376 kb
Host smart-d03a476d-4ca5-42e8-bc7b-ba285216575c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24547
50153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2454750153
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1684807540
Short name T93
Test name
Test status
Simulation time 40359924638 ps
CPU time 2490.57 seconds
Started Aug 08 04:29:45 PM PDT 24
Finished Aug 08 05:11:16 PM PDT 24
Peak memory 288384 kb
Host smart-0742f00e-c275-47b6-bdf7-1be1dd55fb9d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684807540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1684807540
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2716640416
Short name T201
Test name
Test status
Simulation time 38825266 ps
CPU time 3.55 seconds
Started Aug 08 04:29:58 PM PDT 24
Finished Aug 08 04:30:02 PM PDT 24
Peak memory 248428 kb
Host smart-68d6c108-e0c9-414a-acf3-a226dd89efc0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2716640416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2716640416
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3598959713
Short name T568
Test name
Test status
Simulation time 34283646684 ps
CPU time 1077.55 seconds
Started Aug 08 04:30:00 PM PDT 24
Finished Aug 08 04:47:58 PM PDT 24
Peak memory 282396 kb
Host smart-44827075-7e01-4e70-950b-fc6d0c7c7a4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598959713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3598959713
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1804832850
Short name T386
Test name
Test status
Simulation time 137481350 ps
CPU time 8.93 seconds
Started Aug 08 04:29:59 PM PDT 24
Finished Aug 08 04:30:08 PM PDT 24
Peak memory 248172 kb
Host smart-a6058391-afee-4fd6-8b38-1ca4e3a40706
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1804832850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1804832850
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3685854112
Short name T62
Test name
Test status
Simulation time 263875499 ps
CPU time 27.78 seconds
Started Aug 08 04:29:58 PM PDT 24
Finished Aug 08 04:30:26 PM PDT 24
Peak memory 255872 kb
Host smart-d082b402-84c9-4e9a-a51b-f711062697da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36858
54112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3685854112
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3881321787
Short name T374
Test name
Test status
Simulation time 334830472 ps
CPU time 19.52 seconds
Started Aug 08 04:29:55 PM PDT 24
Finished Aug 08 04:30:15 PM PDT 24
Peak memory 248100 kb
Host smart-b599c2f6-419d-4cfd-b873-1a8beab4633d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38813
21787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3881321787
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.4242522764
Short name T330
Test name
Test status
Simulation time 209631302847 ps
CPU time 2661.41 seconds
Started Aug 08 04:29:59 PM PDT 24
Finished Aug 08 05:14:21 PM PDT 24
Peak memory 288396 kb
Host smart-9d791d31-85f5-45c3-8146-eb0ede21b54e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242522764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.4242522764
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.416678493
Short name T704
Test name
Test status
Simulation time 21767491789 ps
CPU time 1453.09 seconds
Started Aug 08 04:29:59 PM PDT 24
Finished Aug 08 04:54:12 PM PDT 24
Peak memory 272064 kb
Host smart-cde002a1-872d-4a80-9c38-56608cc4d1d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416678493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.416678493
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1096765352
Short name T594
Test name
Test status
Simulation time 9313126162 ps
CPU time 394.96 seconds
Started Aug 08 04:29:59 PM PDT 24
Finished Aug 08 04:36:34 PM PDT 24
Peak memory 256376 kb
Host smart-23914bcd-0c37-488d-a99e-737f45f8dc6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096765352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1096765352
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3922067913
Short name T707
Test name
Test status
Simulation time 3283498193 ps
CPU time 43.49 seconds
Started Aug 08 04:29:56 PM PDT 24
Finished Aug 08 04:30:39 PM PDT 24
Peak memory 256332 kb
Host smart-1561e02a-1d36-4a38-bbbb-b7b88e30ea20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39220
67913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3922067913
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1817059055
Short name T691
Test name
Test status
Simulation time 597737972 ps
CPU time 18.97 seconds
Started Aug 08 04:29:57 PM PDT 24
Finished Aug 08 04:30:16 PM PDT 24
Peak memory 247472 kb
Host smart-52c9cba7-c83c-4a45-9ec2-72c2ba368e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18170
59055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1817059055
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2496006443
Short name T115
Test name
Test status
Simulation time 412761613 ps
CPU time 7.32 seconds
Started Aug 08 04:29:59 PM PDT 24
Finished Aug 08 04:30:06 PM PDT 24
Peak memory 248692 kb
Host smart-44d53e56-4928-4bae-aa31-db44c753eeb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24960
06443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2496006443
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1583200062
Short name T32
Test name
Test status
Simulation time 401661799 ps
CPU time 26.39 seconds
Started Aug 08 04:30:03 PM PDT 24
Finished Aug 08 04:30:30 PM PDT 24
Peak memory 248064 kb
Host smart-98b9d42d-e338-4e52-9caa-f268cf49c019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15832
00062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1583200062
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.4053735996
Short name T550
Test name
Test status
Simulation time 61864428573 ps
CPU time 3376.83 seconds
Started Aug 08 04:29:59 PM PDT 24
Finished Aug 08 05:26:16 PM PDT 24
Peak memory 288464 kb
Host smart-fef3eb83-e0e0-455d-923f-4470b0d96b4d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053735996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.4053735996
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.4063660832
Short name T107
Test name
Test status
Simulation time 89854733231 ps
CPU time 2127.93 seconds
Started Aug 08 04:29:59 PM PDT 24
Finished Aug 08 05:05:28 PM PDT 24
Peak memory 305272 kb
Host smart-284c77b9-b857-4bcb-a6e4-2fac89d59e3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063660832 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.4063660832
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.170900280
Short name T200
Test name
Test status
Simulation time 40487211 ps
CPU time 3.52 seconds
Started Aug 08 04:29:56 PM PDT 24
Finished Aug 08 04:30:00 PM PDT 24
Peak memory 248544 kb
Host smart-003da084-d622-408a-9c82-1046ff6f2024
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=170900280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.170900280
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2071337643
Short name T217
Test name
Test status
Simulation time 14021378504 ps
CPU time 1481.92 seconds
Started Aug 08 04:29:56 PM PDT 24
Finished Aug 08 04:54:38 PM PDT 24
Peak memory 285900 kb
Host smart-cc136eb7-8fb4-41a1-b924-901e608b6c5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071337643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2071337643
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2668712316
Short name T552
Test name
Test status
Simulation time 212496709 ps
CPU time 13.67 seconds
Started Aug 08 04:29:54 PM PDT 24
Finished Aug 08 04:30:08 PM PDT 24
Peak memory 248252 kb
Host smart-e31472c5-551c-4e9a-9dc0-779ae202e6ac
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2668712316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2668712316
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1755963292
Short name T388
Test name
Test status
Simulation time 16581544285 ps
CPU time 196.24 seconds
Started Aug 08 04:30:00 PM PDT 24
Finished Aug 08 04:33:17 PM PDT 24
Peak memory 250448 kb
Host smart-ad767dca-777d-4928-b12f-c127055e8e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17559
63292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1755963292
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3088251292
Short name T430
Test name
Test status
Simulation time 7210173140 ps
CPU time 34.49 seconds
Started Aug 08 04:29:58 PM PDT 24
Finished Aug 08 04:30:32 PM PDT 24
Peak memory 248188 kb
Host smart-47d87af7-c377-47e3-b557-ae78ce5d1ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30882
51292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3088251292
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2556960753
Short name T332
Test name
Test status
Simulation time 174517628735 ps
CPU time 2101.74 seconds
Started Aug 08 04:30:01 PM PDT 24
Finished Aug 08 05:05:03 PM PDT 24
Peak memory 272792 kb
Host smart-4e83b175-a346-456f-affb-f455889e405d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556960753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2556960753
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.874271777
Short name T491
Test name
Test status
Simulation time 203458582627 ps
CPU time 1554.27 seconds
Started Aug 08 04:29:59 PM PDT 24
Finished Aug 08 04:55:54 PM PDT 24
Peak memory 272396 kb
Host smart-60fdedd0-745c-4e36-b249-84b5ea4c303b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874271777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.874271777
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1565976438
Short name T624
Test name
Test status
Simulation time 821835932 ps
CPU time 62.51 seconds
Started Aug 08 04:30:01 PM PDT 24
Finished Aug 08 04:31:03 PM PDT 24
Peak memory 255332 kb
Host smart-1c290567-c042-4185-a598-0d9abebd8d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15659
76438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1565976438
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3719423446
Short name T501
Test name
Test status
Simulation time 215492710 ps
CPU time 4.85 seconds
Started Aug 08 04:29:56 PM PDT 24
Finished Aug 08 04:30:01 PM PDT 24
Peak memory 239300 kb
Host smart-5d17244b-20ca-47d5-8f15-10719b8176ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37194
23446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3719423446
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.2699680763
Short name T271
Test name
Test status
Simulation time 1151820517 ps
CPU time 28.93 seconds
Started Aug 08 04:29:57 PM PDT 24
Finished Aug 08 04:30:26 PM PDT 24
Peak memory 248200 kb
Host smart-d80cac92-bba3-464c-a3e0-1ebee9cf3087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26996
80763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2699680763
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2108072578
Short name T571
Test name
Test status
Simulation time 628370797 ps
CPU time 42.07 seconds
Started Aug 08 04:29:57 PM PDT 24
Finished Aug 08 04:30:39 PM PDT 24
Peak memory 256256 kb
Host smart-eefa0385-effb-4cb7-aff4-7da6ab842e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21080
72578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2108072578
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3631040519
Short name T46
Test name
Test status
Simulation time 388177577727 ps
CPU time 1971.37 seconds
Started Aug 08 04:29:58 PM PDT 24
Finished Aug 08 05:02:50 PM PDT 24
Peak memory 288144 kb
Host smart-25230d65-c5ec-4ace-a358-0d495de22bee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631040519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3631040519
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.894040931
Short name T605
Test name
Test status
Simulation time 92955944748 ps
CPU time 8263.04 seconds
Started Aug 08 04:29:57 PM PDT 24
Finished Aug 08 06:47:41 PM PDT 24
Peak memory 370456 kb
Host smart-be35af46-98d2-4f02-a306-c9b6a6bf9eae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894040931 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.894040931
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.4135582020
Short name T188
Test name
Test status
Simulation time 29623044 ps
CPU time 3.5 seconds
Started Aug 08 04:29:58 PM PDT 24
Finished Aug 08 04:30:02 PM PDT 24
Peak memory 248336 kb
Host smart-46bdb2f7-5604-4355-8169-448da65b5cc9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4135582020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.4135582020
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1479308804
Short name T546
Test name
Test status
Simulation time 158158466279 ps
CPU time 2445.19 seconds
Started Aug 08 04:30:02 PM PDT 24
Finished Aug 08 05:10:48 PM PDT 24
Peak memory 282420 kb
Host smart-dfe395a7-b32d-48d5-ab21-99ad827a6991
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479308804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1479308804
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.709634603
Short name T698
Test name
Test status
Simulation time 202223473 ps
CPU time 10.84 seconds
Started Aug 08 04:29:56 PM PDT 24
Finished Aug 08 04:30:07 PM PDT 24
Peak memory 248208 kb
Host smart-387bc0bc-276d-474d-bbc8-a41824e6cb59
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=709634603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.709634603
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3216699504
Short name T417
Test name
Test status
Simulation time 5425848784 ps
CPU time 186.94 seconds
Started Aug 08 04:30:02 PM PDT 24
Finished Aug 08 04:33:09 PM PDT 24
Peak memory 255888 kb
Host smart-378ec30f-055c-41d3-84cf-ba485b2c400f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32166
99504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3216699504
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.117784799
Short name T21
Test name
Test status
Simulation time 539442864 ps
CPU time 21.42 seconds
Started Aug 08 04:29:56 PM PDT 24
Finished Aug 08 04:30:18 PM PDT 24
Peak memory 254820 kb
Host smart-ab07fc38-7a46-4b4a-b00e-ef6a44ac2ca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11778
4799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.117784799
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.793259210
Short name T325
Test name
Test status
Simulation time 483107988390 ps
CPU time 2235.19 seconds
Started Aug 08 04:30:00 PM PDT 24
Finished Aug 08 05:07:16 PM PDT 24
Peak memory 288480 kb
Host smart-5c1e57d0-0707-476f-b53e-a0bf2fb34629
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793259210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.793259210
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3663999554
Short name T455
Test name
Test status
Simulation time 75817260376 ps
CPU time 2316.25 seconds
Started Aug 08 04:29:59 PM PDT 24
Finished Aug 08 05:08:35 PM PDT 24
Peak memory 288164 kb
Host smart-37a55bc1-c6b7-4d96-b7b9-a5e462ec9941
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663999554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3663999554
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1389666348
Short name T588
Test name
Test status
Simulation time 42257736606 ps
CPU time 428.13 seconds
Started Aug 08 04:29:56 PM PDT 24
Finished Aug 08 04:37:04 PM PDT 24
Peak memory 248160 kb
Host smart-e834905d-6528-43fa-b103-9f36dc3f7534
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389666348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1389666348
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1989268992
Short name T439
Test name
Test status
Simulation time 445942304 ps
CPU time 10.76 seconds
Started Aug 08 04:29:58 PM PDT 24
Finished Aug 08 04:30:09 PM PDT 24
Peak memory 254812 kb
Host smart-41e236d3-4ddc-4303-bc73-52b436f1d490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19892
68992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1989268992
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1952119581
Short name T422
Test name
Test status
Simulation time 88253001 ps
CPU time 4.42 seconds
Started Aug 08 04:29:59 PM PDT 24
Finished Aug 08 04:30:04 PM PDT 24
Peak memory 239288 kb
Host smart-013db0fd-96a8-4f12-b287-28053665e3c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19521
19581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1952119581
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1799102123
Short name T405
Test name
Test status
Simulation time 273386978 ps
CPU time 24.58 seconds
Started Aug 08 04:30:03 PM PDT 24
Finished Aug 08 04:30:28 PM PDT 24
Peak memory 255596 kb
Host smart-4060bb7e-735a-4d28-a0c6-9fc2c0acb7d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17991
02123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1799102123
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.444447518
Short name T456
Test name
Test status
Simulation time 327539337 ps
CPU time 18.51 seconds
Started Aug 08 04:29:56 PM PDT 24
Finished Aug 08 04:30:15 PM PDT 24
Peak memory 248104 kb
Host smart-ddccc31f-f0f6-42cf-978a-59a4f4f4eaef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44444
7518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.444447518
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1372539195
Short name T248
Test name
Test status
Simulation time 90226520377 ps
CPU time 2574.6 seconds
Started Aug 08 04:30:01 PM PDT 24
Finished Aug 08 05:12:56 PM PDT 24
Peak memory 288708 kb
Host smart-f99b0f02-73f8-4143-b62c-fc3cbd275796
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372539195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1372539195
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2168181697
Short name T59
Test name
Test status
Simulation time 83966597294 ps
CPU time 8541.28 seconds
Started Aug 08 04:29:57 PM PDT 24
Finished Aug 08 06:52:19 PM PDT 24
Peak memory 394340 kb
Host smart-cdc9290c-74d0-4228-a04e-79ae2abc30ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168181697 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2168181697
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%