Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	100416	1			T3	252		T4	149		T13	8
class_i[0x1]	68397	1			T2	7		T3	5		T4	2462
class_i[0x2]	59469	1			T2	1		T3	176		T13	3
class_i[0x3]	59492	1			T2	19		T3	5224		T4	18

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	76922	1			T2	5		T3	1855		T4	572
alert[0x1]	68979	1			T2	12		T3	1278		T4	684
alert[0x2]	71546	1			T2	5		T3	1299		T4	655
alert[0x3]	70327	1			T2	5		T3	1225		T4	718

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

287466

1

T2

19

T3

5657

T4

2629

esc_ping_fail

308

1

T2

8

T11

4

T12

11

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	76840	1			T2	4		T3	1855		T4	572
esc_integrity_fail	alert[0x1]	68905	1			T2	9		T3	1278		T4	684
esc_integrity_fail	alert[0x2]	71466	1			T2	3		T3	1299		T4	655
esc_integrity_fail	alert[0x3]	70255	1			T2	3		T3	1225		T4	718
esc_ping_fail	alert[0x0]	82	1			T2	1		T11	1		T12	1
esc_ping_fail	alert[0x1]	74	1			T2	3		T11	1		T12	2
esc_ping_fail	alert[0x2]	80	1			T2	2		T11	1		T12	4
esc_ping_fail	alert[0x3]	72	1			T2	2		T11	1		T12	4

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	100319	1			T3	252		T4	149		T13	8
esc_integrity_fail	class_i[0x1]	68321	1			T3	5		T4	2462		T13	9
esc_integrity_fail	class_i[0x2]	59378	1			T3	176		T13	3		T15	4183
esc_integrity_fail	class_i[0x3]	59448	1			T2	19		T3	5224		T4	18
esc_ping_fail	class_i[0x0]	97	1			T42	4		T115	1		T70	1
esc_ping_fail	class_i[0x1]	76	1			T2	7		T11	1		T97	8
esc_ping_fail	class_i[0x2]	91	1			T2	1		T11	3		T12	11
esc_ping_fail	class_i[0x3]	44	1			T97	1		T239	6		T112	1