Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	731707716	0	0	632
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	731707716	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	731707716	731534806	0	0
tb.dut.CheckAccuCntDw	0	0	632	632	0	0
tb.dut.CheckEscCntDw	0	0	632	632	0	0
tb.dut.CheckNAlerts	0	0	632	632	0	0
tb.dut.CheckNClasses	0	0	632	632	0	0
tb.dut.CheckNEscSev	0	0	632	632	0	0
tb.dut.CrashdumpKnownO_A	0	0	731707716	731534806	0	0
tb.dut.EdnKnownO_A	0	0	731707716	731534806	0	0
tb.dut.EscPKnownO_A	0	0	731707716	731534806	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	731707716	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	731707716	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	731707716	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	731707716	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	731707716	80	0	0
tb.dut.IrqAKnownO_A	0	0	731707716	731534806	0	0
tb.dut.IrqBKnownO_A	0	0	731707716	731534806	0	0
tb.dut.IrqCKnownO_A	0	0	731707716	731534806	0	0
tb.dut.IrqDKnownO_A	0	0	731707716	731534806	0	0
tb.dut.TlAReadyKnownO_A	0	0	731707716	731534806	0	0
tb.dut.TlDValidKnownO_A	0	0	731707716	731534806	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	755494992	4249025	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	755494992	16336	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	755494992	15153	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	755494992	15150	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	755494992	16675	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	755494992	15465	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	755494992	15158	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	755494992	15320	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	755494992	15164	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	755494992	14821	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	755494992	15021	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	755494992	14917	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	755494992	15068	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	755494992	16415	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	755494992	16246	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	755494992	15289	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	755494992	15405	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	755494992	16422	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	755494992	15255	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	755494992	15503	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	755494992	16373	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	755494992	15268	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	755494992	15113	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	755494992	16691	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	755494992	16306	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	755494992	15235	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	755494992	16507	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	755494992	16530	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	755494992	15529	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	755494992	15061	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	755494992	16326	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	755494992	15234	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	755494992	15434	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	755494992	15169	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	755494992	15851	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	755494992	16382	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	755494992	15073	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	755494992	15334	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	755494992	15015	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	755494992	16248	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	755494992	15066	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	755494992	15362	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	755494992	16110	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	755494992	15216	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	755494992	15396	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	755494992	16691	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	755494992	15344	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	755494992	15493	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	755494992	15012	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	755494992	16247	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	755494992	16124	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	755494992	15995	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	755494992	15005	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	755494992	16199	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	755494992	14762	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	755494992	14886	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	755494992	15125	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	755494992	16413	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	755494992	14881	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	755494992	15200	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	755494992	15076	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	755494992	16542	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	755494992	15090	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	755494992	15229	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	755494992	15613	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	755494992	15333	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	755494992	15524	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	755494992	15675	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	755494992	15314	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	755494992	15210	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	755494992	30217	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	755494992	14924	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	755494992	15409	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	755494992	15231	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	755494992	16336	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	755494992	15688	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	755494992	16171	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	755494992	16468	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	755494992	15188	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	731707716	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	731707716	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	731707716	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	731707716	6518	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	731707716	230544	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	731707716	378590527	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	731707716	283	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	731707716	857	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	731707716	36	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	731707716	393	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	731462374	291740751	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	731707716	934	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	731707716	910	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	731707716	888	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	731707716	874	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	731707716	1766	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	731707716	186644	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	731707716	1660	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	731707716	65	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	731707716	1192	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	731707716	952	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	731460799	731390320	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	632	632	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	731707716	731534806	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	731707716	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	731707716	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	731707716	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	731707716	387	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	731707716	196223	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	731707716	434658918	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	731707716	286	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	731707716	530	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	731707716	19	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	731707716	234	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	731462374	349530614	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	731707716	602	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	731707716	594	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	731707716	587	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	731707716	576	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	731707716	926	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	731707716	104683	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	731707716	846	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	731707716	61	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	731707716	1287	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	731707716	1047	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	731460799	731390320	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	632	632	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	731707716	731534806	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	731707716	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	731707716	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	731707716	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	731707716	5832	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	731707716	225537	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	731707716	424702432	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	731707716	238	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	731707716	531	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	731707716	25	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	731707716	247	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	731462374	343282688	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	731707716	626	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	731707716	608	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	731707716	598	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	731707716	590	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	731707716	1222	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	731707716	143879	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	731707716	1116	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	731707716	79	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	731707716	1287	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	731707716	1047	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	731460799	731390320	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	632	632	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	731707716	731534806	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	731707716	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	731707716	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	731707716	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	731707716	2579	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	731707716	162964	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	731707716	415893304	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	731707716	267	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	731707716	550	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	731707716	19	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	731707716	251	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	731462374	320380453	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	731707716	617	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	731707716	600	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	731707716	588	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	731707716	579	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	731707716	1991	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	731707716	212636	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	731707716	1907	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	731707716	63	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	731707716	1262	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	731707716	1022	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	731460799	731390320	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	632	632	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	731707716	731534806	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	755494992	157166262	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	755494992	754855042	0	0
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