Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	65	1			T3	1		T13	1		T68	1
class_index[0x1]	61	1			T18	1		T85	1		T24	1
class_index[0x2]	79	1			T20	1		T84	2		T15	1
class_index[0x3]	63	1			T84	1		T63	1		T44	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	102	1			T13	1		T20	1		T84	3
intr_timeout_cnt[1]	58	1			T3	1		T15	1		T24	2
intr_timeout_cnt[2]	42	1			T18	1		T29	1		T82	1
intr_timeout_cnt[3]	16	1			T81	1		T82	2		T50	1
intr_timeout_cnt[4]	12	1			T49	1		T117	1		T252	1
intr_timeout_cnt[5]	9	1			T44	1		T253	1		T39	2
intr_timeout_cnt[6]	12	1			T46	3		T95	1		T56	1
intr_timeout_cnt[7]	10	1			T81	1		T49	1		T253	2
intr_timeout_cnt[8]	3	1			T27	1		T56	1		T254	1
intr_timeout_cnt[9]	4	1			T46	1		T35	1		T255	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	27	1			T13	1		T68	1		T29	3
class_index[0x0]	intr_timeout_cnt[1]	18	1			T3	1		T92	3		T256	1
class_index[0x0]	intr_timeout_cnt[2]	10	1			T253	1		T257	1		T32	1
class_index[0x0]	intr_timeout_cnt[3]	4	1			T258	3		T259	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	1	1			T260	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	2	1			T252	1		T261	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T81	1		T262	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	1	1			T254	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	20	1			T85	1		T48	2		T263	1
class_index[0x1]	intr_timeout_cnt[1]	15	1			T24	1		T92	1		T93	1
class_index[0x1]	intr_timeout_cnt[2]	9	1			T18	1		T49	1		T256	1
class_index[0x1]	intr_timeout_cnt[3]	5	1			T241	1		T264	1		T265	3
class_index[0x1]	intr_timeout_cnt[4]	2	1			T121	1		T266	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	3	1			T253	1		T39	2		-	-
class_index[0x1]	intr_timeout_cnt[6]	5	1			T46	2		T95	1		T56	1
class_index[0x1]	intr_timeout_cnt[7]	1	1			T267	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T268	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	31	1			T20	1		T84	2		T23	5
class_index[0x2]	intr_timeout_cnt[1]	13	1			T15	1		T24	1		T82	1
class_index[0x2]	intr_timeout_cnt[2]	15	1			T29	1		T51	2		T269	1
class_index[0x2]	intr_timeout_cnt[3]	4	1			T81	1		T82	1		T50	1
class_index[0x2]	intr_timeout_cnt[4]	5	1			T252	1		T249	1		T241	1
class_index[0x2]	intr_timeout_cnt[5]	2	1			T267	1		T270	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T119	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	5	1			T253	2		T39	2		T258	1
class_index[0x2]	intr_timeout_cnt[8]	2	1			T27	1		T56	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T255	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	24	1			T84	1		T63	1		T82	1
class_index[0x3]	intr_timeout_cnt[1]	12	1			T46	1		T103	1		T240	1
class_index[0x3]	intr_timeout_cnt[2]	8	1			T82	1		T51	1		T267	2
class_index[0x3]	intr_timeout_cnt[3]	3	1			T82	1		T271	1		T241	1
class_index[0x3]	intr_timeout_cnt[4]	4	1			T49	1		T117	1		T251	1
class_index[0x3]	intr_timeout_cnt[5]	4	1			T44	1		T121	1		T267	1
class_index[0x3]	intr_timeout_cnt[6]	4	1			T46	1		T32	1		T187	1
class_index[0x3]	intr_timeout_cnt[7]	2	1			T49	1		T249	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T46	1		T35	1		-	-