Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	376785	1			T1	87		T2	55		T3	2230
all_values[1]	376785	1			T1	87		T2	55		T3	2230
all_values[2]	376785	1			T1	87		T2	55		T3	2230
all_values[3]	376785	1			T1	87		T2	55		T3	2230

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

750510

1

T1

175

T3

4373

T6

3579

auto[1]

756630

1

T1

173

T2

220

T3

4547

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

896180

1

T1

179

T2

184

T3

4714

auto[1]

610960

1

T1

169

T2

36

T3

4206

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	106931	1			T1	22		T3	533		T6	443
all_values[0]	auto[0]	auto[1]	80551	1			T1	21		T3	511		T6	433
all_values[0]	auto[1]	auto[0]	108506	1			T1	22		T2	55		T3	604
all_values[0]	auto[1]	auto[1]	80797	1			T1	22		T3	582		T6	449
all_values[1]	auto[0]	auto[0]	111029	1			T1	20		T3	630		T6	480
all_values[1]	auto[0]	auto[1]	76842	1			T1	19		T3	515		T6	446
all_values[1]	auto[1]	auto[0]	111852	1			T1	27		T2	46		T3	597
all_values[1]	auto[1]	auto[1]	77062	1			T1	21		T2	9		T3	488
all_values[2]	auto[0]	auto[0]	113041	1			T1	21		T3	576		T6	457
all_values[2]	auto[0]	auto[1]	74671	1			T1	21		T3	512		T6	455
all_values[2]	auto[1]	auto[0]	114340	1			T1	23		T2	36		T3	598
all_values[2]	auto[1]	auto[1]	74733	1			T1	22		T2	19		T3	544
all_values[3]	auto[0]	auto[0]	114468	1			T1	26		T3	580		T6	434
all_values[3]	auto[0]	auto[1]	72977	1			T1	25		T3	516		T6	431
all_values[3]	auto[1]	auto[0]	116013	1			T1	18		T2	47		T3	596
all_values[3]	auto[1]	auto[1]	73327	1			T1	18		T2	8		T3	538