Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	376785	1			T1	87		T2	55		T3	2230
all_pins[1]	376785	1			T1	87		T2	55		T3	2230
all_pins[2]	376785	1			T1	87		T2	55		T3	2230
all_pins[3]	376785	1			T1	87		T2	55		T3	2230

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1201221	1			T1	265		T2	184		T3	6768
values[0x1]	305919	1			T1	83		T2	36		T3	2152
transitions[0x0=>0x1]	202709	1			T1	52		T2	35		T3	1351
transitions[0x1=>0x0]	202960	1			T1	53		T2	35		T3	1352

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	295988	1			T1	65		T2	55		T3	1648
all_pins[0]	values[0x1]	80797	1			T1	22		T3	582		T6	449
all_pins[0]	transitions[0x0=>0x1]	80134	1			T1	21		T3	574		T6	448
all_pins[0]	transitions[0x1=>0x0]	72915	1			T1	18		T2	8		T3	531
all_pins[1]	values[0x0]	299723	1			T1	66		T2	46		T3	1742
all_pins[1]	values[0x1]	77062	1			T1	21		T2	9		T3	488
all_pins[1]	transitions[0x0=>0x1]	42211	1			T1	13		T2	9		T3	228
all_pins[1]	transitions[0x1=>0x0]	45946	1			T1	14		T3	322		T6	223
all_pins[2]	values[0x0]	302052	1			T1	65		T2	36		T3	1686
all_pins[2]	values[0x1]	74733	1			T1	22		T2	19		T3	544
all_pins[2]	transitions[0x0=>0x1]	40536	1			T1	11		T2	19		T3	291
all_pins[2]	transitions[0x1=>0x0]	42865	1			T1	10		T2	9		T3	235
all_pins[3]	values[0x0]	303458	1			T1	69		T2	47		T3	1692
all_pins[3]	values[0x1]	73327	1			T1	18		T2	8		T3	538
all_pins[3]	transitions[0x0=>0x1]	39828	1			T1	7		T2	7		T3	258
all_pins[3]	transitions[0x1=>0x0]	41234	1			T1	11		T2	18		T3	264