Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	106172	1			T3	995		T6	1701		T13	570
accum_cnt_1000	241787	1			T1	11		T3	1175		T6	1604
accum_cnt_100	29796	1			T1	46		T3	135		T6	101
accum_cnt_50	76265	1			T1	49		T3	138		T6	90
accum_cnt_10	163698	1			T1	61		T2	3		T3	1784
accum_cnt_0	450321	1			T1	5		T2	153		T3	1860

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	278609	1			T1	43		T2	39		T3	1664
class_index[0x1]	278609	1			T1	43		T2	39		T3	1664
class_index[0x2]	278609	1			T1	43		T2	39		T3	1664
class_index[0x3]	278609	1			T1	43		T2	39		T3	1664

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	27397	1			T6	542		T24	1074		T77	44
class_index[0x0]	accum_cnt_1000	64097	1			T1	1		T3	8		T6	496
class_index[0x0]	accum_cnt_100	10642	1			T1	20		T3	27		T6	32
class_index[0x0]	accum_cnt_50	22017	1			T1	13		T3	36		T6	37
class_index[0x0]	accum_cnt_10	43805	1			T1	6		T3	1473		T6	8
class_index[0x0]	accum_cnt_0	96948	1			T1	3		T2	39		T3	120
class_index[0x1]	accum_cnt_2000	23896	1			T3	578		T6	627		T13	570
class_index[0x1]	accum_cnt_1000	61728	1			T3	723		T6	653		T17	28
class_index[0x1]	accum_cnt_100	7473	1			T1	11		T3	61		T6	40
class_index[0x1]	accum_cnt_50	20367	1			T1	24		T3	66		T6	32
class_index[0x1]	accum_cnt_10	37506	1			T1	7		T3	123		T6	8
class_index[0x1]	accum_cnt_0	115963	1			T1	1		T2	39		T3	113
class_index[0x2]	accum_cnt_2000	26806	1			T3	417		T10	407		T14	563
class_index[0x2]	accum_cnt_1000	59121	1			T1	10		T3	444		T4	1165
class_index[0x2]	accum_cnt_100	5928	1			T1	15		T3	47		T4	86
class_index[0x2]	accum_cnt_50	14535	1			T1	12		T3	36		T4	70
class_index[0x2]	accum_cnt_10	35770	1			T1	5		T2	3		T3	31
class_index[0x2]	accum_cnt_0	123451	1			T1	1		T2	36		T3	120
class_index[0x3]	accum_cnt_2000	28073	1			T6	532		T14	578		T15	584
class_index[0x3]	accum_cnt_1000	56841	1			T6	455		T17	15		T14	519
class_index[0x3]	accum_cnt_100	5753	1			T6	29		T17	24		T14	28
class_index[0x3]	accum_cnt_50	19346	1			T6	21		T4	99		T17	22
class_index[0x3]	accum_cnt_10	46617	1			T1	43		T3	157		T6	7
class_index[0x3]	accum_cnt_0	113959	1			T2	39		T3	1507		T6	2