Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	6953	1			T70	1		T72	1		T78	26
alert[0x1]	1886	1			T2	1		T3	42		T4	10
alert[0x2]	4621	1			T3	14		T239	1		T71	1
alert[0x3]	12751	1			T12	1		T70	1		T299	1
alert[0x4]	7478	1			T15	222		T115	1		T24	12
alert[0x5]	4531	1			T2	1		T4	5		T15	40
alert[0x6]	10441	1			T72	1		T73	1		T78	55
alert[0x7]	3186	1			T3	114		T15	5		T115	1
alert[0x8]	10437	1			T3	674		T15	111		T12	1
alert[0x9]	3678	1			T11	1		T15	431		T28	5
alert[0xa]	3948	1			T3	85		T15	181		T43	2
alert[0xb]	1463	1			T3	107		T72	1		T73	2
alert[0xc]	2529	1			T2	2		T3	10		T4	16
alert[0xd]	5292	1			T4	54		T15	216		T115	3
alert[0xe]	11623	1			T2	2		T3	21		T4	2
alert[0xf]	6811	1			T3	959		T97	2		T239	1
alert[0x10]	4911	1			T3	1172		T11	1		T15	1868
alert[0x11]	3204	1			T3	164		T15	179		T115	1
alert[0x12]	5300	1			T2	2		T12	1		T24	3
alert[0x13]	5147	1			T4	18		T12	2		T24	26
alert[0x14]	9792	1			T2	1		T4	1		T28	1
alert[0x15]	4440	1			T3	21		T4	17		T15	87
alert[0x16]	6015	1			T15	35		T70	1		T71	1
alert[0x17]	7386	1			T4	13		T68	2815		T239	1
alert[0x18]	4778	1			T2	1		T115	1		T24	97
alert[0x19]	2747	1			T3	700		T4	5		T239	1
alert[0x1a]	7984	1			T4	1		T11	1		T15	163
alert[0x1b]	6686	1			T115	1		T70	1		T71	2
alert[0x1c]	8787	1			T2	1		T42	1		T239	2
alert[0x1d]	8406	1			T3	91		T11	1		T24	23
alert[0x1e]	7756	1			T2	1		T3	1633		T97	1
alert[0x1f]	3230	1			T3	1		T4	16		T15	27
alert[0x20]	6793	1			T2	1		T43	1		T97	1
alert[0x21]	4829	1			T4	2		T15	1035		T43	9
alert[0x22]	7634	1			T4	2		T43	1		T72	1
alert[0x23]	2042	1			T3	26		T4	1		T15	14
alert[0x24]	9215	1			T3	484		T4	89		T12	1
alert[0x25]	14302	1			T3	1738		T4	3		T97	1
alert[0x26]	4411	1			T2	1		T4	8		T15	49
alert[0x27]	12286	1			T2	2		T12	1		T97	1
alert[0x28]	10702	1			T3	502		T4	4		T12	2
alert[0x29]	3497	1			T11	1		T15	209		T24	7
alert[0x2a]	13450	1			T4	2		T15	140		T43	1
alert[0x2b]	7951	1			T3	80		T4	1		T43	2
alert[0x2c]	7173	1			T3	209		T239	1		T70	1
alert[0x2d]	5818	1			T11	1		T15	1255		T71	1
alert[0x2e]	11765	1			T4	2		T15	434		T24	4
alert[0x2f]	13092	1			T2	2		T3	153		T4	2
alert[0x30]	6412	1			T3	34		T4	4		T115	1
alert[0x31]	6000	1			T3	178		T4	3		T15	143
alert[0x32]	3482	1			T2	1		T15	55		T68	335
alert[0x33]	4207	1			T72	2		T78	109		T81	1394
alert[0x34]	8454	1			T15	84		T42	1		T97	1
alert[0x35]	16947	1			T3	403		T4	4		T15	205
alert[0x36]	3442	1			T4	1		T15	715		T43	2
alert[0x37]	5258	1			T3	54		T4	1		T15	184
alert[0x38]	2467	1			T2	1		T68	431		T112	1
alert[0x39]	7271	1			T3	677		T12	1		T42	1
alert[0x3a]	3947	1			T97	1		T81	12		T82	4
alert[0x3b]	9627	1			T15	320		T24	211		T72	1
alert[0x3c]	5300	1			T3	57		T15	116		T12	1
alert[0x3d]	8032	1			T24	28		T72	1		T81	178
alert[0x3e]	2652	1			T3	531		T72	1		T73	1
alert[0x3f]	4013	1			T4	22		T12	1		T72	2
alert[0x40]	3535	1			T3	58		T4	6		T43	11

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	99407	1			T3	4		T12	1		T239	17
class_i[0x1]	121767	1			T2	2		T3	32		T15	40
class_i[0x2]	132298	1			T2	18		T3	68		T4	297
class_i[0x3]	76731	1			T3	10888		T4	18		T15	5

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

429487

1

T3

10992

T4

315

T15

8800

alert_ping_fail

716

1

T2

20

T11

7

T12

16

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	6940	1			T78	26		T81	2103		T277	562
alert_integrity_fail	alert[0x1]	1878	1			T3	42		T4	10		T24	18
alert_integrity_fail	alert[0x2]	4613	1			T3	14		T78	746		T82	12
alert_integrity_fail	alert[0x3]	12745	1			T299	1		T300	3		T301	293
alert_integrity_fail	alert[0x4]	7473	1			T15	222		T24	12		T81	76
alert_integrity_fail	alert[0x5]	4510	1			T4	5		T15	40		T43	33
alert_integrity_fail	alert[0x6]	10423	1			T78	55		T46	2		T277	91
alert_integrity_fail	alert[0x7]	3173	1			T3	114		T15	5		T28	1
alert_integrity_fail	alert[0x8]	10420	1			T3	674		T15	111		T28	1
alert_integrity_fail	alert[0x9]	3668	1			T15	431		T28	5		T78	39
alert_integrity_fail	alert[0xa]	3939	1			T3	85		T15	181		T43	2
alert_integrity_fail	alert[0xb]	1456	1			T3	107		T82	3		T46	4
alert_integrity_fail	alert[0xc]	2514	1			T3	10		T4	16		T15	260
alert_integrity_fail	alert[0xd]	5279	1			T4	54		T15	216		T299	17
alert_integrity_fail	alert[0xe]	11615	1			T3	21		T4	2		T82	6
alert_integrity_fail	alert[0xf]	6799	1			T3	959		T78	26		T81	35
alert_integrity_fail	alert[0x10]	4899	1			T3	1172		T15	1868		T47	1
alert_integrity_fail	alert[0x11]	3196	1			T3	164		T15	179		T24	577
alert_integrity_fail	alert[0x12]	5292	1			T24	3		T50	2		T98	1
alert_integrity_fail	alert[0x13]	5131	1			T4	18		T24	26		T78	1038
alert_integrity_fail	alert[0x14]	9774	1			T4	1		T28	1		T78	44
alert_integrity_fail	alert[0x15]	4425	1			T3	21		T4	17		T15	87
alert_integrity_fail	alert[0x16]	6001	1			T15	35		T46	7		T179	11
alert_integrity_fail	alert[0x17]	7374	1			T4	13		T68	2815		T24	252
alert_integrity_fail	alert[0x18]	4767	1			T24	97		T47	2		T27	1
alert_integrity_fail	alert[0x19]	2741	1			T3	700		T4	5		T78	15
alert_integrity_fail	alert[0x1a]	7967	1			T4	1		T15	163		T24	1
alert_integrity_fail	alert[0x1b]	6672	1			T81	424		T300	204		T54	14
alert_integrity_fail	alert[0x1c]	8776	1			T24	70		T78	59		T81	6
alert_integrity_fail	alert[0x1d]	8397	1			T3	91		T24	23		T44	1
alert_integrity_fail	alert[0x1e]	7743	1			T3	1633		T78	575		T81	306
alert_integrity_fail	alert[0x1f]	3219	1			T3	1		T4	16		T15	27
alert_integrity_fail	alert[0x20]	6779	1			T43	1		T24	16		T44	1
alert_integrity_fail	alert[0x21]	4821	1			T4	2		T15	1035		T43	9
alert_integrity_fail	alert[0x22]	7618	1			T4	2		T43	1		T78	184
alert_integrity_fail	alert[0x23]	2037	1			T3	26		T4	1		T15	14
alert_integrity_fail	alert[0x24]	9206	1			T3	484		T4	89		T68	1891
alert_integrity_fail	alert[0x25]	14288	1			T3	1738		T4	3		T24	12
alert_integrity_fail	alert[0x26]	4401	1			T4	8		T15	49		T68	296
alert_integrity_fail	alert[0x27]	12275	1			T78	31		T277	446		T299	1
alert_integrity_fail	alert[0x28]	10696	1			T3	502		T4	4		T24	33
alert_integrity_fail	alert[0x29]	3490	1			T15	209		T24	7		T78	141
alert_integrity_fail	alert[0x2a]	13440	1			T4	2		T15	140		T43	1
alert_integrity_fail	alert[0x2b]	7943	1			T3	80		T4	1		T43	2
alert_integrity_fail	alert[0x2c]	7152	1			T3	209		T81	68		T82	3
alert_integrity_fail	alert[0x2d]	5804	1			T15	1255		T78	199		T81	11
alert_integrity_fail	alert[0x2e]	11755	1			T4	2		T15	434		T24	4
alert_integrity_fail	alert[0x2f]	13077	1			T3	153		T4	2		T15	17
alert_integrity_fail	alert[0x30]	6400	1			T3	34		T4	4		T78	3379
alert_integrity_fail	alert[0x31]	5991	1			T3	178		T4	3		T15	143
alert_integrity_fail	alert[0x32]	3471	1			T15	55		T68	335		T24	81
alert_integrity_fail	alert[0x33]	4200	1			T78	109		T81	1394		T82	1
alert_integrity_fail	alert[0x34]	8443	1			T15	84		T24	975		T277	184
alert_integrity_fail	alert[0x35]	16933	1			T3	403		T4	4		T15	205
alert_integrity_fail	alert[0x36]	3433	1			T4	1		T15	715		T43	2
alert_integrity_fail	alert[0x37]	5240	1			T3	54		T4	1		T15	184
alert_integrity_fail	alert[0x38]	2456	1			T68	431		T24	25		T81	59
alert_integrity_fail	alert[0x39]	7262	1			T3	677		T277	1430		T47	86
alert_integrity_fail	alert[0x3a]	3941	1			T81	12		T82	4		T46	1
alert_integrity_fail	alert[0x3b]	9619	1			T15	320		T24	211		T78	13
alert_integrity_fail	alert[0x3c]	5292	1			T3	57		T15	116		T43	6
alert_integrity_fail	alert[0x3d]	8020	1			T24	28		T81	178		T82	3
alert_integrity_fail	alert[0x3e]	2647	1			T3	531		T82	6		T46	5
alert_integrity_fail	alert[0x3f]	4007	1			T4	22		T78	63		T82	8
alert_integrity_fail	alert[0x40]	3531	1			T3	58		T4	6		T43	11
alert_ping_fail	alert[0x0]	13	1			T70	1		T72	1		T302	1
alert_ping_fail	alert[0x1]	8	1			T2	1		T112	1		T303	1
alert_ping_fail	alert[0x2]	8	1			T239	1		T71	1		T304	1
alert_ping_fail	alert[0x3]	6	1			T12	1		T70	1		T305	1
alert_ping_fail	alert[0x4]	5	1			T115	1		T302	1		T306	1
alert_ping_fail	alert[0x5]	21	1			T2	1		T64	1		T239	1
alert_ping_fail	alert[0x6]	18	1			T72	1		T73	1		T303	1
alert_ping_fail	alert[0x7]	13	1			T115	1		T303	1		T302	1
alert_ping_fail	alert[0x8]	17	1			T12	1		T97	2		T64	1
alert_ping_fail	alert[0x9]	10	1			T11	1		T70	1		T303	1
alert_ping_fail	alert[0xa]	9	1			T97	1		T239	1		T279	1
alert_ping_fail	alert[0xb]	7	1			T72	1		T73	2		T306	2
alert_ping_fail	alert[0xc]	15	1			T2	2		T115	1		T302	1
alert_ping_fail	alert[0xd]	13	1			T115	3		T70	1		T307	1
alert_ping_fail	alert[0xe]	8	1			T2	2		T11	1		T181	1
alert_ping_fail	alert[0xf]	12	1			T97	2		T239	1		T307	1
alert_ping_fail	alert[0x10]	12	1			T11	1		T12	1		T239	1
alert_ping_fail	alert[0x11]	8	1			T115	1		T302	1		T181	1
alert_ping_fail	alert[0x12]	8	1			T2	2		T12	1		T308	1
alert_ping_fail	alert[0x13]	16	1			T12	2		T70	1		T302	1
alert_ping_fail	alert[0x14]	18	1			T2	1		T278	1		T309	1
alert_ping_fail	alert[0x15]	15	1			T97	1		T71	1		T303	1
alert_ping_fail	alert[0x16]	14	1			T70	1		T71	1		T72	1
alert_ping_fail	alert[0x17]	12	1			T239	1		T70	1		T72	1
alert_ping_fail	alert[0x18]	11	1			T2	1		T115	1		T70	1
alert_ping_fail	alert[0x19]	6	1			T239	1		T310	1		T311	1
alert_ping_fail	alert[0x1a]	17	1			T11	1		T12	1		T239	1
alert_ping_fail	alert[0x1b]	14	1			T115	1		T70	1		T71	2
alert_ping_fail	alert[0x1c]	11	1			T2	1		T42	1		T239	2
alert_ping_fail	alert[0x1d]	9	1			T11	1		T71	1		T73	1
alert_ping_fail	alert[0x1e]	13	1			T2	1		T97	1		T70	2
alert_ping_fail	alert[0x1f]	11	1			T42	2		T239	1		T71	1
alert_ping_fail	alert[0x20]	14	1			T2	1		T97	1		T115	1
alert_ping_fail	alert[0x21]	8	1			T97	1		T278	3		T302	1
alert_ping_fail	alert[0x22]	16	1			T72	1		T83	1		T181	1
alert_ping_fail	alert[0x23]	5	1			T42	1		T70	1		T309	1
alert_ping_fail	alert[0x24]	9	1			T12	1		T97	1		T306	1
alert_ping_fail	alert[0x25]	14	1			T97	1		T71	2		T303	1
alert_ping_fail	alert[0x26]	10	1			T2	1		T302	2		T309	1
alert_ping_fail	alert[0x27]	11	1			T2	2		T12	1		T97	1
alert_ping_fail	alert[0x28]	6	1			T12	2		T71	1		T73	1
alert_ping_fail	alert[0x29]	7	1			T11	1		T311	1		T292	1
alert_ping_fail	alert[0x2a]	10	1			T298	1		T181	2		T287	1
alert_ping_fail	alert[0x2b]	8	1			T64	1		T239	1		T71	1
alert_ping_fail	alert[0x2c]	21	1			T239	1		T70	1		T72	1
alert_ping_fail	alert[0x2d]	14	1			T11	1		T71	1		T182	1
alert_ping_fail	alert[0x2e]	10	1			T37	1		T312	1		T313	1
alert_ping_fail	alert[0x2f]	15	1			T2	2		T12	1		T115	2
alert_ping_fail	alert[0x30]	12	1			T115	1		T73	1		T308	1
alert_ping_fail	alert[0x31]	9	1			T12	1		T97	1		T73	1
alert_ping_fail	alert[0x32]	11	1			T2	1		T72	2		T310	1
alert_ping_fail	alert[0x33]	7	1			T72	2		T307	1		T311	1
alert_ping_fail	alert[0x34]	11	1			T42	1		T97	1		T307	2
alert_ping_fail	alert[0x35]	14	1			T42	1		T239	2		T115	1
alert_ping_fail	alert[0x36]	9	1			T239	1		T73	1		T308	1
alert_ping_fail	alert[0x37]	18	1			T239	1		T70	1		T73	1
alert_ping_fail	alert[0x38]	11	1			T2	1		T112	1		T115	1
alert_ping_fail	alert[0x39]	9	1			T12	1		T42	1		T97	2
alert_ping_fail	alert[0x3a]	6	1			T97	1		T303	1		T305	1
alert_ping_fail	alert[0x3b]	8	1			T72	1		T73	1		T309	1
alert_ping_fail	alert[0x3c]	8	1			T12	1		T72	2		T307	2
alert_ping_fail	alert[0x3d]	12	1			T72	1		T314	1		T315	1
alert_ping_fail	alert[0x3e]	5	1			T72	1		T73	1		T316	1
alert_ping_fail	alert[0x3f]	6	1			T12	1		T72	2		T307	1
alert_ping_fail	alert[0x40]	4	1			T317	1		T311	2		T318	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	99215	1			T3	4		T78	10		T44	33
alert_integrity_fail	class_i[0x1]	121605	1			T3	32		T15	40		T28	2
alert_integrity_fail	class_i[0x2]	132130	1			T3	68		T4	297		T15	8755
alert_integrity_fail	class_i[0x3]	76537	1			T3	10888		T4	18		T15	5
alert_ping_fail	class_i[0x0]	192	1			T12	1		T239	17		T115	2
alert_ping_fail	class_i[0x1]	162	1			T2	2		T12	1		T97	16
alert_ping_fail	class_i[0x2]	168	1			T2	18		T11	7		T112	3
alert_ping_fail	class_i[0x3]	194	1			T12	14		T42	7		T97	1