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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.22 99.99 98.61 97.09 100.00 100.00 99.38 99.48


Total test records in report: 837
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T776 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.848714240 Aug 09 05:34:59 PM PDT 24 Aug 09 05:35:00 PM PDT 24 18354439 ps
T777 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.123292709 Aug 09 05:35:36 PM PDT 24 Aug 09 05:35:40 PM PDT 24 28819109 ps
T778 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2807054160 Aug 09 05:34:41 PM PDT 24 Aug 09 05:34:43 PM PDT 24 7811557 ps
T779 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.38256239 Aug 09 05:34:30 PM PDT 24 Aug 09 05:34:32 PM PDT 24 23080101 ps
T155 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2887573608 Aug 09 05:34:22 PM PDT 24 Aug 09 05:39:47 PM PDT 24 20996000176 ps
T166 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2938782915 Aug 09 05:34:38 PM PDT 24 Aug 09 05:35:01 PM PDT 24 178248218 ps
T780 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.916432247 Aug 09 05:34:26 PM PDT 24 Aug 09 05:37:35 PM PDT 24 5945847986 ps
T781 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1670513668 Aug 09 05:35:36 PM PDT 24 Aug 09 05:35:45 PM PDT 24 217685754 ps
T782 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1667581278 Aug 09 05:34:51 PM PDT 24 Aug 09 05:34:53 PM PDT 24 7964876 ps
T130 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3423421749 Aug 09 05:34:46 PM PDT 24 Aug 09 05:36:38 PM PDT 24 885164324 ps
T783 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1245826966 Aug 09 05:34:39 PM PDT 24 Aug 09 05:34:46 PM PDT 24 420475200 ps
T784 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1188107078 Aug 09 05:34:40 PM PDT 24 Aug 09 05:34:42 PM PDT 24 14720048 ps
T785 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1029563617 Aug 09 05:34:47 PM PDT 24 Aug 09 05:35:30 PM PDT 24 2823933380 ps
T786 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2119432038 Aug 09 05:34:37 PM PDT 24 Aug 09 05:34:38 PM PDT 24 8853939 ps
T787 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1357601088 Aug 09 05:34:47 PM PDT 24 Aug 09 05:34:56 PM PDT 24 133796189 ps
T154 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2940470791 Aug 09 05:34:43 PM PDT 24 Aug 09 05:43:41 PM PDT 24 15963082212 ps
T175 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1034330278 Aug 09 05:34:30 PM PDT 24 Aug 09 05:34:53 PM PDT 24 610502398 ps
T788 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.750957259 Aug 09 05:34:52 PM PDT 24 Aug 09 05:34:54 PM PDT 24 31794106 ps
T164 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1099403202 Aug 09 05:34:56 PM PDT 24 Aug 09 05:35:50 PM PDT 24 551588395 ps
T789 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3338323916 Aug 09 05:34:51 PM PDT 24 Aug 09 05:34:53 PM PDT 24 10493552 ps
T790 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2001136380 Aug 09 05:34:27 PM PDT 24 Aug 09 05:34:28 PM PDT 24 18231029 ps
T791 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.780772460 Aug 09 05:34:21 PM PDT 24 Aug 09 05:34:28 PM PDT 24 40079951 ps
T272 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1525876081 Aug 09 05:34:46 PM PDT 24 Aug 09 05:34:50 PM PDT 24 122756402 ps
T792 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2339500521 Aug 09 05:34:32 PM PDT 24 Aug 09 05:34:39 PM PDT 24 90126703 ps
T793 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1181246585 Aug 09 05:34:37 PM PDT 24 Aug 09 05:34:42 PM PDT 24 128304792 ps
T149 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2510163324 Aug 09 05:35:00 PM PDT 24 Aug 09 05:36:57 PM PDT 24 6501962218 ps
T794 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1217619058 Aug 09 05:34:55 PM PDT 24 Aug 09 05:34:58 PM PDT 24 111396381 ps
T795 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2172155122 Aug 09 05:34:46 PM PDT 24 Aug 09 05:35:22 PM PDT 24 2496329242 ps
T796 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1006258660 Aug 09 05:34:53 PM PDT 24 Aug 09 05:34:55 PM PDT 24 11173944 ps
T797 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3287808514 Aug 09 05:34:45 PM PDT 24 Aug 09 05:34:57 PM PDT 24 85154804 ps
T152 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2234001807 Aug 09 05:34:29 PM PDT 24 Aug 09 05:52:45 PM PDT 24 134627112345 ps
T798 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3203976127 Aug 09 05:35:37 PM PDT 24 Aug 09 05:36:00 PM PDT 24 701164601 ps
T799 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3902578403 Aug 09 05:34:48 PM PDT 24 Aug 09 05:35:00 PM PDT 24 177856231 ps
T128 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3679657134 Aug 09 05:34:44 PM PDT 24 Aug 09 05:36:26 PM PDT 24 1756891408 ps
T800 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.4090393376 Aug 09 05:34:31 PM PDT 24 Aug 09 05:34:35 PM PDT 24 742757033 ps
T801 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3984132595 Aug 09 05:34:46 PM PDT 24 Aug 09 05:34:51 PM PDT 24 30485345 ps
T145 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1642940801 Aug 09 05:34:33 PM PDT 24 Aug 09 05:37:19 PM PDT 24 2479365129 ps
T357 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.949454716 Aug 09 05:34:49 PM PDT 24 Aug 09 05:40:05 PM PDT 24 4368260384 ps
T802 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.777851939 Aug 09 05:34:32 PM PDT 24 Aug 09 05:34:49 PM PDT 24 423693126 ps
T803 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2415912284 Aug 09 05:34:33 PM PDT 24 Aug 09 05:38:42 PM PDT 24 12664086731 ps
T171 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1899293519 Aug 09 05:34:24 PM PDT 24 Aug 09 05:35:11 PM PDT 24 408323372 ps
T153 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2001030927 Aug 09 05:34:50 PM PDT 24 Aug 09 05:40:19 PM PDT 24 2870688598 ps
T804 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3218197059 Aug 09 05:34:38 PM PDT 24 Aug 09 05:34:47 PM PDT 24 119281516 ps
T805 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3605515826 Aug 09 05:34:46 PM PDT 24 Aug 09 05:35:12 PM PDT 24 788422568 ps
T806 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2094238343 Aug 09 05:35:00 PM PDT 24 Aug 09 05:35:01 PM PDT 24 7973581 ps
T807 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2319698392 Aug 09 05:34:40 PM PDT 24 Aug 09 05:34:44 PM PDT 24 29536147 ps
T808 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2857372646 Aug 09 05:34:53 PM PDT 24 Aug 09 05:34:57 PM PDT 24 77416251 ps
T169 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1440761666 Aug 09 05:34:41 PM PDT 24 Aug 09 05:35:03 PM PDT 24 307387498 ps
T809 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3613312280 Aug 09 05:35:12 PM PDT 24 Aug 09 05:37:45 PM PDT 24 4722974030 ps
T810 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2792162723 Aug 09 05:34:41 PM PDT 24 Aug 09 05:36:21 PM PDT 24 1637867558 ps
T811 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3462904919 Aug 09 05:35:02 PM PDT 24 Aug 09 05:35:22 PM PDT 24 649311272 ps
T812 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3138831410 Aug 09 05:34:23 PM PDT 24 Aug 09 05:38:37 PM PDT 24 20864588922 ps
T813 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1857984597 Aug 09 05:34:45 PM PDT 24 Aug 09 05:35:19 PM PDT 24 526859563 ps
T814 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1942749517 Aug 09 05:35:02 PM PDT 24 Aug 09 05:35:05 PM PDT 24 165658750 ps
T815 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.288419275 Aug 09 05:34:44 PM PDT 24 Aug 09 05:34:56 PM PDT 24 172710312 ps
T137 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.122772541 Aug 09 05:34:34 PM PDT 24 Aug 09 05:38:01 PM PDT 24 6424965988 ps
T129 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3451751618 Aug 09 05:34:31 PM PDT 24 Aug 09 05:44:44 PM PDT 24 4866851844 ps
T146 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.540769283 Aug 09 05:34:45 PM PDT 24 Aug 09 05:37:14 PM PDT 24 9082997610 ps
T816 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3575251019 Aug 09 05:34:48 PM PDT 24 Aug 09 05:34:49 PM PDT 24 21458187 ps
T165 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1964558490 Aug 09 05:35:12 PM PDT 24 Aug 09 05:35:16 PM PDT 24 321891657 ps
T817 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.255095081 Aug 09 05:34:54 PM PDT 24 Aug 09 05:35:02 PM PDT 24 216874278 ps
T818 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1908393018 Aug 09 05:34:41 PM PDT 24 Aug 09 05:34:48 PM PDT 24 8598364 ps
T819 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3815118059 Aug 09 05:34:54 PM PDT 24 Aug 09 05:34:57 PM PDT 24 44629025 ps
T156 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.748363494 Aug 09 05:34:25 PM PDT 24 Aug 09 05:39:57 PM PDT 24 8098095058 ps
T820 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.113937901 Aug 09 05:34:40 PM PDT 24 Aug 09 05:34:41 PM PDT 24 6882559 ps
T821 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.935375838 Aug 09 05:34:52 PM PDT 24 Aug 09 05:35:02 PM PDT 24 571284046 ps
T136 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3379841141 Aug 09 05:34:44 PM PDT 24 Aug 09 05:44:45 PM PDT 24 8160458498 ps
T177 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1205661554 Aug 09 05:34:53 PM PDT 24 Aug 09 05:34:55 PM PDT 24 50879007 ps
T150 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1975461190 Aug 09 05:34:33 PM PDT 24 Aug 09 05:36:40 PM PDT 24 1732455717 ps
T170 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3877391623 Aug 09 05:34:49 PM PDT 24 Aug 09 05:34:52 PM PDT 24 35797748 ps
T157 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3847984832 Aug 09 05:34:36 PM PDT 24 Aug 09 05:44:41 PM PDT 24 16671181055 ps
T822 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.835940243 Aug 09 05:34:40 PM PDT 24 Aug 09 05:34:45 PM PDT 24 114101175 ps
T823 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1216299821 Aug 09 05:35:36 PM PDT 24 Aug 09 05:37:26 PM PDT 24 4347726760 ps
T824 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1413468377 Aug 09 05:34:38 PM PDT 24 Aug 09 05:42:21 PM PDT 24 8847581183 ps
T825 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1797430167 Aug 09 05:35:03 PM PDT 24 Aug 09 05:35:04 PM PDT 24 11751534 ps
T826 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.243160821 Aug 09 05:34:54 PM PDT 24 Aug 09 05:34:59 PM PDT 24 120727111 ps
T827 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1998320043 Aug 09 05:34:51 PM PDT 24 Aug 09 05:34:53 PM PDT 24 11744370 ps
T828 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3629591590 Aug 09 05:34:42 PM PDT 24 Aug 09 05:34:51 PM PDT 24 252044332 ps
T829 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1949709272 Aug 09 05:34:23 PM PDT 24 Aug 09 05:34:25 PM PDT 24 9149767 ps
T830 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.924199438 Aug 09 05:34:57 PM PDT 24 Aug 09 05:34:59 PM PDT 24 9111793 ps
T831 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.507832193 Aug 09 05:34:45 PM PDT 24 Aug 09 05:34:51 PM PDT 24 144512416 ps
T832 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1624354799 Aug 09 05:35:02 PM PDT 24 Aug 09 05:35:23 PM PDT 24 341713523 ps
T833 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3537648342 Aug 09 05:34:32 PM PDT 24 Aug 09 05:35:10 PM PDT 24 1894381738 ps
T834 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2228976187 Aug 09 05:34:23 PM PDT 24 Aug 09 05:42:32 PM PDT 24 32903439851 ps
T835 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1001346111 Aug 09 05:34:48 PM PDT 24 Aug 09 05:34:59 PM PDT 24 625123726 ps
T836 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1418202508 Aug 09 05:34:40 PM PDT 24 Aug 09 05:34:43 PM PDT 24 26007390 ps
T837 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4044844399 Aug 09 05:34:56 PM PDT 24 Aug 09 05:35:04 PM PDT 24 457622642 ps

Test location /workspace/coverage/default/30.alert_handler_stress_all.3682092521
Short name T3
Test name
Test status
Simulation time 103880667254 ps
CPU time 3370.98 seconds
Started Aug 09 04:39:23 PM PDT 24
Finished Aug 09 05:35:34 PM PDT 24
Peak memory 305148 kb
Host smart-41c8c491-55de-4fdd-afa1-fdd3a6024ff9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682092521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3682092521
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2712857814
Short name T92
Test name
Test status
Simulation time 30133585497 ps
CPU time 1822.15 seconds
Started Aug 09 04:38:10 PM PDT 24
Finished Aug 09 05:08:33 PM PDT 24
Peak memory 289344 kb
Host smart-cd2e05fa-d1ab-4cfc-b407-167594761e87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712857814 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2712857814
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1373989962
Short name T7
Test name
Test status
Simulation time 490949486 ps
CPU time 20.51 seconds
Started Aug 09 04:38:23 PM PDT 24
Finished Aug 09 04:38:44 PM PDT 24
Peak memory 269560 kb
Host smart-1cf81caf-6412-4a46-bf86-46b1f4fd69f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1373989962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1373989962
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.1928107801
Short name T24
Test name
Test status
Simulation time 263818490193 ps
CPU time 7448.46 seconds
Started Aug 09 04:39:08 PM PDT 24
Finished Aug 09 06:43:17 PM PDT 24
Peak memory 402664 kb
Host smart-e20869a1-88a2-4fc7-b519-985a9317b2f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928107801 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.1928107801
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1356998944
Short name T159
Test name
Test status
Simulation time 4726440419 ps
CPU time 71.76 seconds
Started Aug 09 05:34:55 PM PDT 24
Finished Aug 09 05:36:07 PM PDT 24
Peak memory 239828 kb
Host smart-7c50d5b4-274d-47d1-941e-be3fa33472ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1356998944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1356998944
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.4117768566
Short name T6
Test name
Test status
Simulation time 20921745433 ps
CPU time 1066.09 seconds
Started Aug 09 04:38:56 PM PDT 24
Finished Aug 09 04:56:42 PM PDT 24
Peak memory 289008 kb
Host smart-2d2eb287-6208-46a1-a022-b1e1eb6d19bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117768566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.4117768566
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.4142861221
Short name T81
Test name
Test status
Simulation time 125390910813 ps
CPU time 1720.68 seconds
Started Aug 09 04:38:39 PM PDT 24
Finished Aug 09 05:07:20 PM PDT 24
Peak memory 272852 kb
Host smart-c2f33e95-5523-4b89-b478-5a718d6b21ec
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142861221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.4142861221
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.735322174
Short name T147
Test name
Test status
Simulation time 4453028621 ps
CPU time 575.66 seconds
Started Aug 09 05:34:30 PM PDT 24
Finished Aug 09 05:44:06 PM PDT 24
Peak memory 266676 kb
Host smart-f71dc3e6-a2d9-42f6-8c03-4ee6a4d7d671
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735322174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.735322174
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1697354097
Short name T296
Test name
Test status
Simulation time 158624216530 ps
CPU time 2691.49 seconds
Started Aug 09 04:39:15 PM PDT 24
Finished Aug 09 05:24:07 PM PDT 24
Peak memory 288380 kb
Host smart-55c1c47e-4d68-42cb-99ff-b0cd26f592a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697354097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1697354097
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1801212650
Short name T127
Test name
Test status
Simulation time 14163086252 ps
CPU time 921.13 seconds
Started Aug 09 05:34:29 PM PDT 24
Finished Aug 09 05:49:50 PM PDT 24
Peak memory 265624 kb
Host smart-2fcc7e6b-7c1e-4b84-8235-86b8f606bb4b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801212650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1801212650
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3808054541
Short name T15
Test name
Test status
Simulation time 149238591870 ps
CPU time 2426.14 seconds
Started Aug 09 04:40:00 PM PDT 24
Finished Aug 09 05:20:26 PM PDT 24
Peak memory 286708 kb
Host smart-aa50b591-9b38-4dff-ae79-728c9d369558
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808054541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3808054541
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1881358837
Short name T126
Test name
Test status
Simulation time 6822470187 ps
CPU time 204.33 seconds
Started Aug 09 05:34:45 PM PDT 24
Finished Aug 09 05:38:09 PM PDT 24
Peak memory 273272 kb
Host smart-8b1f2f36-3c2e-43dd-a01c-10d5f56cd4a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1881358837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1881358837
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1079752753
Short name T53
Test name
Test status
Simulation time 52372932903 ps
CPU time 1620.66 seconds
Started Aug 09 04:38:43 PM PDT 24
Finished Aug 09 05:05:44 PM PDT 24
Peak memory 285872 kb
Host smart-41d4ba77-df13-46f5-9217-deb9a20e5cc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079752753 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1079752753
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.3947249546
Short name T28
Test name
Test status
Simulation time 23552702386 ps
CPU time 1509.17 seconds
Started Aug 09 04:39:14 PM PDT 24
Finished Aug 09 05:04:23 PM PDT 24
Peak memory 289340 kb
Host smart-f3f79710-3dfb-48c8-80d0-2683b360407d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947249546 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.3947249546
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3687390435
Short name T121
Test name
Test status
Simulation time 15920058306 ps
CPU time 1671.85 seconds
Started Aug 09 04:39:36 PM PDT 24
Finished Aug 09 05:07:28 PM PDT 24
Peak memory 289096 kb
Host smart-3cf6efc3-236a-48d4-ae50-be130c31c0e2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687390435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3687390435
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1953565486
Short name T189
Test name
Test status
Simulation time 11959713645 ps
CPU time 244.73 seconds
Started Aug 09 05:34:33 PM PDT 24
Finished Aug 09 05:38:37 PM PDT 24
Peak memory 240688 kb
Host smart-29888d8d-b4a9-4f32-93b1-4826e7dd0b0f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1953565486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1953565486
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1936214866
Short name T115
Test name
Test status
Simulation time 11882082656 ps
CPU time 486.25 seconds
Started Aug 09 04:38:42 PM PDT 24
Finished Aug 09 04:46:48 PM PDT 24
Peak memory 248192 kb
Host smart-232907fb-8baf-40e0-9d86-b44b548b46e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936214866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1936214866
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.937887229
Short name T139
Test name
Test status
Simulation time 2152429782 ps
CPU time 206.71 seconds
Started Aug 09 05:34:39 PM PDT 24
Finished Aug 09 05:38:06 PM PDT 24
Peak memory 273696 kb
Host smart-7c338f82-e04e-4bda-be6b-8fd8823e4fdd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=937887229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.937887229
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.565363886
Short name T278
Test name
Test status
Simulation time 255412865428 ps
CPU time 3229.12 seconds
Started Aug 09 04:38:26 PM PDT 24
Finished Aug 09 05:32:15 PM PDT 24
Peak memory 289128 kb
Host smart-83659e1d-8d2e-4dcc-ba54-6e71eb859dd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565363886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.565363886
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.4141855250
Short name T161
Test name
Test status
Simulation time 61660486 ps
CPU time 1.41 seconds
Started Aug 09 05:34:57 PM PDT 24
Finished Aug 09 05:34:59 PM PDT 24
Peak memory 236696 kb
Host smart-6c6be75c-eee8-4deb-ae12-5b152122800a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4141855250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.4141855250
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2679897161
Short name T46
Test name
Test status
Simulation time 659149052593 ps
CPU time 3570.84 seconds
Started Aug 09 04:38:52 PM PDT 24
Finished Aug 09 05:38:23 PM PDT 24
Peak memory 288460 kb
Host smart-7bc0d318-7be1-42cc-8197-81d0d468f172
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679897161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2679897161
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3825207182
Short name T148
Test name
Test status
Simulation time 15173899745 ps
CPU time 1065.1 seconds
Started Aug 09 05:34:41 PM PDT 24
Finished Aug 09 05:52:27 PM PDT 24
Peak memory 265536 kb
Host smart-922f65d8-b75c-4f5a-914f-f665e1cc85d9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825207182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3825207182
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1679928784
Short name T319
Test name
Test status
Simulation time 137173989627 ps
CPU time 2414.03 seconds
Started Aug 09 04:39:04 PM PDT 24
Finished Aug 09 05:19:18 PM PDT 24
Peak memory 282980 kb
Host smart-d8a36ef9-7911-465b-afd7-bf23eba2deb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679928784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1679928784
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3024457831
Short name T68
Test name
Test status
Simulation time 74352551954 ps
CPU time 2468.28 seconds
Started Aug 09 04:38:14 PM PDT 24
Finished Aug 09 05:19:23 PM PDT 24
Peak memory 288528 kb
Host smart-0045639d-b5f7-4eee-a40c-8ec51c5a9a2d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024457831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3024457831
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2234001807
Short name T152
Test name
Test status
Simulation time 134627112345 ps
CPU time 1095.54 seconds
Started Aug 09 05:34:29 PM PDT 24
Finished Aug 09 05:52:45 PM PDT 24
Peak memory 265712 kb
Host smart-3b9e3b53-3833-4f3c-a776-eba10c66d427
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234001807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2234001807
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.558999614
Short name T71
Test name
Test status
Simulation time 84577150721 ps
CPU time 560.57 seconds
Started Aug 09 04:39:46 PM PDT 24
Finished Aug 09 04:49:06 PM PDT 24
Peak memory 247104 kb
Host smart-46389d5b-5597-4ed9-ad79-e6bac1b57ced
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558999614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.558999614
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1925410017
Short name T72
Test name
Test status
Simulation time 13422749946 ps
CPU time 536.34 seconds
Started Aug 09 04:40:06 PM PDT 24
Finished Aug 09 04:49:03 PM PDT 24
Peak memory 247100 kb
Host smart-d8a7f4f5-b859-4fbb-9e4f-28a6aeb593cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925410017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1925410017
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1032445566
Short name T122
Test name
Test status
Simulation time 2778156460 ps
CPU time 237.52 seconds
Started Aug 09 05:34:37 PM PDT 24
Finished Aug 09 05:38:35 PM PDT 24
Peak memory 265488 kb
Host smart-b35d9a5b-e118-4ced-af72-a93a2e84449c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1032445566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1032445566
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.29140052
Short name T324
Test name
Test status
Simulation time 162569036833 ps
CPU time 2392.91 seconds
Started Aug 09 04:38:37 PM PDT 24
Finished Aug 09 05:18:30 PM PDT 24
Peak memory 288964 kb
Host smart-a2441355-84b1-411b-9e20-44a99bc6cfb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29140052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.29140052
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.885956745
Short name T131
Test name
Test status
Simulation time 12715062749 ps
CPU time 1006.23 seconds
Started Aug 09 05:34:51 PM PDT 24
Finished Aug 09 05:51:37 PM PDT 24
Peak memory 265676 kb
Host smart-31b6b783-43fa-4877-af3d-8f68e6dc6632
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885956745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.885956745
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2283164157
Short name T292
Test name
Test status
Simulation time 13617387974 ps
CPU time 462.28 seconds
Started Aug 09 04:38:48 PM PDT 24
Finished Aug 09 04:46:31 PM PDT 24
Peak memory 248072 kb
Host smart-f1b7112e-58cb-431f-a6b2-6e83f97ecf91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283164157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2283164157
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2394961657
Short name T69
Test name
Test status
Simulation time 28803703226 ps
CPU time 1674.36 seconds
Started Aug 09 04:38:52 PM PDT 24
Finished Aug 09 05:06:46 PM PDT 24
Peak memory 272764 kb
Host smart-011f5a1d-5a37-4152-b9b3-9c751983984a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394961657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2394961657
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3831359821
Short name T125
Test name
Test status
Simulation time 19484241497 ps
CPU time 198.78 seconds
Started Aug 09 05:34:56 PM PDT 24
Finished Aug 09 05:38:14 PM PDT 24
Peak memory 272640 kb
Host smart-04876b75-6159-48e8-8ad8-7856f1cc9798
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3831359821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3831359821
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.527943840
Short name T252
Test name
Test status
Simulation time 435579810962 ps
CPU time 10214.1 seconds
Started Aug 09 04:40:18 PM PDT 24
Finished Aug 09 07:30:33 PM PDT 24
Peak memory 363100 kb
Host smart-0c95b690-a262-404b-a82e-480b389c0201
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527943840 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.527943840
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2331841416
Short name T227
Test name
Test status
Simulation time 41113411568 ps
CPU time 2781.65 seconds
Started Aug 09 04:39:34 PM PDT 24
Finished Aug 09 05:25:56 PM PDT 24
Peak memory 288744 kb
Host smart-5a6dfdd0-632f-4d0b-bd54-512186f2e186
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331841416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2331841416
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1073872609
Short name T267
Test name
Test status
Simulation time 295534579235 ps
CPU time 4008.41 seconds
Started Aug 09 04:40:25 PM PDT 24
Finished Aug 09 05:47:14 PM PDT 24
Peak memory 297268 kb
Host smart-7ec9c01f-4789-4021-834a-ae4a87eaf582
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073872609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1073872609
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1176845657
Short name T347
Test name
Test status
Simulation time 10458660 ps
CPU time 1.43 seconds
Started Aug 09 05:34:42 PM PDT 24
Finished Aug 09 05:34:44 PM PDT 24
Peak memory 237632 kb
Host smart-d88efba5-f976-4ea0-8afa-e8d0f636881b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1176845657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1176845657
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2059886145
Short name T670
Test name
Test status
Simulation time 15067052314 ps
CPU time 522.25 seconds
Started Aug 09 04:39:59 PM PDT 24
Finished Aug 09 04:48:42 PM PDT 24
Peak memory 248264 kb
Host smart-e5d1b416-802f-46dc-b746-c434c2896999
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059886145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2059886145
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.1864970238
Short name T49
Test name
Test status
Simulation time 49684625544 ps
CPU time 5236.9 seconds
Started Aug 09 04:38:52 PM PDT 24
Finished Aug 09 06:06:10 PM PDT 24
Peak memory 353840 kb
Host smart-4a3eeb79-f476-4d5a-ac55-8f5a2b8f849f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864970238 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.1864970238
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2650363895
Short name T254
Test name
Test status
Simulation time 219706366724 ps
CPU time 3324.36 seconds
Started Aug 09 04:39:27 PM PDT 24
Finished Aug 09 05:34:51 PM PDT 24
Peak memory 301592 kb
Host smart-c141024e-8edd-4fff-b000-ed9978beb8e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650363895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2650363895
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3263020394
Short name T298
Test name
Test status
Simulation time 99433153104 ps
CPU time 2969.42 seconds
Started Aug 09 04:38:24 PM PDT 24
Finished Aug 09 05:27:54 PM PDT 24
Peak memory 289240 kb
Host smart-14700ec4-edda-477d-aab4-833faf0da1f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263020394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3263020394
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.122772541
Short name T137
Test name
Test status
Simulation time 6424965988 ps
CPU time 206.7 seconds
Started Aug 09 05:34:34 PM PDT 24
Finished Aug 09 05:38:01 PM PDT 24
Peak memory 265644 kb
Host smart-401e5076-2145-4d60-9a05-8def68253cc5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=122772541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.122772541
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1362210164
Short name T307
Test name
Test status
Simulation time 44805767383 ps
CPU time 495.39 seconds
Started Aug 09 04:39:37 PM PDT 24
Finished Aug 09 04:47:53 PM PDT 24
Peak memory 248076 kb
Host smart-366d9929-17ac-4b92-b241-e4bed9711b36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362210164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1362210164
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.949454716
Short name T357
Test name
Test status
Simulation time 4368260384 ps
CPU time 316.45 seconds
Started Aug 09 05:34:49 PM PDT 24
Finished Aug 09 05:40:05 PM PDT 24
Peak memory 265456 kb
Host smart-5054ac53-e121-4100-ab09-f6642d68bb13
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949454716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.949454716
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2525302910
Short name T26
Test name
Test status
Simulation time 4463781611 ps
CPU time 216.09 seconds
Started Aug 09 04:39:04 PM PDT 24
Finished Aug 09 04:42:40 PM PDT 24
Peak memory 252900 kb
Host smart-4074551c-1313-4cc8-b8e5-a95b6cda910c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525302910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2525302910
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3927406782
Short name T253
Test name
Test status
Simulation time 557728743 ps
CPU time 34.12 seconds
Started Aug 09 04:38:52 PM PDT 24
Finished Aug 09 04:39:27 PM PDT 24
Peak memory 255436 kb
Host smart-b6fe27bd-9a14-4f9e-9dcd-d1b0eb647ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39274
06782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3927406782
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.47414297
Short name T284
Test name
Test status
Simulation time 52088869978 ps
CPU time 2836.71 seconds
Started Aug 09 04:38:51 PM PDT 24
Finished Aug 09 05:26:08 PM PDT 24
Peak memory 288340 kb
Host smart-df410982-8f44-4fd9-a0d1-1a213184bb10
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47414297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_hand
ler_stress_all.47414297
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.288085888
Short name T318
Test name
Test status
Simulation time 12816301784 ps
CPU time 519.82 seconds
Started Aug 09 04:39:16 PM PDT 24
Finished Aug 09 04:47:56 PM PDT 24
Peak memory 248068 kb
Host smart-95291c77-7450-4b92-b551-7e70ec31bcbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288085888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.288085888
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.4027955457
Short name T276
Test name
Test status
Simulation time 153582907457 ps
CPU time 2736.26 seconds
Started Aug 09 04:39:53 PM PDT 24
Finished Aug 09 05:25:30 PM PDT 24
Peak memory 288984 kb
Host smart-13b0e5d7-8fbb-450c-925e-a12f6a483d7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027955457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.4027955457
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2641566206
Short name T158
Test name
Test status
Simulation time 119140378 ps
CPU time 3.06 seconds
Started Aug 09 05:34:37 PM PDT 24
Finished Aug 09 05:34:41 PM PDT 24
Peak memory 238640 kb
Host smart-9aec934d-9334-4d04-b755-a3bbe266f33f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2641566206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2641566206
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3679657134
Short name T128
Test name
Test status
Simulation time 1756891408 ps
CPU time 101.83 seconds
Started Aug 09 05:34:44 PM PDT 24
Finished Aug 09 05:36:26 PM PDT 24
Peak memory 257260 kb
Host smart-e3327580-942a-47f4-8f2e-492d0151c54b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3679657134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3679657134
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3024034863
Short name T216
Test name
Test status
Simulation time 44379649 ps
CPU time 3.82 seconds
Started Aug 09 04:38:30 PM PDT 24
Finished Aug 09 04:38:34 PM PDT 24
Peak memory 248496 kb
Host smart-2644edec-8eff-40d7-8eb8-72be0a6a8197
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3024034863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3024034863
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3878402885
Short name T214
Test name
Test status
Simulation time 47092907 ps
CPU time 3.97 seconds
Started Aug 09 04:38:19 PM PDT 24
Finished Aug 09 04:38:23 PM PDT 24
Peak memory 248428 kb
Host smart-72e7ded6-8935-4415-98b0-b015d7aa7d5f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3878402885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3878402885
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3916819078
Short name T208
Test name
Test status
Simulation time 29436576 ps
CPU time 2.57 seconds
Started Aug 09 04:38:47 PM PDT 24
Finished Aug 09 04:38:49 PM PDT 24
Peak memory 248568 kb
Host smart-e085a530-44e8-4956-92eb-cc5084b650b7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3916819078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3916819078
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.4268336519
Short name T219
Test name
Test status
Simulation time 63692245 ps
CPU time 2.98 seconds
Started Aug 09 04:38:53 PM PDT 24
Finished Aug 09 04:38:57 PM PDT 24
Peak memory 248344 kb
Host smart-b9576606-6eaf-4948-8b19-67efb093b4c6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4268336519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.4268336519
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2691882048
Short name T733
Test name
Test status
Simulation time 14678856 ps
CPU time 1.61 seconds
Started Aug 09 05:35:00 PM PDT 24
Finished Aug 09 05:35:02 PM PDT 24
Peak memory 236688 kb
Host smart-25a55c48-eb47-42ff-8126-832e3210193f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2691882048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2691882048
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2262248994
Short name T334
Test name
Test status
Simulation time 126186283709 ps
CPU time 3140.98 seconds
Started Aug 09 04:38:59 PM PDT 24
Finished Aug 09 05:31:20 PM PDT 24
Peak memory 288252 kb
Host smart-50491f11-2641-47f5-ae73-578f778cc54b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262248994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2262248994
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1801668570
Short name T275
Test name
Test status
Simulation time 5678829056 ps
CPU time 23.35 seconds
Started Aug 09 04:39:10 PM PDT 24
Finished Aug 09 04:39:33 PM PDT 24
Peak memory 247576 kb
Host smart-89a230ba-b4b7-4120-8c13-978bb55f83cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18016
68570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1801668570
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2087485023
Short name T241
Test name
Test status
Simulation time 35457096956 ps
CPU time 2366.99 seconds
Started Aug 09 04:39:31 PM PDT 24
Finished Aug 09 05:18:58 PM PDT 24
Peak memory 289096 kb
Host smart-b7fe2bcf-522b-4d04-8e99-d71df4402eef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087485023 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2087485023
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.547468442
Short name T85
Test name
Test status
Simulation time 2854990435 ps
CPU time 24.18 seconds
Started Aug 09 04:40:14 PM PDT 24
Finished Aug 09 04:40:38 PM PDT 24
Peak memory 247952 kb
Host smart-b9af3394-c50b-4bc0-9bbe-987bb413e740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54746
8442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.547468442
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2510163324
Short name T149
Test name
Test status
Simulation time 6501962218 ps
CPU time 117.5 seconds
Started Aug 09 05:35:00 PM PDT 24
Finished Aug 09 05:36:57 PM PDT 24
Peak memory 267116 kb
Host smart-620040be-e7db-4537-8a64-efd19a96edee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2510163324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2510163324
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.278967224
Short name T178
Test name
Test status
Simulation time 2572088552 ps
CPU time 85.07 seconds
Started Aug 09 05:34:32 PM PDT 24
Finished Aug 09 05:35:58 PM PDT 24
Peak memory 240648 kb
Host smart-106a897d-be85-442f-bc16-d40e05b8ea31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=278967224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.278967224
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2219500849
Short name T56
Test name
Test status
Simulation time 392127364847 ps
CPU time 1676.45 seconds
Started Aug 09 04:38:49 PM PDT 24
Finished Aug 09 05:06:46 PM PDT 24
Peak memory 282564 kb
Host smart-09b7dfb5-7cbb-4c67-8931-c7dcc45bdcd4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219500849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2219500849
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.313444560
Short name T119
Test name
Test status
Simulation time 27763903436 ps
CPU time 1120.71 seconds
Started Aug 09 04:38:49 PM PDT 24
Finished Aug 09 04:57:30 PM PDT 24
Peak memory 288188 kb
Host smart-60693e01-44f7-49d6-b6a7-2e4cd646244b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313444560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.313444560
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.465851260
Short name T259
Test name
Test status
Simulation time 123391513969 ps
CPU time 6573.78 seconds
Started Aug 09 04:38:56 PM PDT 24
Finished Aug 09 06:28:30 PM PDT 24
Peak memory 354180 kb
Host smart-a5dc7e53-b589-4937-a907-7925ffc1f3ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465851260 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.465851260
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.300455434
Short name T294
Test name
Test status
Simulation time 10906296995 ps
CPU time 1109.61 seconds
Started Aug 09 04:38:10 PM PDT 24
Finished Aug 09 04:56:40 PM PDT 24
Peak memory 272744 kb
Host smart-76720979-009c-4f5a-953b-4df652d9854d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300455434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.300455434
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2913569834
Short name T311
Test name
Test status
Simulation time 54473275012 ps
CPU time 554.64 seconds
Started Aug 09 04:38:20 PM PDT 24
Finished Aug 09 04:47:34 PM PDT 24
Peak memory 248224 kb
Host smart-d702265b-527e-4fda-91e8-bb821339d3d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913569834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2913569834
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.3120564921
Short name T91
Test name
Test status
Simulation time 115683454136 ps
CPU time 5267.82 seconds
Started Aug 09 04:38:58 PM PDT 24
Finished Aug 09 06:06:47 PM PDT 24
Peak memory 350748 kb
Host smart-c710ee74-07e8-43f7-88c1-fa57210b415d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120564921 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.3120564921
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3408909345
Short name T268
Test name
Test status
Simulation time 347166531 ps
CPU time 23.37 seconds
Started Aug 09 04:39:11 PM PDT 24
Finished Aug 09 04:39:34 PM PDT 24
Peak memory 247524 kb
Host smart-1549b70e-1195-4e82-8584-994967d788bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34089
09345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3408909345
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.507694742
Short name T255
Test name
Test status
Simulation time 735865034 ps
CPU time 46.44 seconds
Started Aug 09 04:39:39 PM PDT 24
Finished Aug 09 04:40:26 PM PDT 24
Peak memory 255732 kb
Host smart-e2c7352b-1bce-4876-80cf-21283a348061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50769
4742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.507694742
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.793290012
Short name T260
Test name
Test status
Simulation time 38066918137 ps
CPU time 2513.27 seconds
Started Aug 09 04:39:46 PM PDT 24
Finished Aug 09 05:21:39 PM PDT 24
Peak memory 288992 kb
Host smart-d224e34f-2482-4466-853d-96941627198d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793290012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.793290012
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.442390048
Short name T274
Test name
Test status
Simulation time 17045587602 ps
CPU time 223.31 seconds
Started Aug 09 04:38:28 PM PDT 24
Finished Aug 09 04:42:11 PM PDT 24
Peak memory 256352 kb
Host smart-755cbfc0-884b-44f9-a21e-938fb3704a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44239
0048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.442390048
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.746944110
Short name T168
Test name
Test status
Simulation time 145993498 ps
CPU time 2.46 seconds
Started Aug 09 05:34:44 PM PDT 24
Finished Aug 09 05:34:47 PM PDT 24
Peak memory 238044 kb
Host smart-4b6f4081-8550-46e2-91ab-58bf7b5b6461
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=746944110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.746944110
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.563024969
Short name T133
Test name
Test status
Simulation time 7220527457 ps
CPU time 194.36 seconds
Started Aug 09 05:34:46 PM PDT 24
Finished Aug 09 05:38:00 PM PDT 24
Peak memory 265732 kb
Host smart-7622c1be-7a81-4c4f-8b9a-444ca8bc5930
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=563024969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.563024969
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1099403202
Short name T164
Test name
Test status
Simulation time 551588395 ps
CPU time 53.93 seconds
Started Aug 09 05:34:56 PM PDT 24
Finished Aug 09 05:35:50 PM PDT 24
Peak memory 240536 kb
Host smart-d9240e4d-c8ea-4fe7-86e2-7bbac83dce11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1099403202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1099403202
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1964558490
Short name T165
Test name
Test status
Simulation time 321891657 ps
CPU time 3.81 seconds
Started Aug 09 05:35:12 PM PDT 24
Finished Aug 09 05:35:16 PM PDT 24
Peak memory 237784 kb
Host smart-a5ffd07b-64cf-4da3-8985-34e4c850ee7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1964558490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1964558490
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2878488420
Short name T167
Test name
Test status
Simulation time 1800596421 ps
CPU time 32.25 seconds
Started Aug 09 05:34:47 PM PDT 24
Finished Aug 09 05:35:19 PM PDT 24
Peak memory 240576 kb
Host smart-89dc5be7-0f71-41c0-903e-f32b4619a33a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2878488420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2878488420
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3987934221
Short name T172
Test name
Test status
Simulation time 129412861 ps
CPU time 6.39 seconds
Started Aug 09 05:34:55 PM PDT 24
Finished Aug 09 05:35:02 PM PDT 24
Peak memory 237920 kb
Host smart-a36ee69a-1973-4a3d-bbfa-072f088531f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3987934221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3987934221
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1975461190
Short name T150
Test name
Test status
Simulation time 1732455717 ps
CPU time 127.34 seconds
Started Aug 09 05:34:33 PM PDT 24
Finished Aug 09 05:36:40 PM PDT 24
Peak memory 265544 kb
Host smart-971d33a5-8d4f-4748-a120-c78c56c8ec27
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1975461190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1975461190
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2938782915
Short name T166
Test name
Test status
Simulation time 178248218 ps
CPU time 22.92 seconds
Started Aug 09 05:34:38 PM PDT 24
Finished Aug 09 05:35:01 PM PDT 24
Peak memory 246008 kb
Host smart-265dfb0f-acb8-4189-8c98-15123e180ce3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2938782915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2938782915
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1440761666
Short name T169
Test name
Test status
Simulation time 307387498 ps
CPU time 21.39 seconds
Started Aug 09 05:34:41 PM PDT 24
Finished Aug 09 05:35:03 PM PDT 24
Peak memory 240548 kb
Host smart-be3016df-ed0b-45be-9c49-13c7854eedbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1440761666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1440761666
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.4109050265
Short name T62
Test name
Test status
Simulation time 11796002142 ps
CPU time 1332.75 seconds
Started Aug 09 04:38:47 PM PDT 24
Finished Aug 09 05:01:00 PM PDT 24
Peak memory 288788 kb
Host smart-9cd98d9e-fa19-4c20-998b-5c96c2c84d28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109050265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.4109050265
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1034330278
Short name T175
Test name
Test status
Simulation time 610502398 ps
CPU time 22.88 seconds
Started Aug 09 05:34:30 PM PDT 24
Finished Aug 09 05:34:53 PM PDT 24
Peak memory 239828 kb
Host smart-b2cd58e5-0f58-4c84-9789-cac00d0c7348
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1034330278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1034330278
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1205661554
Short name T177
Test name
Test status
Simulation time 50879007 ps
CPU time 2.03 seconds
Started Aug 09 05:34:53 PM PDT 24
Finished Aug 09 05:34:55 PM PDT 24
Peak memory 237900 kb
Host smart-84b6a3b8-ba96-4ece-b3ad-54bdd183d68e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1205661554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1205661554
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3877391623
Short name T170
Test name
Test status
Simulation time 35797748 ps
CPU time 3.05 seconds
Started Aug 09 05:34:49 PM PDT 24
Finished Aug 09 05:34:52 PM PDT 24
Peak memory 237916 kb
Host smart-5969c6a9-c4ea-472a-8800-b52dda50d543
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3877391623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3877391623
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1899293519
Short name T171
Test name
Test status
Simulation time 408323372 ps
CPU time 47 seconds
Started Aug 09 05:34:24 PM PDT 24
Finished Aug 09 05:35:11 PM PDT 24
Peak memory 240600 kb
Host smart-712d21b5-7fc3-4531-8c9d-0042941d1366
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1899293519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1899293519
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2109444834
Short name T176
Test name
Test status
Simulation time 1254212134 ps
CPU time 27.18 seconds
Started Aug 09 05:34:41 PM PDT 24
Finished Aug 09 05:35:09 PM PDT 24
Peak memory 240540 kb
Host smart-d01f6c71-7c61-441e-8053-f72e433c2d98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2109444834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2109444834
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1461291949
Short name T25
Test name
Test status
Simulation time 17599782487 ps
CPU time 1700.33 seconds
Started Aug 09 04:39:02 PM PDT 24
Finished Aug 09 05:07:22 PM PDT 24
Peak memory 289160 kb
Host smart-4a8aea03-10ee-40ba-8bd3-d58dfe35c810
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461291949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1461291949
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2875242784
Short name T21
Test name
Test status
Simulation time 17469203987 ps
CPU time 805.69 seconds
Started Aug 09 04:38:58 PM PDT 24
Finished Aug 09 04:52:24 PM PDT 24
Peak memory 281348 kb
Host smart-a4c453ae-de10-4979-8319-4e1ebb587b07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875242784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2875242784
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1615748634
Short name T22
Test name
Test status
Simulation time 161099058980 ps
CPU time 1358.27 seconds
Started Aug 09 04:40:06 PM PDT 24
Finished Aug 09 05:02:45 PM PDT 24
Peak memory 284580 kb
Host smart-b009d5ea-a77b-49de-882f-6ee955bda27d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615748634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1615748634
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3138831410
Short name T812
Test name
Test status
Simulation time 20864588922 ps
CPU time 253.62 seconds
Started Aug 09 05:34:23 PM PDT 24
Finished Aug 09 05:38:37 PM PDT 24
Peak memory 240884 kb
Host smart-6a4a8d01-42be-471a-8aa8-068601f0128f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3138831410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3138831410
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2228976187
Short name T834
Test name
Test status
Simulation time 32903439851 ps
CPU time 488.77 seconds
Started Aug 09 05:34:23 PM PDT 24
Finished Aug 09 05:42:32 PM PDT 24
Peak memory 237692 kb
Host smart-414148f1-9e4e-4410-b0c2-8ffb6d082042
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2228976187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2228976187
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.780772460
Short name T791
Test name
Test status
Simulation time 40079951 ps
CPU time 6.5 seconds
Started Aug 09 05:34:21 PM PDT 24
Finished Aug 09 05:34:28 PM PDT 24
Peak memory 249476 kb
Host smart-33060349-a1af-4776-ba1e-ea857d95c393
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=780772460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.780772460
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1031391017
Short name T769
Test name
Test status
Simulation time 735024408 ps
CPU time 9.65 seconds
Started Aug 09 05:34:37 PM PDT 24
Finished Aug 09 05:34:46 PM PDT 24
Peak memory 240656 kb
Host smart-3cb87b57-9c56-418c-b524-8b1075646958
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031391017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1031391017
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.4161752715
Short name T191
Test name
Test status
Simulation time 262818985 ps
CPU time 5.35 seconds
Started Aug 09 05:34:31 PM PDT 24
Finished Aug 09 05:34:36 PM PDT 24
Peak memory 237552 kb
Host smart-f1f4eea4-8165-44ce-bc7e-668295cfc4f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4161752715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.4161752715
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1949709272
Short name T829
Test name
Test status
Simulation time 9149767 ps
CPU time 1.61 seconds
Started Aug 09 05:34:23 PM PDT 24
Finished Aug 09 05:34:25 PM PDT 24
Peak memory 236672 kb
Host smart-573ddefa-27c8-44f3-b991-bdbaf57ae2d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1949709272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1949709272
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3537648342
Short name T833
Test name
Test status
Simulation time 1894381738 ps
CPU time 37.49 seconds
Started Aug 09 05:34:32 PM PDT 24
Finished Aug 09 05:35:10 PM PDT 24
Peak memory 245780 kb
Host smart-c39f3ea6-3b34-490b-9231-927fc00221ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3537648342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3537648342
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.748363494
Short name T156
Test name
Test status
Simulation time 8098095058 ps
CPU time 331.37 seconds
Started Aug 09 05:34:25 PM PDT 24
Finished Aug 09 05:39:57 PM PDT 24
Peak memory 265572 kb
Host smart-1dfb8d0e-378c-48eb-90d0-6e2ba114b9b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=748363494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.748363494
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.166569359
Short name T138
Test name
Test status
Simulation time 49810853285 ps
CPU time 954.91 seconds
Started Aug 09 05:35:37 PM PDT 24
Finished Aug 09 05:51:32 PM PDT 24
Peak memory 265420 kb
Host smart-b27ff4da-6375-4e58-8580-502637f81cb8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166569359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.166569359
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1911690278
Short name T745
Test name
Test status
Simulation time 521840765 ps
CPU time 13.23 seconds
Started Aug 09 05:34:38 PM PDT 24
Finished Aug 09 05:34:51 PM PDT 24
Peak memory 248856 kb
Host smart-0b70dc22-ce1a-4f99-931e-1be5125d82ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1911690278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1911690278
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2415912284
Short name T803
Test name
Test status
Simulation time 12664086731 ps
CPU time 248.65 seconds
Started Aug 09 05:34:33 PM PDT 24
Finished Aug 09 05:38:42 PM PDT 24
Peak memory 241436 kb
Host smart-0f17ebf4-510d-4a19-9099-2aa6a1499b2c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2415912284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2415912284
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.523968529
Short name T775
Test name
Test status
Simulation time 1638627112 ps
CPU time 192.73 seconds
Started Aug 09 05:35:37 PM PDT 24
Finished Aug 09 05:38:49 PM PDT 24
Peak memory 237512 kb
Host smart-ac4f817d-a63e-4f74-955f-6fe88968f2b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=523968529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.523968529
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2339500521
Short name T792
Test name
Test status
Simulation time 90126703 ps
CPU time 6.41 seconds
Started Aug 09 05:34:32 PM PDT 24
Finished Aug 09 05:34:39 PM PDT 24
Peak memory 248776 kb
Host smart-13d7ccdf-901c-44a2-aa96-e12ae2f7273b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2339500521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2339500521
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1185997314
Short name T358
Test name
Test status
Simulation time 106808623 ps
CPU time 8.27 seconds
Started Aug 09 05:34:31 PM PDT 24
Finished Aug 09 05:34:39 PM PDT 24
Peak memory 252884 kb
Host smart-a6f738fa-9f5e-41e8-8483-f312e1656fe6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185997314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1185997314
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2319698392
Short name T807
Test name
Test status
Simulation time 29536147 ps
CPU time 3.93 seconds
Started Aug 09 05:34:40 PM PDT 24
Finished Aug 09 05:34:44 PM PDT 24
Peak memory 240516 kb
Host smart-846ff5f3-2651-427c-9adc-ae688bc20d41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2319698392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2319698392
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.889397696
Short name T344
Test name
Test status
Simulation time 9356560 ps
CPU time 1.36 seconds
Started Aug 09 05:34:24 PM PDT 24
Finished Aug 09 05:34:25 PM PDT 24
Peak memory 236840 kb
Host smart-c1ab051d-3896-40f8-ba18-6252f199d5b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=889397696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.889397696
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3342798245
Short name T753
Test name
Test status
Simulation time 96462766 ps
CPU time 13.02 seconds
Started Aug 09 05:34:38 PM PDT 24
Finished Aug 09 05:34:51 PM PDT 24
Peak memory 240520 kb
Host smart-10232746-3b58-4afa-9cb9-5bfa64113173
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3342798245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3342798245
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.4036776516
Short name T124
Test name
Test status
Simulation time 3249322394 ps
CPU time 91.86 seconds
Started Aug 09 05:34:39 PM PDT 24
Finished Aug 09 05:36:10 PM PDT 24
Peak memory 265516 kb
Host smart-58981869-9c4b-408b-8726-089bae7808a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4036776516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.4036776516
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.777851939
Short name T802
Test name
Test status
Simulation time 423693126 ps
CPU time 17.16 seconds
Started Aug 09 05:34:32 PM PDT 24
Finished Aug 09 05:34:49 PM PDT 24
Peak memory 248256 kb
Host smart-9b09800f-5b53-435a-8225-66d8e7aa954e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=777851939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.777851939
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1153016717
Short name T201
Test name
Test status
Simulation time 42821278 ps
CPU time 3.3 seconds
Started Aug 09 05:34:49 PM PDT 24
Finished Aug 09 05:34:53 PM PDT 24
Peak memory 248800 kb
Host smart-0417bf9c-9c7a-449b-8778-0118d55ff4ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153016717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1153016717
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3530698329
Short name T174
Test name
Test status
Simulation time 67108606 ps
CPU time 5.37 seconds
Started Aug 09 05:34:42 PM PDT 24
Finished Aug 09 05:34:47 PM PDT 24
Peak memory 237580 kb
Host smart-2d7a0264-861a-4934-9173-701d0dd30f61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3530698329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3530698329
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1908393018
Short name T818
Test name
Test status
Simulation time 8598364 ps
CPU time 1.55 seconds
Started Aug 09 05:34:41 PM PDT 24
Finished Aug 09 05:34:48 PM PDT 24
Peak memory 237640 kb
Host smart-fb3490c0-bb6b-4f8b-ab84-a3aedbd164c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1908393018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1908393018
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3149320529
Short name T192
Test name
Test status
Simulation time 1053940162 ps
CPU time 34.04 seconds
Started Aug 09 05:34:57 PM PDT 24
Finished Aug 09 05:35:36 PM PDT 24
Peak memory 244916 kb
Host smart-3f9aac07-ae60-460f-9efd-ff3be4a8ccbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3149320529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3149320529
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.802531576
Short name T135
Test name
Test status
Simulation time 27361469290 ps
CPU time 277.44 seconds
Started Aug 09 05:34:39 PM PDT 24
Finished Aug 09 05:39:17 PM PDT 24
Peak memory 265580 kb
Host smart-3d959365-5274-40e6-9d70-ed605d1e08e5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802531576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.802531576
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.935375838
Short name T821
Test name
Test status
Simulation time 571284046 ps
CPU time 10.47 seconds
Started Aug 09 05:34:52 PM PDT 24
Finished Aug 09 05:35:02 PM PDT 24
Peak memory 248780 kb
Host smart-abcd0a80-3189-435d-8909-052fc5137047
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=935375838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.935375838
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.413606835
Short name T160
Test name
Test status
Simulation time 31586283 ps
CPU time 2.79 seconds
Started Aug 09 05:34:40 PM PDT 24
Finished Aug 09 05:34:43 PM PDT 24
Peak memory 238692 kb
Host smart-9d616e66-4a61-44fc-b758-d86eb70ee09b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=413606835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.413606835
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1357601088
Short name T787
Test name
Test status
Simulation time 133796189 ps
CPU time 9.22 seconds
Started Aug 09 05:34:47 PM PDT 24
Finished Aug 09 05:34:56 PM PDT 24
Peak memory 240684 kb
Host smart-c1a74dbe-5aba-4caf-9e6c-8f8cad827267
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357601088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1357601088
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1942749517
Short name T814
Test name
Test status
Simulation time 165658750 ps
CPU time 2.9 seconds
Started Aug 09 05:35:02 PM PDT 24
Finished Aug 09 05:35:05 PM PDT 24
Peak memory 239460 kb
Host smart-ee36ef2d-f020-4a6a-a2c0-eebd772100f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1942749517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1942749517
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2046854793
Short name T194
Test name
Test status
Simulation time 1978374375 ps
CPU time 34.72 seconds
Started Aug 09 05:34:44 PM PDT 24
Finished Aug 09 05:35:18 PM PDT 24
Peak memory 245732 kb
Host smart-4bae6a2e-ed50-4893-9c6e-2c3164258380
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2046854793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2046854793
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.786612814
Short name T734
Test name
Test status
Simulation time 124319402 ps
CPU time 9.49 seconds
Started Aug 09 05:34:38 PM PDT 24
Finished Aug 09 05:34:48 PM PDT 24
Peak memory 255396 kb
Host smart-4bd70386-f55c-4488-8118-2feca4eae11f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=786612814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.786612814
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1217619058
Short name T794
Test name
Test status
Simulation time 111396381 ps
CPU time 2.67 seconds
Started Aug 09 05:34:55 PM PDT 24
Finished Aug 09 05:34:58 PM PDT 24
Peak memory 237680 kb
Host smart-841138e0-410c-441d-9cf0-29e5adf8faa7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1217619058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1217619058
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.835940243
Short name T822
Test name
Test status
Simulation time 114101175 ps
CPU time 5.09 seconds
Started Aug 09 05:34:40 PM PDT 24
Finished Aug 09 05:34:45 PM PDT 24
Peak memory 256948 kb
Host smart-7f349740-f3ac-4ae3-a878-e8c08101d644
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835940243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.835940243
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.243160821
Short name T826
Test name
Test status
Simulation time 120727111 ps
CPU time 5.22 seconds
Started Aug 09 05:34:54 PM PDT 24
Finished Aug 09 05:34:59 PM PDT 24
Peak memory 240520 kb
Host smart-fd5f3933-37d3-46f9-8e99-04586681a563
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=243160821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.243160821
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2807054160
Short name T778
Test name
Test status
Simulation time 7811557 ps
CPU time 1.34 seconds
Started Aug 09 05:34:41 PM PDT 24
Finished Aug 09 05:34:43 PM PDT 24
Peak memory 236960 kb
Host smart-426b571e-96dd-4604-b53c-21ea36775235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2807054160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2807054160
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1204340924
Short name T746
Test name
Test status
Simulation time 2640892165 ps
CPU time 37.17 seconds
Started Aug 09 05:34:49 PM PDT 24
Finished Aug 09 05:35:26 PM PDT 24
Peak memory 248868 kb
Host smart-297b6b86-0d4d-4f7c-bd19-f203f5b6330f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1204340924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1204340924
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1642940801
Short name T145
Test name
Test status
Simulation time 2479365129 ps
CPU time 165.76 seconds
Started Aug 09 05:34:33 PM PDT 24
Finished Aug 09 05:37:19 PM PDT 24
Peak memory 265500 kb
Host smart-2f656a91-a5ea-4b14-b43c-9c1f703c030d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1642940801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1642940801
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.392400385
Short name T141
Test name
Test status
Simulation time 4459853806 ps
CPU time 595.78 seconds
Started Aug 09 05:35:35 PM PDT 24
Finished Aug 09 05:45:31 PM PDT 24
Peak memory 273536 kb
Host smart-4c135767-67e4-4a19-b0e7-89552c331e6e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392400385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.392400385
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.462203728
Short name T728
Test name
Test status
Simulation time 382923807 ps
CPU time 8.84 seconds
Started Aug 09 05:34:49 PM PDT 24
Finished Aug 09 05:34:58 PM PDT 24
Peak memory 248848 kb
Host smart-6180e8c1-2ec7-40c2-981a-95fd9f384eff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=462203728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.462203728
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.416030802
Short name T173
Test name
Test status
Simulation time 87284210 ps
CPU time 6.05 seconds
Started Aug 09 05:34:51 PM PDT 24
Finished Aug 09 05:34:57 PM PDT 24
Peak memory 243484 kb
Host smart-9e43af14-34a0-41a5-a864-821a37ecdc29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416030802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.416030802
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3815118059
Short name T819
Test name
Test status
Simulation time 44629025 ps
CPU time 3.08 seconds
Started Aug 09 05:34:54 PM PDT 24
Finished Aug 09 05:34:57 PM PDT 24
Peak memory 240620 kb
Host smart-b303b1ae-2745-4f75-b506-ecfd9aad6400
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3815118059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3815118059
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1800473559
Short name T345
Test name
Test status
Simulation time 17406413 ps
CPU time 1.37 seconds
Started Aug 09 05:34:46 PM PDT 24
Finished Aug 09 05:34:48 PM PDT 24
Peak memory 237656 kb
Host smart-8a68c02f-b5fd-439d-b4ad-6ae16d349156
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1800473559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1800473559
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1624354799
Short name T832
Test name
Test status
Simulation time 341713523 ps
CPU time 21.06 seconds
Started Aug 09 05:35:02 PM PDT 24
Finished Aug 09 05:35:23 PM PDT 24
Peak memory 245732 kb
Host smart-3fb9ea7f-2693-4bef-99eb-c0799835482e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1624354799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1624354799
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2940470791
Short name T154
Test name
Test status
Simulation time 15963082212 ps
CPU time 538.18 seconds
Started Aug 09 05:34:43 PM PDT 24
Finished Aug 09 05:43:41 PM PDT 24
Peak memory 265632 kb
Host smart-33e452a7-7268-4fcc-86b5-70477315b5d1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940470791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2940470791
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3104860262
Short name T726
Test name
Test status
Simulation time 227799176 ps
CPU time 9.19 seconds
Started Aug 09 05:34:42 PM PDT 24
Finished Aug 09 05:34:52 PM PDT 24
Peak memory 248756 kb
Host smart-dc608cc6-c37c-416e-b403-40de6280f716
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3104860262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3104860262
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3543463602
Short name T772
Test name
Test status
Simulation time 357814424 ps
CPU time 12.29 seconds
Started Aug 09 05:34:50 PM PDT 24
Finished Aug 09 05:35:03 PM PDT 24
Peak memory 244312 kb
Host smart-794d56c0-f4e7-4e9b-994c-c69414dfffa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543463602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3543463602
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3263719435
Short name T349
Test name
Test status
Simulation time 96350468 ps
CPU time 7.65 seconds
Started Aug 09 05:34:58 PM PDT 24
Finished Aug 09 05:35:06 PM PDT 24
Peak memory 236772 kb
Host smart-25ef9482-4756-4326-9b85-9fb0b0ce2914
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3263719435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3263719435
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3359302473
Short name T736
Test name
Test status
Simulation time 16535739 ps
CPU time 1.4 seconds
Started Aug 09 05:34:59 PM PDT 24
Finished Aug 09 05:35:01 PM PDT 24
Peak memory 237968 kb
Host smart-6a0ac239-cea6-4344-8674-c8163ec2aabb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3359302473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3359302473
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3462904919
Short name T811
Test name
Test status
Simulation time 649311272 ps
CPU time 20.37 seconds
Started Aug 09 05:35:02 PM PDT 24
Finished Aug 09 05:35:22 PM PDT 24
Peak memory 244860 kb
Host smart-36904193-5136-4691-9294-ad6647a0bb24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3462904919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3462904919
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1245826966
Short name T783
Test name
Test status
Simulation time 420475200 ps
CPU time 7.22 seconds
Started Aug 09 05:34:39 PM PDT 24
Finished Aug 09 05:34:46 PM PDT 24
Peak memory 248740 kb
Host smart-70831bc1-4887-46b9-baca-3f499a330a3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1245826966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1245826966
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.872158496
Short name T735
Test name
Test status
Simulation time 115527709 ps
CPU time 4.84 seconds
Started Aug 09 05:35:39 PM PDT 24
Finished Aug 09 05:35:44 PM PDT 24
Peak memory 253108 kb
Host smart-869417a9-8b16-462f-ab7a-79b009438d39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872158496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.872158496
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.300861170
Short name T353
Test name
Test status
Simulation time 65659875 ps
CPU time 5.19 seconds
Started Aug 09 05:34:51 PM PDT 24
Finished Aug 09 05:34:56 PM PDT 24
Peak memory 236668 kb
Host smart-51310f8d-8bc5-4f93-9bd7-85e74aef7460
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=300861170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.300861170
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.948434133
Short name T750
Test name
Test status
Simulation time 6203857 ps
CPU time 1.42 seconds
Started Aug 09 05:34:40 PM PDT 24
Finished Aug 09 05:34:46 PM PDT 24
Peak memory 236668 kb
Host smart-8ecf4620-44e3-4583-a2c8-1654ce2d70e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=948434133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.948434133
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1029563617
Short name T785
Test name
Test status
Simulation time 2823933380 ps
CPU time 37.91 seconds
Started Aug 09 05:34:47 PM PDT 24
Finished Aug 09 05:35:30 PM PDT 24
Peak memory 245968 kb
Host smart-224da78c-35c6-4e20-96b1-7fa151ec6a53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1029563617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1029563617
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1413468377
Short name T824
Test name
Test status
Simulation time 8847581183 ps
CPU time 462.5 seconds
Started Aug 09 05:34:38 PM PDT 24
Finished Aug 09 05:42:21 PM PDT 24
Peak memory 265512 kb
Host smart-a752e72e-57c3-417a-b2e8-f64974c9b609
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413468377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1413468377
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3034298681
Short name T725
Test name
Test status
Simulation time 646635330 ps
CPU time 22.01 seconds
Started Aug 09 05:34:34 PM PDT 24
Finished Aug 09 05:34:56 PM PDT 24
Peak memory 248804 kb
Host smart-81af5ff6-0444-4ad4-86c4-044a37c051d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3034298681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3034298681
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1001346111
Short name T835
Test name
Test status
Simulation time 625123726 ps
CPU time 11.41 seconds
Started Aug 09 05:34:48 PM PDT 24
Finished Aug 09 05:34:59 PM PDT 24
Peak memory 253028 kb
Host smart-03ddb1c9-d01d-4f46-bdb5-da9aa1482d81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001346111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1001346111
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.684300045
Short name T360
Test name
Test status
Simulation time 66624508 ps
CPU time 2.92 seconds
Started Aug 09 05:34:58 PM PDT 24
Finished Aug 09 05:35:01 PM PDT 24
Peak memory 236796 kb
Host smart-1fb7c395-9973-4b44-adc3-0ff92d3c7f09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=684300045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.684300045
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.401191561
Short name T741
Test name
Test status
Simulation time 7463680 ps
CPU time 1.32 seconds
Started Aug 09 05:34:44 PM PDT 24
Finished Aug 09 05:34:46 PM PDT 24
Peak memory 236752 kb
Host smart-578247e8-260c-4c44-a66b-112de7d023c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=401191561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.401191561
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2809734609
Short name T190
Test name
Test status
Simulation time 1113859154 ps
CPU time 20.66 seconds
Started Aug 09 05:34:49 PM PDT 24
Finished Aug 09 05:35:09 PM PDT 24
Peak memory 244984 kb
Host smart-402917b5-c48a-4524-98e7-b5170bd04313
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2809734609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2809734609
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2873739816
Short name T142
Test name
Test status
Simulation time 2194711922 ps
CPU time 142.45 seconds
Started Aug 09 05:34:51 PM PDT 24
Finished Aug 09 05:37:14 PM PDT 24
Peak memory 265816 kb
Host smart-669d5e69-8e51-44c8-b30b-85f370b9b4ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2873739816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2873739816
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3379841141
Short name T136
Test name
Test status
Simulation time 8160458498 ps
CPU time 601.01 seconds
Started Aug 09 05:34:44 PM PDT 24
Finished Aug 09 05:44:45 PM PDT 24
Peak memory 265488 kb
Host smart-f88a5b5c-adb2-4894-aadc-2f50d945a76c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379841141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3379841141
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3203976127
Short name T798
Test name
Test status
Simulation time 701164601 ps
CPU time 22.68 seconds
Started Aug 09 05:35:37 PM PDT 24
Finished Aug 09 05:36:00 PM PDT 24
Peak memory 248420 kb
Host smart-a07e5ef9-59d9-4165-80f5-f049c7c1f644
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3203976127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3203976127
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.507832193
Short name T831
Test name
Test status
Simulation time 144512416 ps
CPU time 5.88 seconds
Started Aug 09 05:34:45 PM PDT 24
Finished Aug 09 05:34:51 PM PDT 24
Peak memory 239912 kb
Host smart-0d431688-c2b5-4502-bd27-3bc5b92762e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507832193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.507832193
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1670513668
Short name T781
Test name
Test status
Simulation time 217685754 ps
CPU time 8.91 seconds
Started Aug 09 05:35:36 PM PDT 24
Finished Aug 09 05:35:45 PM PDT 24
Peak memory 240460 kb
Host smart-b20eab2a-7cc7-4184-a032-d6527ae4443d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1670513668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1670513668
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.640692348
Short name T767
Test name
Test status
Simulation time 6453124 ps
CPU time 1.44 seconds
Started Aug 09 05:34:56 PM PDT 24
Finished Aug 09 05:34:58 PM PDT 24
Peak memory 235568 kb
Host smart-37e2e29a-280c-4365-a8d5-4accd3fb5806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=640692348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.640692348
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3605515826
Short name T805
Test name
Test status
Simulation time 788422568 ps
CPU time 25.96 seconds
Started Aug 09 05:34:46 PM PDT 24
Finished Aug 09 05:35:12 PM PDT 24
Peak memory 248772 kb
Host smart-421c21dd-6e9e-4247-b1ad-edf9d2f0f1a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3605515826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3605515826
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1675440028
Short name T132
Test name
Test status
Simulation time 3114700216 ps
CPU time 185.83 seconds
Started Aug 09 05:35:36 PM PDT 24
Finished Aug 09 05:38:42 PM PDT 24
Peak memory 266428 kb
Host smart-1d3b9b4f-d45c-4222-bc32-b4004cdbcf4b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1675440028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1675440028
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.671328512
Short name T123
Test name
Test status
Simulation time 7337911032 ps
CPU time 474.66 seconds
Started Aug 09 05:34:54 PM PDT 24
Finished Aug 09 05:42:49 PM PDT 24
Peak memory 272040 kb
Host smart-31255a50-4eca-4f46-a1c1-0b2ad454f5c1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671328512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.671328512
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3042484115
Short name T727
Test name
Test status
Simulation time 418010093 ps
CPU time 10.04 seconds
Started Aug 09 05:34:50 PM PDT 24
Finished Aug 09 05:35:00 PM PDT 24
Peak memory 255148 kb
Host smart-d0c2670e-9420-46fd-8aaf-3e0459dbb5b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3042484115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3042484115
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1525876081
Short name T272
Test name
Test status
Simulation time 122756402 ps
CPU time 3.99 seconds
Started Aug 09 05:34:46 PM PDT 24
Finished Aug 09 05:34:50 PM PDT 24
Peak memory 237676 kb
Host smart-c62f0745-a43e-4ea8-82d3-edd3585e0691
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1525876081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1525876081
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1738162195
Short name T774
Test name
Test status
Simulation time 209537819 ps
CPU time 5.39 seconds
Started Aug 09 05:34:55 PM PDT 24
Finished Aug 09 05:35:01 PM PDT 24
Peak memory 251340 kb
Host smart-78550470-c80a-45a2-8658-7c5ff18e4000
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738162195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1738162195
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3218197059
Short name T804
Test name
Test status
Simulation time 119281516 ps
CPU time 8.49 seconds
Started Aug 09 05:34:38 PM PDT 24
Finished Aug 09 05:34:47 PM PDT 24
Peak memory 236824 kb
Host smart-676eca6f-f667-41fc-a029-08cd2f85d7c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3218197059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3218197059
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.113937901
Short name T820
Test name
Test status
Simulation time 6882559 ps
CPU time 1.42 seconds
Started Aug 09 05:34:40 PM PDT 24
Finished Aug 09 05:34:41 PM PDT 24
Peak memory 237588 kb
Host smart-4ceda0ad-f265-40ae-ac6d-3f8718260896
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=113937901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.113937901
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.4026168978
Short name T738
Test name
Test status
Simulation time 341044907 ps
CPU time 21.77 seconds
Started Aug 09 05:35:04 PM PDT 24
Finished Aug 09 05:35:26 PM PDT 24
Peak memory 245872 kb
Host smart-7d5e41b2-14ab-47fd-8619-179ab7d0f84a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4026168978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.4026168978
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.928889983
Short name T140
Test name
Test status
Simulation time 1355695988 ps
CPU time 123.1 seconds
Started Aug 09 05:35:36 PM PDT 24
Finished Aug 09 05:37:40 PM PDT 24
Peak memory 267940 kb
Host smart-e2cd0d2a-3488-417a-823d-10a680e56ace
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=928889983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.928889983
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3847984832
Short name T157
Test name
Test status
Simulation time 16671181055 ps
CPU time 604.91 seconds
Started Aug 09 05:34:36 PM PDT 24
Finished Aug 09 05:44:41 PM PDT 24
Peak memory 268092 kb
Host smart-138d59e9-36fa-47d7-bf20-ca9f2cb0b4aa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847984832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.3847984832
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.255095081
Short name T817
Test name
Test status
Simulation time 216874278 ps
CPU time 8.29 seconds
Started Aug 09 05:34:54 PM PDT 24
Finished Aug 09 05:35:02 PM PDT 24
Peak memory 251060 kb
Host smart-e113c379-3913-48e6-8fd4-dc815d890045
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=255095081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.255095081
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.214264571
Short name T744
Test name
Test status
Simulation time 29692689 ps
CPU time 4.88 seconds
Started Aug 09 05:34:56 PM PDT 24
Finished Aug 09 05:35:01 PM PDT 24
Peak memory 248864 kb
Host smart-49ebcd91-cff8-4e78-b3f0-dd2bce9b2305
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214264571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.214264571
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.665502070
Short name T773
Test name
Test status
Simulation time 207985912 ps
CPU time 4.94 seconds
Started Aug 09 05:34:51 PM PDT 24
Finished Aug 09 05:34:56 PM PDT 24
Peak memory 237664 kb
Host smart-b2924677-bbd3-442f-9217-db4981e246ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=665502070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.665502070
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1006258660
Short name T796
Test name
Test status
Simulation time 11173944 ps
CPU time 1.45 seconds
Started Aug 09 05:34:53 PM PDT 24
Finished Aug 09 05:34:55 PM PDT 24
Peak memory 235640 kb
Host smart-ec1277eb-157e-41f9-9906-6ba36641c08b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1006258660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1006258660
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3287808514
Short name T797
Test name
Test status
Simulation time 85154804 ps
CPU time 11.39 seconds
Started Aug 09 05:34:45 PM PDT 24
Finished Aug 09 05:34:57 PM PDT 24
Peak memory 245880 kb
Host smart-f41a91b2-7bcd-48ed-8808-94156fe92ca0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3287808514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3287808514
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3613312280
Short name T809
Test name
Test status
Simulation time 4722974030 ps
CPU time 152.92 seconds
Started Aug 09 05:35:12 PM PDT 24
Finished Aug 09 05:37:45 PM PDT 24
Peak memory 265568 kb
Host smart-381b1ba7-4a8d-425f-ae83-7ba04993fd55
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3613312280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3613312280
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2001030927
Short name T153
Test name
Test status
Simulation time 2870688598 ps
CPU time 328.33 seconds
Started Aug 09 05:34:50 PM PDT 24
Finished Aug 09 05:40:19 PM PDT 24
Peak memory 265508 kb
Host smart-b4a6eee4-bcb8-4eea-93e5-fc84a1d955d2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001030927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2001030927
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4044844399
Short name T837
Test name
Test status
Simulation time 457622642 ps
CPU time 8.26 seconds
Started Aug 09 05:34:56 PM PDT 24
Finished Aug 09 05:35:04 PM PDT 24
Peak memory 248740 kb
Host smart-1c194d65-e0de-4eef-a4bb-76c8e6ac0a57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4044844399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.4044844399
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1570722783
Short name T193
Test name
Test status
Simulation time 2247181903 ps
CPU time 144.91 seconds
Started Aug 09 05:34:33 PM PDT 24
Finished Aug 09 05:36:58 PM PDT 24
Peak memory 237760 kb
Host smart-afba2c6b-2263-4bac-a1a5-751782cc2cd2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1570722783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1570722783
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2792162723
Short name T810
Test name
Test status
Simulation time 1637867558 ps
CPU time 99.12 seconds
Started Aug 09 05:34:41 PM PDT 24
Finished Aug 09 05:36:21 PM PDT 24
Peak memory 240568 kb
Host smart-62b58282-1f64-4715-80f8-706a2833fae2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2792162723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2792162723
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.4261297818
Short name T732
Test name
Test status
Simulation time 38827646 ps
CPU time 4.03 seconds
Started Aug 09 05:34:34 PM PDT 24
Finished Aug 09 05:34:38 PM PDT 24
Peak memory 248648 kb
Host smart-e806d2d9-11e9-4336-816b-f406694b582d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4261297818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.4261297818
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.8007484
Short name T356
Test name
Test status
Simulation time 73899271 ps
CPU time 5.65 seconds
Started Aug 09 05:34:39 PM PDT 24
Finished Aug 09 05:34:45 PM PDT 24
Peak memory 240692 kb
Host smart-f0c8abba-6ceb-4d98-aac8-98ceaa247faa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8007484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.alert_handler_csr_mem_rw_with_rand_reset.8007484
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.646675083
Short name T351
Test name
Test status
Simulation time 69815398 ps
CPU time 5.88 seconds
Started Aug 09 05:34:30 PM PDT 24
Finished Aug 09 05:34:35 PM PDT 24
Peak memory 237608 kb
Host smart-cd17e27f-6ee5-43d1-9e3f-81a3f5827176
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=646675083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.646675083
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2001136380
Short name T790
Test name
Test status
Simulation time 18231029 ps
CPU time 1.39 seconds
Started Aug 09 05:34:27 PM PDT 24
Finished Aug 09 05:34:28 PM PDT 24
Peak memory 235704 kb
Host smart-0b9f5cd9-0a46-446b-934f-f5c0dabb1ee9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2001136380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2001136380
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.4025076455
Short name T766
Test name
Test status
Simulation time 3720726209 ps
CPU time 32.42 seconds
Started Aug 09 05:34:43 PM PDT 24
Finished Aug 09 05:35:16 PM PDT 24
Peak memory 245056 kb
Host smart-f0cba364-d2aa-4a52-97c9-0d964282bcee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4025076455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.4025076455
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1216299821
Short name T823
Test name
Test status
Simulation time 4347726760 ps
CPU time 109.66 seconds
Started Aug 09 05:35:36 PM PDT 24
Finished Aug 09 05:37:26 PM PDT 24
Peak memory 265468 kb
Host smart-e849574b-349a-4261-85a6-e212ec56e871
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1216299821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1216299821
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.4205466044
Short name T143
Test name
Test status
Simulation time 2576093251 ps
CPU time 286.46 seconds
Started Aug 09 05:34:31 PM PDT 24
Finished Aug 09 05:39:17 PM PDT 24
Peak memory 269396 kb
Host smart-9f631ae3-3fcf-4a47-bf06-4fe145f21409
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205466044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.4205466044
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.123292709
Short name T777
Test name
Test status
Simulation time 28819109 ps
CPU time 3.53 seconds
Started Aug 09 05:35:36 PM PDT 24
Finished Aug 09 05:35:40 PM PDT 24
Peak memory 250980 kb
Host smart-c0321789-2f1d-4da2-8a04-60eae580ab57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=123292709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.123292709
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1099383003
Short name T758
Test name
Test status
Simulation time 23447087 ps
CPU time 2.52 seconds
Started Aug 09 05:34:24 PM PDT 24
Finished Aug 09 05:34:26 PM PDT 24
Peak memory 238308 kb
Host smart-5f8e38e9-2eac-40df-bd92-3d6fa69a7608
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1099383003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1099383003
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2449668125
Short name T340
Test name
Test status
Simulation time 6487449 ps
CPU time 1.48 seconds
Started Aug 09 05:34:50 PM PDT 24
Finished Aug 09 05:34:52 PM PDT 24
Peak memory 237628 kb
Host smart-0d986bed-46f3-416e-9062-181d840fbfff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2449668125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2449668125
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4025422728
Short name T740
Test name
Test status
Simulation time 11976550 ps
CPU time 1.4 seconds
Started Aug 09 05:34:52 PM PDT 24
Finished Aug 09 05:34:53 PM PDT 24
Peak memory 236952 kb
Host smart-751d698a-ec07-4848-959f-7b7a8c62ea51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4025422728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.4025422728
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1797430167
Short name T825
Test name
Test status
Simulation time 11751534 ps
CPU time 1.43 seconds
Started Aug 09 05:35:03 PM PDT 24
Finished Aug 09 05:35:04 PM PDT 24
Peak memory 237560 kb
Host smart-ed22c518-1131-47a8-a584-629326e15f7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1797430167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1797430167
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.955436613
Short name T757
Test name
Test status
Simulation time 8915519 ps
CPU time 1.21 seconds
Started Aug 09 05:35:08 PM PDT 24
Finished Aug 09 05:35:09 PM PDT 24
Peak memory 235656 kb
Host smart-088e7f93-f263-4727-b822-a36b3bb951d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=955436613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.955436613
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3514139598
Short name T731
Test name
Test status
Simulation time 17247594 ps
CPU time 1.3 seconds
Started Aug 09 05:34:51 PM PDT 24
Finished Aug 09 05:34:53 PM PDT 24
Peak memory 237676 kb
Host smart-96cef78b-f6bc-4539-9525-b5ea8bb5a16d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3514139598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3514139598
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1490107656
Short name T348
Test name
Test status
Simulation time 10248646 ps
CPU time 1.33 seconds
Started Aug 09 05:35:06 PM PDT 24
Finished Aug 09 05:35:07 PM PDT 24
Peak memory 235704 kb
Host smart-6bb2da6a-3278-43d9-a202-7c05618383bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1490107656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1490107656
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.842225356
Short name T342
Test name
Test status
Simulation time 7822217 ps
CPU time 1.49 seconds
Started Aug 09 05:35:02 PM PDT 24
Finished Aug 09 05:35:04 PM PDT 24
Peak memory 236820 kb
Host smart-c0358f9f-27ea-40e4-ae5b-04f01c08a907
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=842225356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.842225356
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1850234588
Short name T743
Test name
Test status
Simulation time 12041768 ps
CPU time 1.35 seconds
Started Aug 09 05:34:56 PM PDT 24
Finished Aug 09 05:34:57 PM PDT 24
Peak memory 237948 kb
Host smart-3147d5ed-c522-472a-a914-0055ab9118a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1850234588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1850234588
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3702242077
Short name T761
Test name
Test status
Simulation time 11985525 ps
CPU time 1.37 seconds
Started Aug 09 05:34:55 PM PDT 24
Finished Aug 09 05:34:56 PM PDT 24
Peak memory 235704 kb
Host smart-76786b1f-8dc6-487f-b950-3a8bd558c889
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3702242077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3702242077
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1212840868
Short name T188
Test name
Test status
Simulation time 572072253 ps
CPU time 70.66 seconds
Started Aug 09 05:34:38 PM PDT 24
Finished Aug 09 05:35:49 PM PDT 24
Peak memory 237712 kb
Host smart-da711b52-3dfa-4fb0-bdbf-360aca5383fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1212840868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1212840868
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.916432247
Short name T780
Test name
Test status
Simulation time 5945847986 ps
CPU time 189.54 seconds
Started Aug 09 05:34:26 PM PDT 24
Finished Aug 09 05:37:35 PM PDT 24
Peak memory 237728 kb
Host smart-8732a786-8081-4702-98eb-12bf28c405c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=916432247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.916432247
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2415084524
Short name T756
Test name
Test status
Simulation time 152504502 ps
CPU time 6.21 seconds
Started Aug 09 05:34:50 PM PDT 24
Finished Aug 09 05:34:56 PM PDT 24
Peak memory 249052 kb
Host smart-8004f67c-1d95-4540-a88b-74676d2446f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2415084524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2415084524
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3315151691
Short name T355
Test name
Test status
Simulation time 138483173 ps
CPU time 10.75 seconds
Started Aug 09 05:34:25 PM PDT 24
Finished Aug 09 05:34:35 PM PDT 24
Peak memory 256940 kb
Host smart-991eab22-4ebb-489d-b460-9ad484916da8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315151691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3315151691
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.789601865
Short name T742
Test name
Test status
Simulation time 72788066 ps
CPU time 5.5 seconds
Started Aug 09 05:34:39 PM PDT 24
Finished Aug 09 05:34:44 PM PDT 24
Peak memory 240620 kb
Host smart-664a9ebb-357d-46c1-a280-ae507f446722
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=789601865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.789601865
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3163857508
Short name T346
Test name
Test status
Simulation time 8463540 ps
CPU time 1.45 seconds
Started Aug 09 05:34:29 PM PDT 24
Finished Aug 09 05:34:31 PM PDT 24
Peak memory 236576 kb
Host smart-1571ad13-3669-47d2-a709-8e9d9a3be939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3163857508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3163857508
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1313784618
Short name T195
Test name
Test status
Simulation time 6982389255 ps
CPU time 37.33 seconds
Started Aug 09 05:34:26 PM PDT 24
Finished Aug 09 05:35:03 PM PDT 24
Peak memory 244868 kb
Host smart-738d4a52-1871-487e-8403-c9109629606a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1313784618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1313784618
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1246200611
Short name T151
Test name
Test status
Simulation time 2313810454 ps
CPU time 295.47 seconds
Started Aug 09 05:34:45 PM PDT 24
Finished Aug 09 05:39:45 PM PDT 24
Peak memory 265608 kb
Host smart-89264f5e-bf5c-423c-b9aa-1b6584969fbb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246200611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1246200611
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1230253746
Short name T754
Test name
Test status
Simulation time 87889506 ps
CPU time 13.18 seconds
Started Aug 09 05:34:32 PM PDT 24
Finished Aug 09 05:34:45 PM PDT 24
Peak memory 248072 kb
Host smart-be10d814-c4f7-4472-a8e8-1641461cddb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1230253746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1230253746
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2657188778
Short name T237
Test name
Test status
Simulation time 10802013 ps
CPU time 1.58 seconds
Started Aug 09 05:35:02 PM PDT 24
Finished Aug 09 05:35:04 PM PDT 24
Peak memory 237704 kb
Host smart-df690d77-30ab-4069-ae24-f650b0c87937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2657188778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2657188778
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3151419866
Short name T760
Test name
Test status
Simulation time 17047232 ps
CPU time 1.32 seconds
Started Aug 09 05:34:53 PM PDT 24
Finished Aug 09 05:34:54 PM PDT 24
Peak memory 237616 kb
Host smart-7b5daaef-706a-4beb-8308-e0d36687fcee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3151419866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3151419866
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1455352997
Short name T730
Test name
Test status
Simulation time 37178448 ps
CPU time 1.34 seconds
Started Aug 09 05:34:49 PM PDT 24
Finished Aug 09 05:34:50 PM PDT 24
Peak memory 237724 kb
Host smart-b8c2cb96-de36-440a-9920-4b38a01257d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1455352997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1455352997
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3695954617
Short name T771
Test name
Test status
Simulation time 12408969 ps
CPU time 1.25 seconds
Started Aug 09 05:34:53 PM PDT 24
Finished Aug 09 05:34:55 PM PDT 24
Peak memory 236752 kb
Host smart-63e996af-e1b1-4c22-8076-c5b9af86b2f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3695954617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3695954617
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3962308927
Short name T764
Test name
Test status
Simulation time 15024428 ps
CPU time 1.52 seconds
Started Aug 09 05:34:59 PM PDT 24
Finished Aug 09 05:35:01 PM PDT 24
Peak memory 236756 kb
Host smart-9ac68d86-abd7-482b-ae07-f373c0141351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3962308927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3962308927
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.4188501083
Short name T770
Test name
Test status
Simulation time 8585474 ps
CPU time 1.4 seconds
Started Aug 09 05:34:54 PM PDT 24
Finished Aug 09 05:34:56 PM PDT 24
Peak memory 236692 kb
Host smart-83156d67-0957-4e17-9eab-e935a92c9ed2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4188501083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.4188501083
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.750957259
Short name T788
Test name
Test status
Simulation time 31794106 ps
CPU time 1.47 seconds
Started Aug 09 05:34:52 PM PDT 24
Finished Aug 09 05:34:54 PM PDT 24
Peak memory 237620 kb
Host smart-c53b18ee-ebc6-4e0a-98d9-8a0d7272a88a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=750957259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.750957259
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2857372646
Short name T808
Test name
Test status
Simulation time 77416251 ps
CPU time 3.83 seconds
Started Aug 09 05:34:53 PM PDT 24
Finished Aug 09 05:34:57 PM PDT 24
Peak memory 237720 kb
Host smart-450d3465-0596-41e1-88a7-a34866a314bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2857372646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2857372646
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.968559789
Short name T343
Test name
Test status
Simulation time 15403269 ps
CPU time 1.77 seconds
Started Aug 09 05:35:01 PM PDT 24
Finished Aug 09 05:35:03 PM PDT 24
Peak memory 237612 kb
Host smart-03029e57-2fe2-4828-b674-1aca84ae8a13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=968559789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.968559789
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2094238343
Short name T806
Test name
Test status
Simulation time 7973581 ps
CPU time 1.39 seconds
Started Aug 09 05:35:00 PM PDT 24
Finished Aug 09 05:35:01 PM PDT 24
Peak memory 237724 kb
Host smart-2adc2a5d-fccd-4668-8782-f824a5aacf7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2094238343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2094238343
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2609578570
Short name T763
Test name
Test status
Simulation time 5754118522 ps
CPU time 331.45 seconds
Started Aug 09 05:34:34 PM PDT 24
Finished Aug 09 05:40:05 PM PDT 24
Peak memory 240728 kb
Host smart-0b3bc970-127e-42cc-92ec-66f7aacb4e06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2609578570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2609578570
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1091911072
Short name T162
Test name
Test status
Simulation time 199062026 ps
CPU time 8.84 seconds
Started Aug 09 05:34:45 PM PDT 24
Finished Aug 09 05:34:54 PM PDT 24
Peak memory 248748 kb
Host smart-17858193-ef95-4677-b770-4047144bf079
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1091911072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1091911072
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.699302016
Short name T354
Test name
Test status
Simulation time 80937116 ps
CPU time 6.84 seconds
Started Aug 09 05:34:29 PM PDT 24
Finished Aug 09 05:34:36 PM PDT 24
Peak memory 256988 kb
Host smart-f050875f-e2d7-4be8-bc5e-4e20ef69bc27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699302016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.699302016
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.4090393376
Short name T800
Test name
Test status
Simulation time 742757033 ps
CPU time 4.44 seconds
Started Aug 09 05:34:31 PM PDT 24
Finished Aug 09 05:34:35 PM PDT 24
Peak memory 240564 kb
Host smart-caedfa10-13a5-4fae-b4e6-d28850157574
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4090393376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.4090393376
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.38256239
Short name T779
Test name
Test status
Simulation time 23080101 ps
CPU time 1.43 seconds
Started Aug 09 05:34:30 PM PDT 24
Finished Aug 09 05:34:32 PM PDT 24
Peak memory 237672 kb
Host smart-0eaa822c-7300-4fec-aa9c-c5e9d16c694f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=38256239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.38256239
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1857984597
Short name T813
Test name
Test status
Simulation time 526859563 ps
CPU time 33.77 seconds
Started Aug 09 05:34:45 PM PDT 24
Finished Aug 09 05:35:19 PM PDT 24
Peak memory 244932 kb
Host smart-6ca2665f-21fd-4835-abc3-cd07af096769
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1857984597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1857984597
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3629591590
Short name T828
Test name
Test status
Simulation time 252044332 ps
CPU time 8.93 seconds
Started Aug 09 05:34:42 PM PDT 24
Finished Aug 09 05:34:51 PM PDT 24
Peak memory 248960 kb
Host smart-18d59948-c812-4d31-9949-85d01d13f1d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3629591590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3629591590
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1384937845
Short name T341
Test name
Test status
Simulation time 7610340 ps
CPU time 1.41 seconds
Started Aug 09 05:34:50 PM PDT 24
Finished Aug 09 05:34:52 PM PDT 24
Peak memory 237632 kb
Host smart-8d677467-a2ba-4ac6-8149-cbb6063e238f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1384937845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.1384937845
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1998320043
Short name T827
Test name
Test status
Simulation time 11744370 ps
CPU time 1.59 seconds
Started Aug 09 05:34:51 PM PDT 24
Finished Aug 09 05:34:53 PM PDT 24
Peak memory 237648 kb
Host smart-a04f9a44-c263-45c8-99a4-1b0135479b97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1998320043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1998320043
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3402699562
Short name T751
Test name
Test status
Simulation time 16259316 ps
CPU time 1.29 seconds
Started Aug 09 05:35:05 PM PDT 24
Finished Aug 09 05:35:06 PM PDT 24
Peak memory 237628 kb
Host smart-95ae0ccc-7701-4dfd-8ce8-c63960d30820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3402699562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3402699562
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3470948968
Short name T747
Test name
Test status
Simulation time 55433279 ps
CPU time 3.25 seconds
Started Aug 09 05:35:01 PM PDT 24
Finished Aug 09 05:35:04 PM PDT 24
Peak memory 237612 kb
Host smart-1bf40e50-d478-4f37-bae4-af424c49427b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3470948968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3470948968
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1667581278
Short name T782
Test name
Test status
Simulation time 7964876 ps
CPU time 1.49 seconds
Started Aug 09 05:34:51 PM PDT 24
Finished Aug 09 05:34:53 PM PDT 24
Peak memory 237684 kb
Host smart-946eff6f-ce95-4ce1-83f9-c907809cc75b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1667581278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1667581278
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3575251019
Short name T816
Test name
Test status
Simulation time 21458187 ps
CPU time 1.37 seconds
Started Aug 09 05:34:48 PM PDT 24
Finished Aug 09 05:34:49 PM PDT 24
Peak memory 236732 kb
Host smart-bb2f7260-8450-4d17-9a3d-7faa52e41b1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3575251019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3575251019
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.4064043568
Short name T163
Test name
Test status
Simulation time 29663383 ps
CPU time 1.38 seconds
Started Aug 09 05:35:11 PM PDT 24
Finished Aug 09 05:35:13 PM PDT 24
Peak memory 235732 kb
Host smart-51cc1e2e-550b-431f-a167-219856962e1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4064043568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.4064043568
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.924199438
Short name T830
Test name
Test status
Simulation time 9111793 ps
CPU time 1.54 seconds
Started Aug 09 05:34:57 PM PDT 24
Finished Aug 09 05:34:59 PM PDT 24
Peak memory 236692 kb
Host smart-1c3e8983-bfd2-4739-b92f-3be68d311aca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=924199438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.924199438
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3338323916
Short name T789
Test name
Test status
Simulation time 10493552 ps
CPU time 1.32 seconds
Started Aug 09 05:34:51 PM PDT 24
Finished Aug 09 05:34:53 PM PDT 24
Peak memory 236748 kb
Host smart-8fd53eb1-db16-4dd6-a3e1-f71c893d83e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3338323916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3338323916
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3984132595
Short name T801
Test name
Test status
Simulation time 30485345 ps
CPU time 5.08 seconds
Started Aug 09 05:34:46 PM PDT 24
Finished Aug 09 05:34:51 PM PDT 24
Peak memory 240904 kb
Host smart-66a88fd0-d05b-48b1-9b9c-7dbcc3ff342d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984132595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3984132595
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3591614783
Short name T755
Test name
Test status
Simulation time 114470400 ps
CPU time 4.82 seconds
Started Aug 09 05:34:42 PM PDT 24
Finished Aug 09 05:34:47 PM PDT 24
Peak memory 236820 kb
Host smart-6dd7fec1-a093-41c3-a022-352f4d497c3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3591614783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3591614783
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2119432038
Short name T786
Test name
Test status
Simulation time 8853939 ps
CPU time 1.55 seconds
Started Aug 09 05:34:37 PM PDT 24
Finished Aug 09 05:34:38 PM PDT 24
Peak memory 236804 kb
Host smart-00ab8a50-138e-46f7-81ec-c6dace14a520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2119432038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2119432038
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2010945851
Short name T762
Test name
Test status
Simulation time 1600606022 ps
CPU time 34.63 seconds
Started Aug 09 05:34:25 PM PDT 24
Finished Aug 09 05:35:00 PM PDT 24
Peak memory 244868 kb
Host smart-ec517c59-c521-43d5-a384-372a933b5caa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2010945851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2010945851
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2543189013
Short name T144
Test name
Test status
Simulation time 1656720787 ps
CPU time 92.49 seconds
Started Aug 09 05:34:32 PM PDT 24
Finished Aug 09 05:36:05 PM PDT 24
Peak memory 265436 kb
Host smart-897c5a74-ffdd-41d2-abf7-3d9f4faa014c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2543189013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2543189013
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3451751618
Short name T129
Test name
Test status
Simulation time 4866851844 ps
CPU time 613.66 seconds
Started Aug 09 05:34:31 PM PDT 24
Finished Aug 09 05:44:44 PM PDT 24
Peak memory 273228 kb
Host smart-9962fed5-8df6-4d78-9b82-5a495bb2f0ca
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451751618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3451751618
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1134540097
Short name T737
Test name
Test status
Simulation time 92252137 ps
CPU time 6.97 seconds
Started Aug 09 05:34:43 PM PDT 24
Finished Aug 09 05:34:50 PM PDT 24
Peak memory 248780 kb
Host smart-17407534-dee2-41ff-adc6-732197d3c95c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1134540097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1134540097
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1015544827
Short name T768
Test name
Test status
Simulation time 768248100 ps
CPU time 6.97 seconds
Started Aug 09 05:34:46 PM PDT 24
Finished Aug 09 05:34:53 PM PDT 24
Peak memory 241364 kb
Host smart-2d56ebc6-7fe7-4604-8519-9339af075d9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015544827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1015544827
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2981313737
Short name T765
Test name
Test status
Simulation time 377634050 ps
CPU time 8.33 seconds
Started Aug 09 05:34:43 PM PDT 24
Finished Aug 09 05:34:51 PM PDT 24
Peak memory 237608 kb
Host smart-754c0d55-783a-4fa5-a37e-abd26abcceea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2981313737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2981313737
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.848714240
Short name T776
Test name
Test status
Simulation time 18354439 ps
CPU time 1.25 seconds
Started Aug 09 05:34:59 PM PDT 24
Finished Aug 09 05:35:00 PM PDT 24
Peak memory 237640 kb
Host smart-58cb3382-f9c1-4ecf-9cee-36b4e27c77ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=848714240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.848714240
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.679964987
Short name T748
Test name
Test status
Simulation time 1125515969 ps
CPU time 19.42 seconds
Started Aug 09 05:34:42 PM PDT 24
Finished Aug 09 05:35:01 PM PDT 24
Peak memory 245820 kb
Host smart-ba5c1ef1-eab5-4194-87bb-3db5f2524297
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=679964987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.679964987
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2042215866
Short name T134
Test name
Test status
Simulation time 67863517242 ps
CPU time 1297.48 seconds
Started Aug 09 05:34:42 PM PDT 24
Finished Aug 09 05:56:20 PM PDT 24
Peak memory 274060 kb
Host smart-f54b6708-0cc7-49b5-9df5-4eeba1c43f17
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042215866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2042215866
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1181246585
Short name T793
Test name
Test status
Simulation time 128304792 ps
CPU time 4.68 seconds
Started Aug 09 05:34:37 PM PDT 24
Finished Aug 09 05:34:42 PM PDT 24
Peak memory 248792 kb
Host smart-d4fa2a44-f715-4cb2-b6a8-867f3ad73eea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1181246585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1181246585
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.449602701
Short name T350
Test name
Test status
Simulation time 325101084 ps
CPU time 6.17 seconds
Started Aug 09 05:34:40 PM PDT 24
Finished Aug 09 05:34:46 PM PDT 24
Peak memory 256104 kb
Host smart-3a1c59f9-0928-43a1-a222-28f657d728f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449602701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.449602701
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1418202508
Short name T836
Test name
Test status
Simulation time 26007390 ps
CPU time 3.68 seconds
Started Aug 09 05:34:40 PM PDT 24
Finished Aug 09 05:34:43 PM PDT 24
Peak memory 240628 kb
Host smart-a0d79e18-31e9-4193-afbe-606b6769891f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1418202508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1418202508
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1188107078
Short name T784
Test name
Test status
Simulation time 14720048 ps
CPU time 1.3 seconds
Started Aug 09 05:34:40 PM PDT 24
Finished Aug 09 05:34:42 PM PDT 24
Peak memory 237560 kb
Host smart-a486f495-351f-4fd4-ac1e-2861d272fe4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1188107078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1188107078
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3902578403
Short name T799
Test name
Test status
Simulation time 177856231 ps
CPU time 12.25 seconds
Started Aug 09 05:34:48 PM PDT 24
Finished Aug 09 05:35:00 PM PDT 24
Peak memory 245804 kb
Host smart-2e8034f2-b8b6-466b-8444-3f391011695f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3902578403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3902578403
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.568958735
Short name T752
Test name
Test status
Simulation time 2290712691 ps
CPU time 19.86 seconds
Started Aug 09 05:34:44 PM PDT 24
Finished Aug 09 05:35:04 PM PDT 24
Peak memory 248864 kb
Host smart-392562c5-44ec-467e-9833-6fed3cc370e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=568958735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.568958735
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2172155122
Short name T795
Test name
Test status
Simulation time 2496329242 ps
CPU time 35.82 seconds
Started Aug 09 05:34:46 PM PDT 24
Finished Aug 09 05:35:22 PM PDT 24
Peak memory 240580 kb
Host smart-ef610862-5cd4-4a94-8d63-fe77c258e15e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2172155122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2172155122
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2885602942
Short name T352
Test name
Test status
Simulation time 67422659 ps
CPU time 9.14 seconds
Started Aug 09 05:34:40 PM PDT 24
Finished Aug 09 05:34:50 PM PDT 24
Peak memory 251948 kb
Host smart-ca2c5a0e-a699-401b-b641-e04268815b51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885602942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2885602942
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.992383158
Short name T359
Test name
Test status
Simulation time 37026173 ps
CPU time 5.43 seconds
Started Aug 09 05:34:44 PM PDT 24
Finished Aug 09 05:34:50 PM PDT 24
Peak memory 240648 kb
Host smart-b98d50cb-117e-46e3-a808-443f68c5082d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=992383158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.992383158
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.462094732
Short name T749
Test name
Test status
Simulation time 21324211 ps
CPU time 1.4 seconds
Started Aug 09 05:34:35 PM PDT 24
Finished Aug 09 05:34:37 PM PDT 24
Peak memory 237676 kb
Host smart-ec12ff6c-7ad4-4f42-9588-9b503c8ff110
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=462094732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.462094732
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.288419275
Short name T815
Test name
Test status
Simulation time 172710312 ps
CPU time 12.04 seconds
Started Aug 09 05:34:44 PM PDT 24
Finished Aug 09 05:34:56 PM PDT 24
Peak memory 248656 kb
Host smart-0a877fc9-4114-4e15-87e8-37a7db0b7831
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=288419275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.288419275
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.540769283
Short name T146
Test name
Test status
Simulation time 9082997610 ps
CPU time 149.43 seconds
Started Aug 09 05:34:45 PM PDT 24
Finished Aug 09 05:37:14 PM PDT 24
Peak memory 265680 kb
Host smart-9cef526a-b856-4b67-97c1-08c4e8e15482
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=540769283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.540769283
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1448172989
Short name T724
Test name
Test status
Simulation time 83457628 ps
CPU time 6.47 seconds
Started Aug 09 05:34:37 PM PDT 24
Finished Aug 09 05:34:44 PM PDT 24
Peak memory 251292 kb
Host smart-57431eaa-44b6-442a-9dd9-2237c612ff6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1448172989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1448172989
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3496226651
Short name T759
Test name
Test status
Simulation time 659510089 ps
CPU time 5.45 seconds
Started Aug 09 05:35:09 PM PDT 24
Finished Aug 09 05:35:14 PM PDT 24
Peak memory 238544 kb
Host smart-59fcbf37-5c60-4101-a7fb-f9e5db0919b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496226651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3496226651
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.4150352752
Short name T196
Test name
Test status
Simulation time 66931547 ps
CPU time 6.33 seconds
Started Aug 09 05:34:39 PM PDT 24
Finished Aug 09 05:34:46 PM PDT 24
Peak memory 237600 kb
Host smart-5e36ece2-f0de-40b2-a3e1-858964ffb102
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4150352752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.4150352752
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.689021326
Short name T339
Test name
Test status
Simulation time 8500149 ps
CPU time 1.31 seconds
Started Aug 09 05:35:38 PM PDT 24
Finished Aug 09 05:35:40 PM PDT 24
Peak memory 236652 kb
Host smart-aba1199f-7824-406b-9407-bbf3c57d8d82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=689021326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.689021326
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2333256314
Short name T739
Test name
Test status
Simulation time 644314525 ps
CPU time 21.41 seconds
Started Aug 09 05:34:56 PM PDT 24
Finished Aug 09 05:35:18 PM PDT 24
Peak memory 248784 kb
Host smart-8761f737-9e0e-49c4-8956-e14c9861f39c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2333256314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2333256314
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3423421749
Short name T130
Test name
Test status
Simulation time 885164324 ps
CPU time 111.31 seconds
Started Aug 09 05:34:46 PM PDT 24
Finished Aug 09 05:36:38 PM PDT 24
Peak memory 265600 kb
Host smart-7e8a66b7-70bc-43bd-b201-2a537aacb46d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3423421749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3423421749
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2887573608
Short name T155
Test name
Test status
Simulation time 20996000176 ps
CPU time 319.91 seconds
Started Aug 09 05:34:22 PM PDT 24
Finished Aug 09 05:39:47 PM PDT 24
Peak memory 269716 kb
Host smart-d9ad8b4f-d8f4-40ec-b664-d558d5d2c420
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887573608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2887573608
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3032315075
Short name T729
Test name
Test status
Simulation time 709302894 ps
CPU time 13.23 seconds
Started Aug 09 05:34:44 PM PDT 24
Finished Aug 09 05:34:57 PM PDT 24
Peak memory 248740 kb
Host smart-7f5699d1-53d3-47b0-b60d-0656319e3f31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3032315075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3032315075
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1710124051
Short name T703
Test name
Test status
Simulation time 21108094224 ps
CPU time 1868.23 seconds
Started Aug 09 04:38:15 PM PDT 24
Finished Aug 09 05:09:24 PM PDT 24
Peak memory 288496 kb
Host smart-5cc8f4fd-6268-494b-891a-db18452a3aed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710124051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1710124051
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.441488680
Short name T449
Test name
Test status
Simulation time 8619387147 ps
CPU time 72.91 seconds
Started Aug 09 04:38:29 PM PDT 24
Finished Aug 09 04:39:42 PM PDT 24
Peak memory 248360 kb
Host smart-dd2d34ba-3006-4c44-915f-238e7b6b3e02
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=441488680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.441488680
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1606617452
Short name T248
Test name
Test status
Simulation time 19477656717 ps
CPU time 180.29 seconds
Started Aug 09 04:38:12 PM PDT 24
Finished Aug 09 04:41:13 PM PDT 24
Peak memory 256412 kb
Host smart-e33b45cd-e2ca-4956-8e87-bcb20e3e642d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16066
17452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1606617452
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1677085241
Short name T489
Test name
Test status
Simulation time 187908711 ps
CPU time 10.41 seconds
Started Aug 09 04:38:17 PM PDT 24
Finished Aug 09 04:38:28 PM PDT 24
Peak memory 255796 kb
Host smart-77d14fe9-206c-49b7-953a-3b3e06b216ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16770
85241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1677085241
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.4220196736
Short name T539
Test name
Test status
Simulation time 107890777543 ps
CPU time 1583.32 seconds
Started Aug 09 04:38:17 PM PDT 24
Finished Aug 09 05:04:41 PM PDT 24
Peak memory 272660 kb
Host smart-cc5a64d6-90cb-489c-9811-6ec1fc7b86fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220196736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.4220196736
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2347563072
Short name T303
Test name
Test status
Simulation time 57728903889 ps
CPU time 379.07 seconds
Started Aug 09 04:38:29 PM PDT 24
Finished Aug 09 04:44:49 PM PDT 24
Peak memory 254836 kb
Host smart-e54a4003-9605-467d-9ae9-53221d07c264
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347563072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2347563072
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3135202142
Short name T438
Test name
Test status
Simulation time 730611068 ps
CPU time 17.46 seconds
Started Aug 09 04:38:31 PM PDT 24
Finished Aug 09 04:38:48 PM PDT 24
Peak memory 255408 kb
Host smart-53959835-226e-44e8-abeb-31102499b0ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31352
02142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3135202142
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3756476214
Short name T273
Test name
Test status
Simulation time 407489929 ps
CPU time 28.38 seconds
Started Aug 09 04:38:15 PM PDT 24
Finished Aug 09 04:38:43 PM PDT 24
Peak memory 248112 kb
Host smart-332dd346-2da7-4002-81fe-7bad8b8f6e00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37564
76214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3756476214
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.787395024
Short name T580
Test name
Test status
Simulation time 2996335176 ps
CPU time 52.2 seconds
Started Aug 09 04:38:10 PM PDT 24
Finished Aug 09 04:39:03 PM PDT 24
Peak memory 248224 kb
Host smart-da2ccfc5-c632-4e21-90ed-f86c117d29d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78739
5024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.787395024
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.4041589372
Short name T473
Test name
Test status
Simulation time 1492628350 ps
CPU time 51.97 seconds
Started Aug 09 04:38:26 PM PDT 24
Finished Aug 09 04:39:18 PM PDT 24
Peak memory 248136 kb
Host smart-da6361a4-a824-4724-b8ac-43dd58516315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40415
89372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.4041589372
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.4106819790
Short name T647
Test name
Test status
Simulation time 8394890860 ps
CPU time 855.53 seconds
Started Aug 09 04:38:24 PM PDT 24
Finished Aug 09 04:52:39 PM PDT 24
Peak memory 272856 kb
Host smart-8b9cb81b-3a5a-41e5-ace7-b5f3a20d35fc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106819790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.4106819790
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.2383262740
Short name T649
Test name
Test status
Simulation time 82076679763 ps
CPU time 2020.54 seconds
Started Aug 09 04:38:11 PM PDT 24
Finished Aug 09 05:11:52 PM PDT 24
Peak memory 297236 kb
Host smart-04e9161e-4cfb-466f-b3c1-8047ff5468dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383262740 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.2383262740
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1600945463
Short name T448
Test name
Test status
Simulation time 54923100172 ps
CPU time 3264.56 seconds
Started Aug 09 04:38:13 PM PDT 24
Finished Aug 09 05:32:38 PM PDT 24
Peak memory 289112 kb
Host smart-11121435-2583-444d-bad8-15ed471dfa4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600945463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1600945463
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3980939772
Short name T609
Test name
Test status
Simulation time 424671012 ps
CPU time 12.36 seconds
Started Aug 09 04:38:20 PM PDT 24
Finished Aug 09 04:38:33 PM PDT 24
Peak memory 248284 kb
Host smart-775c2625-84a1-4ceb-a96f-70fd4149129b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3980939772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3980939772
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1895759141
Short name T384
Test name
Test status
Simulation time 763844673 ps
CPU time 58.99 seconds
Started Aug 09 04:38:26 PM PDT 24
Finished Aug 09 04:39:25 PM PDT 24
Peak memory 255680 kb
Host smart-7674b407-26da-4eb9-abc7-ae981b5ad557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18957
59141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1895759141
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1390643494
Short name T397
Test name
Test status
Simulation time 2259907508 ps
CPU time 35.38 seconds
Started Aug 09 04:38:29 PM PDT 24
Finished Aug 09 04:39:05 PM PDT 24
Peak memory 248132 kb
Host smart-3acf0e89-fd4d-430c-8a7b-f3b0f1ceebaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13906
43494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1390643494
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3007152791
Short name T526
Test name
Test status
Simulation time 50098109485 ps
CPU time 2312.07 seconds
Started Aug 09 04:38:30 PM PDT 24
Finished Aug 09 05:17:02 PM PDT 24
Peak memory 284596 kb
Host smart-297689dc-3046-45ec-a916-455063f0141e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007152791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3007152791
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1842391559
Short name T101
Test name
Test status
Simulation time 276049669897 ps
CPU time 1398.16 seconds
Started Aug 09 04:38:12 PM PDT 24
Finished Aug 09 05:01:30 PM PDT 24
Peak memory 289048 kb
Host smart-ad1bde2e-37a4-455e-a30b-47a9a94d02f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842391559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1842391559
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.199521313
Short name T309
Test name
Test status
Simulation time 11437170496 ps
CPU time 396.5 seconds
Started Aug 09 04:38:37 PM PDT 24
Finished Aug 09 04:45:14 PM PDT 24
Peak memory 255512 kb
Host smart-75b80257-627b-44a9-8346-93809cff573c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199521313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.199521313
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.170238528
Short name T623
Test name
Test status
Simulation time 285593514 ps
CPU time 22.54 seconds
Started Aug 09 04:38:29 PM PDT 24
Finished Aug 09 04:38:52 PM PDT 24
Peak memory 248084 kb
Host smart-ac7f500e-e075-490c-b45e-52f51a93730c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17023
8528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.170238528
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3517095876
Short name T570
Test name
Test status
Simulation time 255685827 ps
CPU time 17.17 seconds
Started Aug 09 04:38:29 PM PDT 24
Finished Aug 09 04:38:46 PM PDT 24
Peak memory 254236 kb
Host smart-dca38207-a32b-4b08-91b7-9ab427a57d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35170
95876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3517095876
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.98671637
Short name T30
Test name
Test status
Simulation time 454839915 ps
CPU time 18.26 seconds
Started Aug 09 04:38:25 PM PDT 24
Finished Aug 09 04:38:44 PM PDT 24
Peak memory 276640 kb
Host smart-55bb50f8-604d-4ef1-9fc4-0f6a05c428e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=98671637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.98671637
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2692692885
Short name T363
Test name
Test status
Simulation time 248407676 ps
CPU time 4.78 seconds
Started Aug 09 04:38:27 PM PDT 24
Finished Aug 09 04:38:31 PM PDT 24
Peak memory 248532 kb
Host smart-f4449cbb-9724-42db-a01b-a155880866d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26926
92885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2692692885
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3078571272
Short name T577
Test name
Test status
Simulation time 776766152 ps
CPU time 14.09 seconds
Started Aug 09 04:38:26 PM PDT 24
Finished Aug 09 04:38:41 PM PDT 24
Peak memory 254996 kb
Host smart-84030cd7-19ec-4d9e-94f5-0d79f25dd455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30785
71272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3078571272
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1260327997
Short name T614
Test name
Test status
Simulation time 10281295075 ps
CPU time 757.87 seconds
Started Aug 09 04:38:41 PM PDT 24
Finished Aug 09 04:51:19 PM PDT 24
Peak memory 265640 kb
Host smart-15c60236-4229-4766-8eab-ff73de0731a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260327997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1260327997
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3167458169
Short name T634
Test name
Test status
Simulation time 1853624862 ps
CPU time 21.26 seconds
Started Aug 09 04:38:46 PM PDT 24
Finished Aug 09 04:39:07 PM PDT 24
Peak memory 248164 kb
Host smart-647da3d2-5186-46b5-8b3e-0290aa5ee3e4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3167458169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3167458169
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.674156229
Short name T461
Test name
Test status
Simulation time 10061850246 ps
CPU time 132.5 seconds
Started Aug 09 04:38:42 PM PDT 24
Finished Aug 09 04:40:54 PM PDT 24
Peak memory 256008 kb
Host smart-a249708c-a388-4077-824d-ad497ce50cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67415
6229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.674156229
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.693208329
Short name T451
Test name
Test status
Simulation time 597638142 ps
CPU time 34.25 seconds
Started Aug 09 04:39:00 PM PDT 24
Finished Aug 09 04:39:35 PM PDT 24
Peak memory 255996 kb
Host smart-878e5ba8-3217-4e24-b241-aa9cf6c19954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69320
8329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.693208329
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.685149227
Short name T329
Test name
Test status
Simulation time 9596521154 ps
CPU time 932.5 seconds
Started Aug 09 04:38:37 PM PDT 24
Finished Aug 09 04:54:09 PM PDT 24
Peak memory 272172 kb
Host smart-67e6e038-b65d-40aa-aaf6-cb2047d83d86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685149227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.685149227
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.3402132276
Short name T453
Test name
Test status
Simulation time 14835412921 ps
CPU time 1429.55 seconds
Started Aug 09 04:38:37 PM PDT 24
Finished Aug 09 05:02:27 PM PDT 24
Peak memory 283060 kb
Host smart-4ce80b29-a0be-42a5-8917-91499cd19265
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402132276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.3402132276
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1889034656
Short name T232
Test name
Test status
Simulation time 602248744 ps
CPU time 19.22 seconds
Started Aug 09 04:38:47 PM PDT 24
Finished Aug 09 04:39:06 PM PDT 24
Peak memory 254936 kb
Host smart-f988bb60-ecdc-4c08-b0b9-d1e8f47b620e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18890
34656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1889034656
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2211795141
Short name T87
Test name
Test status
Simulation time 1450557498 ps
CPU time 21.6 seconds
Started Aug 09 04:38:46 PM PDT 24
Finished Aug 09 04:39:08 PM PDT 24
Peak memory 247368 kb
Host smart-da3dab6e-96f4-42bc-ae5e-d092ae69ef87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22117
95141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2211795141
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.992301254
Short name T626
Test name
Test status
Simulation time 207795266 ps
CPU time 4.61 seconds
Started Aug 09 04:38:52 PM PDT 24
Finished Aug 09 04:38:57 PM PDT 24
Peak memory 248136 kb
Host smart-89b66a91-b15b-4247-9057-a00d61e3261b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99230
1254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.992301254
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.568316001
Short name T674
Test name
Test status
Simulation time 1346471860 ps
CPU time 22.47 seconds
Started Aug 09 04:38:39 PM PDT 24
Finished Aug 09 04:39:02 PM PDT 24
Peak memory 248616 kb
Host smart-85922f92-52ba-45f6-9508-fa3ad9d873e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56831
6001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.568316001
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1687773483
Short name T602
Test name
Test status
Simulation time 8850988466 ps
CPU time 148.63 seconds
Started Aug 09 04:38:49 PM PDT 24
Finished Aug 09 04:41:17 PM PDT 24
Peak memory 256548 kb
Host smart-d1cc9940-a090-4d55-a310-9372d036d25a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687773483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1687773483
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.3627115033
Short name T55
Test name
Test status
Simulation time 22540987407 ps
CPU time 2016.84 seconds
Started Aug 09 04:38:57 PM PDT 24
Finished Aug 09 05:12:34 PM PDT 24
Peak memory 289304 kb
Host smart-05f4a984-0490-4682-b278-8641edeeec67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627115033 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.3627115033
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.44596851
Short name T210
Test name
Test status
Simulation time 115345133 ps
CPU time 3.12 seconds
Started Aug 09 04:38:57 PM PDT 24
Finished Aug 09 04:39:00 PM PDT 24
Peak memory 248420 kb
Host smart-78ea9a94-d6d0-486e-a943-e0142d4c4d23
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=44596851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.44596851
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2809569245
Short name T593
Test name
Test status
Simulation time 13783407923 ps
CPU time 1325.5 seconds
Started Aug 09 04:38:51 PM PDT 24
Finished Aug 09 05:00:56 PM PDT 24
Peak memory 288028 kb
Host smart-b9ee84bf-2436-48a4-9dc8-dc3cfe5bd078
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809569245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2809569245
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2948831382
Short name T226
Test name
Test status
Simulation time 525547508 ps
CPU time 8.44 seconds
Started Aug 09 04:38:54 PM PDT 24
Finished Aug 09 04:39:03 PM PDT 24
Peak memory 248052 kb
Host smart-5f5ce901-bf0e-4963-bf04-bcc7e4845033
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2948831382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2948831382
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1023750223
Short name T1
Test name
Test status
Simulation time 2050304861 ps
CPU time 117.3 seconds
Started Aug 09 04:38:49 PM PDT 24
Finished Aug 09 04:40:47 PM PDT 24
Peak memory 255640 kb
Host smart-4fd99660-74f2-42e1-8aed-3ae7f906e41d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10237
50223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1023750223
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1371736318
Short name T499
Test name
Test status
Simulation time 408269053 ps
CPU time 37.8 seconds
Started Aug 09 04:38:47 PM PDT 24
Finished Aug 09 04:39:25 PM PDT 24
Peak memory 248204 kb
Host smart-7ac568b9-5fc3-47e8-99b3-f2a5c31ec492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13717
36318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1371736318
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3830131954
Short name T320
Test name
Test status
Simulation time 18545689205 ps
CPU time 1015.05 seconds
Started Aug 09 04:38:50 PM PDT 24
Finished Aug 09 04:55:45 PM PDT 24
Peak memory 272088 kb
Host smart-b44b2b35-5a44-4c58-acd9-777956e7c36b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830131954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3830131954
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1125937823
Short name T38
Test name
Test status
Simulation time 41968950785 ps
CPU time 2625.42 seconds
Started Aug 09 04:38:48 PM PDT 24
Finished Aug 09 05:22:34 PM PDT 24
Peak memory 281032 kb
Host smart-09495995-cc02-4ca7-944d-2d17912de8b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125937823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1125937823
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3255923876
Short name T564
Test name
Test status
Simulation time 50027185890 ps
CPU time 490.82 seconds
Started Aug 09 04:38:47 PM PDT 24
Finished Aug 09 04:46:58 PM PDT 24
Peak memory 248060 kb
Host smart-cee66449-a49b-4fe0-8794-3997fda5e040
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255923876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3255923876
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1264055194
Short name T681
Test name
Test status
Simulation time 808323813 ps
CPU time 24.84 seconds
Started Aug 09 04:38:47 PM PDT 24
Finished Aug 09 04:39:12 PM PDT 24
Peak memory 255372 kb
Host smart-5d2e46fd-be96-4daa-913e-e43b4bd1349b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12640
55194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1264055194
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.1909127822
Short name T230
Test name
Test status
Simulation time 1286464802 ps
CPU time 30.92 seconds
Started Aug 09 04:38:50 PM PDT 24
Finished Aug 09 04:39:22 PM PDT 24
Peak memory 247840 kb
Host smart-ee28b205-296c-448e-9e3e-1b875feef798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19091
27822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1909127822
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1190631320
Short name T488
Test name
Test status
Simulation time 328092000 ps
CPU time 33.46 seconds
Started Aug 09 04:38:53 PM PDT 24
Finished Aug 09 04:39:26 PM PDT 24
Peak memory 248224 kb
Host smart-fd54fa1e-11eb-41de-aa57-551eb209e80f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11906
31320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1190631320
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2895669572
Short name T551
Test name
Test status
Simulation time 568940784 ps
CPU time 36.47 seconds
Started Aug 09 04:38:49 PM PDT 24
Finished Aug 09 04:39:26 PM PDT 24
Peak memory 255464 kb
Host smart-91d1b686-0db8-4f12-9e4b-8cfa087c189c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28956
69572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2895669572
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2126784762
Short name T213
Test name
Test status
Simulation time 32574953 ps
CPU time 2.99 seconds
Started Aug 09 04:38:43 PM PDT 24
Finished Aug 09 04:38:47 PM PDT 24
Peak memory 248368 kb
Host smart-d056a1a6-08c5-4695-ab8a-38a45dbf6e92
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2126784762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2126784762
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2010771603
Short name T235
Test name
Test status
Simulation time 689140769 ps
CPU time 9.65 seconds
Started Aug 09 04:38:50 PM PDT 24
Finished Aug 09 04:39:00 PM PDT 24
Peak memory 248116 kb
Host smart-56510073-6e24-4da1-8e03-68e44a26fcfd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2010771603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2010771603
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2427657724
Short name T114
Test name
Test status
Simulation time 1011807896 ps
CPU time 77.27 seconds
Started Aug 09 04:38:47 PM PDT 24
Finished Aug 09 04:40:04 PM PDT 24
Peak memory 256372 kb
Host smart-cc2a1952-4b97-4c1a-a7de-ca0bd63e45a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24276
57724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2427657724
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2689998291
Short name T629
Test name
Test status
Simulation time 333992930 ps
CPU time 19.72 seconds
Started Aug 09 04:38:57 PM PDT 24
Finished Aug 09 04:39:16 PM PDT 24
Peak memory 255472 kb
Host smart-5705213c-181d-4fc9-b21d-d0ea4a3c64e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26899
98291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2689998291
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3799504723
Short name T332
Test name
Test status
Simulation time 34383346965 ps
CPU time 562.76 seconds
Started Aug 09 04:38:50 PM PDT 24
Finished Aug 09 04:48:13 PM PDT 24
Peak memory 271584 kb
Host smart-1f58c8e6-e8f2-4764-8eb9-f03c52f07a4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799504723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3799504723
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.473109753
Short name T445
Test name
Test status
Simulation time 138463388110 ps
CPU time 1906.86 seconds
Started Aug 09 04:38:45 PM PDT 24
Finished Aug 09 05:10:32 PM PDT 24
Peak memory 284356 kb
Host smart-abcbbce3-e706-43a6-a513-49e2fe586dc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473109753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.473109753
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3234572867
Short name T418
Test name
Test status
Simulation time 29862571295 ps
CPU time 296.09 seconds
Started Aug 09 04:38:49 PM PDT 24
Finished Aug 09 04:43:46 PM PDT 24
Peak memory 248188 kb
Host smart-d6ce09f1-e871-4014-9d15-e23f1ad94374
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234572867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3234572867
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3106287755
Short name T715
Test name
Test status
Simulation time 1392436476 ps
CPU time 44.26 seconds
Started Aug 09 04:38:46 PM PDT 24
Finished Aug 09 04:39:30 PM PDT 24
Peak memory 248236 kb
Host smart-716981b3-a615-4c84-a1e8-6832516c63fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31062
87755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3106287755
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3770364024
Short name T410
Test name
Test status
Simulation time 306832361 ps
CPU time 27.95 seconds
Started Aug 09 04:38:51 PM PDT 24
Finished Aug 09 04:39:19 PM PDT 24
Peak memory 248144 kb
Host smart-6c21c8dd-b722-4bfb-b7ce-2ee78e251603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37703
64024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3770364024
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1676166013
Short name T477
Test name
Test status
Simulation time 742996633 ps
CPU time 39.12 seconds
Started Aug 09 04:38:51 PM PDT 24
Finished Aug 09 04:39:30 PM PDT 24
Peak memory 255672 kb
Host smart-b7c9ce8f-e689-41e8-8e17-2b6c6dab1c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16761
66013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1676166013
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.495960621
Short name T705
Test name
Test status
Simulation time 964948313 ps
CPU time 27.31 seconds
Started Aug 09 04:38:49 PM PDT 24
Finished Aug 09 04:39:17 PM PDT 24
Peak memory 256244 kb
Host smart-295e97fc-0fe8-4de0-a70f-8446f69aa5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49596
0621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.495960621
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.19029634
Short name T457
Test name
Test status
Simulation time 5922450208 ps
CPU time 187.55 seconds
Started Aug 09 04:38:51 PM PDT 24
Finished Aug 09 04:41:59 PM PDT 24
Peak memory 256484 kb
Host smart-41e5d365-94d8-4254-bdd6-9d52838227c0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19029634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_hand
ler_stress_all.19029634
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.532576792
Short name T217
Test name
Test status
Simulation time 38339408 ps
CPU time 2.37 seconds
Started Aug 09 04:38:52 PM PDT 24
Finished Aug 09 04:38:55 PM PDT 24
Peak memory 248344 kb
Host smart-48ca2248-5f85-4b45-8cde-6ea23f20a751
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=532576792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.532576792
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1619638025
Short name T642
Test name
Test status
Simulation time 183253179979 ps
CPU time 3002.62 seconds
Started Aug 09 04:38:49 PM PDT 24
Finished Aug 09 05:28:52 PM PDT 24
Peak memory 281028 kb
Host smart-2bd0f288-f54e-4a88-b91a-a881ac6eccb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619638025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1619638025
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1116923459
Short name T587
Test name
Test status
Simulation time 415834700 ps
CPU time 6.74 seconds
Started Aug 09 04:39:04 PM PDT 24
Finished Aug 09 04:39:10 PM PDT 24
Peak memory 248120 kb
Host smart-9814aef2-a62f-4803-85c0-07a0c0e543a0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1116923459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1116923459
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2627790939
Short name T414
Test name
Test status
Simulation time 10526320058 ps
CPU time 133.65 seconds
Started Aug 09 04:38:56 PM PDT 24
Finished Aug 09 04:41:10 PM PDT 24
Peak memory 255972 kb
Host smart-d969f3c7-f1fd-4028-bf2b-294aec6a6cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26277
90939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2627790939
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.519713071
Short name T429
Test name
Test status
Simulation time 470021640 ps
CPU time 29.27 seconds
Started Aug 09 04:39:00 PM PDT 24
Finished Aug 09 04:39:30 PM PDT 24
Peak memory 248092 kb
Host smart-eeddb5c5-08c1-448e-9318-2e09d4ff3252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51971
3071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.519713071
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1716961096
Short name T721
Test name
Test status
Simulation time 80125780489 ps
CPU time 2113.16 seconds
Started Aug 09 04:38:45 PM PDT 24
Finished Aug 09 05:13:59 PM PDT 24
Peak memory 285128 kb
Host smart-b5373295-28fe-4984-b501-59da61a8d63c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716961096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1716961096
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.858777393
Short name T224
Test name
Test status
Simulation time 23903328673 ps
CPU time 1090.91 seconds
Started Aug 09 04:38:49 PM PDT 24
Finished Aug 09 04:57:00 PM PDT 24
Peak memory 272680 kb
Host smart-f05977d9-5de1-41a6-a7e6-98285b572890
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858777393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.858777393
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1997878263
Short name T112
Test name
Test status
Simulation time 2067278872 ps
CPU time 95.9 seconds
Started Aug 09 04:38:45 PM PDT 24
Finished Aug 09 04:40:21 PM PDT 24
Peak memory 248124 kb
Host smart-07d33e67-cad5-4c82-b2ae-77b0096e65ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997878263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1997878263
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2449166841
Short name T541
Test name
Test status
Simulation time 990180621 ps
CPU time 17.12 seconds
Started Aug 09 04:39:00 PM PDT 24
Finished Aug 09 04:39:17 PM PDT 24
Peak memory 254208 kb
Host smart-e902452a-6b3d-4c73-ab7a-ea1771d45acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24491
66841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2449166841
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.449475505
Short name T463
Test name
Test status
Simulation time 628561735 ps
CPU time 24.45 seconds
Started Aug 09 04:38:58 PM PDT 24
Finished Aug 09 04:39:23 PM PDT 24
Peak memory 256320 kb
Host smart-56053b2f-7470-4b2a-9b75-230cb042b9cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44947
5505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.449475505
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1406877199
Short name T238
Test name
Test status
Simulation time 1256822370 ps
CPU time 41.54 seconds
Started Aug 09 04:38:46 PM PDT 24
Finished Aug 09 04:39:28 PM PDT 24
Peak memory 247548 kb
Host smart-a3ce2bac-ad8d-41c9-b7ad-bae110bec0b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14068
77199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1406877199
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2449836022
Short name T16
Test name
Test status
Simulation time 1116776658 ps
CPU time 34.02 seconds
Started Aug 09 04:39:00 PM PDT 24
Finished Aug 09 04:39:34 PM PDT 24
Peak memory 256176 kb
Host smart-262c303f-09d5-4f10-a3ed-a1fcca444136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24498
36022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2449836022
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.773911878
Short name T35
Test name
Test status
Simulation time 13028102918 ps
CPU time 1236.83 seconds
Started Aug 09 04:38:52 PM PDT 24
Finished Aug 09 04:59:29 PM PDT 24
Peak memory 281152 kb
Host smart-13c0cd1b-5d78-417f-b80f-31d7f98ed50b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773911878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_han
dler_stress_all.773911878
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2253978412
Short name T187
Test name
Test status
Simulation time 113364629759 ps
CPU time 5448.88 seconds
Started Aug 09 04:38:54 PM PDT 24
Finished Aug 09 06:09:44 PM PDT 24
Peak memory 353864 kb
Host smart-f599cb0d-37e8-4915-912e-e35cc8b6e679
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253978412 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2253978412
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2991103605
Short name T211
Test name
Test status
Simulation time 117462714 ps
CPU time 3.27 seconds
Started Aug 09 04:38:49 PM PDT 24
Finished Aug 09 04:38:52 PM PDT 24
Peak memory 248552 kb
Host smart-20f92396-6344-47df-bb4e-2fbee4109129
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2991103605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2991103605
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2662141782
Short name T48
Test name
Test status
Simulation time 9319011324 ps
CPU time 1022.54 seconds
Started Aug 09 04:38:48 PM PDT 24
Finished Aug 09 04:55:51 PM PDT 24
Peak memory 284876 kb
Host smart-faa682df-e1f0-42e7-b2f8-794fadd7192c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662141782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2662141782
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1292831300
Short name T395
Test name
Test status
Simulation time 1531417258 ps
CPU time 8.38 seconds
Started Aug 09 04:38:53 PM PDT 24
Finished Aug 09 04:39:01 PM PDT 24
Peak memory 248152 kb
Host smart-714b5f44-72ef-455d-aedb-79dc61267634
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1292831300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1292831300
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1171961191
Short name T75
Test name
Test status
Simulation time 2335449986 ps
CPU time 106.94 seconds
Started Aug 09 04:38:59 PM PDT 24
Finished Aug 09 04:40:46 PM PDT 24
Peak memory 256376 kb
Host smart-7fdf3107-79ef-46eb-a061-37a0054b9b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11719
61191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1171961191
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.876051215
Short name T695
Test name
Test status
Simulation time 1389124901 ps
CPU time 22.04 seconds
Started Aug 09 04:38:58 PM PDT 24
Finished Aug 09 04:39:21 PM PDT 24
Peak memory 248144 kb
Host smart-6c0fec7c-dbb8-4de9-9b35-cf45c440cc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87605
1215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.876051215
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2262013801
Short name T184
Test name
Test status
Simulation time 1725579895 ps
CPU time 25.76 seconds
Started Aug 09 04:38:46 PM PDT 24
Finished Aug 09 04:39:11 PM PDT 24
Peak memory 248148 kb
Host smart-09ef4ac5-30d3-4dd0-949b-328fa9a01f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22620
13801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2262013801
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1994680176
Short name T484
Test name
Test status
Simulation time 2582030124 ps
CPU time 42.42 seconds
Started Aug 09 04:38:58 PM PDT 24
Finished Aug 09 04:39:41 PM PDT 24
Peak memory 248268 kb
Host smart-eb0bd499-58a2-430c-b746-e84d797e46c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19946
80176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1994680176
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.762446880
Short name T261
Test name
Test status
Simulation time 736817956 ps
CPU time 52.64 seconds
Started Aug 09 04:38:46 PM PDT 24
Finished Aug 09 04:39:39 PM PDT 24
Peak memory 248184 kb
Host smart-21379553-12b1-42fc-b5cf-577a108d98ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76244
6880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.762446880
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.346748991
Short name T393
Test name
Test status
Simulation time 71163110 ps
CPU time 7.54 seconds
Started Aug 09 04:38:48 PM PDT 24
Finished Aug 09 04:38:56 PM PDT 24
Peak memory 248116 kb
Host smart-ce8257d2-0720-4cf8-bbc3-02e9d1d45645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34674
8991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.346748991
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1985238548
Short name T265
Test name
Test status
Simulation time 16651417734 ps
CPU time 1567.32 seconds
Started Aug 09 04:38:59 PM PDT 24
Finished Aug 09 05:05:07 PM PDT 24
Peak memory 300976 kb
Host smart-f29b318d-5ba9-4b03-9e9a-7a002970897b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985238548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1985238548
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2611593056
Short name T206
Test name
Test status
Simulation time 33558811 ps
CPU time 3.82 seconds
Started Aug 09 04:39:01 PM PDT 24
Finished Aug 09 04:39:04 PM PDT 24
Peak memory 248444 kb
Host smart-869bf8f2-cb58-42fa-82a8-244d918b2579
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2611593056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2611593056
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3672606631
Short name T389
Test name
Test status
Simulation time 9676344007 ps
CPU time 884.12 seconds
Started Aug 09 04:38:57 PM PDT 24
Finished Aug 09 04:53:41 PM PDT 24
Peak memory 271084 kb
Host smart-fed18788-3e44-4535-8009-e3aca91582ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672606631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3672606631
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3194289193
Short name T637
Test name
Test status
Simulation time 566810818 ps
CPU time 15.09 seconds
Started Aug 09 04:38:54 PM PDT 24
Finished Aug 09 04:39:09 PM PDT 24
Peak memory 248136 kb
Host smart-52558966-1fa8-4f00-adc2-c4eb9588e1a2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3194289193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3194289193
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.519734063
Short name T244
Test name
Test status
Simulation time 7896272921 ps
CPU time 130.4 seconds
Started Aug 09 04:38:53 PM PDT 24
Finished Aug 09 04:41:04 PM PDT 24
Peak memory 255624 kb
Host smart-90fe2e01-a792-4d7b-84ef-dc73faf236d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51973
4063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.519734063
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1642265789
Short name T382
Test name
Test status
Simulation time 207617025 ps
CPU time 12.68 seconds
Started Aug 09 04:38:58 PM PDT 24
Finished Aug 09 04:39:10 PM PDT 24
Peak memory 247580 kb
Host smart-9cb3c1e4-351d-4a1a-9410-c5c86c9447f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16422
65789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1642265789
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1486725970
Short name T83
Test name
Test status
Simulation time 46660963695 ps
CPU time 2516.61 seconds
Started Aug 09 04:38:52 PM PDT 24
Finished Aug 09 05:20:49 PM PDT 24
Peak memory 280932 kb
Host smart-7608e379-ab32-4a1f-a391-470b8e4961df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486725970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1486725970
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1646925987
Short name T594
Test name
Test status
Simulation time 25562045146 ps
CPU time 713.38 seconds
Started Aug 09 04:38:54 PM PDT 24
Finished Aug 09 04:50:47 PM PDT 24
Peak memory 272452 kb
Host smart-df98b9cd-baf1-4081-b84f-9d1d218bf8cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646925987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1646925987
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.4200905836
Short name T607
Test name
Test status
Simulation time 7030870814 ps
CPU time 280.92 seconds
Started Aug 09 04:38:48 PM PDT 24
Finished Aug 09 04:43:29 PM PDT 24
Peak memory 248108 kb
Host smart-192d37a1-7b4f-49d4-953b-33ca45be3a2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200905836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.4200905836
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.897791621
Short name T554
Test name
Test status
Simulation time 588800923 ps
CPU time 33.16 seconds
Started Aug 09 04:38:50 PM PDT 24
Finished Aug 09 04:39:23 PM PDT 24
Peak memory 248208 kb
Host smart-71b0b6b6-b66f-4847-bf58-be390ddb2173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89779
1621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.897791621
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1289972461
Short name T501
Test name
Test status
Simulation time 88171329 ps
CPU time 10.94 seconds
Started Aug 09 04:38:57 PM PDT 24
Finished Aug 09 04:39:08 PM PDT 24
Peak memory 247712 kb
Host smart-3f332568-43ef-4e4e-bf3c-2641238c78c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12899
72461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1289972461
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.213651101
Short name T398
Test name
Test status
Simulation time 722638645 ps
CPU time 41.25 seconds
Started Aug 09 04:38:56 PM PDT 24
Finished Aug 09 04:39:37 PM PDT 24
Peak memory 256428 kb
Host smart-2ab1c661-e3a2-4f31-a6a2-f9eb138b3453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21365
1101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.213651101
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.1617168713
Short name T27
Test name
Test status
Simulation time 50857296347 ps
CPU time 1678.51 seconds
Started Aug 09 04:38:52 PM PDT 24
Finished Aug 09 05:06:50 PM PDT 24
Peak memory 287088 kb
Host smart-d07f4254-041e-4058-8dab-d04944e049dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617168713 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.1617168713
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1554301259
Short name T209
Test name
Test status
Simulation time 13177551 ps
CPU time 2.22 seconds
Started Aug 09 04:38:50 PM PDT 24
Finished Aug 09 04:38:52 PM PDT 24
Peak memory 248396 kb
Host smart-6462c8b4-39b1-4679-b033-791248fa23ce
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1554301259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1554301259
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3831790420
Short name T280
Test name
Test status
Simulation time 24678261626 ps
CPU time 1045.05 seconds
Started Aug 09 04:39:03 PM PDT 24
Finished Aug 09 04:56:28 PM PDT 24
Peak memory 281892 kb
Host smart-7a36c0d4-e6c4-4129-86b3-c7e0014bad79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831790420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3831790420
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3991451096
Short name T507
Test name
Test status
Simulation time 2769303982 ps
CPU time 71.29 seconds
Started Aug 09 04:38:57 PM PDT 24
Finished Aug 09 04:40:08 PM PDT 24
Peak memory 248248 kb
Host smart-1c31d157-a160-495d-bfdb-568832031650
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3991451096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3991451096
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2205402131
Short name T96
Test name
Test status
Simulation time 2220205962 ps
CPU time 51.31 seconds
Started Aug 09 04:38:55 PM PDT 24
Finished Aug 09 04:39:46 PM PDT 24
Peak memory 255916 kb
Host smart-9e3cea4f-0f82-4cf8-9c75-a30540788073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22054
02131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2205402131
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.299795855
Short name T552
Test name
Test status
Simulation time 1224874707 ps
CPU time 71.14 seconds
Started Aug 09 04:38:47 PM PDT 24
Finished Aug 09 04:39:59 PM PDT 24
Peak memory 247700 kb
Host smart-893600e9-133e-4210-8c6e-cc52a15c9a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29979
5855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.299795855
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.4271189161
Short name T322
Test name
Test status
Simulation time 35275965237 ps
CPU time 1480.85 seconds
Started Aug 09 04:39:00 PM PDT 24
Finished Aug 09 05:03:41 PM PDT 24
Peak memory 272068 kb
Host smart-4cbef73c-1fca-4ee8-a66b-986ef416757f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271189161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.4271189161
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1577445132
Short name T77
Test name
Test status
Simulation time 18926458826 ps
CPU time 1069.44 seconds
Started Aug 09 04:38:51 PM PDT 24
Finished Aug 09 04:56:40 PM PDT 24
Peak memory 264620 kb
Host smart-55cd81f4-c60e-4303-a37c-d71d4ef93264
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577445132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1577445132
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3180054157
Short name T304
Test name
Test status
Simulation time 12133033775 ps
CPU time 121.84 seconds
Started Aug 09 04:39:01 PM PDT 24
Finished Aug 09 04:41:03 PM PDT 24
Peak memory 248188 kb
Host smart-8014d4c6-c1d5-4d8a-a6f1-1c9617ae8d9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180054157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3180054157
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.579145705
Short name T538
Test name
Test status
Simulation time 717493491 ps
CPU time 35.1 seconds
Started Aug 09 04:38:50 PM PDT 24
Finished Aug 09 04:39:26 PM PDT 24
Peak memory 256284 kb
Host smart-ae2d3653-b780-4e9f-930e-9f7862131b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57914
5705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.579145705
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1574932551
Short name T404
Test name
Test status
Simulation time 4824127310 ps
CPU time 79.83 seconds
Started Aug 09 04:38:51 PM PDT 24
Finished Aug 09 04:40:11 PM PDT 24
Peak memory 248280 kb
Host smart-ea8350bd-33de-4c36-94ec-d7cb7ead01e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15749
32551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1574932551
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.736233122
Short name T228
Test name
Test status
Simulation time 401753243 ps
CPU time 7.18 seconds
Started Aug 09 04:38:49 PM PDT 24
Finished Aug 09 04:38:56 PM PDT 24
Peak memory 248764 kb
Host smart-ee492025-2a5a-4d16-b1ca-c82674dfaa33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73623
3122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.736233122
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2488935758
Short name T381
Test name
Test status
Simulation time 745552404 ps
CPU time 47.25 seconds
Started Aug 09 04:38:52 PM PDT 24
Finished Aug 09 04:39:40 PM PDT 24
Peak memory 256344 kb
Host smart-f04441ed-3ccf-4f25-a77f-164ab35896d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24889
35758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2488935758
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.287922276
Short name T250
Test name
Test status
Simulation time 222402167433 ps
CPU time 5404.89 seconds
Started Aug 09 04:39:02 PM PDT 24
Finished Aug 09 06:09:07 PM PDT 24
Peak memory 371272 kb
Host smart-bd10ffcd-db06-4d8a-94ca-f5df2d75a3d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287922276 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.287922276
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2749447462
Short name T591
Test name
Test status
Simulation time 13670344756 ps
CPU time 1243.79 seconds
Started Aug 09 04:38:50 PM PDT 24
Finished Aug 09 04:59:34 PM PDT 24
Peak memory 284540 kb
Host smart-fe3b3ce5-3f81-4ee9-aaf5-810903333648
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749447462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2749447462
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3079712100
Short name T222
Test name
Test status
Simulation time 398253702 ps
CPU time 17.48 seconds
Started Aug 09 04:38:49 PM PDT 24
Finished Aug 09 04:39:07 PM PDT 24
Peak memory 248044 kb
Host smart-4fd8ed27-e814-4456-9e36-40abe945b782
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3079712100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3079712100
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.121779104
Short name T231
Test name
Test status
Simulation time 7960701853 ps
CPU time 151.27 seconds
Started Aug 09 04:38:54 PM PDT 24
Finished Aug 09 04:41:25 PM PDT 24
Peak memory 256384 kb
Host smart-d346fcf7-315e-49b4-81a4-16c3089d9318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12177
9104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.121779104
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3799814844
Short name T247
Test name
Test status
Simulation time 624214219 ps
CPU time 38.53 seconds
Started Aug 09 04:38:51 PM PDT 24
Finished Aug 09 04:39:30 PM PDT 24
Peak memory 247852 kb
Host smart-1dd5572f-757a-4c15-8d79-b0a607482c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37998
14844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3799814844
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1547239062
Short name T336
Test name
Test status
Simulation time 22488381273 ps
CPU time 1237.88 seconds
Started Aug 09 04:38:49 PM PDT 24
Finished Aug 09 04:59:27 PM PDT 24
Peak memory 272024 kb
Host smart-15cccfdc-93f1-40b0-9a35-9d5453a6c667
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547239062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1547239062
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.226827249
Short name T676
Test name
Test status
Simulation time 35339720749 ps
CPU time 1880.68 seconds
Started Aug 09 04:38:53 PM PDT 24
Finished Aug 09 05:10:14 PM PDT 24
Peak memory 285736 kb
Host smart-4df1f46e-8648-413e-bffb-3f48c7b1079c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226827249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.226827249
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.875366686
Short name T584
Test name
Test status
Simulation time 33224075307 ps
CPU time 322.32 seconds
Started Aug 09 04:38:43 PM PDT 24
Finished Aug 09 04:44:06 PM PDT 24
Peak memory 247904 kb
Host smart-9323c115-bc46-48ee-955e-dbcea2a38e7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875366686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.875366686
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3485831665
Short name T66
Test name
Test status
Simulation time 3034453424 ps
CPU time 46.3 seconds
Started Aug 09 04:38:57 PM PDT 24
Finished Aug 09 04:39:43 PM PDT 24
Peak memory 256188 kb
Host smart-75b2f196-d445-4ebb-9f95-ffd1f06d6b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34858
31665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3485831665
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.1473286771
Short name T407
Test name
Test status
Simulation time 676644733 ps
CPU time 12.42 seconds
Started Aug 09 04:38:53 PM PDT 24
Finished Aug 09 04:39:06 PM PDT 24
Peak memory 253540 kb
Host smart-aee781fd-30fb-4f7d-a325-88889ad23cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14732
86771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.1473286771
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.307405174
Short name T696
Test name
Test status
Simulation time 202060760 ps
CPU time 14.66 seconds
Started Aug 09 04:38:51 PM PDT 24
Finished Aug 09 04:39:06 PM PDT 24
Peak memory 254388 kb
Host smart-4b1120a9-0637-400b-a0fc-bd0a0d27c948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30740
5174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.307405174
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3566462245
Short name T212
Test name
Test status
Simulation time 48642854 ps
CPU time 3.99 seconds
Started Aug 09 04:38:59 PM PDT 24
Finished Aug 09 04:39:03 PM PDT 24
Peak memory 248400 kb
Host smart-0d2d9b59-b8b5-4c61-a745-5c5340cec7b5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3566462245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3566462245
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3897189505
Short name T571
Test name
Test status
Simulation time 10996270310 ps
CPU time 981.5 seconds
Started Aug 09 04:38:53 PM PDT 24
Finished Aug 09 04:55:14 PM PDT 24
Peak memory 272548 kb
Host smart-60c4f6ab-2ae8-4e93-bb65-24305c66de38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897189505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3897189505
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1020390055
Short name T547
Test name
Test status
Simulation time 856458408 ps
CPU time 15.98 seconds
Started Aug 09 04:38:54 PM PDT 24
Finished Aug 09 04:39:10 PM PDT 24
Peak memory 248164 kb
Host smart-7410f554-8930-44ef-8917-5c38eabfbc4c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1020390055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1020390055
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.4118478886
Short name T668
Test name
Test status
Simulation time 13039337548 ps
CPU time 209.89 seconds
Started Aug 09 04:39:00 PM PDT 24
Finished Aug 09 04:42:30 PM PDT 24
Peak memory 256416 kb
Host smart-f930c59f-ea98-400e-85ef-31b976ca765b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41184
78886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.4118478886
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2443902994
Short name T679
Test name
Test status
Simulation time 438694852 ps
CPU time 18.82 seconds
Started Aug 09 04:38:52 PM PDT 24
Finished Aug 09 04:39:11 PM PDT 24
Peak memory 255464 kb
Host smart-d00985ae-3cfa-40d2-be1c-75307b759a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24439
02994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2443902994
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3623697977
Short name T328
Test name
Test status
Simulation time 94374720541 ps
CPU time 1506.45 seconds
Started Aug 09 04:39:00 PM PDT 24
Finished Aug 09 05:04:07 PM PDT 24
Peak memory 272016 kb
Host smart-b386bcce-207b-4e8e-9ddb-48d6f45e40c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623697977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3623697977
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2969370995
Short name T435
Test name
Test status
Simulation time 48228309944 ps
CPU time 2662.6 seconds
Started Aug 09 04:39:04 PM PDT 24
Finished Aug 09 05:23:27 PM PDT 24
Peak memory 288700 kb
Host smart-3bc529c5-f442-49e5-862b-14c5bc883286
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969370995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2969370995
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2511978966
Short name T308
Test name
Test status
Simulation time 15815952967 ps
CPU time 325.84 seconds
Started Aug 09 04:39:00 PM PDT 24
Finished Aug 09 04:44:26 PM PDT 24
Peak memory 255748 kb
Host smart-0b436dff-3736-4d59-abcf-3e0d86aa4cb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511978966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2511978966
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.969622136
Short name T616
Test name
Test status
Simulation time 1281810727 ps
CPU time 34.28 seconds
Started Aug 09 04:38:51 PM PDT 24
Finished Aug 09 04:39:25 PM PDT 24
Peak memory 248124 kb
Host smart-da5266bd-5764-4a68-b833-ac399fb1847f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96962
2136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.969622136
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.817963880
Short name T63
Test name
Test status
Simulation time 1303662814 ps
CPU time 20.94 seconds
Started Aug 09 04:38:44 PM PDT 24
Finished Aug 09 04:39:05 PM PDT 24
Peak memory 255548 kb
Host smart-7e990483-9d46-431b-a72e-04d45518eddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81796
3880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.817963880
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.3358777929
Short name T505
Test name
Test status
Simulation time 865046283 ps
CPU time 16.03 seconds
Started Aug 09 04:38:57 PM PDT 24
Finished Aug 09 04:39:13 PM PDT 24
Peak memory 255596 kb
Host smart-d7aaa990-cad5-4663-9eac-7f4d9aaf658f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33587
77929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3358777929
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1947287794
Short name T283
Test name
Test status
Simulation time 2730804708 ps
CPU time 34.54 seconds
Started Aug 09 04:38:51 PM PDT 24
Finished Aug 09 04:39:26 PM PDT 24
Peak memory 248376 kb
Host smart-f4ebf852-6549-42ba-be61-8642f72c9feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19472
87794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1947287794
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.755244212
Short name T242
Test name
Test status
Simulation time 699947805188 ps
CPU time 4643.71 seconds
Started Aug 09 04:39:02 PM PDT 24
Finished Aug 09 05:56:26 PM PDT 24
Peak memory 305136 kb
Host smart-1d394a0d-d210-4e42-9b1d-fd7d2d17692b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755244212 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.755244212
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.416279790
Short name T202
Test name
Test status
Simulation time 40485790 ps
CPU time 3.27 seconds
Started Aug 09 04:38:57 PM PDT 24
Finished Aug 09 04:39:00 PM PDT 24
Peak memory 248516 kb
Host smart-5025bada-627e-49a4-ac8f-7e05a2af8dd5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=416279790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.416279790
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.846451077
Short name T412
Test name
Test status
Simulation time 60716583670 ps
CPU time 2003 seconds
Started Aug 09 04:39:02 PM PDT 24
Finished Aug 09 05:12:25 PM PDT 24
Peak memory 281088 kb
Host smart-a4c8c8a5-f96e-471c-b493-f856995fbe1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846451077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.846451077
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.637624574
Short name T476
Test name
Test status
Simulation time 2200171251 ps
CPU time 24.49 seconds
Started Aug 09 04:38:59 PM PDT 24
Finished Aug 09 04:39:23 PM PDT 24
Peak memory 248192 kb
Host smart-930b72de-713a-4ad5-a2d7-c98aa3a13728
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=637624574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.637624574
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.572124869
Short name T17
Test name
Test status
Simulation time 5690197643 ps
CPU time 111.98 seconds
Started Aug 09 04:38:58 PM PDT 24
Finished Aug 09 04:40:50 PM PDT 24
Peak memory 255992 kb
Host smart-1138800d-db11-4805-8ca5-72188429c867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57212
4869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.572124869
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3416912619
Short name T257
Test name
Test status
Simulation time 973565479 ps
CPU time 19.26 seconds
Started Aug 09 04:39:01 PM PDT 24
Finished Aug 09 04:39:20 PM PDT 24
Peak memory 254612 kb
Host smart-9a6781e9-e420-4710-8d62-f0ffe320df27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34169
12619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3416912619
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3321533738
Short name T33
Test name
Test status
Simulation time 74683562767 ps
CPU time 1922.59 seconds
Started Aug 09 04:38:58 PM PDT 24
Finished Aug 09 05:11:01 PM PDT 24
Peak memory 272196 kb
Host smart-dbc62efb-2b05-476b-b95a-55814a257da1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321533738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3321533738
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.4189656798
Short name T515
Test name
Test status
Simulation time 11144378368 ps
CPU time 885.47 seconds
Started Aug 09 04:39:01 PM PDT 24
Finished Aug 09 04:53:46 PM PDT 24
Peak memory 272788 kb
Host smart-3a6755b8-ebb0-4261-b295-42aff3411dda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189656798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.4189656798
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.1513967117
Short name T316
Test name
Test status
Simulation time 243093147394 ps
CPU time 475.21 seconds
Started Aug 09 04:38:59 PM PDT 24
Finished Aug 09 04:46:55 PM PDT 24
Peak memory 248188 kb
Host smart-09ed43b7-bc94-4f24-abe9-51a77f01984b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513967117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1513967117
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1361755423
Short name T387
Test name
Test status
Simulation time 139305338 ps
CPU time 9.4 seconds
Started Aug 09 04:38:54 PM PDT 24
Finished Aug 09 04:39:04 PM PDT 24
Peak memory 248204 kb
Host smart-0c6074b0-52b0-4f92-bb8e-44be6de2152a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13617
55423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1361755423
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3113522779
Short name T199
Test name
Test status
Simulation time 1052115797 ps
CPU time 23.34 seconds
Started Aug 09 04:39:03 PM PDT 24
Finished Aug 09 04:39:27 PM PDT 24
Peak memory 248164 kb
Host smart-d8d1926e-90e1-45d7-9c29-1f5d2eb954f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31135
22779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3113522779
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.390395144
Short name T714
Test name
Test status
Simulation time 306762950 ps
CPU time 28.1 seconds
Started Aug 09 04:39:00 PM PDT 24
Finished Aug 09 04:39:29 PM PDT 24
Peak memory 255732 kb
Host smart-3b7e79a8-25ba-4118-a5fb-d85170ba0752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39039
5144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.390395144
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2412631095
Short name T598
Test name
Test status
Simulation time 348564732 ps
CPU time 22.39 seconds
Started Aug 09 04:38:59 PM PDT 24
Finished Aug 09 04:39:22 PM PDT 24
Peak memory 248564 kb
Host smart-e2e2850b-73ae-4ca5-8336-c06be142c89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24126
31095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2412631095
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1500200708
Short name T57
Test name
Test status
Simulation time 46877857185 ps
CPU time 2849.87 seconds
Started Aug 09 04:39:01 PM PDT 24
Finished Aug 09 05:26:32 PM PDT 24
Peak memory 288116 kb
Host smart-cff95b79-74ae-4cb3-a0d5-921d765dcf80
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500200708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1500200708
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.743890396
Short name T204
Test name
Test status
Simulation time 27922460 ps
CPU time 2.5 seconds
Started Aug 09 04:38:25 PM PDT 24
Finished Aug 09 04:38:27 PM PDT 24
Peak memory 248384 kb
Host smart-de7c9037-7643-4cc3-8d54-03dde9b457a3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=743890396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.743890396
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3358844336
Short name T102
Test name
Test status
Simulation time 53184992425 ps
CPU time 1288.61 seconds
Started Aug 09 04:38:16 PM PDT 24
Finished Aug 09 04:59:45 PM PDT 24
Peak memory 272828 kb
Host smart-bbb6ddfc-8c44-4a67-a09d-f9dc1e281426
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358844336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3358844336
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3917913803
Short name T596
Test name
Test status
Simulation time 1026425384 ps
CPU time 43.31 seconds
Started Aug 09 04:38:21 PM PDT 24
Finished Aug 09 04:39:04 PM PDT 24
Peak memory 248220 kb
Host smart-6db4a9ee-357a-457b-bbef-0cd7b99eb16c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3917913803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3917913803
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.642321376
Short name T722
Test name
Test status
Simulation time 4653060343 ps
CPU time 134.13 seconds
Started Aug 09 04:38:34 PM PDT 24
Finished Aug 09 04:40:49 PM PDT 24
Peak memory 255680 kb
Host smart-a75c0fc6-e138-4bfd-a840-fd69bf237ab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64232
1376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.642321376
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.156258148
Short name T519
Test name
Test status
Simulation time 354549705 ps
CPU time 33.73 seconds
Started Aug 09 04:38:25 PM PDT 24
Finished Aug 09 04:38:59 PM PDT 24
Peak memory 256052 kb
Host smart-4b8b66d2-1453-4d7d-b286-f17b617b4738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15625
8148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.156258148
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.4045346772
Short name T108
Test name
Test status
Simulation time 68816736910 ps
CPU time 2122.1 seconds
Started Aug 09 04:38:22 PM PDT 24
Finished Aug 09 05:13:44 PM PDT 24
Peak memory 272892 kb
Host smart-833cbc79-dba3-43bf-a2a4-061b6b6dcdf1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045346772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.4045346772
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.672620563
Short name T707
Test name
Test status
Simulation time 230014972 ps
CPU time 6.36 seconds
Started Aug 09 04:38:12 PM PDT 24
Finished Aug 09 04:38:19 PM PDT 24
Peak memory 248068 kb
Host smart-51e2c389-81cb-48e4-a38b-f5b9e461a756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67262
0563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.672620563
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2249562059
Short name T89
Test name
Test status
Simulation time 272567402 ps
CPU time 8.92 seconds
Started Aug 09 04:38:18 PM PDT 24
Finished Aug 09 04:38:27 PM PDT 24
Peak memory 255696 kb
Host smart-80ca5f2e-7395-4a86-8163-0f21e4a9c717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22495
62059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2249562059
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.809814306
Short name T9
Test name
Test status
Simulation time 424951486 ps
CPU time 13.26 seconds
Started Aug 09 04:38:27 PM PDT 24
Finished Aug 09 04:38:41 PM PDT 24
Peak memory 272892 kb
Host smart-6e6b9267-ac84-4a86-a54f-34d30ba3a29e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=809814306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.809814306
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3452673670
Short name T258
Test name
Test status
Simulation time 332341629 ps
CPU time 37.83 seconds
Started Aug 09 04:38:29 PM PDT 24
Finished Aug 09 04:39:07 PM PDT 24
Peak memory 256208 kb
Host smart-90c736ae-2897-402c-8fe3-e8abd6035b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34526
73670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3452673670
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.923112943
Short name T411
Test name
Test status
Simulation time 3565709347 ps
CPU time 55.28 seconds
Started Aug 09 04:38:12 PM PDT 24
Finished Aug 09 04:39:08 PM PDT 24
Peak memory 248168 kb
Host smart-7853f771-218f-40a8-bf36-ee9a91130704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92311
2943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.923112943
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3368056876
Short name T262
Test name
Test status
Simulation time 217064210499 ps
CPU time 3510.14 seconds
Started Aug 09 04:38:30 PM PDT 24
Finished Aug 09 05:37:01 PM PDT 24
Peak memory 289304 kb
Host smart-5db3f254-9ffb-4698-bc68-f4cda15f59c9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368056876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3368056876
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.3693089756
Short name T82
Test name
Test status
Simulation time 395078047149 ps
CPU time 5732.77 seconds
Started Aug 09 04:38:25 PM PDT 24
Finished Aug 09 06:13:58 PM PDT 24
Peak memory 297560 kb
Host smart-2800fa52-d727-420c-840d-076a7793d9b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693089756 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.3693089756
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.574548562
Short name T672
Test name
Test status
Simulation time 168381451128 ps
CPU time 2584.91 seconds
Started Aug 09 04:38:54 PM PDT 24
Finished Aug 09 05:21:59 PM PDT 24
Peak memory 287456 kb
Host smart-3731d82b-5440-4725-bd58-37656366ee81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574548562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.574548562
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1944524599
Short name T702
Test name
Test status
Simulation time 1566068667 ps
CPU time 56.52 seconds
Started Aug 09 04:39:02 PM PDT 24
Finished Aug 09 04:39:59 PM PDT 24
Peak memory 256332 kb
Host smart-eb2eb14f-4e8b-445b-9d1e-c01f93983c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19445
24599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1944524599
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1860085879
Short name T493
Test name
Test status
Simulation time 1138288817 ps
CPU time 21.99 seconds
Started Aug 09 04:38:50 PM PDT 24
Finished Aug 09 04:39:13 PM PDT 24
Peak memory 248228 kb
Host smart-65231dc5-097e-49c4-ae1f-00f91a1de63d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18600
85879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1860085879
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.610053269
Short name T333
Test name
Test status
Simulation time 38989591456 ps
CPU time 1855.58 seconds
Started Aug 09 04:39:01 PM PDT 24
Finished Aug 09 05:09:57 PM PDT 24
Peak memory 288920 kb
Host smart-03373adc-603e-4c89-a63b-30cdb893a8da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610053269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.610053269
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.303570645
Short name T302
Test name
Test status
Simulation time 58681119250 ps
CPU time 507.93 seconds
Started Aug 09 04:39:00 PM PDT 24
Finished Aug 09 04:47:28 PM PDT 24
Peak memory 255052 kb
Host smart-80e82a39-1282-4c1a-8e72-36d05c77d7b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303570645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.303570645
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3876142141
Short name T427
Test name
Test status
Simulation time 375649945 ps
CPU time 22.05 seconds
Started Aug 09 04:39:02 PM PDT 24
Finished Aug 09 04:39:24 PM PDT 24
Peak memory 254832 kb
Host smart-2ce194f7-3b54-41d7-8df8-0bacb575c89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38761
42141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3876142141
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2494737047
Short name T603
Test name
Test status
Simulation time 1031550980 ps
CPU time 36.05 seconds
Started Aug 09 04:39:01 PM PDT 24
Finished Aug 09 04:39:37 PM PDT 24
Peak memory 255896 kb
Host smart-ccde403f-86b1-4ff9-9f36-d4eaf6830468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24947
37047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2494737047
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3700014233
Short name T717
Test name
Test status
Simulation time 1054746820 ps
CPU time 13.86 seconds
Started Aug 09 04:38:56 PM PDT 24
Finished Aug 09 04:39:10 PM PDT 24
Peak memory 255956 kb
Host smart-9a880142-4f20-46c3-b820-062ab943c6e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37000
14233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3700014233
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.993776848
Short name T464
Test name
Test status
Simulation time 508262754 ps
CPU time 28.05 seconds
Started Aug 09 04:38:57 PM PDT 24
Finished Aug 09 04:39:26 PM PDT 24
Peak memory 256320 kb
Host smart-c4285a23-8fbc-4080-9f4d-27ed6fac9e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99377
6848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.993776848
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1299956050
Short name T270
Test name
Test status
Simulation time 34803296060 ps
CPU time 2277.11 seconds
Started Aug 09 04:38:56 PM PDT 24
Finished Aug 09 05:16:53 PM PDT 24
Peak memory 288580 kb
Host smart-47a2ba42-5c72-44c6-816b-2a9cb63ba312
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299956050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1299956050
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.241028710
Short name T251
Test name
Test status
Simulation time 128708874106 ps
CPU time 2121.29 seconds
Started Aug 09 04:38:55 PM PDT 24
Finished Aug 09 05:14:17 PM PDT 24
Peak memory 289292 kb
Host smart-6698442d-1a0c-4096-8c4b-69f048f87bb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241028710 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.241028710
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1540657444
Short name T573
Test name
Test status
Simulation time 19493088858 ps
CPU time 1638.61 seconds
Started Aug 09 04:38:57 PM PDT 24
Finished Aug 09 05:06:16 PM PDT 24
Peak memory 287908 kb
Host smart-c9d931b6-3d88-4348-b2c2-7607f551ee63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540657444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1540657444
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.860346737
Short name T673
Test name
Test status
Simulation time 178984225 ps
CPU time 10.27 seconds
Started Aug 09 04:39:02 PM PDT 24
Finished Aug 09 04:39:12 PM PDT 24
Peak memory 255904 kb
Host smart-075ff247-7d14-493d-be3c-81792963caa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86034
6737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.860346737
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.4002400814
Short name T18
Test name
Test status
Simulation time 1696916516 ps
CPU time 50.78 seconds
Started Aug 09 04:38:53 PM PDT 24
Finished Aug 09 04:39:44 PM PDT 24
Peak memory 255556 kb
Host smart-32c3ebdc-475d-4763-b56b-90ff3b961ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40024
00814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.4002400814
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.747756008
Short name T640
Test name
Test status
Simulation time 163014464157 ps
CPU time 1518.34 seconds
Started Aug 09 04:38:59 PM PDT 24
Finished Aug 09 05:04:18 PM PDT 24
Peak memory 272736 kb
Host smart-61a4ba87-9bc1-457b-8878-e47955d403bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747756008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.747756008
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.951366821
Short name T692
Test name
Test status
Simulation time 31834129116 ps
CPU time 318.81 seconds
Started Aug 09 04:39:00 PM PDT 24
Finished Aug 09 04:44:19 PM PDT 24
Peak memory 248072 kb
Host smart-4e8efcac-830c-4e32-8ed5-c3f5505ba6fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951366821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.951366821
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.231040458
Short name T36
Test name
Test status
Simulation time 703494299 ps
CPU time 6.93 seconds
Started Aug 09 04:38:59 PM PDT 24
Finished Aug 09 04:39:06 PM PDT 24
Peak memory 248172 kb
Host smart-ee43ef49-d322-4967-8ae3-0f96cf0b2405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23104
0458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.231040458
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1081538997
Short name T281
Test name
Test status
Simulation time 2658029999 ps
CPU time 35.79 seconds
Started Aug 09 04:38:54 PM PDT 24
Finished Aug 09 04:39:30 PM PDT 24
Peak memory 247928 kb
Host smart-3d0e846a-4149-46f6-971e-3a7dca4f07bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10815
38997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1081538997
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2832872271
Short name T44
Test name
Test status
Simulation time 490951139 ps
CPU time 8.51 seconds
Started Aug 09 04:38:56 PM PDT 24
Finished Aug 09 04:39:05 PM PDT 24
Peak memory 255124 kb
Host smart-c76d3bfa-57d9-4846-9fd9-c1cdb1ab7efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28328
72271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2832872271
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1754854357
Short name T383
Test name
Test status
Simulation time 153842676 ps
CPU time 17.75 seconds
Started Aug 09 04:38:57 PM PDT 24
Finished Aug 09 04:39:15 PM PDT 24
Peak memory 256184 kb
Host smart-1ec9c267-c67a-40fa-9d1c-28a94a7a23d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17548
54357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1754854357
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2205027778
Short name T710
Test name
Test status
Simulation time 31891055393 ps
CPU time 918.4 seconds
Started Aug 09 04:38:59 PM PDT 24
Finished Aug 09 04:54:18 PM PDT 24
Peak memory 281508 kb
Host smart-595ffd0e-e927-4be3-a4e5-e3b7b68f0cad
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205027778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2205027778
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1888466579
Short name T54
Test name
Test status
Simulation time 27627723766 ps
CPU time 1639.04 seconds
Started Aug 09 04:38:56 PM PDT 24
Finished Aug 09 05:06:15 PM PDT 24
Peak memory 286580 kb
Host smart-f8beeb8f-cdca-4175-9aea-c5948cd563fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888466579 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1888466579
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2116825656
Short name T78
Test name
Test status
Simulation time 15645153891 ps
CPU time 1372.84 seconds
Started Aug 09 04:39:03 PM PDT 24
Finished Aug 09 05:01:56 PM PDT 24
Peak memory 289008 kb
Host smart-da62ea7c-58ed-4420-b4a6-dde667339056
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116825656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2116825656
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2995525854
Short name T595
Test name
Test status
Simulation time 1294766209 ps
CPU time 75.85 seconds
Started Aug 09 04:39:00 PM PDT 24
Finished Aug 09 04:40:16 PM PDT 24
Peak memory 255820 kb
Host smart-2ee5c9cc-363a-4182-80d2-7e7a10f0c710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29955
25854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2995525854
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3336180333
Short name T86
Test name
Test status
Simulation time 347172815 ps
CPU time 39.43 seconds
Started Aug 09 04:38:54 PM PDT 24
Finished Aug 09 04:39:34 PM PDT 24
Peak memory 247972 kb
Host smart-2d0d6005-4336-4ac5-a3c5-d6bad4d4c555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33361
80333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3336180333
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1876484448
Short name T600
Test name
Test status
Simulation time 56397781321 ps
CPU time 1718.68 seconds
Started Aug 09 04:38:57 PM PDT 24
Finished Aug 09 05:07:36 PM PDT 24
Peak memory 272800 kb
Host smart-41b639bf-0fb8-461a-a740-a6a9d5e89a94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876484448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1876484448
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2417782543
Short name T492
Test name
Test status
Simulation time 64858156424 ps
CPU time 1718.51 seconds
Started Aug 09 04:39:01 PM PDT 24
Finished Aug 09 05:07:39 PM PDT 24
Peak memory 272728 kb
Host smart-99165901-b3b0-4e9f-bb87-aac7d1c1f233
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417782543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2417782543
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1923666115
Short name T633
Test name
Test status
Simulation time 11543852307 ps
CPU time 464.31 seconds
Started Aug 09 04:39:01 PM PDT 24
Finished Aug 09 04:46:45 PM PDT 24
Peak memory 248208 kb
Host smart-3d6a62cf-3abe-4e65-b665-424564840e9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923666115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1923666115
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3231809166
Short name T575
Test name
Test status
Simulation time 1227491103 ps
CPU time 38.31 seconds
Started Aug 09 04:39:00 PM PDT 24
Finished Aug 09 04:39:38 PM PDT 24
Peak memory 248028 kb
Host smart-4d3b66ea-907f-47cf-97ea-96d41fef2da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32318
09166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3231809166
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3409968404
Short name T20
Test name
Test status
Simulation time 548352529 ps
CPU time 31.68 seconds
Started Aug 09 04:39:00 PM PDT 24
Finished Aug 09 04:39:32 PM PDT 24
Peak memory 247760 kb
Host smart-d23e9ac7-a60b-441f-9681-a7e550a9fbc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34099
68404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3409968404
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.328180988
Short name T32
Test name
Test status
Simulation time 1240026618 ps
CPU time 47.92 seconds
Started Aug 09 04:39:05 PM PDT 24
Finished Aug 09 04:39:53 PM PDT 24
Peak memory 255904 kb
Host smart-4b457144-e477-423b-b98d-279a6951e3e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32818
0988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.328180988
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.4093926084
Short name T535
Test name
Test status
Simulation time 1034026694 ps
CPU time 28.89 seconds
Started Aug 09 04:38:58 PM PDT 24
Finished Aug 09 04:39:27 PM PDT 24
Peak memory 248136 kb
Host smart-6dd65bde-0951-457d-b4ee-f4c4f632152d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40939
26084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.4093926084
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2431127765
Short name T50
Test name
Test status
Simulation time 235948570784 ps
CPU time 1812.26 seconds
Started Aug 09 04:39:00 PM PDT 24
Finished Aug 09 05:09:12 PM PDT 24
Peak memory 288628 kb
Host smart-07ed315e-a893-45b7-bd03-ee5e74ff689f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431127765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2431127765
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.4064670878
Short name T503
Test name
Test status
Simulation time 11915156151 ps
CPU time 940.71 seconds
Started Aug 09 04:39:02 PM PDT 24
Finished Aug 09 04:54:43 PM PDT 24
Peak memory 271908 kb
Host smart-28abb2bf-b4b1-4e28-a61f-1a2495820b68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064670878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.4064670878
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2510961532
Short name T597
Test name
Test status
Simulation time 3362435389 ps
CPU time 229.62 seconds
Started Aug 09 04:39:02 PM PDT 24
Finished Aug 09 04:42:52 PM PDT 24
Peak memory 250360 kb
Host smart-eac35347-d411-47a8-a5fd-dfad8e45ad04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25109
61532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2510961532
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.4269316688
Short name T269
Test name
Test status
Simulation time 6814152362 ps
CPU time 56.69 seconds
Started Aug 09 04:39:01 PM PDT 24
Finished Aug 09 04:39:58 PM PDT 24
Peak memory 248300 kb
Host smart-f8176a9a-0442-4990-824c-5f08c8f35522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42693
16688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.4269316688
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2929554200
Short name T615
Test name
Test status
Simulation time 89182817708 ps
CPU time 1930.18 seconds
Started Aug 09 04:39:03 PM PDT 24
Finished Aug 09 05:11:14 PM PDT 24
Peak memory 272716 kb
Host smart-a9d73519-1b8f-47f3-9c67-57a2ce2eaf76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929554200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2929554200
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2583249809
Short name T430
Test name
Test status
Simulation time 10185776956 ps
CPU time 1109.32 seconds
Started Aug 09 04:38:57 PM PDT 24
Finished Aug 09 04:57:27 PM PDT 24
Peak memory 279744 kb
Host smart-93a4fcc6-447d-4701-975a-4e7057d85500
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583249809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2583249809
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2438526349
Short name T548
Test name
Test status
Simulation time 10137780330 ps
CPU time 255.76 seconds
Started Aug 09 04:39:06 PM PDT 24
Finished Aug 09 04:43:22 PM PDT 24
Peak memory 246816 kb
Host smart-b085a4be-ddbb-406d-9d1f-42f0ac11f947
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438526349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2438526349
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3704765761
Short name T628
Test name
Test status
Simulation time 275321636 ps
CPU time 16.49 seconds
Started Aug 09 04:38:53 PM PDT 24
Finished Aug 09 04:39:09 PM PDT 24
Peak memory 255324 kb
Host smart-5893b4c6-6213-436f-8fae-a2029c0a0633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37047
65761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3704765761
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1027597283
Short name T99
Test name
Test status
Simulation time 732502370 ps
CPU time 19.69 seconds
Started Aug 09 04:39:02 PM PDT 24
Finished Aug 09 04:39:21 PM PDT 24
Peak memory 248124 kb
Host smart-80aec7de-d3f9-4c9b-b137-82a493283266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10275
97283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1027597283
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.4071951535
Short name T434
Test name
Test status
Simulation time 233644537 ps
CPU time 5.65 seconds
Started Aug 09 04:39:02 PM PDT 24
Finished Aug 09 04:39:08 PM PDT 24
Peak memory 239216 kb
Host smart-eb8cba82-3727-4d75-afcf-e6a95eb46321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40719
51535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.4071951535
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2242268008
Short name T443
Test name
Test status
Simulation time 403062477 ps
CPU time 6.46 seconds
Started Aug 09 04:39:05 PM PDT 24
Finished Aug 09 04:39:12 PM PDT 24
Peak memory 251152 kb
Host smart-c46a5cff-78e9-4598-b272-63eacce11fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22422
68008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2242268008
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1533911745
Short name T524
Test name
Test status
Simulation time 26550935559 ps
CPU time 1269.2 seconds
Started Aug 09 04:39:00 PM PDT 24
Finished Aug 09 05:00:09 PM PDT 24
Peak memory 280960 kb
Host smart-d48a117f-eef1-412c-ad4f-95357caae2ee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533911745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1533911745
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1803454909
Short name T378
Test name
Test status
Simulation time 39100315655 ps
CPU time 1289.49 seconds
Started Aug 09 04:39:02 PM PDT 24
Finished Aug 09 05:00:32 PM PDT 24
Peak memory 288936 kb
Host smart-98ebedc0-4a91-4349-b7a6-7060cab2a06e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803454909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1803454909
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.388716102
Short name T422
Test name
Test status
Simulation time 3039324750 ps
CPU time 199.14 seconds
Started Aug 09 04:39:01 PM PDT 24
Finished Aug 09 04:42:20 PM PDT 24
Peak memory 256104 kb
Host smart-dd609d5b-9d25-4a16-b2d6-74685dc2f2df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38871
6102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.388716102
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3963795847
Short name T34
Test name
Test status
Simulation time 747902436 ps
CPU time 13.49 seconds
Started Aug 09 04:39:07 PM PDT 24
Finished Aug 09 04:39:20 PM PDT 24
Peak memory 253764 kb
Host smart-f2403369-2984-462a-aba3-b45cc0149011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39637
95847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3963795847
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.834208870
Short name T41
Test name
Test status
Simulation time 189964137648 ps
CPU time 2748 seconds
Started Aug 09 04:39:02 PM PDT 24
Finished Aug 09 05:24:50 PM PDT 24
Peak memory 287516 kb
Host smart-b420d072-8c53-4497-be6c-6fe311a86a9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834208870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.834208870
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.978541943
Short name T73
Test name
Test status
Simulation time 118453492947 ps
CPU time 469.98 seconds
Started Aug 09 04:39:01 PM PDT 24
Finished Aug 09 04:46:51 PM PDT 24
Peak memory 248224 kb
Host smart-3662a641-9f4a-43e7-9ca2-a3da132fe04f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978541943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.978541943
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3145697873
Short name T406
Test name
Test status
Simulation time 783491766 ps
CPU time 55.34 seconds
Started Aug 09 04:39:08 PM PDT 24
Finished Aug 09 04:40:03 PM PDT 24
Peak memory 255604 kb
Host smart-550bd10f-1134-484c-89c7-a5e79604f398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31456
97873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3145697873
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3536210074
Short name T618
Test name
Test status
Simulation time 566814289 ps
CPU time 26.54 seconds
Started Aug 09 04:39:04 PM PDT 24
Finished Aug 09 04:39:30 PM PDT 24
Peak memory 248188 kb
Host smart-00c39116-0a86-49ef-9054-a7544e95286d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35362
10074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3536210074
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.654460528
Short name T286
Test name
Test status
Simulation time 440531246 ps
CPU time 22.41 seconds
Started Aug 09 04:39:07 PM PDT 24
Finished Aug 09 04:39:29 PM PDT 24
Peak memory 256360 kb
Host smart-9e4ac597-50a2-4feb-bc8a-896123b9e346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65446
0528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.654460528
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2647892363
Short name T290
Test name
Test status
Simulation time 15954059591 ps
CPU time 1783.67 seconds
Started Aug 09 04:39:12 PM PDT 24
Finished Aug 09 05:08:56 PM PDT 24
Peak memory 305260 kb
Host smart-8378b81f-c9e1-486b-a40e-85d7cb84e554
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647892363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2647892363
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3034470783
Short name T646
Test name
Test status
Simulation time 199100505217 ps
CPU time 3051.77 seconds
Started Aug 09 04:39:06 PM PDT 24
Finished Aug 09 05:29:58 PM PDT 24
Peak memory 288348 kb
Host smart-3ffa03da-8053-4fef-ac19-6abd52e0eb19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034470783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3034470783
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1691433251
Short name T439
Test name
Test status
Simulation time 12929865451 ps
CPU time 192.81 seconds
Started Aug 09 04:39:09 PM PDT 24
Finished Aug 09 04:42:22 PM PDT 24
Peak memory 255752 kb
Host smart-9fcb0c0a-a963-45ce-8e8b-5aa7ba3c883f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16914
33251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1691433251
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3167241743
Short name T394
Test name
Test status
Simulation time 2753536911 ps
CPU time 41.89 seconds
Started Aug 09 04:39:06 PM PDT 24
Finished Aug 09 04:39:48 PM PDT 24
Peak memory 248240 kb
Host smart-5d7cd070-1fcf-476f-bbae-50159149373d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31672
41743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3167241743
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3628344045
Short name T536
Test name
Test status
Simulation time 353146076718 ps
CPU time 2060.81 seconds
Started Aug 09 04:39:10 PM PDT 24
Finished Aug 09 05:13:32 PM PDT 24
Peak memory 272304 kb
Host smart-df6b8ccb-e33b-4ca9-93e7-2a6c101d083d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628344045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3628344045
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.757908479
Short name T413
Test name
Test status
Simulation time 13516783340 ps
CPU time 1255.51 seconds
Started Aug 09 04:39:04 PM PDT 24
Finished Aug 09 04:59:59 PM PDT 24
Peak memory 284060 kb
Host smart-d2c0ae82-5fa9-4bad-aadb-8c4d471de30b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757908479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.757908479
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1278607717
Short name T641
Test name
Test status
Simulation time 7402770843 ps
CPU time 270.48 seconds
Started Aug 09 04:39:02 PM PDT 24
Finished Aug 09 04:43:32 PM PDT 24
Peak memory 247976 kb
Host smart-a13dc213-d6be-4418-b52c-a05b92729a44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278607717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1278607717
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1856572175
Short name T619
Test name
Test status
Simulation time 4801579995 ps
CPU time 62.5 seconds
Started Aug 09 04:39:05 PM PDT 24
Finished Aug 09 04:40:08 PM PDT 24
Peak memory 256472 kb
Host smart-4925353d-d3ef-4ed1-92ab-08af658b0fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18565
72175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1856572175
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1506677229
Short name T104
Test name
Test status
Simulation time 388174211 ps
CPU time 12.19 seconds
Started Aug 09 04:39:02 PM PDT 24
Finished Aug 09 04:39:14 PM PDT 24
Peak memory 255900 kb
Host smart-54fba263-1c71-469f-8858-33dbac786618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15066
77229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1506677229
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3728686175
Short name T621
Test name
Test status
Simulation time 117202937 ps
CPU time 13.03 seconds
Started Aug 09 04:39:05 PM PDT 24
Finished Aug 09 04:39:18 PM PDT 24
Peak memory 248692 kb
Host smart-2afdb790-975d-4fe9-aa3a-41259420861d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37286
86175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3728686175
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.712466989
Short name T663
Test name
Test status
Simulation time 3664739250 ps
CPU time 29.85 seconds
Started Aug 09 04:39:10 PM PDT 24
Finished Aug 09 04:39:40 PM PDT 24
Peak memory 256436 kb
Host smart-5f9ab65f-712a-4cd9-9df6-6a57d87534c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71246
6989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.712466989
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.326303896
Short name T51
Test name
Test status
Simulation time 57528908810 ps
CPU time 864.74 seconds
Started Aug 09 04:39:08 PM PDT 24
Finished Aug 09 04:53:33 PM PDT 24
Peak memory 264676 kb
Host smart-d16bf819-12a5-4385-b031-db3c9c1f1177
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326303896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.326303896
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.324758308
Short name T508
Test name
Test status
Simulation time 164625087712 ps
CPU time 2582.69 seconds
Started Aug 09 04:39:11 PM PDT 24
Finished Aug 09 05:22:14 PM PDT 24
Peak memory 298936 kb
Host smart-b8ea6a18-f8af-4056-9391-1cc9ef461b91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324758308 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.324758308
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.4227813483
Short name T80
Test name
Test status
Simulation time 437897372847 ps
CPU time 2606.19 seconds
Started Aug 09 04:39:03 PM PDT 24
Finished Aug 09 05:22:30 PM PDT 24
Peak memory 288896 kb
Host smart-1a8bf952-cc54-4dac-9328-047bce955633
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227813483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.4227813483
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2753557330
Short name T421
Test name
Test status
Simulation time 6124511358 ps
CPU time 141.29 seconds
Started Aug 09 04:39:04 PM PDT 24
Finished Aug 09 04:41:25 PM PDT 24
Peak memory 256268 kb
Host smart-0d87f4ba-d61b-443c-879d-8c2f4bd65d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27535
57330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2753557330
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.4075438135
Short name T229
Test name
Test status
Simulation time 285395868 ps
CPU time 8.77 seconds
Started Aug 09 04:39:13 PM PDT 24
Finished Aug 09 04:39:22 PM PDT 24
Peak memory 247460 kb
Host smart-685eb320-7af4-40ea-9454-c280d4f7a5ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40754
38135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.4075438135
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1766253717
Short name T323
Test name
Test status
Simulation time 19224944972 ps
CPU time 1309.34 seconds
Started Aug 09 04:39:07 PM PDT 24
Finished Aug 09 05:00:56 PM PDT 24
Peak memory 285844 kb
Host smart-6617cc0f-f62b-4f8a-a49f-5181f09be654
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766253717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1766253717
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1517208405
Short name T482
Test name
Test status
Simulation time 6237586743 ps
CPU time 581.06 seconds
Started Aug 09 04:39:00 PM PDT 24
Finished Aug 09 04:48:42 PM PDT 24
Peak memory 272784 kb
Host smart-907d679a-6df6-43cb-90ca-de8f0b0ee124
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517208405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1517208405
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2898042619
Short name T317
Test name
Test status
Simulation time 6190571610 ps
CPU time 271.59 seconds
Started Aug 09 04:39:01 PM PDT 24
Finished Aug 09 04:43:33 PM PDT 24
Peak memory 248208 kb
Host smart-05fcf1ca-427f-400f-9e5d-bd706c7952f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898042619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2898042619
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.845449636
Short name T723
Test name
Test status
Simulation time 189714384 ps
CPU time 4.58 seconds
Started Aug 09 04:39:06 PM PDT 24
Finished Aug 09 04:39:10 PM PDT 24
Peak memory 250400 kb
Host smart-85e741e1-8c90-4dcf-bb6b-af74b150a1f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84544
9636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.845449636
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2452568469
Short name T282
Test name
Test status
Simulation time 794748686 ps
CPU time 46.34 seconds
Started Aug 09 04:39:07 PM PDT 24
Finished Aug 09 04:39:54 PM PDT 24
Peak memory 255688 kb
Host smart-ce1944a7-cf74-4463-ad9c-ba9b410e6b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24525
68469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2452568469
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1940773147
Short name T452
Test name
Test status
Simulation time 674556985 ps
CPU time 19.56 seconds
Started Aug 09 04:39:14 PM PDT 24
Finished Aug 09 04:39:34 PM PDT 24
Peak memory 247680 kb
Host smart-fbfda783-8395-460a-827f-c8f00080b97f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19407
73147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1940773147
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3670375227
Short name T113
Test name
Test status
Simulation time 613297673 ps
CPU time 35.16 seconds
Started Aug 09 04:39:09 PM PDT 24
Finished Aug 09 04:39:44 PM PDT 24
Peak memory 248080 kb
Host smart-faef65db-2545-4b82-97d4-dd270f1aa0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36703
75227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3670375227
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3892510503
Short name T720
Test name
Test status
Simulation time 5266526378 ps
CPU time 117.94 seconds
Started Aug 09 04:39:10 PM PDT 24
Finished Aug 09 04:41:08 PM PDT 24
Peak memory 256476 kb
Host smart-5f5f575b-bcbf-403a-b419-5ded382261b8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892510503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3892510503
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.62610403
Short name T450
Test name
Test status
Simulation time 66876441118 ps
CPU time 2075.89 seconds
Started Aug 09 04:39:10 PM PDT 24
Finished Aug 09 05:13:46 PM PDT 24
Peak memory 288096 kb
Host smart-e8da25c4-8d7d-43d7-9ea5-80d765f92267
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62610403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.62610403
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.4185620934
Short name T592
Test name
Test status
Simulation time 4873417113 ps
CPU time 59.27 seconds
Started Aug 09 04:39:12 PM PDT 24
Finished Aug 09 04:40:12 PM PDT 24
Peak memory 255772 kb
Host smart-5b5dcac7-5f4f-43e2-ae52-4a49e9e0f5f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41856
20934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.4185620934
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1466283084
Short name T420
Test name
Test status
Simulation time 370634933 ps
CPU time 17.89 seconds
Started Aug 09 04:39:11 PM PDT 24
Finished Aug 09 04:39:29 PM PDT 24
Peak memory 255884 kb
Host smart-9864b3d8-23a4-4ee0-beee-4b13d72e3c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14662
83084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1466283084
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1984966448
Short name T712
Test name
Test status
Simulation time 39138520511 ps
CPU time 2014.34 seconds
Started Aug 09 04:39:07 PM PDT 24
Finished Aug 09 05:12:41 PM PDT 24
Peak memory 280744 kb
Host smart-78c4ea7c-62c4-4f91-b471-339d52f966f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984966448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1984966448
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3783828397
Short name T569
Test name
Test status
Simulation time 24691267507 ps
CPU time 1717.53 seconds
Started Aug 09 04:39:05 PM PDT 24
Finished Aug 09 05:07:43 PM PDT 24
Peak memory 282660 kb
Host smart-da040716-1eb6-43b2-b915-8d2402e99592
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783828397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3783828397
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3869722197
Short name T12
Test name
Test status
Simulation time 143665116447 ps
CPU time 522.06 seconds
Started Aug 09 04:39:11 PM PDT 24
Finished Aug 09 04:47:53 PM PDT 24
Peak memory 247108 kb
Host smart-015f06a7-b626-4512-b034-ccd27e345447
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869722197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3869722197
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3189478889
Short name T424
Test name
Test status
Simulation time 564095961 ps
CPU time 42.26 seconds
Started Aug 09 04:39:08 PM PDT 24
Finished Aug 09 04:39:51 PM PDT 24
Peak memory 248616 kb
Host smart-e3d1d24a-8a89-4349-9471-377feaf44446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31894
78889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3189478889
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2089081420
Short name T415
Test name
Test status
Simulation time 1953735191 ps
CPU time 35.68 seconds
Started Aug 09 04:39:02 PM PDT 24
Finished Aug 09 04:39:37 PM PDT 24
Peak memory 247976 kb
Host smart-929180c4-f37f-4463-a640-13d5fc313993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20890
81420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2089081420
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.797769920
Short name T454
Test name
Test status
Simulation time 123550045 ps
CPU time 9.09 seconds
Started Aug 09 04:39:10 PM PDT 24
Finished Aug 09 04:39:19 PM PDT 24
Peak memory 248180 kb
Host smart-d8ac32b6-7bdd-4866-b98f-b09be1b887a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79776
9920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.797769920
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2997845238
Short name T61
Test name
Test status
Simulation time 147157574 ps
CPU time 10 seconds
Started Aug 09 04:39:14 PM PDT 24
Finished Aug 09 04:39:24 PM PDT 24
Peak memory 256324 kb
Host smart-14d36385-364c-4d5b-a6ee-4dac2fcc692a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29978
45238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2997845238
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2073801990
Short name T494
Test name
Test status
Simulation time 184814384148 ps
CPU time 2910.33 seconds
Started Aug 09 04:39:18 PM PDT 24
Finished Aug 09 05:27:48 PM PDT 24
Peak memory 288528 kb
Host smart-034ceb8e-8fbe-4ca7-a173-65ed8b120139
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073801990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2073801990
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1853489195
Short name T675
Test name
Test status
Simulation time 14295805991 ps
CPU time 121.33 seconds
Started Aug 09 04:39:13 PM PDT 24
Finished Aug 09 04:41:15 PM PDT 24
Peak memory 256164 kb
Host smart-cf7317d0-89b5-4532-bae5-534aa5e93201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18534
89195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1853489195
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1416328384
Short name T620
Test name
Test status
Simulation time 3227285777 ps
CPU time 47.8 seconds
Started Aug 09 04:39:04 PM PDT 24
Finished Aug 09 04:39:52 PM PDT 24
Peak memory 256372 kb
Host smart-77026758-33af-4f32-8f34-9750d1992f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14163
28384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1416328384
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3827460241
Short name T509
Test name
Test status
Simulation time 24219571804 ps
CPU time 703.17 seconds
Started Aug 09 04:39:11 PM PDT 24
Finished Aug 09 04:50:54 PM PDT 24
Peak memory 272620 kb
Host smart-47726daa-0be7-425e-8b53-ae18a81b9937
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827460241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3827460241
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3422816422
Short name T643
Test name
Test status
Simulation time 8161277929 ps
CPU time 331.35 seconds
Started Aug 09 04:39:13 PM PDT 24
Finished Aug 09 04:44:44 PM PDT 24
Peak memory 248144 kb
Host smart-c5e1c025-6a32-42c3-8a10-54ecbc0c4d98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422816422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3422816422
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2839557015
Short name T486
Test name
Test status
Simulation time 237750368 ps
CPU time 16.15 seconds
Started Aug 09 04:39:08 PM PDT 24
Finished Aug 09 04:39:25 PM PDT 24
Peak memory 254572 kb
Host smart-a7fa9cbb-439a-4ec5-aafe-3dca009602c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28395
57015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2839557015
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2154513920
Short name T581
Test name
Test status
Simulation time 450263379 ps
CPU time 40.1 seconds
Started Aug 09 04:39:08 PM PDT 24
Finished Aug 09 04:39:48 PM PDT 24
Peak memory 255512 kb
Host smart-952c5756-2c3e-48bf-a23d-efbdd1697b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21545
13920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2154513920
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2764964520
Short name T470
Test name
Test status
Simulation time 144714853 ps
CPU time 7.82 seconds
Started Aug 09 04:39:13 PM PDT 24
Finished Aug 09 04:39:21 PM PDT 24
Peak memory 247804 kb
Host smart-0e691552-0d25-4a49-8566-348295bb03ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27649
64520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2764964520
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3158555169
Short name T236
Test name
Test status
Simulation time 314162710 ps
CPU time 7.08 seconds
Started Aug 09 04:39:11 PM PDT 24
Finished Aug 09 04:39:18 PM PDT 24
Peak memory 248396 kb
Host smart-47744c06-2ecd-408f-95e6-9938f4458b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31585
55169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3158555169
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3266864095
Short name T568
Test name
Test status
Simulation time 9162745413 ps
CPU time 565.36 seconds
Started Aug 09 04:39:13 PM PDT 24
Finished Aug 09 04:48:39 PM PDT 24
Peak memory 256472 kb
Host smart-eafe8d35-9db7-4a5f-a8a1-4504853190e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266864095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3266864095
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1007772973
Short name T200
Test name
Test status
Simulation time 95596790087 ps
CPU time 4217.04 seconds
Started Aug 09 04:39:15 PM PDT 24
Finished Aug 09 05:49:32 PM PDT 24
Peak memory 329960 kb
Host smart-e3ac1a4c-4dff-4e9a-afbe-6db29b49ad42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007772973 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1007772973
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3007295053
Short name T277
Test name
Test status
Simulation time 171644190773 ps
CPU time 1251.37 seconds
Started Aug 09 04:39:13 PM PDT 24
Finished Aug 09 05:00:05 PM PDT 24
Peak memory 288788 kb
Host smart-92e372cb-3b6d-4a9a-aec1-ec6d2a766eb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007295053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3007295053
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3709076784
Short name T458
Test name
Test status
Simulation time 2868732483 ps
CPU time 175.22 seconds
Started Aug 09 04:39:14 PM PDT 24
Finished Aug 09 04:42:10 PM PDT 24
Peak memory 256392 kb
Host smart-dc9d8a20-0655-415c-a97c-0f66e20df9e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37090
76784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3709076784
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2359034653
Short name T667
Test name
Test status
Simulation time 3194308674 ps
CPU time 47.12 seconds
Started Aug 09 04:39:12 PM PDT 24
Finished Aug 09 04:39:59 PM PDT 24
Peak memory 248104 kb
Host smart-06891f9e-71f1-4789-94e7-cb60b9b53f83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23590
34653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2359034653
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.921344399
Short name T295
Test name
Test status
Simulation time 39313573280 ps
CPU time 1634.16 seconds
Started Aug 09 04:39:11 PM PDT 24
Finished Aug 09 05:06:26 PM PDT 24
Peak memory 288824 kb
Host smart-af428e7a-caae-4547-b62f-6143fa96337a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921344399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.921344399
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3169175235
Short name T436
Test name
Test status
Simulation time 5218741103 ps
CPU time 597.76 seconds
Started Aug 09 04:39:13 PM PDT 24
Finished Aug 09 04:49:10 PM PDT 24
Peak memory 272904 kb
Host smart-e7571c1c-4241-49db-ace6-86717b3e4830
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169175235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3169175235
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.935033959
Short name T312
Test name
Test status
Simulation time 67400727519 ps
CPU time 291.65 seconds
Started Aug 09 04:39:12 PM PDT 24
Finished Aug 09 04:44:03 PM PDT 24
Peak memory 248052 kb
Host smart-8bbb3777-ef1a-40b3-a61a-e2edec18e535
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935033959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.935033959
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2531668430
Short name T534
Test name
Test status
Simulation time 3990013913 ps
CPU time 42.92 seconds
Started Aug 09 04:39:14 PM PDT 24
Finished Aug 09 04:39:57 PM PDT 24
Peak memory 256396 kb
Host smart-96deda44-e6a5-4794-9f3e-ab9d1b98724e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25316
68430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2531668430
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.16915766
Short name T713
Test name
Test status
Simulation time 1481372159 ps
CPU time 30.22 seconds
Started Aug 09 04:39:15 PM PDT 24
Finished Aug 09 04:39:45 PM PDT 24
Peak memory 255968 kb
Host smart-3a654e4e-d838-4564-a5c3-c083ee4d38e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16915
766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.16915766
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1359126815
Short name T388
Test name
Test status
Simulation time 4944806688 ps
CPU time 71.74 seconds
Started Aug 09 04:39:11 PM PDT 24
Finished Aug 09 04:40:28 PM PDT 24
Peak memory 256360 kb
Host smart-0d65227b-58d5-433a-b673-35f23699034a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13591
26815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1359126815
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3997713409
Short name T576
Test name
Test status
Simulation time 55332962912 ps
CPU time 2574.72 seconds
Started Aug 09 04:39:13 PM PDT 24
Finished Aug 09 05:22:08 PM PDT 24
Peak memory 285564 kb
Host smart-ece2484a-46a6-4485-bd2d-55dcc33e47cb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997713409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3997713409
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2379750322
Short name T716
Test name
Test status
Simulation time 27744638546 ps
CPU time 3237.32 seconds
Started Aug 09 04:39:13 PM PDT 24
Finished Aug 09 05:33:11 PM PDT 24
Peak memory 304580 kb
Host smart-ec0c0e04-59c9-4c75-b363-f1784429f0a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379750322 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2379750322
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2276643130
Short name T218
Test name
Test status
Simulation time 38909192 ps
CPU time 3.82 seconds
Started Aug 09 04:38:35 PM PDT 24
Finished Aug 09 04:38:39 PM PDT 24
Peak memory 248848 kb
Host smart-75b63c7f-c3fa-4b1b-ad8f-97fb76066a00
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2276643130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2276643130
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.4112950886
Short name T60
Test name
Test status
Simulation time 18274561893 ps
CPU time 698.83 seconds
Started Aug 09 04:38:17 PM PDT 24
Finished Aug 09 04:49:56 PM PDT 24
Peak memory 265560 kb
Host smart-b90cabec-460f-4e51-a29f-3e5d33ce66f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112950886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.4112950886
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3474012071
Short name T5
Test name
Test status
Simulation time 818581027 ps
CPU time 11.96 seconds
Started Aug 09 04:38:28 PM PDT 24
Finished Aug 09 04:38:40 PM PDT 24
Peak memory 248552 kb
Host smart-6ba9cd2b-562f-483e-b8f2-1afdbce1c66e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3474012071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3474012071
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2275858529
Short name T371
Test name
Test status
Simulation time 1840546792 ps
CPU time 18.35 seconds
Started Aug 09 04:38:15 PM PDT 24
Finished Aug 09 04:38:34 PM PDT 24
Peak memory 247752 kb
Host smart-b3eba17b-8a62-4267-ad0d-ee2dd92728b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22758
58529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2275858529
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.4129435565
Short name T678
Test name
Test status
Simulation time 21546999 ps
CPU time 3.19 seconds
Started Aug 09 04:38:27 PM PDT 24
Finished Aug 09 04:38:30 PM PDT 24
Peak memory 239968 kb
Host smart-dad0df5d-ebe6-4205-bd26-54d7a18920ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41294
35565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.4129435565
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3287904518
Short name T233
Test name
Test status
Simulation time 65589387327 ps
CPU time 2022.23 seconds
Started Aug 09 04:38:32 PM PDT 24
Finished Aug 09 05:12:14 PM PDT 24
Peak memory 284168 kb
Host smart-b2a22fa4-1df8-450e-8c74-9e1903318b71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287904518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3287904518
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.726003644
Short name T689
Test name
Test status
Simulation time 12894218536 ps
CPU time 1477.25 seconds
Started Aug 09 04:38:16 PM PDT 24
Finished Aug 09 05:02:53 PM PDT 24
Peak memory 289132 kb
Host smart-1d487607-65d5-46c3-83f4-2421a4c032ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726003644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.726003644
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.26300152
Short name T70
Test name
Test status
Simulation time 39252338282 ps
CPU time 425.7 seconds
Started Aug 09 04:38:16 PM PDT 24
Finished Aug 09 04:45:21 PM PDT 24
Peak memory 248224 kb
Host smart-8ce49130-35b1-47f4-8ec8-2827e2fe17e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26300152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.26300152
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.720841592
Short name T428
Test name
Test status
Simulation time 189830030 ps
CPU time 10.3 seconds
Started Aug 09 04:38:23 PM PDT 24
Finished Aug 09 04:38:34 PM PDT 24
Peak memory 255504 kb
Host smart-c674c4d4-ccb1-4710-bd87-3f08248b4d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72084
1592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.720841592
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1516449240
Short name T586
Test name
Test status
Simulation time 1613319846 ps
CPU time 30.99 seconds
Started Aug 09 04:38:26 PM PDT 24
Finished Aug 09 04:38:57 PM PDT 24
Peak memory 247784 kb
Host smart-502f1401-3201-4103-87a4-8a65ccefb174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15164
49240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1516449240
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3296181234
Short name T31
Test name
Test status
Simulation time 898138756 ps
CPU time 11.05 seconds
Started Aug 09 04:38:27 PM PDT 24
Finished Aug 09 04:38:38 PM PDT 24
Peak memory 277552 kb
Host smart-0b44c4e4-476b-46bf-b018-0edd633b7d75
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3296181234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3296181234
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.310440367
Short name T43
Test name
Test status
Simulation time 259059803 ps
CPU time 27.47 seconds
Started Aug 09 04:38:25 PM PDT 24
Finished Aug 09 04:38:53 PM PDT 24
Peak memory 247428 kb
Host smart-fbc1291c-3165-4b6d-b31f-ded1a0e11ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31044
0367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.310440367
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.4105244347
Short name T558
Test name
Test status
Simulation time 383457033 ps
CPU time 23.04 seconds
Started Aug 09 04:38:14 PM PDT 24
Finished Aug 09 04:38:37 PM PDT 24
Peak memory 248100 kb
Host smart-a29db945-bbc7-4ed5-9931-e69249b43bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41052
44347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.4105244347
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.774524069
Short name T490
Test name
Test status
Simulation time 26389706168 ps
CPU time 1716.51 seconds
Started Aug 09 04:38:19 PM PDT 24
Finished Aug 09 05:06:56 PM PDT 24
Peak memory 281044 kb
Host smart-a4062fc5-be06-4a5b-a02e-97c0c81f457c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774524069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.774524069
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3512106225
Short name T4
Test name
Test status
Simulation time 86877815703 ps
CPU time 3454.18 seconds
Started Aug 09 04:38:30 PM PDT 24
Finished Aug 09 05:36:04 PM PDT 24
Peak memory 317308 kb
Host smart-3f746b3f-83ac-4916-9155-884089df1e9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512106225 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3512106225
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.558433161
Short name T403
Test name
Test status
Simulation time 75911511127 ps
CPU time 1294.31 seconds
Started Aug 09 04:39:11 PM PDT 24
Finished Aug 09 05:00:45 PM PDT 24
Peak memory 288196 kb
Host smart-9ba711c4-8418-4b60-9d6d-a8fa4c1d305e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558433161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.558433161
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3128624417
Short name T638
Test name
Test status
Simulation time 2128626017 ps
CPU time 48.22 seconds
Started Aug 09 04:39:13 PM PDT 24
Finished Aug 09 04:40:01 PM PDT 24
Peak memory 249260 kb
Host smart-7f299a54-b8d0-4c0c-aac6-496db9a70d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31286
24417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3128624417
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1574109279
Short name T76
Test name
Test status
Simulation time 932040401 ps
CPU time 16.2 seconds
Started Aug 09 04:39:11 PM PDT 24
Finished Aug 09 04:39:27 PM PDT 24
Peak memory 247500 kb
Host smart-1eb93dbb-bce4-4a38-a332-f33f097c2e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15741
09279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1574109279
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.257546739
Short name T321
Test name
Test status
Simulation time 16911311810 ps
CPU time 1450.62 seconds
Started Aug 09 04:39:13 PM PDT 24
Finished Aug 09 05:03:24 PM PDT 24
Peak memory 284580 kb
Host smart-19cc6ebf-9cee-4a4d-bac3-2180a71e0889
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257546739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.257546739
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3233858269
Short name T639
Test name
Test status
Simulation time 60360130425 ps
CPU time 1433.17 seconds
Started Aug 09 04:39:13 PM PDT 24
Finished Aug 09 05:03:06 PM PDT 24
Peak memory 288596 kb
Host smart-64856984-30d6-4e1a-a73e-f355f11563b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233858269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3233858269
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2252733347
Short name T478
Test name
Test status
Simulation time 512721195 ps
CPU time 17.85 seconds
Started Aug 09 04:39:15 PM PDT 24
Finished Aug 09 04:39:33 PM PDT 24
Peak memory 255428 kb
Host smart-5bc7e712-9310-4988-8e61-ae1f1036cfc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22527
33347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2252733347
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2711114918
Short name T669
Test name
Test status
Simulation time 6989252018 ps
CPU time 34.14 seconds
Started Aug 09 04:39:12 PM PDT 24
Finished Aug 09 04:39:47 PM PDT 24
Peak memory 248088 kb
Host smart-feb8ce0c-f16c-48e4-8289-787d1cf4f0f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27111
14918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2711114918
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3685500049
Short name T631
Test name
Test status
Simulation time 465281780 ps
CPU time 35.12 seconds
Started Aug 09 04:39:16 PM PDT 24
Finished Aug 09 04:39:51 PM PDT 24
Peak memory 255548 kb
Host smart-42c68414-f7a4-4d3a-b819-482baddc1c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36855
00049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3685500049
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3148763203
Short name T579
Test name
Test status
Simulation time 206809294 ps
CPU time 22.34 seconds
Started Aug 09 04:39:14 PM PDT 24
Finished Aug 09 04:39:37 PM PDT 24
Peak memory 254936 kb
Host smart-9f7887e9-e572-401c-bb8b-52ddbc8086cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31487
63203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3148763203
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.820771211
Short name T557
Test name
Test status
Simulation time 31463980054 ps
CPU time 1795.66 seconds
Started Aug 09 04:39:22 PM PDT 24
Finished Aug 09 05:09:18 PM PDT 24
Peak memory 272600 kb
Host smart-bc733bef-eec5-4a40-97be-fc3be7a81aef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820771211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.820771211
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.799425472
Short name T697
Test name
Test status
Simulation time 2035737170 ps
CPU time 57.41 seconds
Started Aug 09 04:39:23 PM PDT 24
Finished Aug 09 04:40:21 PM PDT 24
Peak memory 255860 kb
Host smart-194ecb61-d90d-4417-a6b9-9b79aa0a3cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79942
5472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.799425472
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2884967530
Short name T466
Test name
Test status
Simulation time 3877307701 ps
CPU time 66.04 seconds
Started Aug 09 04:39:26 PM PDT 24
Finished Aug 09 04:40:32 PM PDT 24
Peak memory 248372 kb
Host smart-39426a14-1a5a-4512-8787-554a5957a1f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28849
67530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2884967530
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.970743209
Short name T338
Test name
Test status
Simulation time 11626453644 ps
CPU time 940.36 seconds
Started Aug 09 04:39:23 PM PDT 24
Finished Aug 09 04:55:04 PM PDT 24
Peak memory 282372 kb
Host smart-11e3a955-de7d-44e0-b469-e20156855b53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970743209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.970743209
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2378975256
Short name T627
Test name
Test status
Simulation time 82112451746 ps
CPU time 1354.44 seconds
Started Aug 09 04:39:29 PM PDT 24
Finished Aug 09 05:02:03 PM PDT 24
Peak memory 272756 kb
Host smart-091d470d-5707-473f-a5d5-c2f2197d9361
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378975256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2378975256
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3990185115
Short name T2
Test name
Test status
Simulation time 49550878793 ps
CPU time 514.93 seconds
Started Aug 09 04:39:23 PM PDT 24
Finished Aug 09 04:47:59 PM PDT 24
Peak memory 248020 kb
Host smart-33270038-6fdc-4f9f-8c34-cbc085ea29ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990185115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3990185115
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2354415522
Short name T396
Test name
Test status
Simulation time 2959159651 ps
CPU time 58.22 seconds
Started Aug 09 04:39:23 PM PDT 24
Finished Aug 09 04:40:22 PM PDT 24
Peak memory 248188 kb
Host smart-2c40c2fc-3052-4bfa-b407-d8367b96afd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23544
15522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2354415522
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1168279295
Short name T699
Test name
Test status
Simulation time 370417751 ps
CPU time 10.19 seconds
Started Aug 09 04:39:24 PM PDT 24
Finished Aug 09 04:39:34 PM PDT 24
Peak memory 247764 kb
Host smart-5570c65d-c1d6-4c2d-a85f-dfd04c8ff0a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11682
79295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1168279295
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3750511329
Short name T677
Test name
Test status
Simulation time 1124182154 ps
CPU time 40.17 seconds
Started Aug 09 04:39:23 PM PDT 24
Finished Aug 09 04:40:03 PM PDT 24
Peak memory 255848 kb
Host smart-2c6c6b99-5516-4d2b-8dc5-064223a220e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37505
11329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3750511329
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3090047566
Short name T401
Test name
Test status
Simulation time 437478561 ps
CPU time 36.15 seconds
Started Aug 09 04:39:29 PM PDT 24
Finished Aug 09 04:40:05 PM PDT 24
Peak memory 255352 kb
Host smart-19dbbcfc-cb40-4bae-be30-0ffd9b709028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30900
47566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3090047566
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3900687529
Short name T419
Test name
Test status
Simulation time 96395734670 ps
CPU time 3918.97 seconds
Started Aug 09 04:39:25 PM PDT 24
Finished Aug 09 05:44:44 PM PDT 24
Peak memory 297444 kb
Host smart-46982b79-daba-459d-9066-8214fa9cc966
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900687529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3900687529
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1257652920
Short name T179
Test name
Test status
Simulation time 89563566603 ps
CPU time 1904.22 seconds
Started Aug 09 04:39:23 PM PDT 24
Finished Aug 09 05:11:08 PM PDT 24
Peak memory 322208 kb
Host smart-980e5c96-9a09-4fc7-a9e4-fc78ef6c7dfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257652920 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1257652920
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2572649708
Short name T694
Test name
Test status
Simulation time 680149661914 ps
CPU time 2817.99 seconds
Started Aug 09 04:39:24 PM PDT 24
Finished Aug 09 05:26:22 PM PDT 24
Peak memory 288596 kb
Host smart-abcbe834-e175-4154-ad47-560b323e684a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572649708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2572649708
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.346099996
Short name T425
Test name
Test status
Simulation time 22483987195 ps
CPU time 309.45 seconds
Started Aug 09 04:39:22 PM PDT 24
Finished Aug 09 04:44:31 PM PDT 24
Peak memory 256472 kb
Host smart-954e32e1-3960-4d35-86d5-1ec4a6aa6cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34609
9996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.346099996
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2340783126
Short name T709
Test name
Test status
Simulation time 1137939619 ps
CPU time 64.03 seconds
Started Aug 09 04:39:23 PM PDT 24
Finished Aug 09 04:40:28 PM PDT 24
Peak memory 255256 kb
Host smart-fb699b9d-8f61-45ac-89db-35d7e0736fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23407
83126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2340783126
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3331255858
Short name T37
Test name
Test status
Simulation time 42391651270 ps
CPU time 971.79 seconds
Started Aug 09 04:39:23 PM PDT 24
Finished Aug 09 04:55:35 PM PDT 24
Peak memory 289076 kb
Host smart-3159de0b-d6fa-4068-8844-348a7a5f0072
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331255858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3331255858
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2607988536
Short name T582
Test name
Test status
Simulation time 877129015591 ps
CPU time 2452.94 seconds
Started Aug 09 04:39:23 PM PDT 24
Finished Aug 09 05:20:17 PM PDT 24
Peak memory 280916 kb
Host smart-506029e8-c6c9-497a-b626-431f584fe974
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607988536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2607988536
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.475679072
Short name T685
Test name
Test status
Simulation time 7564549754 ps
CPU time 335 seconds
Started Aug 09 04:39:23 PM PDT 24
Finished Aug 09 04:44:58 PM PDT 24
Peak memory 247924 kb
Host smart-6d1817f0-595e-408e-9d3a-0108778c9a40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475679072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.475679072
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1217691156
Short name T109
Test name
Test status
Simulation time 5761476628 ps
CPU time 54.75 seconds
Started Aug 09 04:39:29 PM PDT 24
Finished Aug 09 04:40:24 PM PDT 24
Peak memory 248216 kb
Host smart-a52b13ca-a86e-466b-8b03-bd483007d115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12176
91156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1217691156
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.772708974
Short name T361
Test name
Test status
Simulation time 1451035785 ps
CPU time 24 seconds
Started Aug 09 04:39:23 PM PDT 24
Finished Aug 09 04:39:47 PM PDT 24
Peak memory 247644 kb
Host smart-9bc79f02-6d0d-4932-a985-cc2242838095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77270
8974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.772708974
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2676735423
Short name T369
Test name
Test status
Simulation time 772792239 ps
CPU time 14.93 seconds
Started Aug 09 04:39:28 PM PDT 24
Finished Aug 09 04:39:44 PM PDT 24
Peak memory 252332 kb
Host smart-8e247a77-de8d-4908-88bd-5ccc8df04a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26767
35423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2676735423
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.4174832962
Short name T444
Test name
Test status
Simulation time 812279386 ps
CPU time 52.89 seconds
Started Aug 09 04:39:25 PM PDT 24
Finished Aug 09 04:40:17 PM PDT 24
Peak memory 248232 kb
Host smart-83fc5fd0-d9cd-4a88-9b7a-bd473c0553b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41748
32962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.4174832962
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.1917223324
Short name T186
Test name
Test status
Simulation time 145491809304 ps
CPU time 3041.38 seconds
Started Aug 09 04:39:25 PM PDT 24
Finished Aug 09 05:30:06 PM PDT 24
Peak memory 322028 kb
Host smart-99a1f3fc-1d0f-4d11-af20-247a0bf80577
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917223324 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.1917223324
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2791880320
Short name T497
Test name
Test status
Simulation time 15270925653 ps
CPU time 1405.19 seconds
Started Aug 09 04:39:23 PM PDT 24
Finished Aug 09 05:02:48 PM PDT 24
Peak memory 281056 kb
Host smart-77baf9c5-c0d1-4c64-a38f-3ab95867e041
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791880320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2791880320
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2376475274
Short name T612
Test name
Test status
Simulation time 12098060339 ps
CPU time 64.93 seconds
Started Aug 09 04:39:29 PM PDT 24
Finished Aug 09 04:40:34 PM PDT 24
Peak memory 256440 kb
Host smart-722bf36c-b9d7-4391-81cb-971286976739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23764
75274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2376475274
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3281035306
Short name T263
Test name
Test status
Simulation time 731716534 ps
CPU time 40.33 seconds
Started Aug 09 04:39:24 PM PDT 24
Finished Aug 09 04:40:05 PM PDT 24
Peak memory 256368 kb
Host smart-29c1c4c5-ef3d-4ebb-996e-df148fdb0081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32810
35306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3281035306
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.193740269
Short name T335
Test name
Test status
Simulation time 11901477892 ps
CPU time 1139.62 seconds
Started Aug 09 04:39:23 PM PDT 24
Finished Aug 09 04:58:23 PM PDT 24
Peak memory 272824 kb
Host smart-479ac274-d0b9-4049-8e5a-9bbf53f0cb59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193740269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.193740269
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1478079862
Short name T376
Test name
Test status
Simulation time 35898305418 ps
CPU time 1870.02 seconds
Started Aug 09 04:39:23 PM PDT 24
Finished Aug 09 05:10:33 PM PDT 24
Peak memory 288200 kb
Host smart-c495e783-026f-404f-a099-06ffa6d58721
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478079862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1478079862
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2082196392
Short name T239
Test name
Test status
Simulation time 45553528722 ps
CPU time 454.28 seconds
Started Aug 09 04:39:23 PM PDT 24
Finished Aug 09 04:46:58 PM PDT 24
Peak memory 247128 kb
Host smart-bbc0fc0e-fe60-4647-a6c6-b3fead8fd4f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082196392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2082196392
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1816918919
Short name T377
Test name
Test status
Simulation time 148732662 ps
CPU time 8.11 seconds
Started Aug 09 04:39:29 PM PDT 24
Finished Aug 09 04:39:37 PM PDT 24
Peak memory 248564 kb
Host smart-96bb0d2e-2a8d-4ece-bf93-c97be2f6d7dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18169
18919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1816918919
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1868641396
Short name T423
Test name
Test status
Simulation time 1161461510 ps
CPU time 71.83 seconds
Started Aug 09 04:39:22 PM PDT 24
Finished Aug 09 04:40:34 PM PDT 24
Peak memory 255904 kb
Host smart-825b82a8-5b62-4c09-897d-c1fdda5e776b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18686
41396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1868641396
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1065106345
Short name T479
Test name
Test status
Simulation time 630903830 ps
CPU time 21.12 seconds
Started Aug 09 04:39:27 PM PDT 24
Finished Aug 09 04:39:49 PM PDT 24
Peak memory 247808 kb
Host smart-fc9b1221-4591-42df-ac66-76e1ae7736e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10651
06345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1065106345
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3590709208
Short name T537
Test name
Test status
Simulation time 481465458 ps
CPU time 30.69 seconds
Started Aug 09 04:39:23 PM PDT 24
Finished Aug 09 04:39:54 PM PDT 24
Peak memory 255788 kb
Host smart-bd050b63-2263-4af9-bc72-9e1c056e272b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35907
09208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3590709208
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2194548121
Short name T400
Test name
Test status
Simulation time 4914794044 ps
CPU time 292.2 seconds
Started Aug 09 04:39:37 PM PDT 24
Finished Aug 09 04:44:29 PM PDT 24
Peak memory 256448 kb
Host smart-318e32c6-bf86-4f78-b8d5-fed1b3938650
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194548121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2194548121
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.535604767
Short name T40
Test name
Test status
Simulation time 34199562881 ps
CPU time 2383.77 seconds
Started Aug 09 04:39:32 PM PDT 24
Finished Aug 09 05:19:16 PM PDT 24
Peak memory 287384 kb
Host smart-62de63b8-267c-4a4a-823b-75cfbb1ff8e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535604767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.535604767
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3634783915
Short name T706
Test name
Test status
Simulation time 1700494734 ps
CPU time 29.06 seconds
Started Aug 09 04:39:34 PM PDT 24
Finished Aug 09 04:40:04 PM PDT 24
Peak memory 256008 kb
Host smart-4253ecf7-0237-4a0f-977f-0c31f28c82cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36347
83915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3634783915
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.866876345
Short name T459
Test name
Test status
Simulation time 610326024 ps
CPU time 45.35 seconds
Started Aug 09 04:39:31 PM PDT 24
Finished Aug 09 04:40:16 PM PDT 24
Peak memory 255272 kb
Host smart-8cef3fa1-0130-432b-8156-c758b4b5d640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86687
6345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.866876345
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.208987750
Short name T288
Test name
Test status
Simulation time 27099066736 ps
CPU time 1522.87 seconds
Started Aug 09 04:39:30 PM PDT 24
Finished Aug 09 05:04:53 PM PDT 24
Peak memory 272796 kb
Host smart-35c23110-6ddd-487d-945b-d6e0c41ecf8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208987750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.208987750
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1769918215
Short name T315
Test name
Test status
Simulation time 9996092972 ps
CPU time 413.71 seconds
Started Aug 09 04:39:34 PM PDT 24
Finished Aug 09 04:46:28 PM PDT 24
Peak memory 248332 kb
Host smart-1a16712b-e170-467b-90bf-2540438c6a72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769918215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1769918215
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1925657940
Short name T372
Test name
Test status
Simulation time 5484120673 ps
CPU time 73.02 seconds
Started Aug 09 04:39:34 PM PDT 24
Finished Aug 09 04:40:47 PM PDT 24
Peak memory 256344 kb
Host smart-6c6800ea-1690-42dc-a575-96d4d42e674b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19256
57940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1925657940
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.19760325
Short name T289
Test name
Test status
Simulation time 364062338 ps
CPU time 10.35 seconds
Started Aug 09 04:39:31 PM PDT 24
Finished Aug 09 04:39:41 PM PDT 24
Peak memory 247764 kb
Host smart-23489c9c-9207-45a2-bab2-50c5f012d257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19760
325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.19760325
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2067767162
Short name T530
Test name
Test status
Simulation time 75541836 ps
CPU time 9.93 seconds
Started Aug 09 04:39:38 PM PDT 24
Finished Aug 09 04:39:48 PM PDT 24
Peak memory 248588 kb
Host smart-9be5c66b-0669-44a3-a4bb-4f02ea0a6317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20677
67162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2067767162
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1772687649
Short name T426
Test name
Test status
Simulation time 214337272 ps
CPU time 8.98 seconds
Started Aug 09 04:39:33 PM PDT 24
Finished Aug 09 04:39:43 PM PDT 24
Peak memory 254920 kb
Host smart-393794e2-53c4-4fc7-b539-aebe24edf983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17726
87649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1772687649
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.564833932
Short name T107
Test name
Test status
Simulation time 22784744266 ps
CPU time 1897.87 seconds
Started Aug 09 04:39:38 PM PDT 24
Finished Aug 09 05:11:16 PM PDT 24
Peak memory 304764 kb
Host smart-d22f9b22-f736-4558-a044-00184d4051bc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564833932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.564833932
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2271845528
Short name T266
Test name
Test status
Simulation time 57151151636 ps
CPU time 2790.07 seconds
Started Aug 09 04:39:32 PM PDT 24
Finished Aug 09 05:26:02 PM PDT 24
Peak memory 304936 kb
Host smart-bf471c4d-b47f-4035-8136-50b328ffada3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271845528 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2271845528
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1391763635
Short name T682
Test name
Test status
Simulation time 16851162799 ps
CPU time 1604.36 seconds
Started Aug 09 04:39:34 PM PDT 24
Finished Aug 09 05:06:19 PM PDT 24
Peak memory 288808 kb
Host smart-c371fce9-d996-4402-ab1d-734240acba7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391763635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1391763635
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.892026735
Short name T540
Test name
Test status
Simulation time 2420029203 ps
CPU time 70.62 seconds
Started Aug 09 04:39:38 PM PDT 24
Finished Aug 09 04:40:48 PM PDT 24
Peak memory 256056 kb
Host smart-16188ce0-a38f-4d18-94a3-a4b7e76eee04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89202
6735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.892026735
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3472526152
Short name T29
Test name
Test status
Simulation time 1935800182 ps
CPU time 29.15 seconds
Started Aug 09 04:39:30 PM PDT 24
Finished Aug 09 04:39:59 PM PDT 24
Peak memory 248116 kb
Host smart-5377b6ea-4da2-4d2c-969d-9b93fb06e145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34725
26152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3472526152
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.930047081
Short name T331
Test name
Test status
Simulation time 53712977498 ps
CPU time 2930.85 seconds
Started Aug 09 04:39:34 PM PDT 24
Finished Aug 09 05:28:26 PM PDT 24
Peak memory 288504 kb
Host smart-0004083a-9db2-4026-939a-6e9a1482b7b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930047081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.930047081
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1527836481
Short name T475
Test name
Test status
Simulation time 45900924304 ps
CPU time 2759.84 seconds
Started Aug 09 04:39:35 PM PDT 24
Finished Aug 09 05:25:35 PM PDT 24
Peak memory 288964 kb
Host smart-5c0b793b-b584-4353-93dc-473cc4e1f439
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527836481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1527836481
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1010653815
Short name T181
Test name
Test status
Simulation time 8199295577 ps
CPU time 334.82 seconds
Started Aug 09 04:39:30 PM PDT 24
Finished Aug 09 04:45:05 PM PDT 24
Peak memory 248276 kb
Host smart-29e94afb-d74f-4b60-aa49-a11fc111b746
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010653815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1010653815
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.449536771
Short name T365
Test name
Test status
Simulation time 135353283 ps
CPU time 10.08 seconds
Started Aug 09 04:39:31 PM PDT 24
Finished Aug 09 04:39:41 PM PDT 24
Peak memory 253248 kb
Host smart-553ce53b-7a7e-4517-963c-8fa34bb6dd60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44953
6771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.449536771
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3836986652
Short name T630
Test name
Test status
Simulation time 1452596240 ps
CPU time 30.66 seconds
Started Aug 09 04:39:38 PM PDT 24
Finished Aug 09 04:40:08 PM PDT 24
Peak memory 247704 kb
Host smart-01d7ad46-d874-4fb1-99e6-4c9cd885b3f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38369
86652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3836986652
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.572468132
Short name T645
Test name
Test status
Simulation time 395493160 ps
CPU time 14.79 seconds
Started Aug 09 04:39:31 PM PDT 24
Finished Aug 09 04:39:46 PM PDT 24
Peak memory 247724 kb
Host smart-710914dc-14de-4e0b-8e17-65d1f0f94516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57246
8132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.572468132
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1250094460
Short name T392
Test name
Test status
Simulation time 1236655398 ps
CPU time 31.62 seconds
Started Aug 09 04:39:31 PM PDT 24
Finished Aug 09 04:40:02 PM PDT 24
Peak memory 255400 kb
Host smart-fcbaf215-5835-4272-a958-47924f4ba11a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12500
94460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1250094460
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3593845041
Short name T95
Test name
Test status
Simulation time 126786965901 ps
CPU time 1823 seconds
Started Aug 09 04:39:34 PM PDT 24
Finished Aug 09 05:09:58 PM PDT 24
Peak memory 269904 kb
Host smart-ab50f499-b761-4fb9-8582-7ab6003f1519
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593845041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3593845041
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.4000698428
Short name T98
Test name
Test status
Simulation time 118549405022 ps
CPU time 9214.73 seconds
Started Aug 09 04:39:30 PM PDT 24
Finished Aug 09 07:13:06 PM PDT 24
Peak memory 354440 kb
Host smart-13ae84c0-2e07-46c5-939c-3642e4b3f7aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000698428 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.4000698428
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2058442015
Short name T23
Test name
Test status
Simulation time 34155198031 ps
CPU time 700.97 seconds
Started Aug 09 04:39:37 PM PDT 24
Finished Aug 09 04:51:18 PM PDT 24
Peak memory 272788 kb
Host smart-ce03a854-0819-4058-9ea9-d7b684ad173d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058442015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2058442015
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1805624945
Short name T110
Test name
Test status
Simulation time 7593920279 ps
CPU time 144.12 seconds
Started Aug 09 04:39:39 PM PDT 24
Finished Aug 09 04:42:03 PM PDT 24
Peak memory 256556 kb
Host smart-56d4cccd-aa27-44a1-8d35-55e6ef1eca76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18056
24945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1805624945
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1512130254
Short name T442
Test name
Test status
Simulation time 3608099648 ps
CPU time 54.29 seconds
Started Aug 09 04:39:39 PM PDT 24
Finished Aug 09 04:40:34 PM PDT 24
Peak memory 247860 kb
Host smart-8af57f00-aae4-4c3b-9a3a-33e483b06d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15121
30254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1512130254
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.2487598251
Short name T690
Test name
Test status
Simulation time 30768687136 ps
CPU time 1807.45 seconds
Started Aug 09 04:39:37 PM PDT 24
Finished Aug 09 05:09:45 PM PDT 24
Peak memory 281296 kb
Host smart-8213e4fb-9a96-4aa5-80ba-5202e183c7e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487598251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2487598251
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1451274097
Short name T367
Test name
Test status
Simulation time 39866114760 ps
CPU time 2437.25 seconds
Started Aug 09 04:39:36 PM PDT 24
Finished Aug 09 05:20:14 PM PDT 24
Peak memory 288368 kb
Host smart-5a14049a-806a-4ae5-81fa-4d2e41f726b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451274097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1451274097
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2219644001
Short name T362
Test name
Test status
Simulation time 154288677 ps
CPU time 14.81 seconds
Started Aug 09 04:39:33 PM PDT 24
Finished Aug 09 04:39:48 PM PDT 24
Peak memory 248212 kb
Host smart-f8c346da-99fa-4e44-8766-cfcca6884a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22196
44001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2219644001
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2177464275
Short name T550
Test name
Test status
Simulation time 740294739 ps
CPU time 44.76 seconds
Started Aug 09 04:39:34 PM PDT 24
Finished Aug 09 04:40:19 PM PDT 24
Peak memory 256380 kb
Host smart-43905602-39ad-4e03-9d1c-8b2112d11650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21774
64275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2177464275
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.194554343
Short name T560
Test name
Test status
Simulation time 2956293335 ps
CPU time 45.03 seconds
Started Aug 09 04:39:35 PM PDT 24
Finished Aug 09 04:40:20 PM PDT 24
Peak memory 248252 kb
Host smart-b0834f02-e5e9-4ccc-a3af-c2fe7177d934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19455
4343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.194554343
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1836980769
Short name T604
Test name
Test status
Simulation time 330556434673 ps
CPU time 3722.63 seconds
Started Aug 09 04:39:37 PM PDT 24
Finished Aug 09 05:41:40 PM PDT 24
Peak memory 321988 kb
Host smart-b510e7fe-6bc3-49cb-a118-d88aa906bee7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836980769 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1836980769
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2491232779
Short name T650
Test name
Test status
Simulation time 47290225080 ps
CPU time 1888.93 seconds
Started Aug 09 04:39:38 PM PDT 24
Finished Aug 09 05:11:08 PM PDT 24
Peak memory 288408 kb
Host smart-d1a9f982-f24e-44ea-a885-774d0d31685e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491232779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2491232779
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.537458378
Short name T379
Test name
Test status
Simulation time 2673865433 ps
CPU time 152.73 seconds
Started Aug 09 04:39:39 PM PDT 24
Finished Aug 09 04:42:12 PM PDT 24
Peak memory 256456 kb
Host smart-88f8cb5a-2438-4cea-aae4-0f7ad8bb5d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53745
8378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.537458378
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2191391675
Short name T440
Test name
Test status
Simulation time 3569215848 ps
CPU time 58.38 seconds
Started Aug 09 04:39:39 PM PDT 24
Finished Aug 09 04:40:38 PM PDT 24
Peak memory 248212 kb
Host smart-83ca947f-4c0e-4f43-a0eb-29f0a951f159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21913
91675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2191391675
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3093995284
Short name T711
Test name
Test status
Simulation time 16212099377 ps
CPU time 1236.31 seconds
Started Aug 09 04:39:37 PM PDT 24
Finished Aug 09 05:00:14 PM PDT 24
Peak memory 288160 kb
Host smart-5a9ba026-88bd-42b7-b7bf-a58e754245e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093995284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3093995284
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2214898561
Short name T516
Test name
Test status
Simulation time 25634090847 ps
CPU time 1666.61 seconds
Started Aug 09 04:39:38 PM PDT 24
Finished Aug 09 05:07:25 PM PDT 24
Peak memory 272824 kb
Host smart-76903374-7300-4457-b722-c2be8008332e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214898561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2214898561
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2542740857
Short name T313
Test name
Test status
Simulation time 10076461038 ps
CPU time 116.97 seconds
Started Aug 09 04:39:38 PM PDT 24
Finished Aug 09 04:41:35 PM PDT 24
Peak memory 248148 kb
Host smart-a7126cc1-a3bf-452c-9396-25c873931647
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542740857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2542740857
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1041785645
Short name T198
Test name
Test status
Simulation time 669336319 ps
CPU time 37.31 seconds
Started Aug 09 04:39:38 PM PDT 24
Finished Aug 09 04:40:15 PM PDT 24
Peak memory 248148 kb
Host smart-a2fe2d13-0ee3-46d5-b952-a490078cc24c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10417
85645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1041785645
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1692016702
Short name T368
Test name
Test status
Simulation time 1812234631 ps
CPU time 58.73 seconds
Started Aug 09 04:39:37 PM PDT 24
Finished Aug 09 04:40:36 PM PDT 24
Peak memory 248152 kb
Host smart-84a9e3df-b23c-4708-b7e1-694664e8ebd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16920
16702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1692016702
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1106308383
Short name T52
Test name
Test status
Simulation time 286116494 ps
CPU time 7.93 seconds
Started Aug 09 04:39:38 PM PDT 24
Finished Aug 09 04:39:46 PM PDT 24
Peak memory 248264 kb
Host smart-12cd6ab6-2067-4da4-8339-f575c90626e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11063
08383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1106308383
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.432841495
Short name T462
Test name
Test status
Simulation time 4323401565 ps
CPU time 64.37 seconds
Started Aug 09 04:39:39 PM PDT 24
Finished Aug 09 04:40:43 PM PDT 24
Peak memory 256428 kb
Host smart-c9d4065b-0ab7-4a9a-8810-1f30b223e1eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43284
1495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.432841495
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1013294076
Short name T656
Test name
Test status
Simulation time 26884174123 ps
CPU time 1514.42 seconds
Started Aug 09 04:39:39 PM PDT 24
Finished Aug 09 05:04:54 PM PDT 24
Peak memory 272856 kb
Host smart-7ab3de01-1856-4d6f-8bce-3e0ced882c40
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013294076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1013294076
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.1540497216
Short name T243
Test name
Test status
Simulation time 103402944207 ps
CPU time 6128.99 seconds
Started Aug 09 04:39:39 PM PDT 24
Finished Aug 09 06:21:48 PM PDT 24
Peak memory 299988 kb
Host smart-9b29f9a6-d9fb-4c69-a2f6-bb57af61881e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540497216 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.1540497216
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3274290320
Short name T688
Test name
Test status
Simulation time 10181716103 ps
CPU time 1029.01 seconds
Started Aug 09 04:39:45 PM PDT 24
Finished Aug 09 04:56:54 PM PDT 24
Peak memory 272792 kb
Host smart-7d3e1322-79a7-4baa-bab3-55cb4538f8df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274290320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3274290320
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2033863639
Short name T563
Test name
Test status
Simulation time 4220580198 ps
CPU time 91.42 seconds
Started Aug 09 04:39:46 PM PDT 24
Finished Aug 09 04:41:18 PM PDT 24
Peak memory 255924 kb
Host smart-00579294-e5d2-4f0d-8799-40fe97ba094a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20338
63639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2033863639
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.654301433
Short name T661
Test name
Test status
Simulation time 1093360189 ps
CPU time 68.82 seconds
Started Aug 09 04:39:48 PM PDT 24
Finished Aug 09 04:40:57 PM PDT 24
Peak memory 247952 kb
Host smart-86a2d012-46e2-43aa-94a1-2680868bd59e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65430
1433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.654301433
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2894196259
Short name T64
Test name
Test status
Simulation time 15329058006 ps
CPU time 1051.46 seconds
Started Aug 09 04:39:48 PM PDT 24
Finished Aug 09 04:57:19 PM PDT 24
Peak memory 264484 kb
Host smart-d106cfad-2262-4a30-91d2-60b9f40718d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894196259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2894196259
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3780490299
Short name T532
Test name
Test status
Simulation time 22740265101 ps
CPU time 1291.25 seconds
Started Aug 09 04:39:50 PM PDT 24
Finished Aug 09 05:01:22 PM PDT 24
Peak memory 288240 kb
Host smart-21e7e513-3afd-40ab-82c5-750e274b80a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780490299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3780490299
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2823442152
Short name T606
Test name
Test status
Simulation time 25033618758 ps
CPU time 139.12 seconds
Started Aug 09 04:39:45 PM PDT 24
Finished Aug 09 04:42:04 PM PDT 24
Peak memory 248212 kb
Host smart-d948024f-666c-489c-b297-30c270f4efff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823442152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2823442152
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3999155671
Short name T432
Test name
Test status
Simulation time 1598074863 ps
CPU time 38.55 seconds
Started Aug 09 04:39:44 PM PDT 24
Finished Aug 09 04:40:23 PM PDT 24
Peak memory 248188 kb
Host smart-611257ac-04f2-4e4a-b3b2-7e228ebd0397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39991
55671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3999155671
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3188134394
Short name T553
Test name
Test status
Simulation time 673180966 ps
CPU time 34.1 seconds
Started Aug 09 04:39:45 PM PDT 24
Finished Aug 09 04:40:19 PM PDT 24
Peak memory 247616 kb
Host smart-92cbcc8d-f01b-4a0b-bea7-9471f9aed123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31881
34394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3188134394
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2922094138
Short name T556
Test name
Test status
Simulation time 8423178961 ps
CPU time 46.4 seconds
Started Aug 09 04:39:50 PM PDT 24
Finished Aug 09 04:40:37 PM PDT 24
Peak memory 255316 kb
Host smart-50760066-d50c-4fe8-a710-c49fccad58fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29220
94138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2922094138
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.410318707
Short name T408
Test name
Test status
Simulation time 576620810 ps
CPU time 29.17 seconds
Started Aug 09 04:39:45 PM PDT 24
Finished Aug 09 04:40:14 PM PDT 24
Peak memory 256320 kb
Host smart-ece05f96-6886-4e92-8f38-12184211baf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41031
8707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.410318707
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.1368127594
Short name T100
Test name
Test status
Simulation time 58348735294 ps
CPU time 1549.1 seconds
Started Aug 09 04:39:46 PM PDT 24
Finished Aug 09 05:05:36 PM PDT 24
Peak memory 288960 kb
Host smart-7345cc48-8a4e-4984-b6b4-60569414e602
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368127594 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.1368127594
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1248120922
Short name T105
Test name
Test status
Simulation time 370744305374 ps
CPU time 3152.79 seconds
Started Aug 09 04:39:45 PM PDT 24
Finished Aug 09 05:32:19 PM PDT 24
Peak memory 286188 kb
Host smart-6189cf65-9031-4e97-bac5-5059e5871ea5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248120922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1248120922
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2585229746
Short name T651
Test name
Test status
Simulation time 22872355544 ps
CPU time 199.61 seconds
Started Aug 09 04:39:47 PM PDT 24
Finished Aug 09 04:43:06 PM PDT 24
Peak memory 255996 kb
Host smart-07167be1-afcd-4c38-b688-151144875e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25852
29746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2585229746
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.2062361991
Short name T635
Test name
Test status
Simulation time 889832336 ps
CPU time 13.28 seconds
Started Aug 09 04:39:45 PM PDT 24
Finished Aug 09 04:39:58 PM PDT 24
Peak memory 252676 kb
Host smart-0d3237ec-05c8-4360-8d56-fc91d39d1236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20623
61991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2062361991
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1278265625
Short name T182
Test name
Test status
Simulation time 32673552177 ps
CPU time 2189.63 seconds
Started Aug 09 04:39:45 PM PDT 24
Finished Aug 09 05:16:15 PM PDT 24
Peak memory 281016 kb
Host smart-758fbdc8-1c0b-4382-82f2-14abed1892e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278265625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1278265625
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.4079241042
Short name T610
Test name
Test status
Simulation time 58863589751 ps
CPU time 1031.09 seconds
Started Aug 09 04:39:46 PM PDT 24
Finished Aug 09 04:56:57 PM PDT 24
Peak memory 272780 kb
Host smart-bcae5631-c596-493b-ac68-c22bd257326e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079241042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.4079241042
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1637966507
Short name T245
Test name
Test status
Simulation time 1187662607 ps
CPU time 25.65 seconds
Started Aug 09 04:39:45 PM PDT 24
Finished Aug 09 04:40:11 PM PDT 24
Peak memory 248228 kb
Host smart-83c07cfb-0fc3-4b9e-9387-4eb53df31801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16379
66507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1637966507
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1269369490
Short name T65
Test name
Test status
Simulation time 333740731 ps
CPU time 20.29 seconds
Started Aug 09 04:39:47 PM PDT 24
Finished Aug 09 04:40:07 PM PDT 24
Peak memory 247712 kb
Host smart-12a3bed6-6207-4915-9472-d22a364107e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12693
69490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1269369490
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.4012862926
Short name T572
Test name
Test status
Simulation time 904608987 ps
CPU time 59.52 seconds
Started Aug 09 04:39:47 PM PDT 24
Finished Aug 09 04:40:47 PM PDT 24
Peak memory 247616 kb
Host smart-2c5fd6bd-958d-48f3-8e76-e24b606a465e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40128
62926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.4012862926
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.296428944
Short name T370
Test name
Test status
Simulation time 486777135 ps
CPU time 32.01 seconds
Started Aug 09 04:39:47 PM PDT 24
Finished Aug 09 04:40:19 PM PDT 24
Peak memory 255296 kb
Host smart-5b999f1c-4bda-446e-bc0c-d72032153f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29642
8944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.296428944
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.988605185
Short name T671
Test name
Test status
Simulation time 87509601819 ps
CPU time 1541.65 seconds
Started Aug 09 04:39:46 PM PDT 24
Finished Aug 09 05:05:28 PM PDT 24
Peak memory 288892 kb
Host smart-88841523-6569-4e56-b2c2-b1e9158b7bf2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988605185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_han
dler_stress_all.988605185
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1064544201
Short name T664
Test name
Test status
Simulation time 78241341153 ps
CPU time 7019.09 seconds
Started Aug 09 04:39:46 PM PDT 24
Finished Aug 09 06:36:46 PM PDT 24
Peak memory 321740 kb
Host smart-ba897451-82d5-43da-ad02-2fba40622d91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064544201 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1064544201
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3342441993
Short name T220
Test name
Test status
Simulation time 49050415 ps
CPU time 4.1 seconds
Started Aug 09 04:38:25 PM PDT 24
Finished Aug 09 04:38:29 PM PDT 24
Peak memory 248404 kb
Host smart-fadc2ab5-f465-43cf-8004-3c3c251dcd7c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3342441993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3342441993
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.761911060
Short name T544
Test name
Test status
Simulation time 26008755675 ps
CPU time 702.23 seconds
Started Aug 09 04:38:29 PM PDT 24
Finished Aug 09 04:50:12 PM PDT 24
Peak memory 265564 kb
Host smart-870c0a99-542a-49f1-93f8-e4a617d09a74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761911060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.761911060
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3776712577
Short name T498
Test name
Test status
Simulation time 342286659 ps
CPU time 17.23 seconds
Started Aug 09 04:38:22 PM PDT 24
Finished Aug 09 04:38:39 PM PDT 24
Peak memory 248152 kb
Host smart-72eac979-a8cb-4ddd-b47f-154b6a9e955b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3776712577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3776712577
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1624805636
Short name T583
Test name
Test status
Simulation time 1133018126 ps
CPU time 60.58 seconds
Started Aug 09 04:38:21 PM PDT 24
Finished Aug 09 04:39:22 PM PDT 24
Peak memory 255200 kb
Host smart-5cb5350f-dd62-487b-8a48-07f3942bcbd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16248
05636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1624805636
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.261880434
Short name T293
Test name
Test status
Simulation time 47614995842 ps
CPU time 2333.85 seconds
Started Aug 09 04:38:18 PM PDT 24
Finished Aug 09 05:17:12 PM PDT 24
Peak memory 288984 kb
Host smart-8ad61e47-c375-431f-b39e-bf045798bb79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261880434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.261880434
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1577412427
Short name T279
Test name
Test status
Simulation time 58603167124 ps
CPU time 444.91 seconds
Started Aug 09 04:38:21 PM PDT 24
Finished Aug 09 04:45:46 PM PDT 24
Peak memory 256452 kb
Host smart-30aabed7-d4be-4162-b5ba-06a9f55fa176
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577412427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1577412427
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3177082046
Short name T566
Test name
Test status
Simulation time 2215717209 ps
CPU time 34.56 seconds
Started Aug 09 04:38:29 PM PDT 24
Finished Aug 09 04:39:03 PM PDT 24
Peak memory 255772 kb
Host smart-194b86b2-2d33-4a13-b311-1d3ff09aaf18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31770
82046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3177082046
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.626174569
Short name T624
Test name
Test status
Simulation time 327886361 ps
CPU time 29.24 seconds
Started Aug 09 04:38:29 PM PDT 24
Finished Aug 09 04:38:58 PM PDT 24
Peak memory 247884 kb
Host smart-d1313211-ffc6-4aad-8c22-bc9ff9b3b5bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62617
4569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.626174569
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3121270767
Short name T8
Test name
Test status
Simulation time 1446337313 ps
CPU time 64.5 seconds
Started Aug 09 04:38:26 PM PDT 24
Finished Aug 09 04:39:30 PM PDT 24
Peak memory 270920 kb
Host smart-c80c3de9-b1f2-4a37-bf59-85b70a6f4340
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3121270767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3121270767
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2138676015
Short name T39
Test name
Test status
Simulation time 2576646777 ps
CPU time 34.55 seconds
Started Aug 09 04:38:25 PM PDT 24
Finished Aug 09 04:39:00 PM PDT 24
Peak memory 247824 kb
Host smart-b69dc474-8a43-41cc-9ec3-e5d95173aada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21386
76015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2138676015
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1768967627
Short name T471
Test name
Test status
Simulation time 106816873 ps
CPU time 4.24 seconds
Started Aug 09 04:38:32 PM PDT 24
Finished Aug 09 04:38:36 PM PDT 24
Peak memory 248108 kb
Host smart-95c42e9a-926e-4bc1-a4b2-66f9c7861504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17689
67627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1768967627
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3545206529
Short name T585
Test name
Test status
Simulation time 49161812776 ps
CPU time 2732.81 seconds
Started Aug 09 04:38:26 PM PDT 24
Finished Aug 09 05:23:59 PM PDT 24
Peak memory 289116 kb
Host smart-9a5d1ddd-56d6-43f3-a4be-7d1c2de1a9dd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545206529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3545206529
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3344629982
Short name T240
Test name
Test status
Simulation time 362467507039 ps
CPU time 5279.86 seconds
Started Aug 09 04:38:38 PM PDT 24
Finished Aug 09 06:06:39 PM PDT 24
Peak memory 315168 kb
Host smart-8da1e3ef-4de6-4c1c-8eed-5377ccff858c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344629982 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3344629982
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1965197405
Short name T502
Test name
Test status
Simulation time 50309475355 ps
CPU time 1727.74 seconds
Started Aug 09 04:39:56 PM PDT 24
Finished Aug 09 05:08:44 PM PDT 24
Peak memory 272744 kb
Host smart-4737405a-61dc-48a4-9b49-0617c0042911
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965197405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1965197405
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.945708013
Short name T511
Test name
Test status
Simulation time 5271379702 ps
CPU time 157.2 seconds
Started Aug 09 04:39:45 PM PDT 24
Finished Aug 09 04:42:23 PM PDT 24
Peak memory 256060 kb
Host smart-9b196068-b84b-4e96-9877-5bb0a3d5978c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94570
8013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.945708013
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2472825733
Short name T84
Test name
Test status
Simulation time 774278935 ps
CPU time 42.71 seconds
Started Aug 09 04:39:44 PM PDT 24
Finished Aug 09 04:40:27 PM PDT 24
Peak memory 247768 kb
Host smart-aaf3ca7d-8554-4072-a529-0e0d9000f13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24728
25733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2472825733
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3790767645
Short name T287
Test name
Test status
Simulation time 45161331363 ps
CPU time 1319.29 seconds
Started Aug 09 04:39:53 PM PDT 24
Finished Aug 09 05:01:53 PM PDT 24
Peak memory 272172 kb
Host smart-75955af7-862c-4e96-8af6-87c981915abf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790767645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3790767645
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1436417125
Short name T590
Test name
Test status
Simulation time 179979353120 ps
CPU time 2143.52 seconds
Started Aug 09 04:39:55 PM PDT 24
Finished Aug 09 05:15:39 PM PDT 24
Peak memory 288872 kb
Host smart-80cb11a7-447b-461e-9079-2d261873ad54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436417125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1436417125
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2804475751
Short name T42
Test name
Test status
Simulation time 5966887553 ps
CPU time 251.35 seconds
Started Aug 09 04:39:50 PM PDT 24
Finished Aug 09 04:44:01 PM PDT 24
Peak memory 248272 kb
Host smart-e837ea90-0652-4d2e-be19-f9eef5a58ac5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804475751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2804475751
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3077435658
Short name T567
Test name
Test status
Simulation time 575301356 ps
CPU time 35.75 seconds
Started Aug 09 04:39:44 PM PDT 24
Finished Aug 09 04:40:20 PM PDT 24
Peak memory 255412 kb
Host smart-535a069a-a1d3-4c9e-841a-6402c386f298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30774
35658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3077435658
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.966498501
Short name T491
Test name
Test status
Simulation time 146663200 ps
CPU time 5.68 seconds
Started Aug 09 04:39:45 PM PDT 24
Finished Aug 09 04:39:51 PM PDT 24
Peak memory 239960 kb
Host smart-e11bd699-c16a-4f81-b06a-919da78ef1e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96649
8501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.966498501
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1706949973
Short name T45
Test name
Test status
Simulation time 74364997 ps
CPU time 9.41 seconds
Started Aug 09 04:39:53 PM PDT 24
Finished Aug 09 04:40:03 PM PDT 24
Peak memory 248288 kb
Host smart-9d80a517-7f48-4669-8002-dd08c28ced50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17069
49973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1706949973
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2410758706
Short name T447
Test name
Test status
Simulation time 1000663077 ps
CPU time 53.18 seconds
Started Aug 09 04:39:45 PM PDT 24
Finished Aug 09 04:40:38 PM PDT 24
Peak memory 255408 kb
Host smart-aa849bdd-60ae-4765-9f54-f577eb2f6ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24107
58706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2410758706
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.4013887578
Short name T300
Test name
Test status
Simulation time 50799626865 ps
CPU time 1275.9 seconds
Started Aug 09 04:39:51 PM PDT 24
Finished Aug 09 05:01:08 PM PDT 24
Peak memory 288404 kb
Host smart-23b6708e-8eba-4803-b1cc-511dbb1932be
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013887578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.4013887578
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.307259550
Short name T533
Test name
Test status
Simulation time 971775499 ps
CPU time 47.1 seconds
Started Aug 09 04:39:53 PM PDT 24
Finished Aug 09 04:40:40 PM PDT 24
Peak memory 255920 kb
Host smart-1113ac8c-fa58-4a0d-a4b2-8d80359de909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30725
9550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.307259550
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3659035827
Short name T472
Test name
Test status
Simulation time 45130983 ps
CPU time 7.11 seconds
Started Aug 09 04:39:53 PM PDT 24
Finished Aug 09 04:40:01 PM PDT 24
Peak memory 248144 kb
Host smart-ea39d774-bbfc-4cf2-af28-d384d1aa6c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36590
35827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3659035827
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2728153115
Short name T517
Test name
Test status
Simulation time 192699336422 ps
CPU time 2525.62 seconds
Started Aug 09 04:39:51 PM PDT 24
Finished Aug 09 05:21:57 PM PDT 24
Peak memory 289216 kb
Host smart-ad0e2c06-7222-4c23-847c-714d1ae4bd9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728153115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2728153115
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3996185181
Short name T708
Test name
Test status
Simulation time 29945026415 ps
CPU time 1965.37 seconds
Started Aug 09 04:39:53 PM PDT 24
Finished Aug 09 05:12:39 PM PDT 24
Peak memory 285168 kb
Host smart-9e8a93db-918c-418d-ae44-ffc5362bb01e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996185181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3996185181
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3005992117
Short name T506
Test name
Test status
Simulation time 11400703187 ps
CPU time 236.94 seconds
Started Aug 09 04:39:52 PM PDT 24
Finished Aug 09 04:43:49 PM PDT 24
Peak memory 248264 kb
Host smart-47dda180-ed0d-4ae1-bca0-f0198a395305
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005992117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3005992117
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1487785961
Short name T589
Test name
Test status
Simulation time 1545868664 ps
CPU time 53.61 seconds
Started Aug 09 04:39:52 PM PDT 24
Finished Aug 09 04:40:46 PM PDT 24
Peak memory 256120 kb
Host smart-c3210fe3-dd1d-436a-aba4-2beedda5b2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14877
85961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1487785961
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2280493900
Short name T223
Test name
Test status
Simulation time 2894363947 ps
CPU time 50.82 seconds
Started Aug 09 04:39:51 PM PDT 24
Finished Aug 09 04:40:42 PM PDT 24
Peak memory 247700 kb
Host smart-66918c9c-0fc0-4464-85b3-61fb6039674b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22804
93900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2280493900
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1236060899
Short name T518
Test name
Test status
Simulation time 200047174 ps
CPU time 11.85 seconds
Started Aug 09 04:39:52 PM PDT 24
Finished Aug 09 04:40:04 PM PDT 24
Peak memory 248148 kb
Host smart-f11e4435-0e38-4220-8011-9e6725738da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12360
60899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1236060899
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.504654053
Short name T601
Test name
Test status
Simulation time 127053702 ps
CPU time 6.96 seconds
Started Aug 09 04:39:54 PM PDT 24
Finished Aug 09 04:40:01 PM PDT 24
Peak memory 254232 kb
Host smart-66d83f95-3796-4864-97d1-3cffa63905a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50465
4053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.504654053
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2903215535
Short name T652
Test name
Test status
Simulation time 3373228196 ps
CPU time 307.92 seconds
Started Aug 09 04:39:52 PM PDT 24
Finished Aug 09 04:45:00 PM PDT 24
Peak memory 256836 kb
Host smart-4b259822-5c11-43a5-8957-4c5f4bdfd63c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903215535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2903215535
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3950069632
Short name T653
Test name
Test status
Simulation time 22880692528 ps
CPU time 1596.68 seconds
Started Aug 09 04:39:59 PM PDT 24
Finished Aug 09 05:06:36 PM PDT 24
Peak memory 272156 kb
Host smart-6357d4a3-1ebb-4020-bc88-665039cc27a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950069632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3950069632
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3414718899
Short name T599
Test name
Test status
Simulation time 180032069 ps
CPU time 13.36 seconds
Started Aug 09 04:39:51 PM PDT 24
Finished Aug 09 04:40:05 PM PDT 24
Peak memory 253484 kb
Host smart-ad218979-40d4-4ace-873a-6ef338ce05a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34147
18899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3414718899
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2067110351
Short name T93
Test name
Test status
Simulation time 2269664677 ps
CPU time 68.27 seconds
Started Aug 09 04:39:53 PM PDT 24
Finished Aug 09 04:41:02 PM PDT 24
Peak memory 248140 kb
Host smart-af2428d9-fe8d-4978-9d84-15d2a02f55aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20671
10351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2067110351
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.929059126
Short name T330
Test name
Test status
Simulation time 59948494970 ps
CPU time 1373.17 seconds
Started Aug 09 04:40:01 PM PDT 24
Finished Aug 09 05:02:54 PM PDT 24
Peak memory 288152 kb
Host smart-63f37724-80c7-46b4-98d1-ef8414ed65b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929059126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.929059126
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3274652693
Short name T562
Test name
Test status
Simulation time 228966283241 ps
CPU time 1902.84 seconds
Started Aug 09 04:40:00 PM PDT 24
Finished Aug 09 05:11:43 PM PDT 24
Peak memory 272820 kb
Host smart-9a9366a7-3bfb-4fec-86dd-79adfd0465a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274652693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3274652693
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2500667661
Short name T314
Test name
Test status
Simulation time 16022537138 ps
CPU time 292.04 seconds
Started Aug 09 04:39:58 PM PDT 24
Finished Aug 09 04:44:50 PM PDT 24
Peak memory 248308 kb
Host smart-03c7418a-f214-41a3-b4b1-c88abbdae3cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500667661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2500667661
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.532479045
Short name T648
Test name
Test status
Simulation time 116441735 ps
CPU time 11.98 seconds
Started Aug 09 04:39:53 PM PDT 24
Finished Aug 09 04:40:05 PM PDT 24
Peak memory 248208 kb
Host smart-0df9a21b-d8fc-42ca-b78d-38caa2956bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53247
9045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.532479045
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3370599692
Short name T225
Test name
Test status
Simulation time 3248099714 ps
CPU time 35.87 seconds
Started Aug 09 04:39:53 PM PDT 24
Finished Aug 09 04:40:29 PM PDT 24
Peak memory 255316 kb
Host smart-74a9fdc4-c4f0-485b-8af9-be307abe7cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33705
99692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3370599692
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3262349881
Short name T613
Test name
Test status
Simulation time 445951858 ps
CPU time 29.87 seconds
Started Aug 09 04:39:52 PM PDT 24
Finished Aug 09 04:40:22 PM PDT 24
Peak memory 255872 kb
Host smart-8ad762df-3da7-4ff3-88e7-e1c6903fb1a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32623
49881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3262349881
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1864472779
Short name T366
Test name
Test status
Simulation time 4461651848 ps
CPU time 44.97 seconds
Started Aug 09 04:39:53 PM PDT 24
Finished Aug 09 04:40:38 PM PDT 24
Peak memory 256488 kb
Host smart-85e2c14a-4ad9-43ce-8688-20c4279b4024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18644
72779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1864472779
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2561156766
Short name T417
Test name
Test status
Simulation time 3690895836 ps
CPU time 218.64 seconds
Started Aug 09 04:40:01 PM PDT 24
Finished Aug 09 04:43:40 PM PDT 24
Peak memory 256416 kb
Host smart-f3b881b9-490a-4a2d-9486-1ad72d95d9da
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561156766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2561156766
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.402468919
Short name T485
Test name
Test status
Simulation time 112681360160 ps
CPU time 1954.23 seconds
Started Aug 09 04:40:04 PM PDT 24
Finished Aug 09 05:12:38 PM PDT 24
Peak memory 289220 kb
Host smart-cac2d105-4755-4048-bf95-232a39f8ced3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402468919 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.402468919
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2792232069
Short name T14
Test name
Test status
Simulation time 15923281443 ps
CPU time 1461.24 seconds
Started Aug 09 04:40:00 PM PDT 24
Finished Aug 09 05:04:21 PM PDT 24
Peak memory 288220 kb
Host smart-34033a26-24f1-4230-97da-ec5258d3008b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792232069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2792232069
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2984106466
Short name T520
Test name
Test status
Simulation time 6207833458 ps
CPU time 208.78 seconds
Started Aug 09 04:40:00 PM PDT 24
Finished Aug 09 04:43:29 PM PDT 24
Peak memory 250500 kb
Host smart-0ce1c96f-bdbb-49d5-a64e-6d28999e2609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29841
06466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2984106466
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1427631820
Short name T500
Test name
Test status
Simulation time 1655792575 ps
CPU time 36.42 seconds
Started Aug 09 04:40:00 PM PDT 24
Finished Aug 09 04:40:37 PM PDT 24
Peak memory 248136 kb
Host smart-a815bdf1-a748-461c-92ef-51051cb1256e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14276
31820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1427631820
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.2455183995
Short name T197
Test name
Test status
Simulation time 19839396314 ps
CPU time 959.93 seconds
Started Aug 09 04:40:00 PM PDT 24
Finished Aug 09 04:56:00 PM PDT 24
Peak memory 272644 kb
Host smart-52856f1a-14a6-4563-8c38-4b0eeddff8e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455183995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2455183995
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.825288409
Short name T701
Test name
Test status
Simulation time 53745762839 ps
CPU time 1319.5 seconds
Started Aug 09 04:40:00 PM PDT 24
Finished Aug 09 05:02:00 PM PDT 24
Peak memory 286048 kb
Host smart-5148ff49-78e9-4890-afa1-71b8d61dad1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825288409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.825288409
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2151089656
Short name T588
Test name
Test status
Simulation time 1963407993 ps
CPU time 29.64 seconds
Started Aug 09 04:39:59 PM PDT 24
Finished Aug 09 04:40:29 PM PDT 24
Peak memory 248212 kb
Host smart-ed39b516-cdd1-4826-bd99-14acff21cb3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21510
89656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2151089656
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1698328533
Short name T446
Test name
Test status
Simulation time 339529798 ps
CPU time 31.53 seconds
Started Aug 09 04:40:00 PM PDT 24
Finished Aug 09 04:40:32 PM PDT 24
Peak memory 248324 kb
Host smart-d529885d-9083-499c-9093-be96f799b45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16983
28533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1698328533
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.4148291914
Short name T390
Test name
Test status
Simulation time 316915984 ps
CPU time 21.08 seconds
Started Aug 09 04:40:01 PM PDT 24
Finished Aug 09 04:40:22 PM PDT 24
Peak memory 248200 kb
Host smart-40f8d9fe-ea4e-479a-81d8-6e9250fddf0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41482
91914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.4148291914
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2080145936
Short name T691
Test name
Test status
Simulation time 783785475 ps
CPU time 27.07 seconds
Started Aug 09 04:39:59 PM PDT 24
Finished Aug 09 04:40:26 PM PDT 24
Peak memory 255360 kb
Host smart-cc3bba88-8cb7-4975-9dec-d8ffd2583a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20801
45936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2080145936
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1284222109
Short name T527
Test name
Test status
Simulation time 955676883 ps
CPU time 57.83 seconds
Started Aug 09 04:40:02 PM PDT 24
Finished Aug 09 04:41:00 PM PDT 24
Peak memory 256184 kb
Host smart-a58317c0-a2a4-4f5c-a2ba-da27f632adf4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284222109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1284222109
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.1977352711
Short name T103
Test name
Test status
Simulation time 154901492350 ps
CPU time 2594.04 seconds
Started Aug 09 04:39:59 PM PDT 24
Finished Aug 09 05:23:13 PM PDT 24
Peak memory 289356 kb
Host smart-02c60ed7-19c5-4102-bf82-67c3b01a8e8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977352711 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.1977352711
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.735862304
Short name T246
Test name
Test status
Simulation time 11399025172 ps
CPU time 250.24 seconds
Started Aug 09 04:39:58 PM PDT 24
Finished Aug 09 04:44:08 PM PDT 24
Peak memory 256448 kb
Host smart-235e37a5-9975-4e0a-b1aa-b062ac95d9f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73586
2304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.735862304
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3960843740
Short name T74
Test name
Test status
Simulation time 1102232364 ps
CPU time 63.86 seconds
Started Aug 09 04:40:00 PM PDT 24
Finished Aug 09 04:41:04 PM PDT 24
Peak memory 248216 kb
Host smart-748eb703-a799-4f91-9dc2-201cf09cf67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39608
43740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3960843740
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2679358637
Short name T285
Test name
Test status
Simulation time 6178288004 ps
CPU time 653.14 seconds
Started Aug 09 04:40:06 PM PDT 24
Finished Aug 09 04:50:59 PM PDT 24
Peak memory 270764 kb
Host smart-dbf0a81c-162a-4c56-8301-e0a7a74ebde3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679358637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2679358637
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.886983375
Short name T11
Test name
Test status
Simulation time 3864675748 ps
CPU time 145.38 seconds
Started Aug 09 04:40:07 PM PDT 24
Finished Aug 09 04:42:32 PM PDT 24
Peak memory 248232 kb
Host smart-cac9025c-3e43-41a7-bc6d-02d784cc1e3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886983375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.886983375
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1157421449
Short name T79
Test name
Test status
Simulation time 607370871 ps
CPU time 21.68 seconds
Started Aug 09 04:40:00 PM PDT 24
Finished Aug 09 04:40:22 PM PDT 24
Peak memory 248140 kb
Host smart-d49e6d78-98d9-4ae4-a930-6ec490e4b577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11574
21449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1157421449
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1732560041
Short name T693
Test name
Test status
Simulation time 4370719105 ps
CPU time 53.17 seconds
Started Aug 09 04:39:59 PM PDT 24
Finished Aug 09 04:40:52 PM PDT 24
Peak memory 248208 kb
Host smart-b2c6074a-b56c-4732-88f3-dbb7a183041b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17325
60041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1732560041
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2741482950
Short name T117
Test name
Test status
Simulation time 1070429996 ps
CPU time 24.1 seconds
Started Aug 09 04:40:01 PM PDT 24
Finished Aug 09 04:40:25 PM PDT 24
Peak memory 247592 kb
Host smart-2a2c8958-72e1-4905-ad6a-ce222996be96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27414
82950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2741482950
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2671575803
Short name T622
Test name
Test status
Simulation time 1256032489 ps
CPU time 28.84 seconds
Started Aug 09 04:39:59 PM PDT 24
Finished Aug 09 04:40:28 PM PDT 24
Peak memory 256340 kb
Host smart-7583b918-5735-494f-9ccf-18960db490ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26715
75803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2671575803
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2705342670
Short name T496
Test name
Test status
Simulation time 22700806080 ps
CPU time 341.72 seconds
Started Aug 09 04:40:06 PM PDT 24
Finished Aug 09 04:45:48 PM PDT 24
Peak memory 256476 kb
Host smart-d52709d4-78ce-41aa-a132-79af86bfaf8c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705342670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2705342670
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1708932504
Short name T94
Test name
Test status
Simulation time 19388640851 ps
CPU time 1897.43 seconds
Started Aug 09 04:40:06 PM PDT 24
Finished Aug 09 05:11:44 PM PDT 24
Peak memory 297468 kb
Host smart-0421b16d-67c8-44bc-a915-e1fa8dbd47e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708932504 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1708932504
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.34854348
Short name T405
Test name
Test status
Simulation time 102063355109 ps
CPU time 1748.52 seconds
Started Aug 09 04:40:05 PM PDT 24
Finished Aug 09 05:09:14 PM PDT 24
Peak memory 288256 kb
Host smart-c7570c3f-1d85-4488-8a4a-586a8763b127
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34854348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.34854348
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2960944180
Short name T234
Test name
Test status
Simulation time 7834682296 ps
CPU time 248.29 seconds
Started Aug 09 04:40:08 PM PDT 24
Finished Aug 09 04:44:16 PM PDT 24
Peak memory 255992 kb
Host smart-96b49603-5a79-4b08-a9ef-0320a9c5643d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29609
44180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2960944180
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1454208405
Short name T374
Test name
Test status
Simulation time 678488891 ps
CPU time 27.98 seconds
Started Aug 09 04:40:12 PM PDT 24
Finished Aug 09 04:40:40 PM PDT 24
Peak memory 248140 kb
Host smart-1d5a45f5-7214-4fbc-852c-6942f089f106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14542
08405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1454208405
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.1895563656
Short name T297
Test name
Test status
Simulation time 40670204242 ps
CPU time 2512.4 seconds
Started Aug 09 04:40:07 PM PDT 24
Finished Aug 09 05:21:59 PM PDT 24
Peak memory 288452 kb
Host smart-2b281bf7-9dc0-48d2-8ef8-d4010c1f9c13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895563656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1895563656
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.379818808
Short name T465
Test name
Test status
Simulation time 5729111895 ps
CPU time 628.37 seconds
Started Aug 09 04:40:06 PM PDT 24
Finished Aug 09 04:50:35 PM PDT 24
Peak memory 272204 kb
Host smart-d4f89b61-4ee3-46a5-b1e9-f0ec87b6a0a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379818808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.379818808
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.4096514202
Short name T654
Test name
Test status
Simulation time 1008938595 ps
CPU time 32.15 seconds
Started Aug 09 04:40:07 PM PDT 24
Finished Aug 09 04:40:39 PM PDT 24
Peak memory 255652 kb
Host smart-7a194cac-6365-4234-acbb-9831e63bf468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40965
14202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.4096514202
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.701533437
Short name T474
Test name
Test status
Simulation time 669065270 ps
CPU time 43.54 seconds
Started Aug 09 04:40:07 PM PDT 24
Finished Aug 09 04:40:51 PM PDT 24
Peak memory 248096 kb
Host smart-4cf4b916-ecc3-42a5-bed0-f47952e7707a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70153
3437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.701533437
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1342034957
Short name T574
Test name
Test status
Simulation time 1485448007 ps
CPU time 39.4 seconds
Started Aug 09 04:40:07 PM PDT 24
Finished Aug 09 04:40:47 PM PDT 24
Peak memory 255352 kb
Host smart-f83d5222-1abf-4699-a705-001c463a8201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13420
34957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1342034957
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.20475326
Short name T644
Test name
Test status
Simulation time 2621132018 ps
CPU time 169.91 seconds
Started Aug 09 04:40:08 PM PDT 24
Finished Aug 09 04:42:58 PM PDT 24
Peak memory 256464 kb
Host smart-1949f3bd-0edc-4dcd-9409-41cbc3ed0a63
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20475326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_hand
ler_stress_all.20475326
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.4129834170
Short name T47
Test name
Test status
Simulation time 15917746752 ps
CPU time 1403.99 seconds
Started Aug 09 04:40:04 PM PDT 24
Finished Aug 09 05:03:29 PM PDT 24
Peak memory 288928 kb
Host smart-beb7af8c-25ee-42cf-934d-81d4b24bd7cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129834170 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.4129834170
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3931514490
Short name T469
Test name
Test status
Simulation time 203562101509 ps
CPU time 2828.35 seconds
Started Aug 09 04:40:06 PM PDT 24
Finished Aug 09 05:27:15 PM PDT 24
Peak memory 287372 kb
Host smart-b030ac41-ca34-4aad-852b-2104f38db05c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931514490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3931514490
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1599780132
Short name T545
Test name
Test status
Simulation time 1391098754 ps
CPU time 33.57 seconds
Started Aug 09 04:40:12 PM PDT 24
Finished Aug 09 04:40:46 PM PDT 24
Peak memory 255600 kb
Host smart-33280c5a-5b0a-4f42-bba9-55331456b4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15997
80132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1599780132
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.696020319
Short name T221
Test name
Test status
Simulation time 951858381 ps
CPU time 43.57 seconds
Started Aug 09 04:40:04 PM PDT 24
Finished Aug 09 04:40:48 PM PDT 24
Peak memory 247668 kb
Host smart-86090d55-42ff-4d05-8b08-38f17972334d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69602
0319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.696020319
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.919223158
Short name T561
Test name
Test status
Simulation time 12438990182 ps
CPU time 1271.17 seconds
Started Aug 09 04:40:08 PM PDT 24
Finished Aug 09 05:01:19 PM PDT 24
Peak memory 289036 kb
Host smart-8b6cc00a-a35d-4319-9a7f-a9ae85c167b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919223158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.919223158
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.849233721
Short name T10
Test name
Test status
Simulation time 13064861334 ps
CPU time 1064.35 seconds
Started Aug 09 04:40:11 PM PDT 24
Finished Aug 09 04:57:56 PM PDT 24
Peak memory 281876 kb
Host smart-f86e3ab2-a92e-4aa5-aec8-d201a1c906d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849233721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.849233721
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3966497723
Short name T305
Test name
Test status
Simulation time 5852520556 ps
CPU time 214.18 seconds
Started Aug 09 04:40:07 PM PDT 24
Finished Aug 09 04:43:41 PM PDT 24
Peak memory 248212 kb
Host smart-140ac284-f640-40b2-9222-64062783b420
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966497723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3966497723
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1070070821
Short name T431
Test name
Test status
Simulation time 328023008 ps
CPU time 22.23 seconds
Started Aug 09 04:40:12 PM PDT 24
Finished Aug 09 04:40:35 PM PDT 24
Peak memory 248132 kb
Host smart-0b953ce7-e13f-4607-9f03-449d864e1fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10700
70821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1070070821
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.695593192
Short name T578
Test name
Test status
Simulation time 1240086950 ps
CPU time 23.31 seconds
Started Aug 09 04:40:08 PM PDT 24
Finished Aug 09 04:40:31 PM PDT 24
Peak memory 247604 kb
Host smart-6038bb0e-4b52-46df-8d71-5f0a497ece5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69559
3192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.695593192
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.203280152
Short name T565
Test name
Test status
Simulation time 151263047 ps
CPU time 19.18 seconds
Started Aug 09 04:40:06 PM PDT 24
Finished Aug 09 04:40:25 PM PDT 24
Peak memory 247724 kb
Host smart-78d5396c-8704-4004-94b0-c451149d330c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20328
0152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.203280152
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2753752192
Short name T655
Test name
Test status
Simulation time 1073674713 ps
CPU time 29.6 seconds
Started Aug 09 04:40:07 PM PDT 24
Finished Aug 09 04:40:37 PM PDT 24
Peak memory 256344 kb
Host smart-aa96043b-4dc2-4132-8705-d9bb7463c14d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27537
52192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2753752192
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3390470692
Short name T683
Test name
Test status
Simulation time 124704622534 ps
CPU time 3603.56 seconds
Started Aug 09 04:40:07 PM PDT 24
Finished Aug 09 05:40:11 PM PDT 24
Peak memory 296840 kb
Host smart-72db6a75-1658-4eda-9010-97bda3e2ff48
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390470692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3390470692
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1959517097
Short name T636
Test name
Test status
Simulation time 41969014104 ps
CPU time 2813.59 seconds
Started Aug 09 04:40:14 PM PDT 24
Finished Aug 09 05:27:08 PM PDT 24
Peak memory 288464 kb
Host smart-e12ea98a-f5f3-4f25-b0b3-09dae8b46604
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959517097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1959517097
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.284799483
Short name T460
Test name
Test status
Simulation time 10840889592 ps
CPU time 185.12 seconds
Started Aug 09 04:40:11 PM PDT 24
Finished Aug 09 04:43:16 PM PDT 24
Peak memory 256284 kb
Host smart-f898654a-ba15-4396-bb4a-1f6abe49391a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28479
9483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.284799483
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.4222544928
Short name T325
Test name
Test status
Simulation time 111014138166 ps
CPU time 1795.23 seconds
Started Aug 09 04:40:14 PM PDT 24
Finished Aug 09 05:10:10 PM PDT 24
Peak memory 272716 kb
Host smart-b1ff666e-789a-44e9-b3d9-68ba157a209c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222544928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.4222544928
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1600076658
Short name T555
Test name
Test status
Simulation time 17712207369 ps
CPU time 1018.97 seconds
Started Aug 09 04:40:11 PM PDT 24
Finished Aug 09 04:57:10 PM PDT 24
Peak memory 287140 kb
Host smart-ef36bde9-92bc-4e51-80d5-022629f37458
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600076658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1600076658
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2274917930
Short name T531
Test name
Test status
Simulation time 20082804430 ps
CPU time 243.98 seconds
Started Aug 09 04:40:11 PM PDT 24
Finished Aug 09 04:44:15 PM PDT 24
Peak memory 248228 kb
Host smart-891e8c27-c505-43e0-92d9-0aab277f7a57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274917930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2274917930
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2049074059
Short name T67
Test name
Test status
Simulation time 328276678 ps
CPU time 34.84 seconds
Started Aug 09 04:40:12 PM PDT 24
Finished Aug 09 04:40:47 PM PDT 24
Peak memory 255624 kb
Host smart-ec8de9f0-8756-4ebd-b734-ff3dc37648c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20490
74059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2049074059
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3921561476
Short name T659
Test name
Test status
Simulation time 726617962 ps
CPU time 43.93 seconds
Started Aug 09 04:40:16 PM PDT 24
Finished Aug 09 04:41:00 PM PDT 24
Peak memory 248072 kb
Host smart-28655784-f948-41b9-aa06-f741c9ae59ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39215
61476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3921561476
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.404820317
Short name T483
Test name
Test status
Simulation time 155045914 ps
CPU time 18.8 seconds
Started Aug 09 04:40:14 PM PDT 24
Finished Aug 09 04:40:33 PM PDT 24
Peak memory 256332 kb
Host smart-679e885c-7a4b-4c53-9983-ce1ae97f040c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40482
0317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.404820317
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2495721573
Short name T399
Test name
Test status
Simulation time 237310838 ps
CPU time 10.38 seconds
Started Aug 09 04:40:12 PM PDT 24
Finished Aug 09 04:40:23 PM PDT 24
Peak memory 248204 kb
Host smart-f72de7a4-5877-4514-9da1-044cbc4e5366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24957
21573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2495721573
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.4010113921
Short name T59
Test name
Test status
Simulation time 69597219686 ps
CPU time 3754.86 seconds
Started Aug 09 04:40:14 PM PDT 24
Finished Aug 09 05:42:50 PM PDT 24
Peak memory 305280 kb
Host smart-92dece26-e567-45ec-8268-7d7ad3808ffa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010113921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.4010113921
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2249251011
Short name T617
Test name
Test status
Simulation time 30131986736 ps
CPU time 1532.27 seconds
Started Aug 09 04:40:11 PM PDT 24
Finished Aug 09 05:05:44 PM PDT 24
Peak memory 289316 kb
Host smart-e5472ca7-43ce-4682-9198-9ce0fdde60f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249251011 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2249251011
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.979847437
Short name T487
Test name
Test status
Simulation time 10718228255 ps
CPU time 426.8 seconds
Started Aug 09 04:41:50 PM PDT 24
Finished Aug 09 04:48:57 PM PDT 24
Peak memory 271928 kb
Host smart-3b108cac-14cc-4048-9f87-a786b766cd5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979847437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.979847437
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1957695581
Short name T373
Test name
Test status
Simulation time 2782441146 ps
CPU time 122.1 seconds
Started Aug 09 04:40:11 PM PDT 24
Finished Aug 09 04:42:13 PM PDT 24
Peak memory 250432 kb
Host smart-bdc05c27-2290-4122-8246-a5a01ac14306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19576
95581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1957695581
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2825660573
Short name T116
Test name
Test status
Simulation time 731341162 ps
CPU time 41.39 seconds
Started Aug 09 04:40:10 PM PDT 24
Finished Aug 09 04:40:51 PM PDT 24
Peak memory 248128 kb
Host smart-ebfade8d-0cec-4701-85a3-144f0aca1147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28256
60573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2825660573
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1987607187
Short name T559
Test name
Test status
Simulation time 37038463601 ps
CPU time 922.26 seconds
Started Aug 09 04:40:13 PM PDT 24
Finished Aug 09 04:55:35 PM PDT 24
Peak memory 272704 kb
Host smart-12ccf266-c492-44d1-8b47-756128094cc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987607187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1987607187
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1282192262
Short name T549
Test name
Test status
Simulation time 29153792750 ps
CPU time 794.08 seconds
Started Aug 09 04:40:17 PM PDT 24
Finished Aug 09 04:53:32 PM PDT 24
Peak memory 272052 kb
Host smart-381b5981-3684-4988-b22b-eeb1e6c79c68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282192262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1282192262
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3747630153
Short name T700
Test name
Test status
Simulation time 7718162566 ps
CPU time 318.32 seconds
Started Aug 09 04:40:11 PM PDT 24
Finished Aug 09 04:45:29 PM PDT 24
Peak memory 247180 kb
Host smart-fa7b99af-bdff-4862-82f8-28b7831836fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747630153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3747630153
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.926070147
Short name T391
Test name
Test status
Simulation time 912359965 ps
CPU time 16 seconds
Started Aug 09 04:40:16 PM PDT 24
Finished Aug 09 04:40:32 PM PDT 24
Peak memory 252764 kb
Host smart-627b481b-a0eb-41ae-9ddf-24282d2687f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92607
0147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.926070147
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3004773555
Short name T58
Test name
Test status
Simulation time 3968426837 ps
CPU time 66.19 seconds
Started Aug 09 04:40:13 PM PDT 24
Finished Aug 09 04:41:20 PM PDT 24
Peak memory 247968 kb
Host smart-c69cc117-792f-4887-b762-e23a6d4d8b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30047
73555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3004773555
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.351620211
Short name T522
Test name
Test status
Simulation time 7309568993 ps
CPU time 29.17 seconds
Started Aug 09 04:40:13 PM PDT 24
Finished Aug 09 04:40:43 PM PDT 24
Peak memory 255504 kb
Host smart-2666a5a5-f35b-4fb5-905c-136ccf653d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35162
0211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.351620211
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1652580131
Short name T605
Test name
Test status
Simulation time 1523479452 ps
CPU time 43.53 seconds
Started Aug 09 04:41:52 PM PDT 24
Finished Aug 09 04:42:35 PM PDT 24
Peak memory 256236 kb
Host smart-4a4717d4-c6cb-40c4-aa91-75ec567634fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16525
80131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1652580131
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2202083576
Short name T249
Test name
Test status
Simulation time 165026575569 ps
CPU time 2827.54 seconds
Started Aug 09 04:40:21 PM PDT 24
Finished Aug 09 05:27:28 PM PDT 24
Peak memory 284576 kb
Host smart-17c9f105-5821-4417-83bc-eb9b6b5b7f62
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202083576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2202083576
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.4159145699
Short name T528
Test name
Test status
Simulation time 34568934726 ps
CPU time 1776.96 seconds
Started Aug 09 04:40:19 PM PDT 24
Finished Aug 09 05:09:57 PM PDT 24
Peak memory 281868 kb
Host smart-2f3b11ef-4e11-4c24-978d-2b60f98bd41a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159145699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.4159145699
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.626025477
Short name T416
Test name
Test status
Simulation time 889570770 ps
CPU time 81.08 seconds
Started Aug 09 04:40:19 PM PDT 24
Finished Aug 09 04:41:40 PM PDT 24
Peak memory 255836 kb
Host smart-982c65e0-43ba-428b-8220-30024d9df9f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62602
5477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.626025477
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2666713282
Short name T657
Test name
Test status
Simulation time 192927066 ps
CPU time 19.62 seconds
Started Aug 09 04:40:25 PM PDT 24
Finished Aug 09 04:40:45 PM PDT 24
Peak memory 248144 kb
Host smart-7a8fee2a-53ac-4488-b372-f1b5528afdf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26667
13282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2666713282
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.263843028
Short name T326
Test name
Test status
Simulation time 32503429492 ps
CPU time 2064.71 seconds
Started Aug 09 04:40:21 PM PDT 24
Finished Aug 09 05:14:46 PM PDT 24
Peak memory 284516 kb
Host smart-f78b022d-90ab-4ca0-a232-20c8fce2f5d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263843028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.263843028
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3715159951
Short name T455
Test name
Test status
Simulation time 561499329460 ps
CPU time 2132.57 seconds
Started Aug 09 04:40:22 PM PDT 24
Finished Aug 09 05:15:55 PM PDT 24
Peak memory 288160 kb
Host smart-cdb89570-2a18-4f0c-86f1-c2d0c5e4fc9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715159951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3715159951
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.4184137599
Short name T310
Test name
Test status
Simulation time 36690633469 ps
CPU time 363.33 seconds
Started Aug 09 04:40:20 PM PDT 24
Finished Aug 09 04:46:24 PM PDT 24
Peak memory 255152 kb
Host smart-2ccd4526-12ce-4c9c-8fcc-8629864a2327
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184137599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.4184137599
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2823359214
Short name T525
Test name
Test status
Simulation time 1136474614 ps
CPU time 73.76 seconds
Started Aug 09 04:40:20 PM PDT 24
Finished Aug 09 04:41:34 PM PDT 24
Peak memory 248212 kb
Host smart-b2c3ff15-8ac5-4065-aa64-e19c254bb2f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28233
59214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2823359214
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2604628685
Short name T386
Test name
Test status
Simulation time 141900867 ps
CPU time 5.27 seconds
Started Aug 09 04:40:20 PM PDT 24
Finished Aug 09 04:40:25 PM PDT 24
Peak memory 247788 kb
Host smart-650ffb4c-1d08-452f-85dc-c1748297af07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26046
28685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2604628685
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1208164234
Short name T120
Test name
Test status
Simulation time 517612079 ps
CPU time 36.02 seconds
Started Aug 09 04:40:21 PM PDT 24
Finished Aug 09 04:40:57 PM PDT 24
Peak memory 248336 kb
Host smart-8bda1b16-6fe9-40d2-a146-e89eb6076be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12081
64234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1208164234
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.262206512
Short name T364
Test name
Test status
Simulation time 161083756 ps
CPU time 9.31 seconds
Started Aug 09 04:40:25 PM PDT 24
Finished Aug 09 04:40:34 PM PDT 24
Peak memory 254268 kb
Host smart-6683883c-f7da-4dfd-9cf3-c76c409e4f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26220
6512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.262206512
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.286329674
Short name T90
Test name
Test status
Simulation time 94281365686 ps
CPU time 1566.98 seconds
Started Aug 09 04:40:21 PM PDT 24
Finished Aug 09 05:06:28 PM PDT 24
Peak memory 286988 kb
Host smart-ad680cef-9fd9-4b1e-8fc2-858410602f82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286329674 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.286329674
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.732832285
Short name T203
Test name
Test status
Simulation time 13757045 ps
CPU time 2.3 seconds
Started Aug 09 04:38:32 PM PDT 24
Finished Aug 09 04:38:34 PM PDT 24
Peak memory 248420 kb
Host smart-8777e4da-19da-4fd1-8979-d391c0719e1f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=732832285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.732832285
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1826632905
Short name T291
Test name
Test status
Simulation time 44193206091 ps
CPU time 1261.78 seconds
Started Aug 09 04:38:26 PM PDT 24
Finished Aug 09 04:59:28 PM PDT 24
Peak memory 288884 kb
Host smart-204bbf9f-bd16-419b-ada4-372c57aa1a8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826632905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1826632905
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.4089236100
Short name T513
Test name
Test status
Simulation time 630718515 ps
CPU time 28.92 seconds
Started Aug 09 04:38:39 PM PDT 24
Finished Aug 09 04:39:08 PM PDT 24
Peak memory 248132 kb
Host smart-ea7936b7-b44d-4f16-98b3-711884ae8cec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4089236100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.4089236100
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.61309085
Short name T514
Test name
Test status
Simulation time 3076628677 ps
CPU time 121.97 seconds
Started Aug 09 04:38:16 PM PDT 24
Finished Aug 09 04:40:18 PM PDT 24
Peak memory 256008 kb
Host smart-19509c8e-7f41-44a1-b935-0f6d7e6d3952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61309
085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.61309085
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2139240036
Short name T680
Test name
Test status
Simulation time 151125295 ps
CPU time 15.78 seconds
Started Aug 09 04:38:26 PM PDT 24
Finished Aug 09 04:38:42 PM PDT 24
Peak memory 248104 kb
Host smart-e4dea3d6-5a30-4b65-8828-a699270966b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21392
40036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2139240036
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3559290676
Short name T665
Test name
Test status
Simulation time 17791537316 ps
CPU time 733.37 seconds
Started Aug 09 04:38:24 PM PDT 24
Finished Aug 09 04:50:37 PM PDT 24
Peak memory 272636 kb
Host smart-c0bdee34-ba59-4702-9503-7515afda1899
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559290676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3559290676
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.727280984
Short name T523
Test name
Test status
Simulation time 18401347269 ps
CPU time 872.22 seconds
Started Aug 09 04:38:24 PM PDT 24
Finished Aug 09 04:52:57 PM PDT 24
Peak memory 270760 kb
Host smart-161f9aaa-d09b-409a-a568-ca3bdcfa3864
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727280984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.727280984
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.479828402
Short name T529
Test name
Test status
Simulation time 15060673291 ps
CPU time 321.9 seconds
Started Aug 09 04:38:23 PM PDT 24
Finished Aug 09 04:43:45 PM PDT 24
Peak memory 248048 kb
Host smart-1023198a-4261-4a28-b5fa-08446ab0a59b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479828402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.479828402
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1716679537
Short name T480
Test name
Test status
Simulation time 1354486987 ps
CPU time 31.18 seconds
Started Aug 09 04:38:26 PM PDT 24
Finished Aug 09 04:38:57 PM PDT 24
Peak memory 248120 kb
Host smart-7d21fa27-7582-45cd-a246-4037a332d253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17166
79537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1716679537
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3472576963
Short name T185
Test name
Test status
Simulation time 1535335315 ps
CPU time 11.51 seconds
Started Aug 09 04:38:25 PM PDT 24
Finished Aug 09 04:38:37 PM PDT 24
Peak memory 253148 kb
Host smart-b1c257ab-d28e-4058-aa25-a5199e58ff01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34725
76963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3472576963
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1022290102
Short name T106
Test name
Test status
Simulation time 679723569 ps
CPU time 43.15 seconds
Started Aug 09 04:38:27 PM PDT 24
Finished Aug 09 04:39:10 PM PDT 24
Peak memory 247824 kb
Host smart-63a1be01-1795-4bbc-95d8-f9735d7f865a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10222
90102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1022290102
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1771629454
Short name T402
Test name
Test status
Simulation time 16468831458 ps
CPU time 75.7 seconds
Started Aug 09 04:38:29 PM PDT 24
Finished Aug 09 04:39:44 PM PDT 24
Peak memory 255892 kb
Host smart-841b6f86-2001-4cac-ab63-c16c5b50af08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17716
29454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1771629454
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3035871026
Short name T299
Test name
Test status
Simulation time 76336447601 ps
CPU time 1027.9 seconds
Started Aug 09 04:38:35 PM PDT 24
Finished Aug 09 04:55:43 PM PDT 24
Peak memory 288592 kb
Host smart-bf61e783-87b4-45be-a2c4-b1c99b175e0f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035871026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3035871026
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2201301224
Short name T271
Test name
Test status
Simulation time 79894505944 ps
CPU time 6770.77 seconds
Started Aug 09 04:38:36 PM PDT 24
Finished Aug 09 06:31:28 PM PDT 24
Peak memory 337088 kb
Host smart-3f326a80-e347-4d38-9c25-2b35a0e20eed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201301224 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2201301224
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3003136398
Short name T111
Test name
Test status
Simulation time 31681116 ps
CPU time 3.08 seconds
Started Aug 09 04:38:39 PM PDT 24
Finished Aug 09 04:38:42 PM PDT 24
Peak memory 248872 kb
Host smart-473c4a54-1141-4e61-b83d-6ed943b57418
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3003136398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3003136398
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.410525912
Short name T118
Test name
Test status
Simulation time 7135770728 ps
CPU time 726.6 seconds
Started Aug 09 04:38:43 PM PDT 24
Finished Aug 09 04:50:49 PM PDT 24
Peak memory 272148 kb
Host smart-5322326f-db94-4278-aaa0-506525576088
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410525912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.410525912
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2034803642
Short name T180
Test name
Test status
Simulation time 1200431768 ps
CPU time 51.93 seconds
Started Aug 09 04:38:23 PM PDT 24
Finished Aug 09 04:39:15 PM PDT 24
Peak memory 248552 kb
Host smart-98e740dd-1b99-4837-b9db-4152cd30dff2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2034803642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2034803642
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2342777307
Short name T437
Test name
Test status
Simulation time 1894756798 ps
CPU time 111.4 seconds
Started Aug 09 04:38:32 PM PDT 24
Finished Aug 09 04:40:23 PM PDT 24
Peak memory 255792 kb
Host smart-a4291ed0-8564-40b8-a6e0-17b363440891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23427
77307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2342777307
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2919831736
Short name T409
Test name
Test status
Simulation time 75779481 ps
CPU time 2.83 seconds
Started Aug 09 04:38:32 PM PDT 24
Finished Aug 09 04:38:36 PM PDT 24
Peak memory 240012 kb
Host smart-49fd8ff3-97dd-4e2b-8a87-bee81b2ce3dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29198
31736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2919831736
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3238365647
Short name T327
Test name
Test status
Simulation time 26826911705 ps
CPU time 1127.29 seconds
Started Aug 09 04:38:32 PM PDT 24
Finished Aug 09 04:57:19 PM PDT 24
Peak memory 281048 kb
Host smart-96ce6d10-e516-458f-acac-debe2bdf3e4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238365647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3238365647
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1619195851
Short name T684
Test name
Test status
Simulation time 29232926240 ps
CPU time 1645.07 seconds
Started Aug 09 04:38:29 PM PDT 24
Finished Aug 09 05:05:55 PM PDT 24
Peak memory 272816 kb
Host smart-7839e206-08c5-4e32-8c04-3f155f88e4fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619195851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1619195851
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2662380134
Short name T660
Test name
Test status
Simulation time 26943498537 ps
CPU time 319.68 seconds
Started Aug 09 04:38:31 PM PDT 24
Finished Aug 09 04:43:50 PM PDT 24
Peak memory 248272 kb
Host smart-740f8fa8-bc55-43f6-a40c-3c91da6077ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662380134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2662380134
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.741196450
Short name T183
Test name
Test status
Simulation time 1288364498 ps
CPU time 64.99 seconds
Started Aug 09 04:38:35 PM PDT 24
Finished Aug 09 04:39:40 PM PDT 24
Peak memory 255392 kb
Host smart-d0d277c0-9278-466c-a15a-3ac2748a19db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74119
6450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.741196450
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2639911795
Short name T521
Test name
Test status
Simulation time 332053585 ps
CPU time 11.54 seconds
Started Aug 09 04:38:26 PM PDT 24
Finished Aug 09 04:38:38 PM PDT 24
Peak memory 247720 kb
Host smart-e5682b50-afa4-4aae-9b51-0a4e1064bc45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26399
11795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2639911795
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2120295231
Short name T662
Test name
Test status
Simulation time 249432519 ps
CPU time 32.14 seconds
Started Aug 09 04:38:32 PM PDT 24
Finished Aug 09 04:39:04 PM PDT 24
Peak memory 248124 kb
Host smart-14c56f17-2abb-4b5d-95ce-456a08ebf7ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21202
95231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2120295231
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1378269062
Short name T666
Test name
Test status
Simulation time 407532799 ps
CPU time 14.09 seconds
Started Aug 09 04:38:51 PM PDT 24
Finished Aug 09 04:39:05 PM PDT 24
Peak memory 254940 kb
Host smart-3d0a4b4f-e591-47b0-a38a-fdf9fd428801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13782
69062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1378269062
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2848387520
Short name T687
Test name
Test status
Simulation time 33511825 ps
CPU time 4.51 seconds
Started Aug 09 04:38:40 PM PDT 24
Finished Aug 09 04:38:45 PM PDT 24
Peak memory 252152 kb
Host smart-e9f89a88-e04e-4c1e-a71e-dbe1ea528d66
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848387520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2848387520
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.1326199244
Short name T264
Test name
Test status
Simulation time 94778969310 ps
CPU time 4622.2 seconds
Started Aug 09 04:38:31 PM PDT 24
Finished Aug 09 05:55:34 PM PDT 24
Peak memory 330192 kb
Host smart-311f9371-3152-4881-ad2d-961a27f95a87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326199244 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.1326199244
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2960614763
Short name T205
Test name
Test status
Simulation time 41015430 ps
CPU time 3.98 seconds
Started Aug 09 04:38:45 PM PDT 24
Finished Aug 09 04:38:49 PM PDT 24
Peak memory 248428 kb
Host smart-235b5487-1754-45aa-bb22-3c7791e76d63
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2960614763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2960614763
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1507618169
Short name T301
Test name
Test status
Simulation time 139385125890 ps
CPU time 2412.25 seconds
Started Aug 09 04:38:44 PM PDT 24
Finished Aug 09 05:18:56 PM PDT 24
Peak memory 289280 kb
Host smart-bf51d59a-0dd9-45b6-98e3-2e080987aff7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507618169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1507618169
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1684527349
Short name T433
Test name
Test status
Simulation time 2159431757 ps
CPU time 24.98 seconds
Started Aug 09 04:38:50 PM PDT 24
Finished Aug 09 04:39:15 PM PDT 24
Peak memory 248216 kb
Host smart-decf9f74-e316-4fc3-9156-897afa520334
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1684527349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1684527349
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1670481439
Short name T719
Test name
Test status
Simulation time 4908767342 ps
CPU time 298.87 seconds
Started Aug 09 04:38:36 PM PDT 24
Finished Aug 09 04:43:35 PM PDT 24
Peak memory 251300 kb
Host smart-3e753b13-f27b-46bf-9663-aee3f28d90e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16704
81439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1670481439
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2209157058
Short name T698
Test name
Test status
Simulation time 2076080538 ps
CPU time 54.18 seconds
Started Aug 09 04:38:35 PM PDT 24
Finished Aug 09 04:39:30 PM PDT 24
Peak memory 248192 kb
Host smart-d40e0156-50b8-454b-975e-4e7560619145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22091
57058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2209157058
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.971460473
Short name T337
Test name
Test status
Simulation time 21883877951 ps
CPU time 1138.36 seconds
Started Aug 09 04:38:49 PM PDT 24
Finished Aug 09 04:57:47 PM PDT 24
Peak memory 281104 kb
Host smart-69135f15-3967-4f9d-bb62-aea912f1427e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971460473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.971460473
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.649161766
Short name T468
Test name
Test status
Simulation time 113756336154 ps
CPU time 2061.94 seconds
Started Aug 09 04:38:53 PM PDT 24
Finished Aug 09 05:13:15 PM PDT 24
Peak memory 280332 kb
Host smart-96b821fc-d556-4e87-80b4-b94e8af558eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649161766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.649161766
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.4035475277
Short name T97
Test name
Test status
Simulation time 12479443993 ps
CPU time 478.64 seconds
Started Aug 09 04:38:46 PM PDT 24
Finished Aug 09 04:46:44 PM PDT 24
Peak memory 248208 kb
Host smart-f80af22f-d2b1-4cff-9296-9ea9d63b5baf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035475277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.4035475277
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3993681805
Short name T19
Test name
Test status
Simulation time 501139580 ps
CPU time 8.73 seconds
Started Aug 09 04:38:25 PM PDT 24
Finished Aug 09 04:38:34 PM PDT 24
Peak memory 248080 kb
Host smart-292484a0-b0af-437e-bc8e-c1eac2438f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39936
81805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3993681805
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.4222820914
Short name T88
Test name
Test status
Simulation time 1906096882 ps
CPU time 25.1 seconds
Started Aug 09 04:38:34 PM PDT 24
Finished Aug 09 04:38:59 PM PDT 24
Peak memory 254188 kb
Host smart-09bcff6f-ccb8-4831-a524-7771080c02cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42228
20914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.4222820914
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3688155044
Short name T718
Test name
Test status
Simulation time 126604420 ps
CPU time 15.38 seconds
Started Aug 09 04:38:43 PM PDT 24
Finished Aug 09 04:38:59 PM PDT 24
Peak memory 248164 kb
Host smart-4657faf8-1aa1-47fa-ad8e-a027256fc282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36881
55044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3688155044
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3641294082
Short name T512
Test name
Test status
Simulation time 1358392827 ps
CPU time 42.4 seconds
Started Aug 09 04:38:35 PM PDT 24
Finished Aug 09 04:39:18 PM PDT 24
Peak memory 255396 kb
Host smart-4c667a3f-2044-41b3-8456-8ac5780cbce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36412
94082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3641294082
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.193690060
Short name T467
Test name
Test status
Simulation time 45030439758 ps
CPU time 2931.77 seconds
Started Aug 09 04:38:44 PM PDT 24
Finished Aug 09 05:27:36 PM PDT 24
Peak memory 304592 kb
Host smart-a48dd49d-11c7-4181-a9d0-4d90d918f86c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193690060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.193690060
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3295403245
Short name T215
Test name
Test status
Simulation time 15753856 ps
CPU time 2.69 seconds
Started Aug 09 04:38:47 PM PDT 24
Finished Aug 09 04:38:50 PM PDT 24
Peak memory 248584 kb
Host smart-6dbcc286-f0ef-4fd1-a3ee-c57615db6670
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3295403245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3295403245
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2957262008
Short name T13
Test name
Test status
Simulation time 62625388434 ps
CPU time 2075.72 seconds
Started Aug 09 04:38:46 PM PDT 24
Finished Aug 09 05:13:22 PM PDT 24
Peak memory 288868 kb
Host smart-d2b31cbb-6345-4281-aac6-78069c6c298c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957262008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2957262008
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3756519551
Short name T543
Test name
Test status
Simulation time 1735301520 ps
CPU time 10.1 seconds
Started Aug 09 04:38:43 PM PDT 24
Finished Aug 09 04:38:53 PM PDT 24
Peak memory 248160 kb
Host smart-ad75c9dd-97ba-44c2-a23c-d4b459ae509b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3756519551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3756519551
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1766758519
Short name T456
Test name
Test status
Simulation time 1938680052 ps
CPU time 28.28 seconds
Started Aug 09 04:38:49 PM PDT 24
Finished Aug 09 04:39:18 PM PDT 24
Peak memory 255448 kb
Host smart-95b6079a-35fa-45c4-91a6-1bdac7e1b7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17667
58519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1766758519
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3693289703
Short name T542
Test name
Test status
Simulation time 369696838 ps
CPU time 13.73 seconds
Started Aug 09 04:38:41 PM PDT 24
Finished Aug 09 04:38:55 PM PDT 24
Peak memory 256364 kb
Host smart-43ab191c-b2d1-4ad5-8d1f-4923a296de3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36932
89703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3693289703
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1359403642
Short name T375
Test name
Test status
Simulation time 88593171403 ps
CPU time 2713.63 seconds
Started Aug 09 04:38:37 PM PDT 24
Finished Aug 09 05:23:51 PM PDT 24
Peak memory 286048 kb
Host smart-7424a29a-4861-4f56-bf1a-2d136dd31137
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359403642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1359403642
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1308422092
Short name T704
Test name
Test status
Simulation time 1548550875 ps
CPU time 49.97 seconds
Started Aug 09 04:38:47 PM PDT 24
Finished Aug 09 04:39:37 PM PDT 24
Peak memory 255748 kb
Host smart-5efa97a3-d66d-47e1-a4a0-58ab07b2c67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13084
22092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1308422092
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.317047581
Short name T495
Test name
Test status
Simulation time 724042935 ps
CPU time 22.25 seconds
Started Aug 09 04:38:50 PM PDT 24
Finished Aug 09 04:39:12 PM PDT 24
Peak memory 248192 kb
Host smart-fb5ce459-f7de-4310-8eaa-f5ba217cad69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31704
7581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.317047581
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1037029505
Short name T256
Test name
Test status
Simulation time 1774191005 ps
CPU time 31.67 seconds
Started Aug 09 04:38:44 PM PDT 24
Finished Aug 09 04:39:16 PM PDT 24
Peak memory 255444 kb
Host smart-d61e0515-6e9b-40f3-a263-e7a42220233f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10370
29505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1037029505
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.441063222
Short name T481
Test name
Test status
Simulation time 945161815 ps
CPU time 30.74 seconds
Started Aug 09 04:38:45 PM PDT 24
Finished Aug 09 04:39:16 PM PDT 24
Peak memory 255660 kb
Host smart-b77c6ffe-9a70-454a-be6e-708493a9ee35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44106
3222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.441063222
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2110159838
Short name T658
Test name
Test status
Simulation time 122085568674 ps
CPU time 3133 seconds
Started Aug 09 04:38:38 PM PDT 24
Finished Aug 09 05:30:51 PM PDT 24
Peak memory 321432 kb
Host smart-90830773-bffe-4996-8f60-909bed19d914
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110159838 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2110159838
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2889622128
Short name T207
Test name
Test status
Simulation time 37592108 ps
CPU time 2.89 seconds
Started Aug 09 04:38:47 PM PDT 24
Finished Aug 09 04:38:50 PM PDT 24
Peak memory 248392 kb
Host smart-90d4370e-aa7c-4d98-986b-48160640f622
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2889622128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2889622128
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1137308752
Short name T686
Test name
Test status
Simulation time 6211756802 ps
CPU time 882.36 seconds
Started Aug 09 04:38:54 PM PDT 24
Finished Aug 09 04:53:36 PM PDT 24
Peak memory 272512 kb
Host smart-de83c0ad-a736-43a4-b4b2-5d52efbb01bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137308752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1137308752
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2868737754
Short name T625
Test name
Test status
Simulation time 4086499288 ps
CPU time 32.24 seconds
Started Aug 09 04:38:44 PM PDT 24
Finished Aug 09 04:39:16 PM PDT 24
Peak memory 248180 kb
Host smart-e0450ed6-72b3-4dfd-af39-5ab87ea89129
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2868737754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2868737754
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3222241903
Short name T380
Test name
Test status
Simulation time 2164447322 ps
CPU time 123.06 seconds
Started Aug 09 04:38:44 PM PDT 24
Finished Aug 09 04:40:47 PM PDT 24
Peak memory 255960 kb
Host smart-3631b669-a002-49bd-99f2-e7b23ad43a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32222
41903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3222241903
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2977422659
Short name T608
Test name
Test status
Simulation time 746658720 ps
CPU time 51.75 seconds
Started Aug 09 04:38:42 PM PDT 24
Finished Aug 09 04:39:34 PM PDT 24
Peak memory 248160 kb
Host smart-5556b7d3-e193-4a77-9fa5-2a54215ff508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29774
22659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2977422659
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1711852826
Short name T632
Test name
Test status
Simulation time 95067005699 ps
CPU time 1413.81 seconds
Started Aug 09 04:38:47 PM PDT 24
Finished Aug 09 05:02:21 PM PDT 24
Peak memory 272004 kb
Host smart-d8a600d5-6a2f-419f-adf1-971a553d803e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711852826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1711852826
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2621762354
Short name T546
Test name
Test status
Simulation time 87845642374 ps
CPU time 2601.18 seconds
Started Aug 09 04:38:46 PM PDT 24
Finished Aug 09 05:22:07 PM PDT 24
Peak memory 281000 kb
Host smart-c970925e-904a-4c1f-90fc-2bdde3b41e74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621762354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2621762354
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3103206691
Short name T306
Test name
Test status
Simulation time 15072138528 ps
CPU time 163.05 seconds
Started Aug 09 04:38:48 PM PDT 24
Finished Aug 09 04:41:31 PM PDT 24
Peak memory 248604 kb
Host smart-35aac1da-a0d7-4b9a-9028-0c9bf8324e09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103206691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3103206691
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2584457479
Short name T385
Test name
Test status
Simulation time 614559924 ps
CPU time 34.47 seconds
Started Aug 09 04:38:45 PM PDT 24
Finished Aug 09 04:39:19 PM PDT 24
Peak memory 256180 kb
Host smart-a039e917-f3ac-41d2-80a6-12c5825e5354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25844
57479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2584457479
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3009994290
Short name T504
Test name
Test status
Simulation time 847122414 ps
CPU time 46.43 seconds
Started Aug 09 04:38:47 PM PDT 24
Finished Aug 09 04:39:34 PM PDT 24
Peak memory 247692 kb
Host smart-92091a9e-49cf-4973-91dc-7d7c04294e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30099
94290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3009994290
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2305401632
Short name T510
Test name
Test status
Simulation time 3313006593 ps
CPU time 47.64 seconds
Started Aug 09 04:38:37 PM PDT 24
Finished Aug 09 04:39:25 PM PDT 24
Peak memory 255432 kb
Host smart-8c37f44c-d8cf-4768-a643-e090c1b4f3b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23054
01632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2305401632
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1277361635
Short name T441
Test name
Test status
Simulation time 729706308 ps
CPU time 34.53 seconds
Started Aug 09 04:38:50 PM PDT 24
Finished Aug 09 04:39:24 PM PDT 24
Peak memory 256272 kb
Host smart-9b19ab22-e59f-46b4-9931-982139e3446f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12773
61635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1277361635
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1133129686
Short name T611
Test name
Test status
Simulation time 149888969607 ps
CPU time 2265.06 seconds
Started Aug 09 04:38:49 PM PDT 24
Finished Aug 09 05:16:34 PM PDT 24
Peak memory 282444 kb
Host smart-e4e03bbd-f77a-41a4-9c66-18415476c372
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133129686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1133129686
Directory /workspace/9.alert_handler_stress_all/latest
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