Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	107621	1			T4	576		T5	6126		T17	9
class_i[0x1]	61955	1			T3	1		T4	5		T5	659
class_i[0x2]	54008	1			T4	5		T17	2		T15	1
class_i[0x3]	62632	1			T3	3208		T4	5125		T8	7

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	71604	1			T3	785		T4	1306		T5	1397
alert[0x1]	72538	1			T3	809		T4	1470		T5	2008
alert[0x2]	71871	1			T3	795		T4	1918		T5	1718
alert[0x3]	70203	1			T3	820		T4	1017		T5	1662

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

285960

1

T3

3209

T4

5711

T5

6785

esc_ping_fail

256

1

T8

7

T15

3

T16

4

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	71531	1			T3	785		T4	1306		T5	1397
esc_integrity_fail	alert[0x1]	72469	1			T3	809		T4	1470		T5	2008
esc_integrity_fail	alert[0x2]	71817	1			T3	795		T4	1918		T5	1718
esc_integrity_fail	alert[0x3]	70143	1			T3	820		T4	1017		T5	1662
esc_ping_fail	alert[0x0]	73	1			T8	3		T15	1		T16	2
esc_ping_fail	alert[0x1]	69	1			T8	2		T15	1		T16	1
esc_ping_fail	alert[0x2]	54	1			T8	1		T15	1		T16	1
esc_ping_fail	alert[0x3]	60	1			T8	1		T61	1		T64	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	107573	1			T4	576		T5	6126		T17	9
esc_integrity_fail	class_i[0x1]	61910	1			T3	1		T4	5		T5	659
esc_integrity_fail	class_i[0x2]	53924	1			T4	5		T17	2		T6	14
esc_integrity_fail	class_i[0x3]	62553	1			T3	3208		T4	5125		T8	1
esc_ping_fail	class_i[0x0]	48	1			T15	1		T64	1		T221	2
esc_ping_fail	class_i[0x1]	45	1			T8	1		T305	6		T330	1
esc_ping_fail	class_i[0x2]	84	1			T15	1		T61	6		T64	8
esc_ping_fail	class_i[0x3]	79	1			T8	6		T15	1		T16	4