Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	658293941	0	0	622
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	658293941	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	658293941	658149647	0	0
tb.dut.CheckAccuCntDw	0	0	622	622	0	0
tb.dut.CheckEscCntDw	0	0	622	622	0	0
tb.dut.CheckNAlerts	0	0	622	622	0	0
tb.dut.CheckNClasses	0	0	622	622	0	0
tb.dut.CheckNEscSev	0	0	622	622	0	0
tb.dut.CrashdumpKnownO_A	0	0	658293941	658149647	0	0
tb.dut.EdnKnownO_A	0	0	658293941	658149647	0	0
tb.dut.EscPKnownO_A	0	0	658293941	658149647	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	658293941	60	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	658293941	60	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	658293941	60	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	658293941	60	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	658293941	60	0	0
tb.dut.IrqAKnownO_A	0	0	658293941	658149647	0	0
tb.dut.IrqBKnownO_A	0	0	658293941	658149647	0	0
tb.dut.IrqCKnownO_A	0	0	658293941	658149647	0	0
tb.dut.IrqDKnownO_A	0	0	658293941	658149647	0	0
tb.dut.TlAReadyKnownO_A	0	0	658293941	658149647	0	0
tb.dut.TlDValidKnownO_A	0	0	658293941	658149647	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	681836655	3511512	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	681836655	10228	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	681836655	11291	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	681836655	10723	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	681836655	10982	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	681836655	9914	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	681836655	10852	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	681836655	11938	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	681836655	9945	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	681836655	9912	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	681836655	9757	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	681836655	10734	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	681836655	10151	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	681836655	9701	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	681836655	12020	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	681836655	10097	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	681836655	10116	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	681836655	10013	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	681836655	9739	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	681836655	11171	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	681836655	10901	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	681836655	10767	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	681836655	11144	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	681836655	9861	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	681836655	10003	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	681836655	9795	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	681836655	10337	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	681836655	11131	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	681836655	11167	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	681836655	10025	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	681836655	10053	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	681836655	10749	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	681836655	12253	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	681836655	10109	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	681836655	10991	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	681836655	10062	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	681836655	11148	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	681836655	11196	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	681836655	10028	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	681836655	10875	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	681836655	11041	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	681836655	9964	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	681836655	11091	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	681836655	9693	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	681836655	10915	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	681836655	9831	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	681836655	11048	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	681836655	9881	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	681836655	9873	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	681836655	9905	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	681836655	11213	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	681836655	10929	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	681836655	10999	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	681836655	11171	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	681836655	9946	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	681836655	11244	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	681836655	9793	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	681836655	11004	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	681836655	9946	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	681836655	11148	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	681836655	11215	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	681836655	9525	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	681836655	11174	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	681836655	10939	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	681836655	11296	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	681836655	11057	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	681836655	12302	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	681836655	12190	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	681836655	9837	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	681836655	11083	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	681836655	18324	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	681836655	9867	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	681836655	11098	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	681836655	10022	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	681836655	9857	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	681836655	10023	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	681836655	11184	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	681836655	11110	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	681836655	9630	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	658293941	60	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	658293941	60	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	658293941	60	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	658293941	3543	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	658293941	268129	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	658293941	297807599	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	658293941	218	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	658293941	876	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	658293941	28	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	658293941	435	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	658168769	232463522	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	658293941	945	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	658293941	923	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	658293941	908	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	658293941	891	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	658293941	878	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	658293941	90077	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	658293941	792	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	658293941	56	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	658293941	984	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	658293941	804	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	658166773	658099325	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	658293941	658149647	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	658293941	60	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	658293941	60	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	658293941	60	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	658293941	2610	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	658293941	172252	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	658293941	382184642	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	658293941	184	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	658293941	463	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	658293941	15	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	658293941	174	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	658168769	308037139	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	658293941	510	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	658293941	501	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	658293941	496	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	658293941	490	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	658293941	617	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	658293941	83897	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	658293941	560	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	658293941	40	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	658293941	962	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	658293941	782	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	658166773	658099325	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	658293941	658149647	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	658293941	60	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	658293941	60	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	658293941	60	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	658293941	3991	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	658293941	168676	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	658293941	367408939	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	658293941	186	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	658293941	453	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	658293941	24	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	658293941	210	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	658168769	306624049	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	658293941	511	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	658293941	499	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	658293941	486	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	658293941	479	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	658293941	1033	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	658293941	138140	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	658293941	958	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	658293941	50	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	658293941	943	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	658293941	763	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	658166773	658099325	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	658293941	658149647	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	658293941	60	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	658293941	60	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	658293941	60	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	658293941	5655	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	658293941	165123	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	658293941	379031287	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	658293941	151	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	658293941	460	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	658293941	22	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	658293941	189	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	658168769	314634913	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	658293941	532	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	658293941	524	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	658293941	512	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	658293941	498	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	658293941	901	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	658293941	89661	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	658293941	824	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	658293941	54	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	658293941	987	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	658293941	807	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	658166773	658099325	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	658293941	658149647	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	681836655	141648993	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	681836655	681164451	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	681836655	681164451	0	0
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